Programming method for flash memory based on mirror bit architecture, flash memory and device
By successively reducing programming conditions and using data pre-read/write techniques, the overprogramming problem in mirrored bit architecture flash memory is solved, improving programming success rate and data read accuracy, and enhancing the reliability of flash memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI XINCUN TIANXIA ELECTRONIC TECH CO LTD
- Filing Date
- 2025-01-20
- Publication Date
- 2026-07-21
AI Technical Summary
Flash memory based on a mirrored bit architecture is prone to overprogramming during the programming process, which leads to decreased programming reliability and affects the accuracy of data reading from storage cells.
The program employs a method of progressively weakening programming conditions to repeatedly program unsuccessfully programmed memory cells. Before programming, the data from the target mirror memory cell is read into an independent memory cell. By detecting and erasing the over-programmed memory cells, the program is ensured to be successful.
This improves the success rate of memory cell programming, reduces overprogramming, and enhances the accuracy of data reading and the reliability of flash memory.
Smart Images
Figure CN122435967A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory chip technology, and more particularly to a programming method, flash memory, and device for flash memory based on a mirrored bit architecture. Background Technology
[0002] With the continuous development of semiconductor storage technology, flash memory, as a non-volatile memory, has been widely used in various electronic devices. Flash memory based on the Twin Bit architecture, with its Twin Bit Cell physical structure design, can improve the reliability and efficiency of data storage.
[0003] The structure and read operation conditions of the mirror bit architecture are as follows: Figure 1 As shown, two adjacent memory cells (memory cell M0 and memory cell M1) share the same control gate and are mirror images of each other. This design may cause interference when reading data from one memory cell, a phenomenon known as the "second bit effect." To minimize this interference, a specific pass voltage (e.g., pass voltage Vpass = 5.8V, Vpass = ...) needs to be applied to its mirror image (e.g., memory cell M1) when performing a read operation on the target memory cell (e.g., memory cell M0). Figure 1 The VCG0 in the image is used to ensure that the operated memory cell can be read accurately. For example, when performing a read operation on memory cell M1, the specific read operation conditions applied to the mirror memory cells M1 and M2 can be Vd = 0.6V, VCG0 = 5.8V, VWL = 3.6V, and VCG1 = 0V.
[0004] However, due to its special mirrored bit structure, over-programming (over-pgm) may occur during the programming of memory cells in flash memory based on mirrored bit architecture using existing flash memory programming methods. This means that if the threshold voltage (Vt) of some memory cells is too high, the memory cells on their adjacent control gates (i.e., their mirrored memory cells) cannot be read correctly, thus affecting the overall programming reliability. Summary of the Invention
[0005] The purpose of this invention is to provide a programming method, flash memory, and device for flash memory based on a mirrored bit architecture, in order to solve at least one of the above-mentioned technical problems.
[0006] In a first aspect, this application provides a programming method for flash memory based on a mirrored bit architecture, the method comprising:
[0007] Step 1: Program multiple memory cells in the flash memory based on the mirror bit architecture according to standard programming conditions;
[0008] Step 2: Check whether each target memory unit being programmed has been successfully programmed;
[0009] Step 3: When at least one target memory cell fails to be programmed, reprogram each target memory cell that has been programmed according to the first programming condition;
[0010] Repeat steps 2 and 3 until all target memory cells are successfully programmed or the number of programming cycles reaches the first threshold. The first programming condition is weaker than the previous programming condition. The programming conditions for each programming cycle include one or more of programming voltage, programming current, and programming duration.
[0011] Optionally, the method further includes setting the first programming conditions based on the ambient temperature of the target storage unit.
[0012] Optionally, the target storage unit is the same storage unit in the flash memory located below the target word line;
[0013] Before programming multiple storage cells in the flash memory based on the mirror bit architecture according to standard programming conditions, the method further includes: reading data from the target mirror storage cell of the target storage cell into a preset independent storage cell.
[0014] Optionally, after the loop programming ends, the method further includes:
[0015] Step 4: Perform a programming check on the target storage unit;
[0016] Step 5: When at least one target storage cell has been programmed, erase the two storage cells below the target word line, the two storage cells including the target storage cell and the target mirror storage cell.
[0017] Step 6: After both storage cells are successfully erased, the data written to the independent storage cell is written to the two erased storage cells.
[0018] Optionally, erasing the two storage cells below the target word line includes erasing the two storage cells below the target word line under a first erasure condition, wherein the first erasure condition is weaker than the standard erasure condition.
[0019] Optionally, writing the data written to the independent storage unit to the two erased storage units includes: writing the data written to the independent storage unit to the two erased storage units under a second programming condition, wherein the second programming condition is weaker than the standard programming condition.
[0020] Optionally, if the two storage cells are not completely erased successfully, the process of erasing the two storage cells under the target word line with the first erasure condition is repeated until both storage cells are completely erased successfully or the number of erase cycles reaches the second threshold.
[0021] Optionally, the threshold voltage of the memory cell moves at a rate that is between one-half and one-thirtieth of the rate that moves under the standard programming conditions under the second programming condition.
[0022] Optionally, the threshold voltage of the storage cell moves at a speed that is one-half to one-thirtieth of the speed that moves under the standard erase condition in the first erase condition.
[0023] Optionally, the step of performing a programming check on the target storage unit includes:
[0024] The threshold voltage of the target storage cell is detected to see if it exceeds a preset voltage value. If it exceeds the preset voltage value, it is determined that the target storage cell has been overprogrammed.
[0025] Optionally, the step of checking whether the target storage unit has been programmed includes: detecting whether the storage current stored in the target mirror storage unit represented by data "1" is less than a preset current value; if it is less than the preset current value, it is determined that the target storage unit has been programmed.
[0026] Optionally, before writing the data written into the independent storage unit to the two erased storage units, the method further includes: using a third programming condition to perform threshold voltage repair on the abnormal storage unit in the two storage units, wherein the abnormal storage unit is the data "0" and the threshold voltage is within a preset abnormal voltage range for the target storage unit and / or the target mirror storage unit.
[0027] Optionally, the independent storage unit is the SRAM in the chip where the flash memory is located, or the independent storage unit is two storage units on an additional word line added to the flash memory.
[0028] Optionally, the threshold voltage of the memory cell moves at one-tenth the speed under the second programming condition compared to the speed under the standard programming condition.
[0029] Optionally, the threshold voltage of the storage cell moves at a rate that is one-tenth of the rate that moves under the standard erase condition in the first erase condition.
[0030] In a second aspect, this application provides a flash memory, which is a flash memory based on a mirrored bit architecture programmed according to the programming method for flash memory based on a mirrored bit architecture as described in any embodiment of this application.
[0031] In a third aspect, this application provides an electronic device comprising a flash memory based on a mirrored bit architecture, programmed according to the programming method for a flash memory based on a mirrored bit architecture as described in any embodiment of this application.
[0032] The programming method, flash memory, and device for flash memory based on mirror bit architecture in this application improve the programming success rate of target memory cells by repeatedly programming target memory cells that have been programmed but not successfully programmed. By specifically adopting the method of successively weakening programming conditions for repeated programming, the over-programming of memory cells in flash memory based on mirror bit architecture can be further reduced, thereby reducing the impact of reading data from the mirror memory cells corresponding to the programmed memory cells. Attached Figure Description
[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation on the scope of this application.
[0034] Figure 1 This is a schematic diagram of a structure of mirrored storage units in one embodiment;
[0035] Figure 2 This is a flowchart illustrating a programming method for a flash memory based on a mirrored bit architecture in one embodiment.
[0036] Figure 3 This is a schematic diagram of the structure of two mirror-image memory cells in a flash memory in one embodiment;
[0037] Figure 4 This is a threshold voltage distribution diagram of a memory cell in a flash memory under normal conditions in one embodiment;
[0038] Figure 5 This is a threshold voltage distribution diagram of a memory cell in a flash memory during multiple programming processes in one embodiment;
[0039] Figure 6 This is a threshold voltage distribution diagram of a memory cell in a flash memory during multiple programming processes in another embodiment;
[0040] Figure 7 This is a schematic diagram of a flash memory structure that includes additional word lines in one embodiment;
[0041] Figure 8 This is a flowchart illustrating a programming method for a flash memory based on a mirrored bit architecture, as described in another embodiment. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0043] All terms used in this application (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.
[0044] For example, the terms "first" and "second" used in this application are only used to distinguish similar objects and differentiate the first object from another object, rather than to describe a specific order or sequence, nor should they be interpreted as indicating or implying relative importance.
[0045] This application proposes a programming method for flash memory based on a mirrored bit architecture, combining... Figure 2 As shown, the method includes:
[0046] Step 210: Program multiple memory cells in the flash memory based on the mirror bit architecture according to standard programming conditions.
[0047] In this application, combined with Figure 1 As shown, in a flash memory based on a mirrored bit architecture, two adjacent memory cells (memory cell M1 and memory cell M2) share a single select gate. These two memory cells are mirrored bits (twin bits), meaning that the mirrored memory cell of memory cell M1 is memory cell M2, and the mirrored memory cell of memory cell M2 is memory cell M1. Specifically, the memory cell can be a floating gate memory.
[0048] Combination Figure 3 As shown, flash memory includes multiple storage cells, which form a storage cell array. Storage cells in the same row are arranged serially to form a storage cell. Adjacent storage cells with a mirrored bit architecture share the same word line (WL). The storage cell currently being programmed is called the target storage cell, the word line where the target storage cell is located is called the target word line, and the mirrored bit storage cell of the target storage cell is called the target mirrored storage cell. Figure 3 and Figure 1 VWL in the text represents the voltage applied to the word line WL where the memory cell is located. The memory cell where M0 is located and the memory cell where M1 is located are both memory cells on the word line WL0.
[0049] In one embodiment, programming can be performed on some or all of the memory cells within the same memory cell. That is, the target memory cell is the memory cell within the same memory cell below the target word line in the flash memory; specifically, the target memory cell includes all memory cells within the same memory cell below the target word line. For example, if a WL (Write-Only) has 1024 memory cells, all 1024 memory cells can be programmed simultaneously to improve programming efficiency.
[0050] Programming (PGM) is the process of writing data into the memory cells. The programming operation involves applying specific voltage pulses to change the threshold voltage of the memory cells, thereby enabling data storage. PGM is one of the crucial steps for the normal operation of flash memory chips, determining how data is stored and the accuracy of data retrieval.
[0051] Specifically, during the programming of a memory cell, hot electrons are accelerated in the SG (storage gate below the source / drain) region and injected into the floating gate (FG). This increases the charge on the floating gate, thereby changing the threshold voltage of the memory cell. During the erasure of the memory cell, electrons are removed directly from the floating gate (FG) to the word line (SG) via the FN structure, without passing through the channel oxide layer. This erasure mechanism helps reduce damage to the channel oxide layer during the erasure process, thereby improving the reliability and lifespan of the memory.
[0052] Standard programming conditions are set for memory cells being programmed for the first time, and are the same as regular programming conditions. Each programming session includes one or more of the following: programming voltage, programming current, and programming duration. Programming voltage represents the voltage applied to the memory cell during programming; it can be a pulse voltage. For the first programming session, the programming voltage typically needs to be high enough, for example, a peak voltage of 10V under standard programming conditions, to generate a sufficient electric field in the SG region below the source / drain to accelerate hot electrons and inject them into the floating gate (FG). Programming current refers to the current flowing through the memory cell during programming. The magnitude of the programming current can be indirectly controlled by limiting the supply voltage or using other protective measures. Programming duration refers to the duration for which the programming voltage and current are applied to the memory cell, ensuring that the memory cell is fully programmed and reaches the expected threshold voltage. For example, the programming duration under standard programming conditions is between several hundred nanoseconds and several microseconds.
[0053] In one embodiment, the programming conditions also include the ambient temperature of the storage unit being programmed.
[0054] Step 220: Check whether each target memory cell has been successfully programmed. If yes, end the programming process; otherwise, proceed to step 230.
[0055] In this embodiment, for each target storage unit being programmed, a programming check is performed after each programming operation to determine whether the programming was successful. Specifically, the programming status of each target storage unit can be detected, the data in each storage unit can be read, and it can be determined whether the data status in the target storage unit matches the expected value. If it matches the expected value, the programming is considered successful; otherwise, the programming is considered unsuccessful.
[0056] like Figure 4 The diagram illustrates the threshold voltage distribution of a memory cell in a flash memory. Here, EV represents the erase verification voltage, Rd represents the read voltage, PV represents the programming verification voltage, and VPASS represents the pass voltage, where the read voltage Rd = 0V. Ideally, after a memory cell in the target flash memory is successfully programmed, the threshold voltage Vt of the memory cell with data "1" is less than or equal to EV, and the threshold voltage of the memory cell with data "0" falls within the range of PV and VPASS values. A successfully programmed memory cell can be... Figure 4 The storage unit in the middle is a "1" for data.
[0057] In one embodiment, the successful programming detection process for each target memory unit that has completed programming once includes:
[0058] 1- Apply detection voltage: Apply a specific detection voltage to the target memory cell being detected. This detection voltage is usually lower than the programming voltage, but sufficient to put the memory cell into a conduction or cutoff state, thereby allowing its threshold voltage to be detected.
[0059] 2- Read current or voltage: After applying the detection voltage, read the current passing through the target memory cell or the voltage across the target memory cell. This current or voltage value will reflect the threshold voltage of the memory cell.
[0060] 3. Comparison and Judgment: The read current or voltage value is compared with a preset threshold. If the read value meets the preset condition (e.g., greater than or less than a certain threshold), the programming is considered successful; otherwise, the programming is considered unsuccessful.
[0061] For example, the threshold voltage of a successfully programmed target memory cell should increase from the initial 0.5V to 2.0V. However, the threshold voltage of a target memory cell that is unsuccessfully programmed (e.g., insufficient programming voltage, short programming time) fails to reach the expected value of 2.0V and only increases to 1.0V. During the detection process, a detection voltage of 1.5V is applied to the target memory cell, and its state under this voltage is detected. Since 1.5V is lower than the threshold voltage of 2.0V after successful programming, the successfully programmed target memory cell should be in the off state, meaning the current should be very small (close to 0). Since 1.5V is higher than the actual threshold voltage of 1.0V for the unsuccessfully programmed target memory cell, the unsuccessfully programmed target memory cell will be in the on state, meaning the current will be relatively large.
[0062] If the current reading through the target memory cell is 0.1μA (far less than the preset cutoff current threshold, for example, 1μA), the memory cell is considered successfully programmed; conversely, if the current reading through the target memory cell is 10μA (far greater than the preset cutoff current threshold of 1μA), the target memory cell is considered unsuccessfully programmed.
[0063] By detecting each target storage unit, if any target storage unit fails to be programmed, step 230 is executed. If all target storage units are successfully programmed, the programming of the current target storage unit ends.
[0064] for example Figure 5 and Figure 6 As shown, after the first programming is completed, only the memory cells corresponding to the green lines are successfully programmed, while the memory cells corresponding to the red lines (i.e., the memory cells within the Rd and PV intervals) are not successfully programmed. Then, proceed to step 230 below.
[0065] For example Figure 6 As shown, after the second programming is completed, a small number of memory cells (i.e., memory cells in the Rd and PV intervals) are still not successfully programmed. Then, the following step 230 is executed.
[0066] Step 230: Reprogram each target storage unit that has been programmed according to the first programming conditions.
[0067] In this embodiment, when at least one target storage unit fails to be programmed, all target storage units are reprogrammed. The reprogramming process is similar to step 210, except that the programming conditions (i.e., the first programming conditions) implemented this time are weaker than the previous programming conditions.
[0068] Weaker programming conditions include one or more of the following: lower programming voltage, lower programming current, and shorter programming time. For example, if programming voltage is included as a programming condition, then the programming voltage under the first programming condition is lower than the programming voltage under the previous programming condition.
[0069] For example, when the current programming is the second programming, the programming conditions for the second programming (the first programming condition) are weaker than the standard programming conditions (the previous programming conditions); when the current programming is the third programming, the programming conditions for the third programming (the first programming condition) are weaker than the second programming conditions (the previous programming conditions); when the current programming is the fourth programming, the programming conditions for the fourth programming (the first programming condition) are weaker than the third programming conditions (the previous programming conditions); and so on, until all target memory units are successfully programmed or the number of programming iterations reaches the threshold of the first iteration.
[0070] The threshold for the first count is any preset and suitable value, such as 3, 4, 5, 8, 10, or any other suitable number of times.
[0071] The initial shift speed of the threshold voltage of the target memory cell under the first programming condition is lower than the standard shift speed of the threshold voltage of the target memory cell under the standard programming condition. For example, under the second programming condition, the shift speed of the threshold voltage of the target memory cell is half or even lower than that under the previous programming condition.
[0072] In this embodiment, the moving speed of the threshold voltage represents the rate of change of the threshold voltage of the memory cell. This rate of change can be either an increasing rate or a decreasing rate. For example, when programming the memory cell, this moving speed is the rate of increase of the threshold voltage; when erasing the memory cell, this moving speed is the rate of decrease of the threshold voltage.
[0073] For the same target memory unit, the programming conditions are gradually weakened with each iteration, thus avoiding overprogramming. For example... Figure 5 As shown, if the programming conditions remain unchanged each time, the target storage unit that failed to be programmed in the previous programming will be prone to overprogramming when subjected to the same programming conditions, which will affect the reading of data in the corresponding mirror storage unit.
[0074] like Figure 6As shown, by gradually setting the current programming conditions (programming intensity) to be weaker than the previous programming conditions (previous programming intensity), overprogramming is less likely to occur. This makes it easier for the threshold voltage of the target memory cell to reach a state that is both greater than PV and less than VPASS (i.e., no overprogramming), thus avoiding the impact on the target mirror memory cell. By performing multiple programming operations under successively decreasing programming conditions, the risk of overprogramming can be reduced, assuming all target memory cells are successfully programmed.
[0075] In one embodiment, a first programming condition is set based on the number or proportion of target memory cells that have not been successfully programmed. For example, when the number or proportion of target memory cells that have not been successfully programmed exceeds a preset threshold, both the programming voltage and the programming time are reduced; when the number or proportion of target memory cells that have not been successfully programmed is less than the preset threshold, only the programming voltage is reduced.
[0076] In one embodiment, the first programming conditions are set based on the ambient temperature of the target storage unit.
[0077] In this embodiment, a predefined correspondence between ambient temperature and the first programming condition is established. The higher the ambient temperature, the greater the reduction in the first programming condition compared to the previous programming condition. Before programming begins, the ambient temperature of the target storage unit can be detected, the reduction degree can be determined based on the ambient temperature, and the first programming condition can be determined based on the determined reduction degree and the previous programming condition.
[0078] In one embodiment, the first programming condition is set based on the ambient temperature and the number or proportion of target storage cells that have not been successfully programmed.
[0079] In this embodiment, the ambient temperature and the number or proportion of unprogrammed target storage units are further combined. When the ambient temperature is higher and the number or proportion of unprogrammed target storage units is higher, the degree of reduction of the first programming condition relative to the previous programming condition is greater.
[0080] By adjusting the initial programming conditions in conjunction with ambient temperature, the memory cells can achieve good programming results under different ambient temperatures, thereby improving the accuracy and reliability of programming.
[0081] In one embodiment, when all target memory cells are successfully programmed, the programming of the current target memory cell ends, and other memory cells in the flash memory that need to be programmed are selected as new target memory cells. The programming continues according to steps 210 to 230 above until the programming of all memory cells that need to be programmed is completed.
[0082] In one embodiment, the target storage cell is the same storage cell in the flash memory located below the target word line. Before step 210, the method further includes: reading the data in the target mirror storage cell of the target storage cell into a preset independent storage cell.
[0083] In this embodiment, to avoid the programming process of the target storage unit affecting the data reading and writing of the target mirror storage unit, the data in the target mirror storage unit can be read out in advance and written to a preset independent storage unit. Furthermore, the data in both the target storage unit and the target mirror storage unit are read out and written to the preset independent storage unit.
[0084] This independent storage unit is a pre-defined storage unit dedicated to storing data in the target storage unit and / or the target mirror storage unit. For example, one or more independent storage units (e.g., spare pages or cache areas) can be pre-defined in flash memory or external storage. These independent storage units will not be used during non-overprogramming detection to ensure the security and availability of read data.
[0085] Specifically, the independent storage unit is the SRAM within the chip where the flash memory resides. Utilizing the on-chip SRAM as an independent storage unit for data in both the target storage unit and the target mirror storage unit can significantly reduce data access latency and improve data processing speed.
[0086] In one embodiment, a separate storage unit is two storage units on an additional word line in the flash memory.
[0087] Specifically, an additional word line can be added to the flash memory. The two memory cells under this word line do not have independent addresses that can be manipulated by the user like conventional memory cells. They are not used for user storage, but only to temporarily store information of the mirrored bit cells during programming for verification during programming checks. During the flash memory chip design, one word line can be reserved as a word line that does not require programming, or an additional word line that does not require programming can be added. The two memory cells under this word line are used to write data into the target memory cell and / or the target mirrored memory cell.
[0088] like Figure 7As shown, Extra-WL is an additional word line. The two memory cells under Extra-WL (Extra-CG1 and Extra-CG0) are used to write data to the target memory cell and / or the target mirror memory cell, respectively. For example, when programming all memory cells under the word line WL0 containing M0, or programming all memory cells under the word line M1, the data in all memory cells under the word line M0 is written to the memory cells under the word line Extra-CG0, and the data in all memory cells under the word line M1 is written to the memory cells under the word line Extra-CG1.
[0089] Flash memory typically has a very high number of word lines, such as 1024 or more. The cost increase from adding an extra word line (Extra-WL) is lower than the cost increase from adding additional SRAM. For example, in a flash memory with 1024 word lines, the cost increase from adding an extra word line (Extra-WL) is less than 0.1%.
[0090] In this embodiment, before programming the target storage unit, the data in the corresponding target mirror storage unit is read out and securely stored, which effectively prevents the risk of data loss or damage in the target mirror storage unit. It also provides a basis for subsequent data recovery and verification, further enhancing the fault tolerance and data consistency of the flash memory.
[0091] In one embodiment, such as Figure 8 As shown, another programming method for flash memory based on a mirrored bit architecture is provided, which includes:
[0092] Step 810: Read the data from the target mirror storage unit of the target storage unit into the preset independent storage unit.
[0093] Specifically, all memory cells under the same word line can be used as target memory cells to be programmed at once. The data in the target mirror memory cell corresponding to each target memory cell is read out and written to the preset SRAM, or written to one of the memory cells under an added word line.
[0094] For example, the target storage unit is Figure 7 All storage units under the column containing M0 shown in the diagram, the target mirror storage unit is Figure 7 All storage cells under the same stripe M1 can read data from and write data to all storage cells under the same stripe M1. Figure 7The data in each target image storage unit is read out and written to the corresponding storage unit under the Extra-CG0 or Extra-CG1 strip.
[0095] Step 820: Program multiple storage cells in the flash memory based on the mirror bit architecture according to standard programming conditions.
[0096] Step 830: Check whether each target memory cell has been successfully programmed. If yes, proceed to step 850; otherwise, proceed to step 840.
[0097] Step 840: Reprogram each target memory cell that has been programmed according to the first programming conditions.
[0098] The programming voltage under the first programming condition is lower than the programming voltage under the previous programming condition. Steps 820 to 840 are executed in the same way as steps 210 to 230 described above, and will not be repeated here. By repeatedly executing steps 830 to 840, the programming conditions are gradually weakened for target memory cells that have not yet been successfully programmed, in order to reduce the occurrence of overprogramming. When it is detected that all target memory cells have been successfully programmed, or when the number of programming iterations reaches the first threshold, step 850 is executed.
[0099] Step 850: Perform an overprogramming check on the target memory cell. If no overprogramming is found, the programming process ends; if at least one target memory cell is found to be overprogrammed, proceed to step 860.
[0100] In this embodiment, an overprogramming check is performed on the target memory cells that have been programmed to detect whether at least one of the currently programmed target memory cells has been overprogrammed. This can be done by reading the threshold voltage or other relevant parameters of the target memory cell. These parameters reflect the programming status of the memory cell, and the presence of overprogramming is determined based on the read threshold voltage or other relevant parameters.
[0101] In one embodiment, it is detected whether the threshold voltage of the target storage cell exceeds a preset voltage value. If it exceeds the preset voltage value, it is determined that the target storage cell has been overprogrammed.
[0102] For each target memory cell, its threshold voltage can be checked to see if it exceeds a preset voltage value. If it does, it indicates that overprogramming has occurred. For example... Figure 5 As shown, the memory cell corresponding to the red curve represents a case of overprogramming. The threshold voltage of this overprogrammed memory cell is greater than the pass voltage VPASS.
[0103] In this embodiment, a reasonable preset voltage value is set according to the design specifications and process parameters of the memory cell. This preset voltage typically represents the maximum threshold voltage that the memory cell should have after normal programming, and is used to distinguish between normal programming and overprogramming states. For threshold voltage measurement, a dedicated test circuit can be used to measure the threshold voltage of the target memory cell. The measured threshold voltage is compared with the preset voltage value. If the threshold voltage of the target memory cell exceeds the preset voltage, it is determined that the memory cell has been overprogrammed.
[0104] By programming the recognition based on preset voltage values, the efficiency of recognition can be improved.
[0105] In one embodiment, it is detected whether the storage current stored in the target mirror storage cell, represented by data "1", is less than a preset current value. If it is less than the preset current value, it is determined that the target storage cell has been overprogrammed.
[0106] Because of the relationship between the target memory cell and the target mirror memory cell, the current status of the target mirror memory cell can be detected, and the over-programming of the target memory cell corresponding to the target mirror memory cell can be identified based on the current status it reflects.
[0107] The preset current value is also a suitable current value set according to the design specifications and process parameters of the memory cell. For the target mirror memory cell with data "1", its storage current is measured to see if it is less than the preset current value. If it is less, the corresponding target memory cell is determined to have been overprogrammed. By performing overprogramming detection on the target memory cell based on the target mirror memory cell, the accuracy of overprogramming detection can be improved.
[0108] The two overprogramming detection methods mentioned above can be used in combination to further improve the comprehensiveness of overprogramming detection.
[0109] Step 860: Erase the two memory cells below the target word line.
[0110] The two memory units consist of a target memory unit and a target mirror memory unit. When a target memory unit has been programmed, all memory units (including the target memory unit and the target mirror memory unit) on the same target word line are erased. Appropriate erasure conditions can be set, and memory units are erased under these conditions.
[0111] In one embodiment, two memory cells below the target word line are erased under a first erase condition, which is weaker than the standard erase condition.
[0112] The standard erase conditions refer to the erase conditions used only in the case of the first erase of the memory cell, and not the erase conditions implemented in the programming environment as described in this application. Standard erase conditions are consistent with erase conditions used in a conventional erase environment, and include one or more of the following: standard erase voltage, standard erase duration, etc. The first erase condition includes one or more of the following: first erase voltage, first erase duration, etc., wherein at least one of the following exists: the first erase voltage is less than the standard erase voltage, and / or the first erase duration is less than the standard erase duration.
[0113] Performing an erase under a first erase condition, which is weaker than the standard erase condition, can reduce the threshold voltage of the target mirror memory cell. The threshold voltage of the memory cell under the first erase condition moves at a lower rate than that of the memory cell under the standard erase condition.
[0114] In one embodiment, the first erasure condition is set based on one or more factors such as the ambient temperature of the target storage cell, the number or proportion of target storage cells that were not successfully erased.
[0115] For example, when the number or proportion of target storage cells that failed to be erased exceeds a preset threshold, the erase voltage and erase duration are reduced simultaneously; when the number or proportion of target storage cells that failed to be erased is less than the preset threshold, only the erase voltage is reduced.
[0116] Similar to the programming conditions, a predefined relationship is established between ambient temperature and the first erase condition. The higher the ambient temperature, the greater the reduction in the first erase condition compared to the previous erase condition. Before erasure begins, the ambient temperature of the target storage cell can be detected, the reduction level can be determined based on the ambient temperature, and the first erase condition can be determined based on the determined reduction level and the previous erase condition.
[0117] By adjusting the first erase condition in conjunction with the ambient temperature, the storage unit can achieve good erase results under different ambient temperatures, improving the accuracy and reliability of the erase process.
[0118] In one embodiment, before erasing, the data in all successfully programmed target memory cells is read out to a preset independent memory cell. For example, all target memory cells under the M0 line are written to a preset SRAM or one of the memory cells under an added word line.
[0119] Step 870: Check whether the two memory cells were successfully erased. If yes, proceed to step 880; otherwise, return to step 860.
[0120] The success of the erasure can also be verified by reading the threshold voltage or other relevant parameters of each of the two memory cells. If at least one memory cell fails to be erased, the process returns to step 860. If both are successfully erased, the process proceeds to step 880.
[0121] In one embodiment, if two memory cells are not completely erased successfully, the eraser process is repeated on the two memory cells below the target word line according to the first erase condition until both memory cells are completely erased or the number of erase cycles reaches the second threshold. Similar to the first threshold, the second threshold can be any suitable value preset, such as 3, 4, 5, 8, 10, or any suitable number of times.
[0122] If at least one target storage unit or target mirror unit fails to be erased, then all target storage units are erased again. The erasure conditions used in the second erasure can be the same as the previous erasure conditions, or weaker erasure conditions can be used.
[0123] Weaker erase conditions include one or more of the following: lower erase voltage and lower erase duration. For example, if the erase condition includes erase voltage, then the erase voltage under the first erase condition is lower than the erase voltage under the previous erase condition.
[0124] In one embodiment, it can be detected whether the incompletely erased storage cells belong to either the over-programmed target storage cells or the target mirror storage cells corresponding to the over-programmed target storage cells. If they belong to either the over-programmed target storage cells or the target mirror storage cells corresponding to the over-programmed target storage cells, then the process returns to step 860. If the incompletely erased storage cells do not belong to either the over-programmed target storage cells or the target mirror storage cells corresponding to the over-programmed target storage cells, then the process proceeds to step 880.
[0125] Step 880: The data written to the independent storage cell is written to the two storage cells that are being erased.
[0126] After confirming that both storage cells below the target word have been successfully erased, the data previously written to the independent storage cells is rewritten to these two erased storage cells to restore the integrity and consistency of the stored data.
[0127] Similarly, programming conditions for writing can be set, including one or more of programming voltage, programming duration, and programming current. Writing under these set programming conditions can improve the integrity and consistency of data writing.
[0128] Specifically, the data written to the independent storage cell is written to the two storage cells that are being erased under the second programming condition, which is weaker than the standard programming condition.
[0129] Optionally, the second programming conditions may include one or more of the following: a second programming voltage, a second programming current, and a second programming duration. For example, the second programming conditions may be the same as the first programming conditions used last time. By using second programming conditions that are weaker than the standard programming conditions for writing, the success rate of data being written correctly can be improved.
[0130] For example, the second moving speed of the threshold voltage of a memory cell under the second programming condition is lower than the standard moving speed of the threshold voltage of a memory cell under the standard programming condition. For instance, the second moving speed is half or even lower than the standard moving speed.
[0131] The programming of the target storage unit is complete when no programming has been performed, or when data has been successfully written to both storage units.
[0132] The programming method for flash memory based on mirrored bit architecture in this application performs an overprogramming check on the target storage cell after the end of the loop programming, and takes corresponding corrective measures when overprogramming is detected, so as to ensure the accuracy and reliability of the stored data.
[0133] In one embodiment, the threshold voltage of the memory cell moves at a rate that is one-half to one-thirtieth of the rate that moves under standard programming conditions in the second programming condition.
[0134] Specifically, the threshold voltage of the memory cell moves at one-tenth the speed under the second programming condition compared to the standard programming condition.
[0135] In one embodiment, the threshold voltage of the memory cell moves at a speed that is one-half to one-thirtieth of the speed that moves under standard erase conditions in the first erase condition.
[0136] Specifically, the threshold voltage of the memory cell moves at one-tenth the speed under the first erase condition compared to the standard erase condition.
[0137] By programming under the second programming condition and erasing under the first erasing condition, the reliability of erasing and programming can be improved.
[0138] In one embodiment, before step 880, the method further includes: repairing the threshold voltages of the two memory cells to restore the corresponding threshold voltages to a preset normal voltage range.
[0139] Because the erase process may cause a drop in the threshold voltage of the target mirror storage cell and / or the target storage cell, appropriate programming conditions are used to repair the threshold voltage of the two storage cells before writing. Specifically, threshold voltage repair can be performed on abnormal storage cells among the two storage cells. The abnormal storage cell is the target storage cell and / or the target mirror storage cell with data "0" and a threshold voltage within a preset abnormal voltage range.
[0140] Optionally, a third programming condition is used to perform threshold voltage repair on the abnormal memory cells in the two memory cells.
[0141] An abnormal voltage range is preset. After the erase step of the memory cell is completed, it is detected whether the threshold voltage of the memory cell whose erased data is "0" is within the abnormal voltage range. If so, the memory cell is determined to be an abnormal memory cell.
[0142] Once abnormal memory cells are identified, specific third programming conditions are used to repair their threshold voltages. These third programming conditions may include different programming voltages, programming times, or the effective width of the programming pulse, with the aim of adjusting the threshold voltage of the abnormal memory cells back to the normal range.
[0143] The third programming condition can be set based on the threshold voltage of the abnormal memory cell. For example, if the threshold voltage of the abnormal memory cell is too low, its threshold voltage can be increased by increasing the programming voltage or extending the programming time; conversely, if the threshold voltage is too high, it may be necessary to decrease the programming voltage or shorten the programming time. Furthermore, the change in threshold voltage can be finely controlled by adjusting parameters such as the effective width, interval, or number of programming pulses. By specifically setting the third programming condition according to the threshold voltage of the abnormal memory cell, the recovery efficiency of the abnormal memory cell can be improved.
[0144] After repairing using the third programming condition, these memory cells can be scanned again to verify whether their threshold voltages have been adjusted to the normal voltage range. If the threshold voltages of some memory cells still fail to meet the requirements, the above repair process can be repeated.
[0145] In this embodiment, by repairing abnormal storage units before writing, the accuracy and reliability of data writing can be improved.
[0146] In one embodiment, a flash memory is provided, which is a flash memory based on a mirrored bit architecture programmed according to the programming method for flash memory based on a mirrored bit architecture according to any embodiment of this application.
[0147] In one embodiment, an electronic device is provided, which includes flash memory based on a mirrored bit architecture programmed according to the method in any of the above embodiments.
[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
[0149] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of this application and form different embodiments. For example, all the embodiments above can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.
Claims
1. A programming method for flash memory based on a mirrored bit architecture, characterized in that, The method includes: Step 1: Program multiple memory cells in the flash memory based on the mirror bit architecture according to standard programming conditions; Step 2: Check whether each target memory unit being programmed has been successfully programmed; Step 3: When at least one target memory cell fails to be programmed, reprogram each target memory cell that has been programmed according to the first programming condition; Repeat steps 2 and 3 until all target memory cells are successfully programmed or the number of programming cycles reaches the first threshold. The first programming condition is weaker than the previous programming condition. The programming conditions for each programming cycle include one or more of programming voltage, programming current, and programming duration.
2. The programming method according to claim 1, characterized in that, The method further includes: The first programming conditions are set according to the ambient temperature of the target storage unit.
3. The programming method according to claim 1, characterized in that, The target storage unit is the same storage unit located below the target word line in the flash memory. Before programming the multiple storage cells in the flash memory based on the mirrored bit architecture according to standard programming conditions, the method further includes: The data in the target mirror storage unit of the target storage unit is read out to the preset independent storage unit.
4. The programming method according to claim 3, characterized in that, After the loop programming ends, the method further includes: Step 4: Perform a programming check on the target storage unit; Step 5: When at least one target storage cell has been programmed, erase the two storage cells below the target word line, the two storage cells including the target storage cell and the target mirror storage cell. Step 6: After both storage cells are successfully erased, the data written to the independent storage cell is written to the two erased storage cells.
5. The programming method according to claim 4, characterized in that, The step of erasing the two memory cells below the target word line includes: erasing the two memory cells below the target word line with a first erasure condition, wherein the first erasure condition is weaker than the standard erasure condition. The step of writing the data written into the independent storage unit to the two erased storage units includes: writing the data written into the independent storage unit to the two erased storage units under a second programming condition, wherein the second programming condition is weaker than the standard programming condition.
6. The programming method according to claim 5, characterized in that, If the two memory cells are not completely erased, the process of erasing the two memory cells under the target word line with the first erasure condition is repeated until the two memory cells are completely erased or the number of erase cycles reaches the second threshold. The threshold voltage of the memory cell moves at a rate that is one-half to one-thirtieth of the rate that moves under the standard programming conditions under the second programming condition. The threshold voltage of the memory cell moves at a speed that is one-half to one-thirtieth of the speed that moves under the standard erase condition in the first erase condition.
7. The programming method according to claim 4, characterized in that, The programming check performed on the target storage unit includes: The threshold voltage of the target memory cell is detected to see if it exceeds a preset voltage value. If it does, the target memory cell is determined to have been overprogrammed; and / or The system detects whether the storage current stored in the target image storage unit, represented by data "1", is less than a preset current value. If it is less than the preset current value, it determines that the target storage unit has been overprogrammed.
8. The programming method according to claim 4, characterized in that, Before writing the data written to the independent storage cell to the two erased storage cells, the method further includes: The abnormal storage cell in the two storage cells is repaired by a third programming condition. The abnormal storage cell is the data "0" and the threshold voltage is within the preset abnormal voltage range of the target storage cell and / or the target mirror storage cell.
9. The programming method according to any one of claims 5 to 8, characterized in that, The independent storage unit is the SRAM in the chip where the flash memory is located, or the independent storage unit is two storage units on an additional word line added to the flash memory; The threshold voltage of the memory cell moves at one-tenth the speed under the second programming condition compared to the speed under the standard programming condition. The threshold voltage of the memory cell moves at one-tenth the speed under the first erase condition compared to the standard erase condition.
10. A flash memory, characterized in that, The flash memory is a flash memory based on a mirrored bit architecture programmed according to any one of claims 1 to 9.
11. An electronic device, characterized in that, include: The flash memory as described in claim 10.