Storage device testing method based on custom industrial language, terminal and device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU HUAXING YUANCHUANG TECH CO LTD
- Filing Date
- 2026-04-29
- Publication Date
- 2026-07-21
Smart Images
Figure CN122435971A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of storage device testing, and in particular relates to a storage device testing method, terminal and device based on a custom industrial language. Background Technology
[0002] In semiconductor memory device testing, traditional solutions employ static pattern vector files to drive testing. This requires pre-generating a massive number of fixed test vectors and downloading them entirely to the test device. This approach lacks logical control capabilities such as loops and conditional jumps; complex algorithms can only be expanded into massive vectors, resulting in huge file sizes and significantly consuming test device storage resources. Furthermore, static vectors cannot be flexibly scheduled; modifications to the process require regenerating the complete pattern, leading to time-consuming loading and transmission, inefficient test program scheduling, long testing times for individual chips, and overall low testing efficiency. Summary of the Invention
[0003] This application provides a storage device testing method, terminal, and device based on a custom industrial language, which reduces the storage pressure on the testing device, improves test program scheduling, and enhances testing efficiency.
[0004] This application discloses a storage device testing method based on a custom industrial language, including: Obtain test scripts for storage devices written in industrial languages; Intermediate representations and intermediate representation information are extracted from the industrial language program of the storage device test script; A binary instruction sequence is generated based on the intermediate representation and intermediate representation information, and the binary instruction sequence is transmitted to the test device so that the test device can perform storage device testing according to the binary instruction sequence.
[0005] Optionally, the extraction of the intermediate representation from the industrial language program of the storage device test script includes: Lexical and syntactic analysis are performed on the test script of the storage device to generate an abstract syntax tree; Semantic analysis is performed on the abstract syntax tree to determine the logical nodes in the abstract syntax tree used for test program control; A corresponding intermediate representation is generated based on each of the logical nodes.
[0006] Optionally, extracting intermediate representation information from the industrial language program of the storage device test script includes: Extract macro definitions and identifiers from the industrial language program of the test script for the storage device; The intermediate representation information is obtained by determining the macro definitions and parameter values of identifiers in the industrial language program associated with the intermediate representation.
[0007] Optionally, generating a binary instruction sequence based on the intermediate representation and the intermediate representation information includes: Generate a corresponding binary identifier based on the control type represented by the intermediate representation; According to the preset instruction encoding rules of the test equipment, the binary identifier is set in the first field of the preset instruction, the intermediate representation information is converted into binary parameters, and the binary parameters are set in the second field of the preset instruction to generate a binary intermediate representation; Based on the first field, the second field, and the reserved field, a binary instruction sequence that the test equipment can parse and execute is formed according to the preset instruction encoding rules.
[0008] Optionally, the test device includes an FPGA chip, and the binary intermediate representation is 64 bits in size, including a first field for storing the binary identifier, a second field for storing the binary parameters, and the reserved field.
[0009] Optionally, converting the intermediate representation information into binary parameters includes: If the intermediate representation information is a relative address jump, convert the intermediate representation information into binary parameters for an absolute physical address jump.
[0010] Optionally, transmitting the binary instruction sequence to the test device includes: Based on the program sequence of the test script for the storage device, multiple binary instruction sequences generated are set as a binary instruction stream, and the binary instruction stream is transmitted to the test device.
[0011] This application also discloses a storage device testing method based on a custom industrial language, including: The test terminal receives a binary instruction sequence, which is a storage device test script written in an industrial language obtained by the test terminal. The intermediate representation and intermediate representation information are extracted from the industrial language program of the storage device test script and generated based on the intermediate representation and intermediate representation information. The received binary instruction sequence is parsed and executed to perform storage device testing.
[0012] Another test terminal of this application includes: The industrial language module is used to obtain test scripts for storage devices written in industrial languages; The information extraction module is used to extract intermediate representations and intermediate representation information from the industrial language program of the test script of the storage device; The test control module is used to generate a binary instruction sequence based on the intermediate representation and intermediate representation information, and transmit the binary instruction sequence to the test device so that the test device performs storage device testing according to the binary instruction sequence.
[0013] Another aspect of this application is a testing device, comprising: The information receiving module is used to receive a binary instruction sequence transmitted by the test terminal. The binary instruction sequence is a storage device test script written in an industrial language obtained by the test terminal. The intermediate representation and intermediate representation information are extracted from the industrial language program of the storage device test script and generated based on the intermediate representation and intermediate representation information. The device testing module is used to parse and execute the received binary instruction sequence to perform storage device testing.
[0014] As can be seen from the above technical solution, the storage device testing method based on a custom industrial language obtains the industrial language test script, extracts the intermediate representation and information, and finally generates a binary instruction sequence which is transmitted to the test device for execution. Replacing static vectors with binary instructions results in a significantly smaller instruction size compared to traditional patterns, directly reducing the storage pressure on the test device. The intermediate representation can be quickly mapped to executable instructions without the need for full vector generation and transmission, shortening loading time and improving test program scheduling efficiency. Binary instructions support logical execution such as loops and jumps, eliminating the need for point-by-point vector expansion, shortening the test execution path, and thus improving overall test efficiency. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is one of the flowcharts of the storage device testing method based on a custom industrial language in the embodiments of this application; Figure 2 This is a flowchart of the storage device testing method S200 based on a custom industrial language in an embodiment of this application; Figure 3 This is a flowchart of the storage device testing method S300 based on a custom industrial language in an embodiment of this application; Figure 4 This is the second flowchart of the storage device testing method based on a custom industrial language in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the test terminal in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the test equipment in the embodiments of this application; Figure 7 A schematic diagram of the structure of a computer device suitable for implementing the methods of the embodiments of this application is provided for the purposes of this application. Detailed Implementation
[0017] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not limiting, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without such specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.
[0018] In this embodiment, traditional testing schemes for semiconductor memory typically use static vector pattern files to drive the test process. Taking semiconductor memory chip testing as an example, in related technologies, when performing read / write tests on a 256MB flash memory chip, a complete vector pattern file needs to be pre-constructed. This vector pattern file needs to generate corresponding test vectors one by one according to the chip's memory address. Each memory cell corresponds to a set of vector data containing address signals, control signals, data signals, and comparison signals. The test equipment needs to load all vector data into the on-chip memory cell of the FPGA chip. The FPGA chip outputs signals to the memory chip under test sequentially according to the vector sequence, while simultaneously acquiring feedback signals and performing comparison operations. When the capacity of the chip under test increases to 1GB or more, the size of the vector pattern file will increase accordingly. The on-chip storage resources of the FPGA chip cannot meet the storage requirements of the vector data, and external storage cells are needed to expand the capacity. When the test process is adjusted, the complete vector pattern file needs to be regenerated and reloaded, which reduces the scheduling speed of the test program and increases the overall test time. Traditional vector pattern files contain only fixed signal sequences and lack program control logic. They cannot perform operations such as loop execution, conditional jumps, and dynamic address generation. Complex test algorithms require the expansion of a large amount of vector data to be implemented.
[0019] To address at least one of the problems existing in the prior art, this embodiment discloses a storage device testing method based on a custom industrial language, such as... Figure 1 As shown, the method includes: S100: Obtain the storage device test script written in an industrial language.
[0020] S200: Extract the intermediate representation and intermediate representation information from the industrial language program of the storage device test script.
[0021] S300: Generate a binary instruction sequence based on the intermediate representation and intermediate representation information, and transmit the binary instruction sequence to the test device so that the test device performs storage device testing according to the binary instruction sequence.
[0022] In this embodiment of the application, the storage device testing method based on a custom industrial language first obtains a test script. The test script is written in a custom industrial language. The custom industrial language is a special language designed to adapt to the storage device testing scenario and can express the control logic and operation instructions in the testing process.
[0023] The storage device test script contains all the operation instructions and flow control statements required for storage device testing. Operation instructions include address operation instructions, data read / write instructions, signal sampling instructions, and result comparison instructions. Flow control statements include loop statements, jump statements, and conditional execution statements. The storage device test script can be obtained by the user inputting script content through an editing interface, or by reading a pre-written script file from the storage unit.
[0024] Specifically, after obtaining the storage device test script written in the industrial language, the intermediate representation extraction step is performed to extract the intermediate representation and its information from the industrial language program of the storage device test script. The intermediate representation retains all the logical relationships and operational information in the test script. The intermediate representation information consists of parameter information used in conjunction with the intermediate representation, including variable values, address information, parameters corresponding to identifiers, and specific values after macro definition expansion. The intermediate representation and its information correspond to each other, together forming the logical expression of the test script, which differs from the flat expression of the traditional vector mode.
[0025] After extracting the intermediate representation and its information, a binary instruction sequence can be generated based on the intermediate representation and its information. The binary instruction sequence is an instruction form that the test equipment (e.g., an FPGA test chip) can directly parse and execute. Each binary instruction corresponds to a specific operation or control action in the test process. A large number of generated binary instruction sequences are transmitted to the test equipment. After receiving the binary instruction sequences, the test equipment parses and executes each instruction sequentially according to the order of the instruction sequence, completing the test process for the storage device. When the test equipment executes test operations according to the binary instruction sequence, it outputs corresponding test signals to the storage device under test according to the control and parameter information in the instructions, collects the feedback signals from the storage device under test, and performs result judgment operations. This application replaces static vectors with binary instructions, resulting in a much smaller instruction size than traditional patterns, directly reducing the storage pressure on the test equipment. The intermediate representation can be quickly mapped to executable instructions without the need for full vector generation and transmission, shortening loading time and improving test program scheduling efficiency. Binary instructions support logical execution such as loops and jumps, eliminating the need for point-by-point vector expansion, shortening the test execution path, and thus improving overall test efficiency.
[0026] In alternative implementations, such as Figure 2 As shown, step S200, which extracts the intermediate representation from the industrial language program of the storage device test script, includes: S210: Perform lexical and syntactic analysis on the test script of the storage device to generate an abstract syntax tree.
[0027] S220: Perform semantic analysis on the abstract syntax tree to determine the logical nodes in the abstract syntax tree used for test program control.
[0028] S230: Generate a corresponding intermediate representation based on each of the logical nodes.
[0029] In this embodiment, the storage device test script is first subjected to lexical and syntactic analysis. Lexical analysis converts the character stream in the script into a sequence of word symbols, identifying basic units such as keywords, identifiers, constants, and operators in the script. Syntactic analysis, based on preset grammar rules, combines the sequence of word symbols into a grammatical structure, determines whether the script conforms to the grammatical specifications of the custom industrial language, and generates an abstract syntax tree.
[0030] The Abstract Syntax Tree (ABST) is a tree-structured data representation where each node corresponds to a syntactic unit in the script, and the connections between nodes correspond to the syntactic logic relationships within the script, providing a clear visual representation of the script's overall structure. Node types in the ABST include instruction nodes, loop nodes, conditional nodes, jump nodes, and operation nodes, with each type corresponding to a different syntactic function.
[0031] It should be noted that after the abstract syntax tree (API) is generated, semantic analysis is performed on it. Semantic analysis verifies the semantic validity of each node in the API and determines the logical nodes used for test program control. This semantic analysis includes variable definition checks, parameter type matching checks, address range validity checks, loop structure integrity checks, and jump target validity checks. The logical nodes used for test program control are those in the API that perform flow control functions, including loop control nodes, conditional branch nodes, unconditional jump nodes, and subroutine call nodes.
[0032] After identifying logical nodes, a corresponding intermediate representation is generated for each logical node. For example, the intermediate representations for NOP and IDXI retain the control functions and associated parameters of the logical node. For instance, when a loop execution node exists in the abstract syntax tree, semantic analysis determines that this node is the logical node controlled by the test program. Based on this loop execution node, an intermediate representation containing the loop count, the start position of the loop body, and the end position of the loop body is generated. The intermediate representation records all information about the loop control in a structured form, eliminating the need to expand the loop body into a repetitive sequence of operations, thus reducing the data volume of the intermediate representation.
[0033] In an optional implementation, extracting intermediate representation information from the industrial language program of the storage device test script includes: Extract macro definitions and identifiers from the industrial language program of the test script for the storage device; The intermediate representation information is obtained by determining the macro definitions and parameter values of identifiers in the industrial language program associated with the intermediate representation.
[0034] In this embodiment, the process of extracting intermediate representation information from the industrial language program of the storage device test script first extracts macro definitions and identifiers from the industrial language program of the storage device test script. Macro definitions are predefined constants or substitution rules in the script, used to simplify the script writing process and improve script reusability. Identifiers are symbols used in the script to represent objects such as variables, registers, control signals, and address ranges; each identifier corresponds to a specific test resource or test parameter. When extracting macro definitions, statements in the script identified by macro definition keywords are identified, and the names of the macro definitions and their corresponding substitution contents are obtained. When extracting identifiers, all syntactic units in the script are traversed, user-defined identifiers and system-preset identifiers are identified, and the names and occurrence positions of the identifiers are recorded.
[0035] Specifically, after extracting macro definitions and identifiers, the parameter values of macro definitions and identifiers in the industrial language program related to the intermediate representation are determined to obtain the intermediate representation information. When determining parameter values, all generated intermediate representations are traversed, and the macro definitions and identifiers referenced in the intermediate representations are identified. Macro definitions are expanded into their corresponding specific numerical values, and identifiers are replaced with their corresponding actual parameters. The intermediate representation information includes numerical parameters, address parameters, and control parameters. Numerical parameters are the specific data in the test operation, address parameters are the memory unit addresses corresponding to the test operation, and control parameters are the execution status control parameters of the test equipment.
[0036] For example, a storage device test script may contain macro definition statements, defining specific values as macro names. When the intermediate representation references this macro name, the macro name is replaced with the specific value corresponding to the macro definition, and this value constitutes the intermediate representation information. When the intermediate representation references an identifier representing a register, the register number corresponding to that identifier is determined, and the register number is used as a component of the intermediate representation information.
[0037] In this embodiment, the process of generating a binary instruction sequence based on the intermediate representation and intermediate representation information is executed according to preset rules to ensure that the generated binary instruction sequence can be correctly parsed by the test device. For example... Figure 3 As shown, step S300, which generates a binary instruction sequence based on the intermediate representation and the intermediate representation information, includes: S310: Generate a corresponding binary identifier based on the control type represented by the intermediate representation; S320: According to the preset instruction encoding rules of the test equipment, the binary identifier is set in the first field of the preset instruction, the intermediate representation information is converted into binary parameters, and the binary parameters are set in the second field of the preset instruction to generate a binary intermediate representation; S330: Based on the first field, the second field, and the reserved field, a binary instruction sequence that the test device can parse and execute is formed according to the preset instruction encoding rules.
[0038] Specifically, the process begins by generating a corresponding binary identifier based on the control type represented by the intermediate representation. These control types include address generation control, data read / write control, flow jump control, and result comparison control. Different control types correspond to different binary identifiers, which serve as codes to distinguish instruction functions. The testing equipment determines the execution function of the instruction by recognizing the binary identifier. The correspondence between control types and binary identifiers is pre-defined and stored in the instruction generation module. When generating binary identifiers, the target code can be obtained by querying the correspondence table.
[0039] It should be noted that after generating the binary identifier, it is set in the first field of the preset instruction according to the preset instruction encoding rules of the test equipment. The preset instruction encoding rules are the instruction format rules that the test equipment hardware can recognize, specifying the position, length, and function of each field in the instruction. The first field is the field in the instruction used to identify the function type. At the same time, the intermediate representation information is converted into binary parameters. The intermediate representation information exists in the form of numerical values, addresses, identifiers, etc., and needs to be converted into binary format to adapt to the encoding requirements of the instruction.
[0040] The binary parameters are the binary codes corresponding to the intermediate representation information, containing operands, address values, counter values, jump offsets, etc., used to assist in the execution of instructions. The binary parameters are set in the second field of the preset instruction. The second field is used to store execution parameters in the instruction, working in conjunction with the first field to express the instruction's function. After setting the first and second fields, a binary intermediate representation is generated. The binary intermediate representation is the core component of the instruction, containing all execution information. Specifically, based on the first field, the second field, and reserved fields, a binary instruction sequence that the test equipment can parse and execute is formed according to preset instruction encoding rules. Reserved fields are preset fields in the instruction, used to meet hardware format requirements. The values of reserved fields are set according to preset rules. For example, a reserved segment is PC, used to indicate the binary instruction sequence, with a length of one byte. Its preset setting rule is to increment by 1 sequentially according to the order of the binary instruction sequence in the entire binary instruction stream formed by all binary instruction sequences.
[0041] In an optional implementation, the test device includes an FPGA chip, and the binary intermediate representation is 64 bits in size, including a first field for storing the binary identifier, a second field for storing the binary parameters, and the reserved field.
[0042] Each binary instruction sequence independently completes an operation, while multiple instruction sequences cooperate to complete the entire test process. For example, when the intermediate representation is a data read control type, a corresponding data read binary identifier is generated, placed in the first field, and the binary parameters corresponding to the read address are placed in the second field. Combined with the reserved field, a data read binary instruction is formed. In this embodiment, the test equipment includes an FPGA chip, which is a field-programmable gate array device capable of outputting, acquiring, and comparing test signals through hardware programming, adapting to the high-speed execution requirements of storage device testing. The size of the binary intermediate representation is set to 64 bits. The 64-bit length can meet the encoding requirements of various instructions in storage device testing, while also adapting to the data processing bit width of the FPGA chip, improving the efficiency of instruction parsing and execution. The 64-bit binary intermediate representation includes multiple fields: a first field for storing the binary identifier, a second field for storing the binary parameters, and a reserved field. The first and second fields are divided into 64-bit spaces according to a preset bit allocation rule, and the number of bits in each field is fixed to ensure the uniformity of the instruction format. For example, the first field allocates 8 bits to store binary identifiers, supporting 256 different instruction control types to meet the needs of various operations in storage device testing. The second field allocates 56 bits to store binary parameters, supporting large-capacity address and numerical representations to adapt to the testing requirements of large-capacity storage devices. Those skilled in the art will understand that the 64-bit instruction length and field allocation ratio can be adjusted according to the hardware architecture of the testing equipment and testing requirements; adjusting the number of field bits does not affect the core logic of instruction generation and execution.
[0043] For example, in a specific case, the intermediate representation can be generated based on Table 1, which indicates that the corresponding binary identification sequence can be generated.
[0044] Table 1
[0045] As shown in Table 1, Byte_0 is the first field, and the desired fields from Byte_1 to Byte_7 can be selected as the second field, with the other fields reserved. According to Table 1, the NOP instruction will be compiled as 0x0000000000000000CMD as the current value, and the IDXI8 instruction will be compiled as 0x0000000000008023 CMD as the current value.
[0046] For industrial language test script T1: HPATTestSDEFCS=C1SDEFSCLK=C2SDEFSER_INC=C10SDEFSER_CLR=C11SDEFSER_JMP=C12STARTREAD_DATANOPLRD00:NOPCSSER_CLRIDXI830CS SCLKWSER_INCNOPCSSCLKR SER_INCNOPCSSCLKR SER_INCJNI2.-1CS SCLKRSER_JMPNOPNOPJNI3LRD00NOPSTPSEND Where SDEF is a macro definition. SDEF CS = C1 indicates that CS identifies the C0 register, where C0~C31 are control flag bits, represented by a 32-bit data segment, where each bit represents a Cn register. See the example above: NOP CS SER_CLR CS and SER_CLR represent the selection of registers C1 and C11 respectively, with a FLAG value of 0x00000802.
[0047] When forming a binary instruction sequence that the test device can parse and execute based on the first field, the second field, and the reserved fields according to a preset instruction encoding rule, the binary instruction sequence can be formed based on the first field, the second field, and the reserved fields. For example, as shown in Table 2, the first field is Cmd, the second field is Param, and the reserved fields include CURRENT PC, Mode, Flag, and Reserve. These fields are set according to the binary instruction format that the FPGA can parse to form the binary instruction sequence. For example, the binary instruction format that the FPGA can execute may include the fields shown in Table 2, totaling 16 bytes.
[0048] Table 2
[0049] For example, for T1 above, a binary instruction sequence can be obtained, where the Reserve field is not shown: NOP command line PC: 0 Mode: 0 Cmd: 0x00 Param: 00-00-00-00-00-00-00 Flag: 00-00-00-00 LRD00:NOPCSSER_CLR PC: 1 Mode: 0 Cmd: 0x00 Param: 00-00-00-00-00-00-00 Flag: 02-08-00-00 IDXI830CS SCLKWSER_INC PC: 2 Mode: 0 Cmd: 0x23 Param: 80-00-00-1E-00-00-00 Flag: 06-04-00-00 NOPCSSCLKR SER_INC PC: 3 Mode: 0 Cmd: 0x00 Param: 00-00-00-00-00-00-00 Flag: 06-04-00-00 NOPCSSCLKR SER_INC PC: 4 Mode: 0 Cmd: 0x00 Param: 00-00-00-00-00-00-00 Flag: 06-04-00-00 JNI2.-1CS SCLKRSER_JMP PC: 5 Mode: 0 Cmd: 0x12 Param: 02-00-00-04-00-00-00 Flag: 06-10-00-00 NOP PC: 6 Mode: 0 Cmd: 0x00 Param: 00-00-00-00-00-00-00 Flag: 00-00-00-00 NOP PC: 7 Mode: 0 Cmd: 0x00 Param: 00-00-00-00-00-00-00 Flag: 00-00-00-00 JNI3LRD00 PC: 8 Mode: 0 Cmd: 0x12 Param: 04-00-00-01-00-00-00 Flag: 00-00-00-00 NOP PC: 9 Mode: 0 Cmd: 0x00 Param: 00-00-00-00-00-00-00 Flag: 00-00-00-00 STPS PC: 10 Mode: 0 Cmd: 0x03 Param: 00-00-00-00-00-00-00 Flag: 00-00-00-00 In this embodiment of the application, S320 converting the intermediate representation information into binary parameters includes: S321: If the intermediate representation information is a relative address jump, convert the intermediate representation information into binary parameters for an absolute physical address jump.
[0050] Specifically, FPGAs support absolute address jumps but not relative address jumps, leading to the need for large amounts of test data in the form of test vectors in existing technologies. This application converts the intermediate representation of a binary instruction sequence into binary parameters for an absolute physical address jump when the intermediate representation information is a relative address jump. Absolute physical address jumps are based on the instruction storage start position of the test device, using a complete physical address to represent the jump target location. The test device hardware only supports absolute physical address parsing. Specifically, during the conversion process, the absolute physical address of the current instruction is calculated or obtained, and the offset value for the relative address jump is obtained. The absolute physical address of the current instruction and the offset value are then calculated to obtain the absolute physical address of the jump target. The calculation rule is to add the offset value to the absolute physical address of the current instruction to obtain the absolute physical address of the target location. A positive offset value indicates a backward jump, and a negative offset value indicates a forward jump. The calculated absolute physical address is converted into binary format to form the binary parameters for the absolute physical address jump, which are then used to fill the second field of the instruction. By converting relative addresses to absolute physical addresses, jump statements in the script can be correctly recognized and executed by the test device, maintaining the flexibility of script writing and compatibility with hardware execution.
[0051] For example, the industrial language JNI2.-1CS SCLKRSER_JMP, after being compiled into a binary instruction sequence, is: PC: 5 Mode: 0 Cmd: 0x12 Param: 02-00-00-04-00-00-00 Flag: 06-10-00-00. Here, the relative address jump of -1 needs to be converted into the absolute address jump of "04" during the compilation process to point to the binary instruction sequence of "PC: 4" to achieve loop execution.
[0052] In an optional implementation, step S300, which transmits the binary instruction sequence to the test device, includes: S340: Based on the program sequence of the test script for the storage device, the generated multiple binary instruction sequences are set as a binary instruction stream, and the binary instruction stream is transmitted to the test device.
[0053] In this embodiment, the process of transmitting the binary instruction sequence to the test device is executed in program order, ensuring that the logical order of instruction execution is consistent with the script. Based on the program order of the test script on the storage device, the generated multiple binary instruction sequences are set as a binary instruction stream. The program order is the order in which the statements in the script are written, corresponding to the execution order of the test process. The binary instruction stream is continuously transmitted binary data, with multiple binary instructions arranged sequentially according to the execution order, forming an uninterrupted data stream and improving data transmission efficiency. The format of the instruction stream is adapted to the transmission interface between the test device and the instruction generation module. The transmission interface can be a high-speed serial interface, a parallel interface, an Ethernet interface, etc.
[0054] Specifically, after forming the binary instruction stream, it is transmitted to the test equipment. For example, the binary instruction stream is transmitted to the FPGA test equipment in the form of a binary file (.bin). The interface module of the test equipment receives the binary instruction stream and stores it in the instruction storage unit. The execution module of the test equipment reads the binary instructions sequentially from the instruction storage unit, parses the instruction function and execution parameters according to the field information in the instructions, and completes the corresponding test operation. During the transmission, the binary instruction stream maintains the complete instruction order and content, without changing the logical relationship between instructions, ensuring that the test process is executed according to the logic designed in the script.
[0055] Based on the same principle, this application also discloses a storage device testing method based on a custom industrial language, which can be used to test devices, such as... Figure 4 As shown, the method includes: S400: Receives a binary instruction sequence transmitted by the test terminal. The binary instruction sequence is generated by the test terminal obtaining a storage device test script written in an industrial language, extracting intermediate representation and intermediate representation information from the industrial language program of the storage device test script, and generating the instruction sequence based on the intermediate representation and intermediate representation information. S500: Parse and execute the received binary instruction sequence to perform storage device testing.
[0056] Since the principle behind this method for solving the problem is similar to that of the methods and apparatus described above, the implementation of this system can be found in the implementation of the methods and apparatus, and will not be repeated here.
[0057] Based on the same principle, this application also discloses a test terminal, such as... Figure 5 As shown, the terminal includes: Industrial language module 11 is used to obtain storage device test scripts written in industrial language; Information extraction module 12 is used to extract intermediate representation and intermediate representation information from the industrial language program of the test script of the storage device; The test control module 13 is used to generate a binary instruction sequence based on the intermediate representation and intermediate representation information, and transmit the binary instruction sequence to the test device so that the test device performs storage device testing according to the binary instruction sequence.
[0058] Since the principle by which this terminal solves the problem is similar to the methods and devices described above, the implementation of this terminal can be found in the implementation of the methods and devices, and will not be repeated here.
[0059] Based on the same principle, this application also discloses a testing device, such as... Figure 6 As shown, the device includes: Information receiving module 21 is used to receive a binary instruction sequence transmitted by the test terminal. The binary instruction sequence is generated based on the intermediate representation and intermediate representation information obtained by the test terminal from the industrial language program of the storage device test script. The device testing module 22 is used to parse and execute the received binary instruction sequence to perform storage device testing.
[0060] Since the principle by which this device solves the problem is similar to the methods and apparatus described above, the implementation of this device can be found in the implementation of the methods and apparatus, and will not be repeated here.
[0061] This application uses specific embodiments to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the methods and ideas of this application. At the same time, for those skilled in the art, there may be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
[0062] This application also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described method.
[0063] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.
[0064] Those skilled in the art will understand that the embodiments of this application can be provided as methods, systems, or computer programs, producing the systems, apparatuses, modules, or units described in the above embodiments. Specifically, they can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer device; specifically, a computer device can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.
[0065] In a typical example, the computer device specifically includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the method executed by the client as described above, or the method executed by the server as described above.
[0066] The following is for reference. Figure 7 It shows a schematic diagram of the structure of a computer device 600 suitable for implementing the embodiments of this application.
[0067] like Figure 7 As shown, the computer device 600 includes a central processing unit (CPU) 601, which can perform various appropriate tasks and processes according to programs stored in read-only memory (ROM) 602 or programs loaded from storage section 608 into random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the computer device 600. The CPU 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.
[0068] The following components are connected to I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to I / O interface 605 as needed. Removable media 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 610 as needed so that computer programs read from them can be installed as needed in storage section 608.
[0069] In particular, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program including program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 609, and / or installed from removable medium 611.
[0070] Computer-readable media include both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.
[0071] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.
[0072] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0073] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0074] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0075] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0076] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0077] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.
[0078] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.
[0079] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
Claims
1. A storage device testing method based on a custom industrial language, characterized in that, include: Obtain test scripts for storage devices written in industrial languages; Intermediate representations and intermediate representation information are extracted from the industrial language program of the storage device test script; A binary instruction sequence is generated based on the intermediate representation and intermediate representation information, and the binary instruction sequence is transmitted to the test device so that the test device can perform storage device testing according to the binary instruction sequence.
2. The storage device testing method based on a custom industrial language according to claim 1, characterized in that, The intermediate representation extracted from the industrial language program of the storage device test script includes: Lexical and syntactic analysis are performed on the test script of the storage device to generate an abstract syntax tree; Semantic analysis is performed on the abstract syntax tree to determine the logical nodes in the abstract syntax tree used for test program control; A corresponding intermediate representation is generated based on each of the logical nodes.
3. The storage device testing method based on a custom industrial language according to claim 1, characterized in that, The intermediate representation information extracted from the industrial language program of the storage device test script includes: Extract macro definitions and identifiers from the industrial language program of the test script for the storage device; The intermediate representation information is obtained by determining the macro definitions and parameter values of identifiers in the industrial language program associated with the intermediate representation.
4. The storage device testing method based on a custom industrial language according to claim 1, characterized in that, The step of generating a binary instruction sequence based on the intermediate representation and the intermediate representation information includes: Generate a corresponding binary identifier based on the control type represented by the intermediate representation; According to the preset instruction encoding rules of the test equipment, the binary identifier is set in the first field of the preset instruction, the intermediate representation information is converted into binary parameters, and the binary parameters are set in the second field of the preset instruction to generate a binary intermediate representation; Based on the first field, the second field, and the reserved field, a binary instruction sequence that the test equipment can parse and execute is formed according to the preset instruction encoding rules.
5. The storage device testing method based on a custom industrial language according to claim 4, characterized in that, The test equipment includes an FPGA chip, the binary intermediate representation is 64 bits in size, and the binary instruction sequence includes a first field for storing the binary identifier, a second field for storing the binary parameters, and a reserved field.
6. The storage device testing method based on a custom industrial language according to claim 4, characterized in that, The step of converting the intermediate representation information into binary parameters includes: If the intermediate representation information is a relative address jump, convert the intermediate representation information into binary parameters for an absolute physical address jump.
7. The storage device testing method based on a custom industrial language according to claim 4, characterized in that, The step of transmitting the binary instruction sequence to the test device includes: Based on the program sequence of the test script for the storage device, multiple binary instruction sequences generated are set as a binary instruction stream, and the binary instruction stream is transmitted to the test device.
8. A storage device testing method based on a custom industrial language, characterized in that, include: The test terminal receives a binary instruction sequence, which is a storage device test script written in an industrial language obtained by the test terminal. The intermediate representation and intermediate representation information are extracted from the industrial language program of the storage device test script and generated based on the intermediate representation and intermediate representation information. The received binary instruction sequence is parsed and executed to perform storage device testing.
9. A test terminal, characterized in that, include: The industrial language module is used to obtain test scripts for storage devices written in industrial languages; The information extraction module is used to extract intermediate representations and intermediate representation information from the industrial language program of the test script of the storage device; The test control module is used to generate a binary instruction sequence based on the intermediate representation and intermediate representation information, and transmit the binary instruction sequence to the test device so that the test device performs storage device testing according to the binary instruction sequence.
10. A testing device, characterized in that, include: The information receiving module is used to receive a binary instruction sequence transmitted by the test terminal. The binary instruction sequence is a storage device test script written in an industrial language obtained by the test terminal. The intermediate representation and intermediate representation information are extracted from the industrial language program of the storage device test script and generated based on the intermediate representation and intermediate representation information. The device testing module is used to parse and execute the received binary instruction sequence to perform storage device testing.