DDR5 memory chip automatic screening method, device and medium

Abstract

The present application relates to the technical field of semiconductor memory testing, and discloses a DDR5 memory chip automatic screening method, equipment and medium, the present application obtains the read-write-keep record formed by the DDR5 memory chip under the initial keep window, divides the storage segment according to the line page address and bank address bearing relationship, and gathers the keep response generation path response candidate area;According to the prequel keep response, the induced keep timing is generated and the read-write-keep retest is executed, and the delay flip induced record is obtained;The ECS intervention record formed during the retest is obtained, the ECS intervention moment is matched with the induced keep window end moment and the first external read-back moment, the clear pollution boundary state is generated;Then, the clear pollution boundary record is generated, the equivalent induced retest is executed for the same storage segment, the storage segment screening state is generated, and the DDR5 memory chip screening level is output.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory testing technology, specifically to an automated screening method, equipment, and medium for DDR5 memory chips. Background Technology

[0002] DDR5 memory chips are typically used in applications with high requirements for continuous operation, such as servers, database devices, artificial intelligence computing platforms, and industrial control equipment. After chip packaging, the production end generally uses automated screening equipment to perform write, hold, and readback tests on the memory array, and classifies them based on the results of re-screening after high-temperature aging. Taking server memory chip screening as an example, after high-temperature holding, the chip enters the cooling retesting stage. The data pattern written in the previous round may cause adjacent memory cells to form different charge coupling states. Subsequently, when experiencing refresh interval changes and reverse pattern writing, some critical memory cells show a decrease in hold capability. Such memory cells can usually still read back the correct data within a fixed hold window. However, in real operation, changes in server load cycles, sleep wake-up, and long-term high-density access will repeatedly change the thermal state and write history of the chip, making it easier for it to change from a testable state to a state that is easy to flip.

[0003] Existing DDR5 memory chip screening technologies typically identify memory cells with insufficient retention capabilities by adjusting hold time, test temperature, and write patterns. They also incorporate on-chip error correction status or error checking and flushing information to assist in assessing chip reliability. These technologies can cover many explicit retention failure scenarios. However, in screening for thermally induced weak memory cells, the screening evidence may not be entirely consistent with the original memory state. Specifically, on-chip error correction may correct errors caused by weak memory cells before data output, ensuring that the readback results seen by external testing equipment are still correct; the error checking and flushing process may also complete error checking internally within the chip. Correction and write-back alter the error context upon which subsequent retests rely. Consequently, when the hot path and pattern history have already induced weak bit risks, the testing equipment relies solely on external read-back results, error counts, or retest results after clearing. This makes it difficult to distinguish between different states, such as the memory cell itself being stable, the weak bit being corrected by on-chip error correction, and the error context being temporarily restored after clearing. Therefore, the automated screening of DDR5 memory chips still requires a reliable screening mechanism that can correlate the hot path induction process, pattern history, on-chip error correction consumption, clearing intervention time, and retest recovery state to improve the reliability of identifying delay-flipping weak memory cells. Summary of the Invention

[0004] To achieve the above objectives, the present invention provides the following technical solution: An automated screening method for DDR5 memory chips includes the following steps: The read / write hold records formed by the DDR5 memory chip under the initial hold window are obtained. The memory is divided into segments according to the row and page address and bank address concatenation relationship of the DDR5 memory array. The hold responses in the read / write hold records are aggregated according to the memory segments to generate path response candidate areas. Obtain the preceding hold responses of the path response candidate region, process the preceding hold responses using the preceding response succession method, generate the induced hold sequence, and perform read-write hold retest on the path response candidate region according to the induced hold sequence to generate delayed flip induced records. Acquire the ECS intervention record generated during the read-write-hold retest execution, match the ECS intervention time in the ECS intervention record with the end time of the hold window in the induced hold time sequence and the first external readback time to generate the clean contamination boundary state; According to the state of the cleanup contamination boundary, the delayed flip-induced record is split into the pre-boundary induced record segment and the post-boundary retest record segment to generate the cleanup boundary record. Based on the cleanup boundary record, an equivalent induced retest path is generated for the same storage segment and the retest is performed to generate the storage segment screening state. Then, according to the distribution of the storage segment screening state in the DDR5 storage array, the DDR5 memory chip screening level is output.

[0005] Furthermore, generating a path response candidate area includes: obtaining read-write holding records formed within the same initial holding window, assigning the logical addresses in the read-write holding records to the row page addresses and bank addresses of the DDR5 storage array, and forming storage segments within the same bank according to the address range of consecutive and repeatedly accessible rows and pages; Read-write hold records that fail to uniquely connect to the row page address and the bank address are marked as address accept confirmations and are excluded from the path response candidate area generation; hold responses in read-write hold records are aggregated by storage segment, ECS count changes that can uniquely connect to the storage segment are incorporated into the preceding hold response of the corresponding storage segment, and ECS count changes that fail to uniquely connect to the storage segment are written to the chip-level ECS prompt record; Multiple hold responses within the same storage segment are accumulated. Hold responses that are not reproduced in subsequent read / write hold records of the same storage segment and are not reproduced in adjacent storage segments are downweighted to form hold response strength. Hold response strength, address acceptance trust status, and reproduction status of adjacent storage segments are used as candidate admission conditions. Storage segments that meet the candidate admission conditions are written into the path response candidate area.

[0006] Furthermore, generating the induced hold sequence includes: reading the preceding hold responses corresponding to each storage segment in the candidate area of ​​the read path response; within the storage segment uniquely connected to the row page address and bank address, sorting the hold edge response, pattern acceptance response, and thermal hysteresis response in the preceding hold responses; during sorting, first excluding responses whose corresponding readback change amplitude does not exceed the error range of the test equipment, and then sorting them from high to low according to the number of recurrences within the same storage segment; when the pattern acceptance response is uniquely located at the top of the sort, the pattern reversal induced path is determined; when the hold... When the edge response is uniquely located at the top of the sort order, the edge-induced path is determined. When the thermal hysteresis response is uniquely located at the top of the sort order, and the thermal hysteresis response is formed by the same memory segment, the same write pattern, and the same hold window configuration, the thermal path-induced path is determined. The induced hold timing is generated according to the determined induced path configuration of the write pattern, induced hold window, and readback time. The ECS count change of the preceding hold response is retained along with the induced hold timing and does not participate in the determination of the induced path. If a unique top-ranking response is not formed, the induced hold timing is not generated.

[0007] Furthermore, generating a delayed flip-over trigger record includes: performing read-write hold retests on the same storage segment according to the triggered hold sequence; in the same retest round, comparing the immediate verification readback result of the last write pattern before hold with the first external readback result after hold; when the immediate verification readback result is consistent with the last write pattern, but the first external readback result after hold is inconsistent with the last write pattern, the corresponding retest round is recorded as a delayed flip-over trigger event, and a delayed flip-over trigger record is generated based on the delayed flip-over trigger events of the same storage segment; when at least one of the following occurs—the immediate verification readback result is inconsistent with the last write pattern, the address access order cannot be reproduced, the triggered hold window execution is interrupted, or the first external readback after hold is missing—the corresponding retest round is not written into the delayed flip-over trigger record.

[0008] Furthermore, the process of generating a cleanup contamination boundary state includes: establishing a cleanup judgment interval before external readback, starting from the actual end time of the inducing hold window and ending at the actual time of the first external readback after hold; acquiring ECS ​​intervention records generated during the read-write hold retest, and comparing the ECS count reading results before and after the start and end points of the cleanup judgment interval before external readback to form ECS count changes; verifying the connection between the ECS statistical range and the storage segment address range in the delay flip inducing record, using the same storage segment and the same retest round as objects; when the ECS statistical range can uniquely connect to the corresponding storage segment address range, timing matching is performed using the corresponding ECS ​​intervention record; when the ECS statistical range cannot uniquely connect to the corresponding storage segment address range, the corresponding storage segment is determined as a cleanup pending review state; the ECS count reading results do not participate in determining the ECS intervention time.

[0009] Furthermore, the state of the cleanup contamination boundary includes the cleanup contamination state, the cleanup credible state, and the cleanup pending verification state; Timing matching is performed on the ECS intervention time, including: when the ECS intervention time is later than the actual end time of the induced hold window but earlier than the actual time of the first external readback after hold, and the ECS count change can be uniquely attributed to the same storage segment and manifested as an increase in the ECS count, a cleanup contamination state is generated; when an ECS intervention record covering the complete period of the cleanup judgment interval before the external readback is formed, and no ECS intervention time that can be attributed to the same storage segment is formed within this interval, and no ECS count increase that can be attributed to the same storage segment is formed, a cleanup trustworthy state is generated; when neither the cleanup contamination state nor the cleanup trustworthy state judgment conditions are met, a cleanup pending review state is generated.

[0010] Furthermore, generating cleanup boundary records includes: using the same storage segment and the same retest round as objects, mapping delayed flip-induced records to cleanup contamination boundary states; when the cleanup contamination boundary state is a cleanup trusted state, writing the corresponding delayed flip-induced record into the pre-boundary induced record segment; when the cleanup contamination boundary state is a cleanup contamination state, writing the corresponding delayed flip-induced record into the post-boundary retest record segment; and when the cleanup contamination boundary state is a cleanup pending verification state, determining the corresponding storage segment as a screening pending confirmation state. Based on the pre-boundary induced record segment, the post-boundary retest record segment, and the cleaned contamination boundary status, a clean boundary record is generated. For the same storage segment corresponding to the post-boundary retest record segment, if the storage segment address range can be uniquely accepted, the address access order can be reproduced, and the induced sustain window configuration can be executed within the current test program's allowed range, the induced path type, write pattern, address access order, and induced sustain window configuration of the corresponding retest round are used to generate an equivalent induced retest path. If at least one of the following occurs: the storage segment address range cannot be uniquely accepted, the address access order cannot be reproduced, or the induced sustain window configuration cannot be executed within the current test program's allowed range, an equivalent induced retest path is not generated.

[0011] Furthermore, the storage segmentation screening status is generated and the DDR5 memory chip screening level is output, including: after executing the equivalent induced retest path, obtaining the ECS intervention record formed during the execution of the retest round, and matching the ECS intervention time with the actual end time of the induced hold window and the actual time of the first external readback after hold for the retest round to generate the clean contamination boundary status corresponding to the retest round. When the cleanup contamination boundary state corresponding to the retest round is a cleanup trustworthy state, an equivalent retest result is generated based on the immediate verification readback result and the first external readback result after holding for that retest round. If either the induced record segment before the boundary or the equivalent retest result satisfies the delayed flip confirmation condition that the immediate verification readback result is consistent with the last write pattern before holding, and the first external readback result after holding is inconsistent with the last write pattern before holding, the corresponding storage segment is determined to be in a delayed flip confirmation state. If there are cleanup pending verification states and equivalent induced retest states in the same storage segment... If at least one of the following occurs: test path not executed, equivalent induced retest path executed but no equivalent retest result generated, the corresponding storage segment is identified as a screening pending confirmation state; based on the execution result of the induced hold timing, if the same storage segment that has executed the induced hold timing does not meet the delay flip confirmation condition and is not identified as a screening pending confirmation state, the corresponding storage segment is identified as a delay flip unconfirmed state; output the DDR5 memory chip screening level according to the distribution of delay flip confirmed state, screening pending confirmation state, and delay flip unconfirmed state in the DDR5 memory array.

[0012] Furthermore, to achieve the above objectives, the present invention also provides an automated screening device for DDR5 memory chips, including a memory and a processor; the memory stores a computer program, and when the processor executes the computer program, it implements the above-mentioned automated screening method for DDR5 memory chips.

[0013] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described automated screening method for DDR5 memory chips.

[0014] This invention provides an automated screening method, device, and medium for DDR5 memory chips, which has the following beneficial effects: 1. This invention addresses the problem that delay flip evidence in DDR5 memory chip retention testing is easily obscured by ECS flushing actions. It first attaches the read / write retention records formed under the initial retention window to the bank address and row / page address range, and then aggregates the preceding retention responses according to memory segments. This allows subsequent retesting objects to converge from the coarse-grained readback results of the entire array to path response candidate regions with retention anomalies. Based on this, this invention generates induced retention timing sequences based on retention edge responses, pattern attachment responses, and thermal hysteresis responses. This enables the retesting process to focus on the pattern history, retention edges, and thermal path conditions that may be exposed by weak memory cells, rather than simply extending the retention time for repeated screening.

[0015] 2. Furthermore, this invention performs time-series matching between the ECS intervention time during the read-write hold retest and the actual end time of the induced hold window, as well as the actual time of the first external readback after hold. It also generates a cleanup contamination boundary state by combining the ECS statistical range and ECS count changes. This distinguishes whether the first external readback result after hold is credible evidence of cleanup, evidence of cleanup contamination, or evidence to be verified. By splitting the delay flip induced record into a pre-boundary induced record segment and a post-boundary retest record segment, this invention can avoid directly using readback results affected by ECS cleanup actions as the basis for delay flip confirmation, thus improving the reliability of evidence in the DDR5 weak memory segmentation screening conclusion.

[0016] 3. Simultaneously, this invention generates equivalent induced retest paths for the retest record segments after the boundary. Within the same memory segment, the induced path type, write pattern, address access order, and induced hold window configuration are used to re-execute the retest. The equivalent retest results are only admitted when a cleanup trust state is formed in the retest round. Thus, without polluting the original path response candidate area and induced hold timing, external readback evidence that can be used to confirm delay flips is obtained again. Finally, this invention outputs chip screening levels based on the distribution of delay flip confirmed state, screened unconfirmed state, and delay flip unconfirmed state in the DDR5 memory array. This allows the chip screening results to simultaneously reflect local weak memory segments, array diffusion risks, and boundaries to be reviewed, improving the targeting and traceability of automated DDR5 memory chip screening. Attached Figure Description

[0017] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is the S4 flowchart of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1 and Figure 2 This embodiment provides an automated screening method for DDR5 memory chips, including the following specific steps: In one implementation, S1, the read-write hold records formed by the DDR5 memory chip under the initial hold window are obtained, the memory is divided into segments according to the row and page addresses and bank addresses of the DDR5 memory array, and the hold responses in the read-write hold records are aggregated according to the memory segments to generate a path response candidate area. The specific process includes the following steps.

[0020] The screening system performs an initial hold window test on the DDR5 memory chips to be screened. The initial hold window is a write-and-hold test interval configured by the chip test program. Within this test interval, the screening system writes test patterns to the DDR5 memory array, so that the memory cells maintain the data state under the conditions jointly limited by the hold temperature, hold duration and refresh configuration. After the hold window ends, an external readback is performed. The read-write hold records come from the write, hold and external readback processes within the same initial hold window, including the test time, logical address, write pattern number, external readback result, and bank address and row / page address confirmed by the address arrangement information of the chip test program or test device.

[0021] The screening system assigns the logical addresses in the read / write retention records to the row / page addresses and bank addresses of the DDR5 memory array. This assignment process is based on the address arrangement information in the chip test program, the address access order saved by the test equipment, and the repeated access results of the same address. This ensures that each read / write retention record falls into the corresponding bank address and row / page address relationship. Read / write retention records that can be uniquely assigned to the row / page address and bank address are included in the memory segmentation. Read / write retention records that cannot be uniquely assigned to the row / page address and bank address are marked as address assignments and require confirmation. The test time, logical address, and external readback results are retained as source verification records.

[0022] After establishing the address acceptance relationship, the screening system forms storage segments within the same bank based on the continuous and repeatable address ranges of rows and pages. Repeatable access means that the test device can locate the same row and page address range in the same address access order within the same initial hold window and the corresponding verification window. The storage segments are used to accept hold response aggregation and path response candidate area generation. The address range within the same storage segment remains unchanged within the same round of initial hold window. Subsequent steps involving the same storage segment's induced testing, ECS intervention verification, and equivalent induced retesting all use the storage segment division result as the basis for object acceptance. When there are cases of redundancy repair, address remapping, and test device access paths that cannot be reproduced within the same bank, the corresponding read / write hold records enter the address acceptance confirmation process.

[0023] After completing the storage segmentation, the screening system aggregates the hold responses in the read-write hold records according to the storage segment. The hold response refers to the change in the hold status of the storage cell reflected by the write, hold, and external readback processes within the initial hold window of the same storage segment. It is formed by the trend of the readback result approaching the failure boundary, the readback change under different write patterns, the readback change between the temperature rise hold and the temperature drop retest after object correspondence confirmation, and the reproduction of the hold response in adjacent storage segments under the same write pattern and the same hold window. When the above contents belong to the same storage segment, the same write pattern, and the same hold window configuration, the screening system aggregates them into the preceding hold response of that storage segment. The temperature drop retest result that does not meet the object correspondence relationship is entered into the retest pending confirmation record. When the initial hold window is not configured with temperature rise hold and temperature drop retest, the screening system does not form a thermal hysteresis type hold response, and does not write the missing item as a normal response into the preceding hold response. The preceding hold response is used to generate the induced hold timing in the next step.

[0024] When maintaining a hold response by storage segment, the filtering system synchronously processes ECS count changes. If the statistical range corresponding to the ECS count change can uniquely correspond to the address range of a certain storage segment and does not cover other storage segments, the filtering system incorporates the ECS count change into the preceding hold response of the corresponding storage segment, making it participate in the subsequent cleanup boundary review as an on-chip correction prompt. If the statistical range corresponding to the ECS count change cannot uniquely correspond to a certain storage segment, covers multiple storage segments, or the test configuration does not output a locatable ECS count change, the filtering system writes the corresponding information into the chip-level ECS prompt record. The chip-level ECS prompt record serves as an auxiliary record for the subsequent ECS cleanup contamination boundary review and does not enter the preceding hold response of a specific storage segment.

[0025] For any storage segment, the screening system first converts the hold response corresponding to the object within that storage segment into a unified evaluation caliber. Specifically, the screening system uses the total number of bits that have been read back within the same storage segment and can be uniquely accepted to the same row / page address range as the comparable bits. It compares the external readback result after hold with the last write pattern before hold bit by bit to obtain the readback inconsistency bits, and forms the external readback deviation value based on the ratio of the readback inconsistency bits to the comparable bits. For readback changes under different write patterns, the screening system compares the readback inconsistency bit distribution corresponding to different write patterns within the same storage segment and the same address range to form the pattern response change value. For thermal hysteresis response, the screening system compares the readback inconsistency bit distribution between temperature-up hold and temperature-down retest under the same storage segment, the same write pattern, and the same hold window configuration to form the thermal hysteresis response change value. When any of the following occurs: the comparable bits are zero, the readback data is missing, or the address range cannot be uniquely accepted, the screening system does not form a corresponding response value and writes the corresponding record into the candidate record to be reviewed.

[0026] The screening system generates a unified response value for the same storage segment based on external readback deviation, pattern response change, and thermal hysteresis response change. It then performs cumulative processing and weight reduction on the unified response value based on the number of times the corresponding response is reproduced within the same storage segment, the reproduction status of adjacent storage segments, and the test equipment error range. This results in a sustained response strength. The cumulative processing and weight reduction are performed using a pre-established response calibration table, which is jointly calibrated from standard samples of the same batch, historical DDR5 memory chip samples of the same model, and the test equipment error range. The response calibration table records at least the response type, the range of reproduction times, the reproduction status of adjacent storage segments, and the corresponding processing coefficient. When multiple sustained responses are reproduced within the same storage segment, the screening system increases the contribution of the corresponding response to the sustained response strength according to the response calibration table. For sustained responses that occur only once and are not reproduced in subsequent read / write sustained records or adjacent storage segments, the screening system reduces the contribution of the corresponding response to the sustained response strength according to the response calibration table, retains its source record, and does not use it as an independent basis for admission to the path response candidate area.

[0027] In a preferred implementation, the corresponding processing coefficients in the response calibration table are determined by the response distributions of stable and risky samples under the same test procedure. The screening system first calculates the upper distribution boundaries of external readback deviation, pattern response change, and thermal hysteresis response change in stable samples as the low-risk upper limit. Then, it calculates the lower distribution boundaries of response in risky samples that can form delay flip-induced events in subsequent retests as the candidate admission level. If the number of times the same response type is reproduced in the same storage segment increases, the corresponding processing coefficient is higher than the processing coefficient corresponding to a single response. If the response only occurs once and is not reproduced in adjacent storage segments, the corresponding processing coefficient is lower than the processing coefficient corresponding to the reproduced response. The response intensity is maintained by correcting the external readback deviation, pattern response change, and thermal hysteresis response change values ​​with the corresponding processing coefficients. If any response value fails to form, it is not padded with zeros to participate in the candidate admission, but is retained as a candidate record to be reviewed.

[0028] When the number of samples in the same batch is insufficient to complete the update of the response calibration table for this batch, the screening system uses the response calibration table of the historical DDR5 memory chip of the same model to perform the candidate admission for the current batch, and retains the hold-up response strength, number of recurrences and verification results formed in this batch as calibration samples for subsequent batches. Hold-up responses that have not been verified in this batch are not written into the response calibration table update chain.

[0029] The screening system generates candidate admission criteria based on the strength of the hold-up response, the address acceptance reliability, and the reproducibility of adjacent storage segments. These criteria are determined by separating stable and risky samples from the same batch of standard samples. Stable samples are used to establish a low-risk upper limit after correction for the test equipment's error range, while risky samples are used to establish candidate admission levels for latency flipping tendencies. When the address acceptance reliability is such that the segment can uniquely accept both the row / page address and the bank address, and the hold-up response strength meets the candidate admission level, the screening system writes the corresponding storage segment into the path response candidate area. If the address acceptance reliability is such that the segment can uniquely accept both the row / page address and the bank address, and the hold-up response strength does not meet the candidate admission level, but adjacent storage segments with row / page adjacency within the same bank exhibit corresponding hold-up response reproducibility, the screening system writes the corresponding storage segment into the candidate pending review record. If the address acceptance reliability cannot uniquely accept both the row / page address and the bank address, the screening system does not write the corresponding storage segment into the path response candidate area.

[0030] When there are insufficient standard samples in the same batch, the screening system uses the low-risk upper limit and candidate admission level in the historical DDR5 memory chip screening samples of the same model as the initial candidate admission conditions for the current batch, and retains the newly formed candidate records to be reviewed in the current batch for subsequent batch calibration. The hold responses that have not been reviewed in the current batch are not written into the candidate admission condition update chain, and the candidate records to be reviewed are not entered into the master induced hold timing configuration of the next step. When storage segments with verifiable row and page adjacency relationships enter the path response candidate area in the same bank, they are used as the basis for supplementary review of the neighborhood.

[0031] This step outputs the path response candidate area and the preceding hold response corresponding to each storage segment in the path response candidate area. The path response candidate area limits the retest objects in the next step, and the preceding hold response limits the configuration basis for inducing hold timing in the next step. The read and write hold records formed under the initial hold window are processed by address acceptance, storage segment division, hold response aggregation, ECS counting granularity isolation and candidate admission processing to form the path response candidate area that can be directly accepted by the next step.

[0032] In one implementation, S2, the preceding hold response of the path response candidate area is obtained, the preceding hold response is processed by the preceding hold response in the preceding hold method to generate the induced hold sequence, and the read-write hold retest is performed on the path response candidate area according to the induced hold sequence to generate the delayed flip induced record. The specific process includes the following steps.

[0033] This step takes over the path response candidate area output by S1 and the preceding hold response corresponding to each storage segment in the path response candidate area. The path response candidate area is used to limit the read-write hold retest objects in this step, and the preceding hold response is used to determine the triggering path and retest timing of each storage segment. This step uses the storage segment boundaries, bank addresses, row and page address ranges and address access order determined by S1, without re-dividing the storage segments. The candidate records to be reviewed formed in S1 do not generate the triggering hold timing of this step, but are only retained as source reference records for adjacent storage segments within the same bank.

[0034] In this embodiment, the preceding response inheritance method refers to using the storage segment boundary, bank address, row and page address range and address access order formed by S1 as the basis for selecting the trigger path, the basis for retesting timing configuration and the basis for clearing the boundary verification prompt, respectively, based on the storage segment boundary, bank address, row and page address range and address access order formed by S1. The ECS count change is only retained along with the triggering and holding timing and does not participate in the triggering path sorting.

[0035] For any storage segment in the path response candidate area, the filtering system reads the preceding hold response corresponding to the storage segment and extracts the hold edge response, pattern acceptance response, thermal hysteresis response, and ECS count changes that have been incorporated into the preceding hold response from the preceding hold response. The hold edge response comes from the trend of the readback results of the same storage segment approaching the failure boundary within the initial hold window; the pattern acceptance response comes from the readback changes of the same storage segment under different write patterns; the thermal hysteresis response comes from the readback changes between the temperature rise hold and the temperature drop retest after object correspondence confirmation; the ECS count change comes from the ECS count changes in S1 that can be uniquely accepted to the corresponding storage segment.

[0036] The screening system first checks the preceding hold response. If the storage segment corresponding to the preceding hold response cannot be uniquely attached to the row page address and bank address, the storage segment will not be included in the generation of the induced hold sequence. If the hot hysteresis response in the preceding hold response cannot be formed by the same storage segment, the same write pattern, and the same hold window configuration, the hot hysteresis response will not participate in the determination of the induced path. The ECS count changes that have been incorporated into the preceding hold response are retained along with the subsequently generated induced hold sequence, but will not participate in the determination of the induced path.

[0037] After completing the acceptance check, the screening system sorts the hold edge response, pattern acceptance response, and thermal hysteresis response within the storage segments that have been uniquely accepted to the row page address and bank address. During sorting, the hold edge response is compared with the readback deviation to the test equipment error range, while the pattern acceptance response and thermal hysteresis response are compared with the readback change to the test equipment error range. The readback deviation is formed by comparing the external readback result after hold within the same storage segment with the last written pattern before hold, bit by bit, and is expressed as the ratio of the number of inconsistent readback bits to the number of comparable bits. The readback change is formed by the difference in the distribution of inconsistent readback bits under different write pattern conditions within the same storage segment, as well as the difference in the distribution of inconsistent readback bits under the corresponding tests of temperature hold and temperature reduction retests. The comparable bits are those within the same storage segment that have completed readback and can be uniquely accepted to the same row page address. The number of bits in the range; when any of the following occurs, such as zero comparable bits, missing readback data, or address range not being uniquely accepted, the corresponding response will not be sorted. Responses exceeding the test equipment error range will be sorted from highest to lowest based on the number of recurrences within the same storage segment. Responses not exceeding the test equipment error range will not be sorted. The number of recurrences is derived from the number of times the corresponding response appears in the same storage segment under the same address access order, the same write pattern correspondence, and the same hold window configuration. The test equipment error range is derived from the calibration records formed by the same test equipment under the current test program configuration and the test results of the same batch of standard samples. The sorting result serves as the basis for determining the triggering path. The readback results after this step will not be written back to update the current round of sorting results. When no response enters the sorting, or when multiple responses entering the sorting do not form a unique first and second position, the screening system will not generate the triggering hold timing sequence for that storage segment.

[0038] The test equipment error range is preferably formed by repeated write and readback calibration under the current test program. The screening system statistically analyzes the repeated readback differences under the same address range, the same write pattern, and the same hold window configuration in the standard sample, and takes the maximum stable difference caused by the readback fluctuation of the test equipment itself as the error range. If the readback deviation or readback change does not exceed the error range, it is considered that the influence of the test equipment fluctuation cannot be ruled out, and it will not be included in the induction path sorting.

[0039] When the pattern acceptance response is uniquely located at the top of the sort, the screening system determines the pattern reversal triggering path. This path uses the write pattern that corresponds to the pattern acceptance response and has the highest reproduction number as the baseline pattern. When there are multiple write patterns with the same reproduction number and the baseline pattern cannot be uniquely determined, the screening system does not generate a pattern reversal triggering path. When the baseline pattern can be uniquely determined, the screening system selects the test pattern with the opposite logical value of the corresponding bit of the baseline pattern from the test pattern set configured in the chip test program, under the same address bit width, as the triggering pattern. When the chip test program does not configure a completely opposite test pattern, the test pattern with the most flipped bits and supported by the device under test is selected as the candidate triggering pattern according to the bit-by-bit comparison results under the same address bit width. If there are multiple candidate triggering patterns, the candidate triggering pattern with the highest sorting order is selected as the triggering pattern according to the test pattern order preset in the chip test program, and a pattern reversal triggering path configuration is formed.

[0040] When the hold edge response is uniquely ranked first in the sorting, the filtering system determines the hold edge triggering path. This path follows the write pattern and address access order confirmed in S1, and uses the hold duration, hold temperature and refresh configuration in the initial hold window as the configuration basis to form the hold edge triggering path configuration.

[0041] When the thermal hysteresis response is uniquely located at the top of the sorting list, and the thermal hysteresis response is formed by the same storage segment, the same write pattern, and the same hold window configuration, the screening system determines the thermal path induction path. This path is configured with the induction hold window according to the heating hold and cooling retest relationship confirmed by the object in S1, and the same storage segment, the same write pattern, and the same address access order are kept unchanged, thus forming the thermal path induction path configuration.

[0042] When the edge response, pattern acceptance response, and thermal hysteresis response do not form a unique first and second order, the screening system does not generate an induced hold sequence, and the corresponding storage segment does not enter the read-write hold retest in this step.

[0043] The screening system generates induced hold timing based on the determined induced path configuration. The induced hold timing includes the memory segment number, bank address, row and page address range, address access order, write pattern, induced hold window, immediate verification readback plan time, and first external readback plan time after hold. The induced hold window is jointly limited by the initial hold window, the determined induced path, and the test range allowed by the chip test program. The induced hold window does not exceed the maximum hold duration, maximum hold temperature, and stable operating range of the test equipment jointly limited by the chip test program, DDR5 chip specification constraints, and test equipment calibration records. When the proposed induced hold window exceeds the aforementioned range, the screening system does not generate the induced hold timing for that memory segment, but retains the corresponding memory segment number and the proposed window content. When the standard samples in the same batch are insufficient to calibrate the induced hold window, the induced hold window configuration confirmed by historical DDR5 memory chip screening samples of the same model, corresponding to the current test program configuration, and corresponding to the same induced path type is used as the initial configuration for the current batch. The results of the retest that has not been completed in this batch are not written back to update the induced hold window.

[0044] The screening system performs read-write hold retests on the storage segments in the path response candidate area according to the induced hold timing sequence. In each retest round, write, instant check readback, induced hold, and first external readback after hold are performed under the same storage segment, the same address access order, and the same induced hold timing sequence. The instant check readback is used to confirm the data status after the last write before hold, and the first external readback after hold is used to confirm whether a delayed flip has occurred after passing through the induced hold window. During the retest execution, the screening system records the actual time of the instant check readback, the actual end time of the induced hold window, and the actual time of the first external readback after hold.

[0045] For pattern reversal induced paths, the screening system performs immediate verification readback of the induced pattern after it is written, and uses the immediate verification readback result of the induced pattern as the immediate verification readback result of the last written pattern before it is retained. For edge retention induced paths and hot path induced paths, the screening system uses the immediate verification readback result after the last written pattern before it is retained in the corresponding path as the comparison benchmark. The delayed reversal determination is based on the same retest round, the same storage segment and the last written pattern before it is retained as the object boundary.

[0046] When, in the same retesting round, the immediate verification readback result is consistent with the last write pattern before holding, but the first external readback result after holding is inconsistent with the last write pattern, the screening system will record the corresponding retesting round as a delayed flip-induced event.

[0047] The screening system generates delay flip-inducing records based on delay flip-inducing events in the same storage segment. The delay flip-inducing records include storage segment number, bank address, row and page address range, induced hold timing number, induced path type, write pattern, real-time verification readback result, first external readback result after hold, actual end time of induced hold window, and actual time of first external readback after hold. The delay flip-inducing records are not directly used as the output basis for DDR5 memory chip screening level, but as the input records for the next step of ECS intervention timing matching and cleanup contamination boundary determination.

[0048] When at least one of the following occurs in the same retest round: the immediate verification readback result is inconsistent with the last write pattern before hold, the address access order cannot be reproduced, the hold window execution is interrupted, the hold temperature does not reach the hold window configuration, or the first external readback after hold is missing, the screening system will not write the corresponding retest round into the delayed flip trigger record, and will retain the corresponding storage segment number, the hold trigger timing number, and the time when the anomaly occurred.

[0049] This step outputs the delayed flip-induced record and the corresponding induced hold timeline anchor. The induced hold timeline anchor includes the actual end time of the induced hold window and the actual time of the first external readback after hold. It is used for the next step to perform timeline matching with the ECS intervention record, thereby generating the clean contamination boundary state.

[0050] In one implementation, S3, the ECS intervention record formed during the read-write hold retest is obtained, and the ECS intervention time in the ECS intervention record is matched with the hold window end time and the first external readback time in the induced hold time sequence to generate the clean contamination boundary state, which specifically includes the following processing steps.

[0051] This step takes over the delayed flip-induced record and the corresponding induced hold timing anchor point output by S2. The delayed flip-induced record is used to limit the storage segments and retest rounds participating in the cleanup contamination determination in this step. The induced hold timing anchor point comes from the induced hold timing and is used to provide the actual end time of the induced hold window and the actual time of the first external readback after hold in the same retest round. This step takes the delayed flip-induced record and the induced hold timing anchor point as the processing objects and does not update the delayed flip-induced result and induced hold timing already formed by S2.

[0052] The screening system starts with the actual end time of the induced hold window and ends with the actual time of the first external readback after hold, forming a pre-external readback clearing judgment interval. This interval is used to limit the time boundary for ECS intervention records to participate in timing matching. The time resolution range is jointly limited by the test equipment clock synchronization accuracy, ECS command log timestamp accuracy, and external readback sampling timestamp accuracy, and is formed according to the maximum time uncertainty in the calibration records of the three under the current test configuration. When any one of the test equipment clock synchronization accuracy, ECS command log timestamp accuracy, or external readback sampling timestamp accuracy fails to complete the calibration of the current test configuration, the corresponding retest round enters the clearing pending verification state.

[0053] The filtering system acquires ECS intervention records generated during the read-write hold retest. These records document ECS command execution information, ECS statistical range, start and end times of record coverage, and record source. The ECS intervention time is determined by time information characterizing the actual execution of the ECS command from the chip test program, test device command log, and memory controller command records. If the actual execution time of the ECS command cannot be confirmed for the corresponding record, the ECS intervention time is not written, and the corresponding storage segment is designated as a state to be cleared and reviewed. The ECS count read results are only used to generate ECS count changes and do not participate in determining the ECS intervention time. The ECS statistical range is used to represent the chip range, bank range, and row / page address range that the ECS intervention record can correspond to.

[0054] The filtering system reads the ECS count read result most recently completed before the start of the external readback pre-flush judgment interval, and reads the ECS count read result for the first completed read after the end of the external readback pre-flush judgment interval. If the statistical ranges of the two ECS count read results are consistent and can be uniquely attributed to the same storage segment address range, the filtering system compares the two ECS count read results and generates a corresponding ECS ​​count change for the storage segment. If the two ECS count read results cannot correspond to the same statistical range, or cannot be uniquely attributed to the same storage segment address range, no corresponding ECS ​​count change is generated for the storage segment. The corresponding storage segment is designated as a state to be cleared and reviewed. When the ECS count read result after the end of the external readback clearing judgment interval is greater than the ECS count read result before the start of the external readback clearing judgment interval, it is determined that the ECS count has increased. When the two ECS count read results are equal, a change in the ECS count without increase is formed. When the subsequent ECS count read result is less than the previous ECS count read result, or when the ECS count read result carries any of the following flags: count wrap-around flag, reset flag, or read failure flag, no valid ECS count change is formed, and the corresponding storage segment is designated as a state to be cleared and reviewed.

[0055] The screening system uses the same storage segment and the same retest round as the object to verify the connection relationship between the ECS statistical range and the storage segment address range in the delay flip-induced record. When the ECS statistical range can uniquely connect to the corresponding storage segment address range, the corresponding ECS ​​intervention record is used for timing matching; when the ECS statistical range cannot uniquely connect to the corresponding storage segment address range, the corresponding storage segment is determined to be in a state of pending cleanup and verification, and the ECS intervention record is not written into the cleanup contamination state and cleanup trusted state of a single storage segment.

[0056] After completing the ECS statistical range acceptance check, the screening system performs time-series matching between the ECS intervention time and the external readback pre-cleaning judgment interval. If the ECS intervention time is earlier than the start of the external readback pre-cleaning judgment interval and is not within the time resolution range of the actual end time of the induced hold window, it will not be used as the basis for cleaning contamination in the first external readback result after hold. If the ECS intervention time is later than the end of the external readback pre-cleaning judgment interval and is not within the time resolution range of the actual time of the first external readback after hold, it will not be used as the basis for cleaning contamination in this external readback result. The cleaning contamination boundary status includes cleaning contamination status, cleaning credible status, and cleaning pending verification status.

[0057] When the corresponding retest round has been determined to be in a state of pending review, the screening system will no longer generate a state of cleanup contamination or a state of cleanup trust for that retest round.

[0058] When the ECS intervention time is later than the actual end time of the induced hold window and earlier than the actual time of the first external readback after hold, and does not fall within the time resolution range of the two boundary times, and the change in ECS count can be uniquely attributed to the same storage segment and manifested as an increase in ECS count, the screening system generates a clean contamination status. The clean contamination status is used to indicate that the result of the first external readback after hold in this retest round may be affected by the ECS cleanup action, and the corresponding delayed flip induced record enters the boundary retest record processing in the next step.

[0059] When the start and end times of the ECS intervention record generated during the read-write hold retest cover the complete period of the external readback pre-cleanup judgment interval, and no ECS intervention time that can be connected to the same storage segment is formed within this interval, and the ECS count change can be uniquely connected to the same storage segment and does not show an increase in the ECS count, the screening system generates a cleanup trust status. The complete coverage period means that the start time of the ECS intervention record is not later than the start time of the external readback pre-cleanup judgment interval, the end time of the coverage is not earlier than the end time of the external readback pre-cleanup judgment interval, and there is no record interruption marker between the start time of the coverage and the end time of the coverage. The cleanup trust status is used to indicate that the first external readback result after the hold of this retest round did not detect ECS cleanup intervention, and the corresponding delayed flip induced record enters the boundary pre-induced record segment processing in the next step.

[0060] When neither the criteria for determining the contamination state nor the reliable state for cleaning is met, the screening system generates a pending cleanup state. The pending cleanup state is used to address situations where the ECS statistical range cannot be uniquely attributed to the corresponding storage segment address range, the ECS count change cannot be uniquely attributed to the same storage segment, the ECS intervention time is within the time resolution range of the actual end time of the induced hold window, the ECS intervention time is within the time resolution range of the actual time of the first external readback after hold, the cleanup judgment interval before external readback lacks a complete ECS intervention record, the actual execution time of the ECS command cannot be confirmed, or the ECS count read result shows wrap-around, reset, or read failure. The pending cleanup state is not used as a reliable cleanup state, nor is it directly written into the boundary retest conclusion as a contamination state for cleaning.

[0061] The screening system generates a cleanup contamination boundary record based on the cleanup contamination boundary status. This record includes the storage segment number, retest round, actual end time of the induced hold window, actual time of the first external readback after hold, ECS statistical range, ECS count change, and the cleanup contamination boundary status. When the ECS intervention time is determined, the cleanup contamination boundary record is written with that time. When the ECS intervention time is not determined, the record is marked as "undetermined." For cleanup contamination status, the record uses the ECS intervention time as the cleanup contamination boundary time. For a cleanup confidence status, no cleanup contamination boundary time is set in the record. For a cleanup pending verification status, no cleanup contamination boundary time is set in the record, and the record is written with the "pending verification" status.

[0062] When the same storage segment forms different cleanup and contamination boundary states in multiple retesting rounds, the screening system retains the cleanup and contamination boundary states separately for each retesting round, without merging multiple retesting rounds into a single state. Retesting rounds that form a cleanup and contamination state will be retested and recorded in the next step after entering the boundary. Retesting rounds that form a cleanup and trustworthy state will trigger record segment processing before entering the boundary in the next step. Retesting rounds that form a cleanup and verification pending state will not be included in the generation of high-trust screening conclusions.

[0063] This step outputs the cleanup contamination boundary status and cleanup contamination boundary record. The cleanup contamination boundary status is used to identify whether the ECS cleanup action may intervene in the evidence formation process between the actual end of the hold window and the first external readback after hold in the same storage segment and the same retest round. The cleanup contamination boundary record is used in the next step to split the delayed flip induced record into the pre-boundary induced record segment and the post-boundary retest record segment, and to provide the temporal boundary basis for the generation of the equivalent induced retest path.

[0064] In one implementation, S4, according to the state of the cleaned contamination boundary, the delayed flip-induced record is split into a pre-boundary induced record segment and a post-boundary retest record segment to generate a cleaned boundary record. Based on the cleaned boundary record, an equivalent induced retest path is generated for the same storage segment and the retest is performed to generate a storage segment screening state. Then, according to the distribution of the storage segment screening state in the DDR5 storage array, the DDR5 memory chip screening level is output.

[0065] This step follows the delayed flip-over induced record output by S2, the induced hold timing execution result formed when S2 executes the induced hold timing, and the clean contamination boundary status and clean contamination boundary record output by S3. The delayed flip-over induced record is used to provide the induced path type, write pattern, address access order, induced hold window, immediate verification readback result, and first external readback result after hold for the same storage segment in the corresponding retest round. The induced hold timing execution result is used to record the retest rounds in which the induced hold timing has been executed but no delayed flip-over induced record has been formed. The clean contamination boundary record is used to provide the storage segment number, bank address, row and page address range, and retest round corresponding to the clean contamination boundary status. This step does not change the clean contamination boundary status already formed by S3, but only performs evidence diversion and retest confirmation on the delayed flip-over induced record based on the clean contamination boundary status.

[0066] This step is limited to processing storage segments in the path response candidate area that have already executed induced hold sequences. Candidate records awaiting review that have not entered the S2 induced hold sequence generation are not involved in the determination of the delay flip confirmation status and the pass-through level. For storage segments in the path response candidate area that have executed induced hold sequences but have not formed delay flip induced records, the screening system retains the induced hold sequence execution results of the corresponding retest round. The induced hold sequence execution results include storage segment number, bank address, row and page address range, retest round, induced path type, write pattern, immediate verification readback result, first external readback result after hold, and induced hold window execution status, which are used to generate the delay flip unconfirmed status in this step.

[0067] The screening system uses the same storage segment and the same retesting round as objects, and matches the delayed flip-induced record with the clean-up contamination boundary record. When the storage segment number, bank address, row and page address range, and retesting round are all consistent, the delayed flip-induced record and the clean-up contamination boundary record are determined to belong to the same evidence object. If any object field is inconsistent, no pre-boundary induced record segment and post-boundary retesting record segment are generated for the delayed flip-induced record, and the corresponding storage segment is determined to be in the screening pending confirmation state.

[0068] When the cleanup of contamination boundary is in a reliable state, the screening system writes the corresponding delayed flip induced record into the pre-boundary induced record segment and writes the pre-boundary induced record segment marker into the cleanup boundary record. The cleanup of contamination boundary time is not set. When writing the pre-boundary induced record segment, the screening system retains the induced path type, writing pattern, address access order, actual end time of the induced hold window, and actual time of the first external readback after hold in the delayed flip induced record.

[0069] When the contamination boundary is in the contamination clearing state, the screening system writes the corresponding delayed flip-induced record into the post-boundary retest record segment and marks the post-boundary retest record segment in the contamination clearing boundary record. The post-boundary retest record segment is used to receive delayed flip-induced records that may be affected by the ECS clearing action in the first external readback result after holding. The delayed flip-induced records written into the post-boundary retest record segment are not directly used to generate the delayed flip confirmation state. When writing into the post-boundary retest record segment, the screening system retains the induction path type, writing pattern, address access order and induction holding window configuration of this retest round.

[0070] When the state of the cleaned contamination boundary is the state of cleaned pending verification, the screening system does not write the corresponding delayed flip-induced record into the pre-boundary induced record segment and the post-boundary retest record segment. Instead, it writes the cleaned pending verification state mark into the cleaned boundary record and determines the corresponding storage segment as the state of screening pending confirmation. The state of screening pending confirmation does not participate in the determination of the delayed flip confirmation state and the pass screening level.

[0071] The screening system generates a clean boundary record based on the pre-boundary induced record segment, the post-boundary retest record segment, and the clean boundary status. The clean boundary record is written with the storage segment number, bank address, row and page address range, retest round, clean boundary status, pre-boundary induced record segment marker, and post-boundary retest record segment marker, which is used to limit whether an equivalent induced retest path is generated for the same storage segment in the future.

[0072] For the same storage segment corresponding to the post-boundary retest record segment, the screening system, when the storage segment address range can be uniquely accepted, the address access order can be reproduced, and the induced hold window configuration can be executed within the current test program's allowed range, uses the induced path type, write pattern, address access order, and induced hold window configuration of the corresponding retest round to generate an equivalent induced retest path. The current test program's allowed range is jointly limited by the chip test program, DDR5 chip specification constraints, and test equipment calibration records. The storage segment address range can be uniquely accepted, meaning that the same bank address and the same row / page address range can be consistent with the storage segment boundary formed by S1. The address access order can be reproduced, meaning that the access log of the same test equipment on the corresponding storage segment can reproduce the address access order in the post-boundary retest record segment. The equivalent induced retest path is used to keep the induced conditions consistent with the retest round affected by the cleanup contamination, and to re-form the first external readback result after hold and the corresponding cleanup contamination boundary state.

[0073] If at least one of the following occurs: the storage segment address range cannot be uniquely accepted, the address access order cannot be reproduced, the induced hold window configuration cannot be executed within the range allowed by the current test program, or the address remapping or redundancy repair causes the corresponding storage segment boundary to change, the screening system will not generate an equivalent induced retest path and will determine the corresponding storage segment as a screening pending confirmation state.

[0074] When generating an equivalent induced retest path, the screening system reads the induced path type, write pattern, address access order, and induced hold window configuration from the retest record segment after clearing the boundary record. Within the same storage segment, it generates a new write, immediate verification readback, induced hold, and first external readback process after hold. In the new retest round, after the screening system completes the write and before entering the induced hold phase, it executes the same immediate verification readback as S2, based on the last write pattern before hold. If the immediate verification readback result is inconsistent with the last write pattern before hold, the induced hold and first external readback after hold are not executed, and the corresponding storage segment is designated as a screening pending confirmation state.

[0075] After executing the equivalent induced retest path, the screening system obtains the ECS intervention records generated during the execution of the retest round and performs time-series matching between the ECS intervention time and the actual end time of the induced hold window and the actual time of the first external readback after hold for the retest round. This generates the cleanup contamination boundary state corresponding to the retest round. When the cleanup contamination boundary state corresponding to the retest round is a cleanup credible state, the screening system generates the equivalent retest result based on the real-time verification readback result and the first external readback result after hold for the retest round. When the cleanup contamination boundary state corresponding to the retest round is either a cleanup contamination state or a cleanup pending verification state, the screening system does not use the retest round to generate a delayed flip confirmation state and a pass screening level. It does not continue to generate the equivalent induced retest path based on the retest round and determines the corresponding storage segment as a screening pending confirmation state. The generation of the equivalent induced retest path does not rely on future ECS results as a prerequisite for execution. The cleanup contamination boundary state after retesting is only used for result admission after the retest is completed.

[0076] The screening system generates a storage segment screening status based on the pre-boundary induced record segment, the equivalent retest result, and the induced hold timing execution result. When either the pre-boundary induced record segment or the equivalent retest result satisfies the delayed flip confirmation condition that the immediate verification readback result is consistent with the last write pattern before hold, and the first external readback result after hold is inconsistent with the last write pattern before hold, the corresponding storage segment is determined to be in the delayed flip confirmation status.

[0077] If the same storage segment is not identified as a delayed flip confirmation state, and at least one of the following situations occurs: a cleanup pending verification state, an equivalent induced retest path not executed, or an equivalent induced retest path executed but no equivalent retest result generated, the corresponding storage segment will be identified as a screening pending confirmation state. The screening pending confirmation state is used to indicate that the storage segment has not obtained a retest result under the cleanup trusted state and does not have a boundary pre-induced record segment.

[0078] Based on the execution results of the induced hold sequence, if the same storage segment that has been executed with the induced hold sequence does not meet the delayed flip confirmation condition and is not identified as a state to be screened for confirmation, the corresponding storage segment will be identified as a delayed flip unconfirmed state. The delayed flip unconfirmed state is used to indicate that the storage segment has not formed delayed flip evidence in the retest rounds in which the induced hold sequence has been executed.

[0079] The screening system outputs DDR5 memory chip screening levels based on the distribution of delayed flip-over confirmed, screening pending, and delayed flip-over unconfirmed states within the DDR5 storage array. When outputting screening levels, the system uses the storage segment screening state as the basic object, determining the bank and row / page address range of the delayed flip-over confirmed state within the DDR5 storage array. For continuous row / page clustering, the system uses the storage segment division results of continuous rows / pages within the same bank in S1 as the judgment basis. For cross-bank distribution, the system uses the bank address corresponding to the storage segment screening state as the judgment basis. When the same DDR5 memory chip simultaneously meets the trigger conditions for multiple screening levels, the screening system determines the final output level in the order of array diffusion risk level, local weak storage segment level, pending review level, and passed screening level. When delayed flip confirmation states are distributed across multiple banks and do not belong to the same consecutive row / page address range, the filtering system outputs the array diffusion risk level; when the array diffusion risk level is not met and delayed flip confirmation states are concentrated in adjacent row / page address ranges within the same bank, the filtering system outputs the local weak storage segmentation level; when no delayed flip confirmation state has been formed and there are filtering states pending confirmation, the filtering system outputs the review level; when no delayed flip confirmation state has been formed and there are no filtering states pending confirmation, the filtering system outputs the pass level.

[0080] When multiple memory segment filtering states exist simultaneously within the same DDR5 memory chip, the filtering system first determines whether there are delayed flip-over confirmation states distributed across multiple banks and not belonging to the same continuous row / page address range. If so, it outputs the array diffusion risk level. If the array diffusion risk level is not met and delayed flip-over confirmation states are concentrated within adjacent row / page address ranges in the same bank, it outputs the local weak memory segmentation level. If no delayed flip-over confirmation state has formed and there are filtering states awaiting confirmation, it outputs the pending review level. If no delayed flip-over confirmation state has formed and there are no filtering states awaiting confirmation, it outputs the passed filtering level.

[0081] The storage segmentation screening status and DDR5 memory chip screening level are only used as the screening output for this step and do not write back the update path response candidate area, induce hold timing, or clean up the contamination boundary status.

[0082] This step outputs the brush boundary record, storage segment screening status, and DDR5 memory chip screening level. The brush boundary record is used to preserve the boundary impact of the ECS brushing action on the delay flip evidence. The storage segment screening status is used to characterize the screening results of the same storage segment after brush boundary processing and equivalent retesting. The DDR5 memory chip screening level is used to automatically screen the entire DDR5 memory chip according to the distribution of the storage segment screening status in the DDR5 storage array.

[0083] In one embodiment, the present invention also provides an automated screening device for DDR5 memory chips. The automated screening device for DDR5 memory chips includes a processor and a memory. The memory is communicatively connected to the processor. The memory stores a computer program and data records generated during the automated screening process of DDR5 memory chips. When the processor executes the computer program, it implements the aforementioned automated screening method for DDR5 memory chips.

[0084] Specifically, the DDR5 memory chip automated screening device can be a test control unit in the chip testing equipment, a screening control device that communicates with the chip testing equipment, or a data processing device integrated into the DDR5 memory chip testing platform. The processor can obtain the read-write holding record formed by the DDR5 memory chip under the initial holding window, the address arrangement information in the chip test program, the address access order saved by the test equipment, the ECS intervention record, the ECS count reading result, and the external readback result through the test interface. The test interface can be a data interface connected to the chip testing equipment, memory controller, or test program log acquisition unit, which is used to enable the processor to obtain the input records required to execute S1 to S4.

[0085] The memory includes a program storage area and a data storage area. The program storage area stores computer programs that can be executed by the processor. The data storage area stores read / write hold records, storage segmentation results, path response candidate areas, preceding hold responses, induced hold timing, delayed flip-induced records, induced hold timing execution results, ECS intervention records, clean contamination boundary status, clean contamination boundary records, clean boundary records, equivalent induced retest paths, equivalent retest results, storage segment screening status, and DDR5 memory chip screening levels. Each data record is associated according to the storage segment number, bank address, row / page address range, and retest round, so that the processor can take over the object boundaries formed by the preceding steps when executing subsequent processing.

[0086] When the processor executes the computer program stored in memory, it first obtains the read / write hold records formed by the DDR5 memory chip under the initial hold window, and divides the memory into segments according to the row / page address and bank address connection relationship of the DDR5 memory array. The processor aggregates the hold responses in the read / write hold records according to the memory segments to form the preceding hold response, and generates a path response candidate area based on the hold response strength, address acceptance confidence status, and the reproduction of adjacent memory segments. For read / write hold records that cannot be uniquely accepted to the row / page address and bank address, the processor marks the corresponding record as an address acceptance confirmation and prevents the corresponding record from participating in the generation of the path response candidate area.

[0087] The processor continues to acquire the preceding hold responses corresponding to each memory segment in the path response candidate area, and performs hold edge responses, pattern acceptance responses, and thermal hysteresis responses in the preceding hold responses for acceptance checks and sorting. The processor determines the pattern reversal induced path, hold edge induced path, or thermal path induced path based on the sorting results, and generates the induced hold timing sequence. The processor controls the test equipment to perform read-write hold retests on the memory segments in the path response candidate area according to the induced hold timing sequence, and generates a delayed flip induced record based on the immediate verification readback result of the last write pattern before hold and the first external readback result after hold. For retest rounds where the immediate verification readback result is inconsistent with the last write pattern before hold, the address access order cannot be reproduced, the induced hold window execution is interrupted, or the first external readback after hold is missing, the processor does not write the corresponding retest round into the delayed flip induced record.

[0088] During the read-write hold retest, the processor acquires the ECS intervention record and forms a pre-external readback clearing judgment interval with the actual end time of the induced hold window as the starting point and the actual time of the first external readback after hold as the ending point. The processor performs timing matching between the ECS intervention time and the pre-external readback clearing judgment interval, and generates clearing contamination boundary states and clearing contamination boundary records by combining the continuation relationship between the ECS statistical range and the corresponding storage segment address range, and the ECS count change. The clearing contamination boundary states include clearing contamination state, clearing trusted state, and clearing pending verification state.

[0089] According to the cleanup contamination boundary state, the processor splits the delayed flip-induced record into a pre-boundary induced record segment and a post-boundary retest record segment, and generates a cleanup boundary record. When the cleanup contamination boundary state is a cleanup trusted state, the processor writes the corresponding delayed flip-induced record into the pre-boundary induced record segment; when the cleanup contamination boundary state is a cleanup contamination state, the processor writes the corresponding delayed flip-induced record into the post-boundary retest record segment; when the cleanup contamination boundary state is a cleanup pending verification state, the processor does not write the corresponding delayed flip-induced record into the pre-boundary induced record segment and the post-boundary retest record segment, and determines the corresponding storage segment as a screening pending confirmation state.

[0090] For the same storage segment after the write boundary is retested, the processor generates an equivalent induced retest path based on the boundary record clearing. When generating the equivalent induced retest path, the processor uses the induced path type, write pattern, address access order, and induced hold window configuration of the corresponding retest round, and generates a new write, immediate verification readback, induced hold, and first external readback process after hold within the same storage segment. When the storage segment address range cannot be uniquely accepted, the address access order cannot be reproduced, the induced hold window configuration cannot be executed within the range allowed by the current test program, or the address remapping or redundancy repair causes the boundary of the corresponding storage segment to change, the processor does not generate an equivalent induced retest path and determines the corresponding storage segment as a state to be screened and confirmed.

[0091] After the processor executes the equivalent induced retest path, it acquires the ECS intervention record formed during the execution of the retest round, and performs timing matching between the ECS intervention time and the actual end time of the induced hold window and the actual time of the first external readback after hold for the retest round. This generates the cleanup contamination boundary state corresponding to the retest round. When the cleanup contamination boundary state corresponding to the retest round is a cleanup trusted state, the processor generates the equivalent retest result based on the real-time verification readback result and the first external readback result after hold for the retest round. When the cleanup contamination boundary state corresponding to the retest round is a cleanup contamination state or a cleanup pending verification state, the processor does not use the retest round to generate a delayed flip confirmation state and pass the screening level, and determines the corresponding storage segment as a screening pending confirmation state.

[0092] The processor generates a storage segment filtering state based on the pre-boundary induced record segment, the equivalent retest result, and the induced hold timing execution result. If either the pre-boundary induced record segment or the equivalent retest result satisfies the delayed flip confirmation condition that the immediate verification readback result is consistent with the last write pattern before hold, or the first external readback result after hold is inconsistent with the last write pattern before hold, the processor determines the corresponding storage segment as a delayed flip confirmation state. If the same storage segment is not determined as a delayed flip confirmation state, and at least one of the following situations occurs: a clear pending verification state, an equivalent induced retest path not executed, or an equivalent retest result not generated after the execution of the equivalent induced retest path, the processor determines the corresponding storage segment as a filtering pending confirmation state. If the same storage segment that has executed the induced hold timing does not meet the delayed flip confirmation condition and is not determined as a filtering pending confirmation state, the processor determines the corresponding storage segment as a delayed flip unconfirmed state.

[0093] The processor outputs the DDR5 memory chip screening level based on the distribution of delayed flip-over confirmed states, screening pending states, and delayed flip-over unconfirmed states in the DDR5 memory array. When delayed flip-over confirmed states are concentrated in adjacent row and page address ranges within the same bank, the processor outputs a local weak memory segmentation level. When delayed flip-over confirmed states are distributed across multiple banks and do not belong to the same consecutive row and page address range, the processor outputs an array diffusion risk level. When no delayed flip-over confirmed states are formed within the processing scope and no screening pending states exist, the processor outputs a pass screening level. When no delayed flip-over confirmed states are formed within the processing scope and screening pending states exist, the processor outputs a pending review level. The memory segmentation screening states and DDR5 memory chip screening levels generated by the processor are only used as screening outputs and do not write back the update path response candidate area, induce hold-up timing, or clean up contaminated boundary states.

[0094] In one embodiment, the present invention also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the aforementioned automated screening method for DDR5 memory chips. The computer-readable storage medium can be a non-volatile memory, a disk, an optical disk, a solid-state memory, a flash memory, or other storage medium capable of storing a computer program executed by a processor.

[0095] The computer program includes program instructions that enable the processor to perform data acquisition, address acceptance, memory segmentation, hold response convergence, candidate admission, induced hold timing generation, read-write hold retesting, ECS intervention timing matching, clean contamination boundary state generation, clean boundary record generation, equivalent induced retesting path generation, memory segment screening state generation, and DDR5 memory chip screening level output. When the processor loads and executes the program instructions, it maintains the object acceptance relationship between each data record according to the memory segment number, bank address, row and page address range, and retest round. When any of the following situations occur, such as address not being uniquely accepted, readback data being missing, ECS intervention timing not being confirmed, ECS statistical range not being uniquely accepted, or equivalent induced retesting path not being executed, it generates a record to be confirmed or a screening status to be confirmed according to the corresponding exception handling method in the aforementioned DDR5 memory chip automated screening method.

[0096] When the computer program is executed by the processor, it enables the processor to generate a path response candidate region based on the read-write hold record of the DDR5 memory chip, generate an induced hold timing based on the preceding hold response of the path response candidate region and perform a read-write hold retest, generate a clean contamination boundary state based on the ECS intervention record formed during the read-write hold retest, and generate a storage segmentation screening state and a DDR5 memory chip screening level based on the clean contamination boundary state and the equivalent induced retest results.

[0097] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented in software, the above embodiments can be implemented, in whole or in part, as a computer program product. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution.

[0098] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An automated screening method for DDR5 memory chips, characterized in that, Includes the following steps: The read / write hold records formed by the DDR5 memory chip under the initial hold window are obtained. The memory is divided into segments according to the row and page address and bank address concatenation relationship of the DDR5 memory array. The hold responses in the read / write hold records are aggregated according to the memory segments to generate path response candidate areas. Obtain the preceding hold responses of the path response candidate region, process the preceding hold responses using the preceding response succession method, generate the induced hold sequence, and perform read-write hold retest on the path response candidate region according to the induced hold sequence to generate delayed flip induced records. Acquire the ECS intervention record generated during the read-write-hold retest execution, match the ECS intervention time in the ECS intervention record with the end time of the hold window in the induced hold time sequence and the first external readback time to generate the clean contamination boundary state; According to the state of the cleanup contamination boundary, the delayed flip-induced record is split into the pre-boundary induced record segment and the post-boundary retest record segment to generate the cleanup boundary record. Based on the cleanup boundary record, an equivalent induced retest path is generated for the same storage segment and the retest is performed to generate the storage segment screening state. Then, according to the distribution of the storage segment screening state in the DDR5 storage array, the DDR5 memory chip screening level is output.

2. The automated screening method for DDR5 memory chips according to claim 1, characterized in that, The process of generating a path response candidate area includes: obtaining read-write hold records formed within the same initial hold window, assigning the logical addresses in the read-write hold records to the row page addresses and bank addresses of the DDR5 storage array, and forming storage segments within the same bank according to the address range of consecutive and repeatedly accessible rows and pages; Read-write hold records that fail to uniquely connect to the row page address and the bank address are marked as address accept confirmations and are excluded from the path response candidate area generation; hold responses in read-write hold records are aggregated by storage segment, ECS count changes that can uniquely connect to the storage segment are incorporated into the preceding hold response of the corresponding storage segment, and ECS count changes that fail to uniquely connect to the storage segment are written to the chip-level ECS prompt record; Multiple hold responses within the same storage segment are accumulated. Hold responses that are not reproduced in subsequent read / write hold records of the same storage segment and are not reproduced in adjacent storage segments are downweighted to form hold response strength. Hold response strength, address acceptance trust status, and reproduction status of adjacent storage segments are used as candidate admission conditions. Storage segments that meet the candidate admission conditions are written into the path response candidate area.

3. The automated screening method for DDR5 memory chips according to claim 2, characterized in that, Generating a hold-inducing sequence includes: ranking the preceding hold responses corresponding to each storage segment in the read path response candidate area; within the storage segment uniquely connected to the row / page address and bank address, sorting the hold-in edge responses, pattern acceptance responses, and thermal hysteresis responses among the preceding hold responses; during sorting, responses whose corresponding readback change amplitude does not exceed the test equipment error range are first excluded, and then sorted from high to low according to the number of recurrences within the same storage segment; when the pattern acceptance response is uniquely located at the top of the sort, the pattern reversal induced path is determined; when the hold-in edge... When the response is uniquely located at the top of the sort order, the hold edge induced path is determined; when the thermal hysteresis response is uniquely located at the top of the sort order, and the thermal hysteresis response is formed by the same memory segment, the same write pattern, and the same hold window configuration, the thermal path induced path is determined; the write pattern, induced hold window, and readback time are configured according to the determined induced path, and the induced hold timing is generated; the ECS count change of the preceding hold response is retained along with the induced hold timing and does not participate in the determination of the induced path; when no unique top of the sort order is formed, no induced hold timing is generated.

4. The automated screening method for DDR5 memory chips according to claim 3, characterized in that, Generating a delayed flip-over trigger record includes: performing read-write hold retests on the same storage segment according to the triggered hold sequence; in the same retest round, comparing the immediate verification readback result of the last write pattern before hold with the first external readback result after hold; when the immediate verification readback result is consistent with the last write pattern, but the first external readback result after hold is inconsistent with the last write pattern, the corresponding retest round is recorded as a delayed flip-over trigger event, and a delayed flip-over trigger record is generated based on the delayed flip-over trigger events of the same storage segment; when at least one of the following occurs—the immediate verification readback result is inconsistent with the last write pattern, the address access order cannot be reproduced, the triggered hold window execution is interrupted, or the first external readback after hold is missing—the corresponding retest round is not written into the delayed flip-over trigger record.

5. The automated screening method for DDR5 memory chips according to claim 4, characterized in that, The process of generating a cleanup contamination boundary state includes: establishing a cleanup judgment interval before external readback, starting from the actual end time of the inducing hold window and ending at the actual time of the first external readback after hold; acquiring ECS ​​intervention records generated during the read-write hold retest, and comparing the ECS count reading results before and after the start and end times of the cleanup judgment interval before external readback to form ECS count changes; verifying the connection between the ECS statistical range and the storage segment address range in the delay flip inducing record, using the same storage segment and the same retest round as objects; when the ECS statistical range can uniquely connect to the corresponding storage segment address range, timing matching is performed using the corresponding ECS ​​intervention record; when the ECS statistical range cannot uniquely connect to the corresponding storage segment address range, the corresponding storage segment is determined as a cleanup pending review state; the ECS count reading results do not participate in determining the ECS intervention time.

6. The automated screening method for DDR5 memory chips according to claim 5, characterized in that, The status of the cleanup contamination boundary includes the cleanup contamination status, the cleanup credible status, and the cleanup pending verification status. Timing matching of ECS intervention time includes: when the ECS intervention time is later than the actual end time of the induced hold window but earlier than the actual time of the first external readback after hold, and the ECS count change can be uniquely attributed to the same storage segment and manifested as an increase in the ECS count, a clean contamination state is generated. When an ECS intervention record covering the entire period of the pre-readback clearing judgment interval is formed, and no ECS intervention time that can be connected to the same storage segment is formed within this interval, and no ECS count that can be connected to the same storage segment increases, a clearing trustworthy state is generated; when the judgment conditions for clearing contamination state and clearing trustworthy state are not met, a clearing pending review state is generated.

7. The automated screening method for DDR5 memory chips according to claim 6, characterized in that, Generating cleanup boundary records includes: mapping delayed flip-induced records to cleanup contamination boundary states for the same storage segment and the same retest round; writing the corresponding delayed flip-induced record to the pre-boundary induced record segment when the cleanup contamination boundary state is a cleanup trusted state; writing the corresponding delayed flip-induced record to the post-boundary retest record segment when the cleanup contamination boundary state is a cleanup contamination state; and determining the corresponding storage segment as a screening pending confirmation state when the cleanup contamination boundary state is a cleanup pending verification state. Based on the pre-boundary induced record segment, the post-boundary retest record segment, and the cleaned contamination boundary status, a clean boundary record is generated. For the same storage segment corresponding to the post-boundary retest record segment, if the storage segment address range can be uniquely accepted, the address access order can be reproduced, and the induced sustain window configuration can be executed within the current test program's allowed range, the induced path type, write pattern, address access order, and induced sustain window configuration of the corresponding retest round are used to generate an equivalent induced retest path. If at least one of the following occurs: the storage segment address range cannot be uniquely accepted, the address access order cannot be reproduced, or the induced sustain window configuration cannot be executed within the current test program's allowed range, an equivalent induced retest path is not generated.

8. The automated screening method for DDR5 memory chips according to claim 7, characterized in that, Generate storage segment screening status and output DDR5 memory chip screening level, including: after executing the equivalent induced retest path, obtain the ECS intervention record formed during the execution of the retest round, and perform timing matching between the ECS intervention time and the actual end time of the induced hold window and the actual time of the first external readback after hold for the retest round, and generate the clean contamination boundary status corresponding to the retest round. When the cleanup contamination boundary state corresponding to the retest round is a cleanup trustworthy state, an equivalent retest result is generated based on the immediate verification readback result and the first external readback result after holding for that retest round. If either the induced record segment before the boundary or the equivalent retest result satisfies the delayed flip confirmation condition that the immediate verification readback result is consistent with the last write pattern before holding, and the first external readback result after holding is inconsistent with the last write pattern before holding, the corresponding storage segment is determined to be in a delayed flip confirmation state. If there are cleanup pending verification states and equivalent induced retest states in the same storage segment... If at least one of the following occurs: test path not executed, equivalent induced retest path executed but no equivalent retest result generated, the corresponding storage segment is identified as a screening pending confirmation state; based on the execution result of the induced hold timing, if the same storage segment that has executed the induced hold timing does not meet the delay flip confirmation condition and is not identified as a screening pending confirmation state, the corresponding storage segment is identified as a delay flip unconfirmed state; output the DDR5 memory chip screening level according to the distribution of delay flip confirmed state, screening pending confirmation state, and delay flip unconfirmed state in the DDR5 memory array.

9. An automated screening device for DDR5 memory chips, characterized in that, It includes a memory and a processor; the memory stores a computer program, and when the processor executes the computer program, it implements the DDR5 memory chip automated screening method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the DDR5 memory chip automated screening method according to any one of claims 1 to 8.

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