Power supply circuit and electronic device

Abstract

The application discloses a power supply circuit and electronic equipment, and provides the power supply circuit, which comprises a battery module, a power management circuit, a restart circuit and a processor. The battery module is connected with the voltage input end of the processor through the power management circuit, and the control end of the processor is connected with the control end of the power management circuit. The restart circuit is connected with the power management circuit. The power management circuit is used for outputting a trigger signal to the restart circuit in the case that no control instruction from the processor is received within a preset time period. The restart circuit is used for generating a first control signal and a second control signal according to the trigger signal, and outputting the first control signal and the second control signal to the power management circuit. The power management circuit is used for controlling the battery module to stop supplying power to the processor according to the first control signal, and controlling the battery module to supply power to the processor again according to the second control signal, so that the processor is restarted.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a power supply circuit and electronic equipment. Background Technology

[0002] Currently, electronic devices such as mobile phones and tablets are becoming increasingly complex. Although rigorous testing and system updates have reduced the probability of system crashes, it is theoretically impossible to completely avoid them. For example, when a mobile phone's processor completely freezes, a regular shutdown procedure cannot restart the electronic device.

[0003] In related technologies, taking mobile phones as an example, the common approach is to have the user press and hold a specific combination of physical buttons, such as pressing and holding the power button and volume button, to force the phone system to power down and then power on, thus achieving a hard reboot after the phone freezes.

[0004] However, related technologies may have drawbacks such as data loss, abnormal system status, or hardware damage due to the inability to effectively restart after a system crash. For example, different manufacturers use inconsistent button combinations for system restart schemes, which can easily confuse users. Users may accidentally enter recovery mode or fastboot mode, leading to factory reset, data loss, or exacerbation of abnormal system conditions. Especially when an electronic device crashes during charging and the user fails to notice in time, the system may remain frozen for an extended period. This can cause the device to continuously draw high current, leading to over-discharge of the battery; or it can cause abnormal charging logic, preventing the battery from charging properly. Prolonged exposure to such abnormal states can easily cause irreversible damage to battery life and may even lead to hardware failure. Summary of the Invention

[0005] This application provides a power supply circuit and electronic device that at least solves the problems in the related art of data loss, abnormal system status, or hardware damage caused by the inability to effectively restart after a system crash.

[0006] In a first aspect, this application provides a power supply circuit, including: a battery module, a power management circuit, a restart circuit, and a processor. The battery module is connected to the voltage input terminal of the processor through the power management circuit, and the control terminal of the processor is connected to the control terminal of the power management circuit. The restart circuit is connected to the power management circuit. The power management circuit is used to output a trigger signal to the restart circuit if no control command is received from the processor within a preset time period; The restart circuit is used to generate a first control signal and a second control signal based on the trigger signal, and output the first control signal and the second control signal to the power management circuit. The power management circuit is used to control the battery module to stop supplying power to the processor according to the first control signal, and to control the battery module to supply power to the processor again according to the second control signal, so as to restart the processor.

[0007] Secondly, this application provides an electronic device, including a power supply circuit as described in the first aspect.

[0008] In the embodiments of this application, the power supply circuit includes a battery module, a power management circuit, a restart circuit, and a processor. The battery module is connected to the voltage input terminal of the processor through the power management circuit, and the control terminal of the processor is connected to the control terminal of the power management circuit. The restart circuit is connected to the power management circuit. The power management circuit is used to output a trigger signal to the restart circuit if no control command is received from the processor within a preset time period. The restart circuit is used to generate a first control signal and a second control signal according to the trigger signal, and output the first control signal and the second control signal to the power management circuit. The power management circuit is used to control the battery module to stop supplying power to the processor according to the first control signal, and to control the battery module to resume supplying power to the processor according to the second control signal, so as to restart the processor. In this way, when the power management circuit does not receive a control command from the processor, it automatically generates a trigger signal and outputs it to the restart circuit. The restart circuit generates the first control signal and the second control signal according to the trigger signal, and controls the power management circuit to automatically execute the operation of stopping and resuming power supply from the battery module to the processor. Therefore, when the processor is unable to send control commands due to a crash, the power management circuit can autonomously detect this abnormal state and trigger the restart circuit to automatically complete the operation of stopping and restoring power supply, so as to restart the processor. The whole process does not require manual intervention, avoiding the risk of data loss due to user misoperation. Without user intervention, it automatically cuts off and restores the power supply to the processor, realizing automatic restart after the processor crashes, avoiding the problems of data loss, abnormal system status or hardware damage caused by the inability to effectively restart after a crash. Attached Figure Description

[0009] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 A schematic diagram of a power supply circuit provided for some embodiments of this application; Figure 2 A schematic diagram of a power supply circuit provided for some embodiments of this application; Figure 3 A schematic diagram of a power supply circuit provided for some embodiments of this application; Figure 4 A schematic diagram of a power supply circuit provided for some embodiments of this application; Figure 5 A schematic diagram of a power supply circuit provided for some embodiments of this application; Figure 6 A schematic diagram of a power supply circuit provided for some embodiments of this application; Figure 7 A schematic diagram of a power supply circuit provided for some embodiments of this application; Figure 8 Schematic diagram of an electronic device provided for some embodiments of this application; Figure 9 A schematic flowchart illustrating a control method for an electronic device provided in some embodiments of this application; Figure 10 A schematic flowchart illustrating a control method for an electronic device provided in some embodiments of this application.

[0010] Explanation of reference numerals in the attached figures: 10 - Power supply circuit; 100 - Battery module; 200 - Power management circuit; 210 - Charging management chip; 211 - Battery switching unit; Q bat - Battery switching transistor; 212- Battery protection unit; 2121- Battery temperature detection unit; 2122- Battery undervoltage protection unit; 213- Constant power unit; 214- Switch control unit; LDO- Low dropout linear regulator; Rpu- Pull-up resistor; NTC- Thermistor; 220- Delay module; 221- Clock unit; RTC- Clock unit; 222- Timing capacitor; CRTC- Timing capacitor; 230- Discharge management chip; 231- Voltage adjustment unit; 300- Reset circuit; 310- First reset module; 311- Level conversion element; R pull - Resistor; 320 - Second restart module; 321 - Toggle switch; 330 - Third restart module; Q2 - Second switch element; 340 - Fourth restart module; Q1 - First switch element; 400 - Processor; 500 - Power button; 600 - Combination button; Vcore - Processor voltage input; SPMI - Control terminal; VDD_IN - Voltage input terminal; VDD_OUT - Voltage output terminal; EN - Enable terminal; A1 - First input terminal; A2 - Second input terminal; B - Output terminal; GPIO - Control interface; RESET_N - Reset terminal; 800 - Electronic device. Detailed Implementation

[0011] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0012] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0013] In the description of this application, it should be understood that the terms "inner" and "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0014] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0015] Currently, electronic devices such as mobile phones and tablets are becoming increasingly complex. Although rigorous testing and system updates have reduced the probability of system crashes, theoretically, it is still impossible to completely avoid them. For example, when a mobile phone's processor completely freezes, a conventional shutdown operation cannot restart the electronic device. Related technologies, taking mobile phones as an example, typically involve users pressing and holding specific physical button combinations, such as the power button and volume buttons, to force the phone to power down and then power on again, achieving a hard reboot after a crash. However, these technologies may fail to effectively restart after a system crash due to user error. For instance, different manufacturers use different button combinations for system reboot schemes, which can easily confuse users. Users may accidentally put the electronic device into recovery mode or fastboot mode, leading to factory reset, data loss, and other problems, thus failing to effectively restart after a system crash.

[0016] Based on this, embodiments of this application can incorporate a restart circuit in electronic devices such as mobile phones. When the power management circuit does not receive control commands from the processor, it automatically generates a trigger signal and outputs it to the restart circuit. The restart circuit then automatically performs power-stopping and power-restoring operations based on the trigger signal. Thus, when the processor is unable to send control commands due to a system crash, the power management circuit can autonomously detect this abnormal state and trigger the restart circuit to automatically complete the power-stopping and power-restoring operations. The entire process requires no user intervention, avoiding the risk of data loss due to user error. By automatically cutting off and restoring power to the processor without user intervention, automatic restart after a system crash is achieved.

[0017] The power supply circuit and electronic equipment provided in the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0018] In some embodiments of this application, such as Figure 1 As shown, this application embodiment provides a power supply circuit 10, which may include: a battery module 100, a power management circuit 200, a restart circuit 300, and a processor 400. The battery module 100 is connected to the voltage input terminal Vcore of the processor 400 through the power management circuit 200, and the control terminal of the processor 400 is connected to the control terminal of the power management circuit 200; the restart circuit 300 is connected to the power management circuit 200. The power management circuit 200 is used to: output a trigger signal to the restart circuit 300 if no control command is received from the processor 400 within a preset time period; The restart circuit 300 is used to: generate a first control signal and a second control signal according to the trigger signal, and output the first control signal and the second control signal to the power management circuit 200; The power management circuit 200 is used to: control the battery module 100 to stop supplying power to the processor 400 according to the first control signal, and control the battery module 100 to supply power to the processor 400 again according to the second control signal, so as to restart the processor 400.

[0019] In this embodiment, the battery module 100 is a rechargeable battery used to store electrical energy and provide operating voltage for the processor 400 and other functional modules. The battery module 100 includes, but is not limited to, lithium-ion batteries and lithium polymer batteries.

[0020] In this embodiment, the power management circuit 200 is a power management integrated circuit used to receive control commands from the processor 400 and manage and distribute the power of the battery module 100. The power management circuit 200 includes, but is not limited to, a charging management integrated circuit, a system power management integrated circuit, a charge pump, a low-dropout linear regulator, and a DC-DC converter. The power management circuit 200 integrates a microcontroller (not shown) and a control interface GPIO. The control terminal SPMI of the power management circuit 200 can receive SPMI control commands from the processor 400 via a control bus, which may include a data line SPMI_SDA and a clock line SPMI_CLK. When the microcontroller does not receive an SPMI control command from the processor 400 within a preset time period, it outputs a trigger signal through the control interface GPIO.

[0021] The control interface GPIO of the power management circuit 200 can be a general-purpose input / output interface or other types of electrical output interfaces. This application embodiment does not limit the specific type of the control interface of the power management circuit 200.

[0022] In the case where the power management circuit 200 includes a charging management chip and a discharging management chip, the control interface can be the control interface of the charging management chip or the control interface of the discharging management chip. The specific location of the control interface is not limited in the embodiments of this application.

[0023] In this embodiment, the restart circuit 300 includes, but is not limited to, a level conversion circuit or a switch control circuit, used to receive the trigger signal output by the power management circuit 200 and generate a first control signal and a second control signal based on the trigger signal. The restart circuit 300 includes, but is not limited to, impedance elements, switching units, delay units, level conversion elements, etc., and this application does not impose specific limitations on these. The restart circuit 300 is connected to the control interface GPIO of the power management circuit 200, used to control the internal trigger terminal of the power management circuit 200 or an external switching transistor when a trigger signal is received, thereby controlling the on / off power supply to the processor 400.

[0024] In this embodiment, the processor 400 is an application processor or a system-on-a-chip (SoC) used to run the operating system and applications, and periodically sends control commands to the control terminal SPMI of the power management circuit 200 via the control terminal SPMI to indicate that the power management circuit 200 is in normal working condition. The processor 400 includes, but is not limited to, a central processing unit, a microcontroller, a digital signal processor, a system-on-a-chip, etc., and this application does not impose specific limitations on it.

[0025] It should be noted that in related technologies, when a mobile phone system completely freezes, the user typically forces the system to power down and then power on again by pressing and holding a specific combination of physical buttons, achieving a hard reboot. However, this solution has significant drawbacks: button combinations vary between different manufacturers, which can easily confuse users and lead to data loss or exacerbated system anomalies due to misoperation; at the same time, this solution directly exposes system stability issues to users, deepening their concerns about product stability and creating a negative experience; furthermore, when the phone freezes while stationary or charging, users cannot detect it immediately, and the system may continuously consume high current, leading to over-discharge of the battery, further affecting charging recovery and product reputation. Based on this, this application embodiment sets up a power management circuit 200 and a restart circuit 300, so that the power management circuit 200 automatically generates a trigger signal when it does not receive control commands from the processor 400, and the restart circuit 300 generates a first control signal and a second control signal based on the trigger signal, controlling the power management circuit 200 to automatically complete the operation of stopping and restoring power supply, realizing automatic restart after the processor 400 freezes without user intervention.

[0026] Thus, in this embodiment, when the power management circuit 200 does not receive a control command from the processor 400, it automatically generates a trigger signal and outputs it to the restart circuit 300. The restart circuit 300 generates a first control signal and a second control signal based on the trigger signal, controlling the power management circuit 200 to automatically execute the operation of stopping and restoring power supply from the battery module 100 to the processor 400. Therefore, when the processor 400 is unable to send control commands due to a system crash, the power management circuit 200 can autonomously detect this abnormal state and trigger the restart circuit 300 to automatically complete the operation of stopping and restoring power supply, thereby restarting the processor. The entire process requires no manual intervention, avoiding the risk of data loss due to user error. By automatically cutting off and restoring power to the processor without user intervention, the power supply to the processor 400 is automatically cut off, achieving automatic restart after a system crash and avoiding problems such as data loss, abnormal system status, or hardware damage caused by the inability to effectively restart after a system crash.

[0027] In some embodiments of this application, in order to simplify the circuit structure, reduce hardware costs, and make full use of the existing resources of the charging management chip, this application may also adopt a scheme in which the trigger signal is directly output from the control interface inside the charging management chip. For example, as Figure 2 As shown, the power management circuit 200 includes a charging management chip 210, which has a control interface GPIO. The charging management chip 210 is used to: switch the output state of the control interface GPIO of the charging management chip 210 from a first level state to a second level state to generate a trigger signal when no control instruction is received from the processor 400 within a preset time period; and output the trigger signal to the restart circuit 300 through the control interface GPIO of the charging management chip 210.

[0028] In this embodiment, the charging management chip 210 integrates a microcontroller, which is connected to a watchdog timer (not shown) inside the processor 400 to monitor whether the processor 400 periodically sends control commands. When the processor 400 is running normally and has not crashed, the processor 400 periodically sends control commands to the microcontroller of the charging management chip 210 via the SPMI bus or I2C bus. After receiving the control command, the microcontroller keeps the control interface GPIO in a first level state (e.g., a high level state). At this time, the restart circuit 300 does not operate, and the power management circuit 200 continues to supply power to the processor 400 normally.

[0029] When the processor 400 crashes and is unable to send control commands, the microcontroller of the charging management chip 210 determines that the processor 400 is in a crashed state if it does not receive control commands from the processor 400 within a preset time period. The microcontroller then switches the output state of the control interface GPIO from a first level state to a second level state, for example, from high level to low level, or from low level to high level. This level transition signal is output to the restart circuit 300 as a trigger signal through the control interface GPIO.

[0030] The control interface GPIO of the charging management chip 210 can be a general-purpose input / output interface or other types of electrical output interfaces. This application embodiment does not limit the specific type of the control interface of the power management circuit 200.

[0031] Thus, this embodiment integrates the trigger signal generation function into the microcontroller and GPIO control interface within the charging management chip 210, eliminating the need for additional independent detection chips or complex logic circuits. This enables autonomous detection of the processor 400's crash state and automatic generation of trigger signals. The charging management chip 210 utilizes its existing microcontroller resources and GPIO control interface, generating trigger signals simply by changing the output level of the GPIO. This results in a simple circuit structure, low cost, and ease of integration, while simultaneously improving system reliability and response speed, achieving rapid detection of the processor 400's crash state and efficient output of trigger signals.

[0032] In some embodiments of this application, in order to utilize the existing battery switch unit inside the charging management chip 210 to cut off the power supply path without adding additional external switching devices, further simplifying the circuit structure and reducing hardware costs, this application may also adopt a scheme in which the battery switch unit is turned off by the control interface GPIO of the charging management chip 210 through the first restart module 310.

[0033] For example, such as Figure 2 As shown, the charging management chip 210 includes a battery switch unit 211, and the output terminal of the battery module 100 is coupled to the voltage input terminal of the processor 400 through the battery switch unit 211. The restart circuit 300 includes a first restart module 310, and the control interface GPIO of the charging management chip 210 is coupled to the control terminal of the battery switch unit 211 through the first restart module 310. The first restart module 310 is used to: generate a first control signal according to the trigger signal, and output the first control signal to the control terminal of the battery switch unit 211 to turn off the battery switch unit 211 and stop the battery module 100 from supplying power to the processor 400.

[0034] In this embodiment, the battery switch unit 211 is a battery power supply switch (e.g., a MOSFET) integrated within the charging management chip 210, connected in series between the positive terminal of the battery module 100 and the voltage input terminal of the processor 400, used to control the on and off of the power supply path from the battery module 100 to the processor 400. The control terminal (e.g., the gate of the MOSFET) of the battery switch unit 211 is coupled to the output terminal of the first restart module 310, used to receive the first control signal output by the first restart module 310.

[0035] The first restart module 310 includes an impedance element (e.g., a resistor) or a level shifting circuit. Its input is connected to the control interface GPIO of the charging management chip 210, and its output is coupled to the control terminal of the battery switch unit 211. When the control interface GPIO of the charging management chip 210 outputs a trigger signal (e.g., switching from a high level to a low level), the first restart module 310 generates a first control signal based on the trigger signal, such as pulling the control terminal of the battery switch unit 211 low, thereby turning off the battery switch unit 211. After the battery switch unit 211 is turned off, the power supply path from the battery module 100 to the processor 400 is cut off, and the processor 400 is completely powered down.

[0036] Thus, this embodiment utilizes the battery switch unit 211 integrated within the charging management chip 210 as a power supply path cut-off switch, and converts the trigger signal output from the control interface GPIO into a first control signal recognizable by the control terminal of the battery switch unit 211 through the first restart module 310, thereby achieving the function of automatically cutting off the power supply path when the processor 400 crashes. This solution eliminates the need for additional external switching devices, fully utilizes the existing hardware resources of the charging management chip 210, and features a compact circuit structure, high integration, and low cost, while ensuring the reliability and response speed of the power supply path cut-off.

[0037] In a specific example, the battery switching unit 211 can be a transistor switch. For example, as... Figure 4 As shown, the battery switching unit 211 includes a battery switching transistor Q. bat Battery switching transistor Q bat The input terminal is connected to the battery module 100, and the battery switch transistor Q... bat The output terminal is coupled to the voltage input terminal of the processor 400, and the battery switching transistor Q... bat The control terminal is coupled to the control interface GPIO of the charging management chip 210 through the first restart module 310.

[0038] Battery switching transistor Q bat This refers to a metal-oxide-semiconductor field-effect transistor (MOSFET), including but not limited to N-channel MOSFETs or P-channel MOSFETs. Taking a P-channel MOSFET as an example, the battery switch Q... bat The input terminal is the source, connected to the positive terminal of the battery module 100; the battery switch transistor Q... bat The output terminal is the drain, connected to the voltage input terminal of the processor 400; the battery switch transistor Q... bat The control terminal is the gate, which is connected to the control interface GPIO of the charging management chip 210 through the first restart module 310.

[0039] The first restart module 310 includes a resistor R. pull resistance Rpull The first terminal is connected to the GPIO control interface of the charging management chip 210, and the resistor R pull The second terminal is connected to the battery switch transistor Q. bat The gate is coupled. When the control interface GPIO of the charging management chip 210 outputs a trigger signal (e.g., switching from high to low level), the battery switching transistor Q... bat The gate voltage is controlled by resistor R pull Pull low, causing the battery switch Q to... bat The gate-source voltage Vgs satisfies the turn-on threshold condition (for a P-channel MOSFET, it turns on when the gate voltage is lower than the source voltage), and the battery switch Q... bat The power supply path from battery module 100 to processor 400 is cut off. When the trigger signal disappears, the output state of the control interface GPIO returns from low to high, and the battery switch Q... bat The gate voltage is pulled high, and the battery switch Q... bat Reconnect to restore power supply from battery module 100 to processor 400.

[0040] Thus, in this embodiment of the application, a transistor switch (such as a MOSFET) is used as the battery switch Q. bat Utilizing its characteristics of fast switching speed, low on-resistance, and low power consumption, precise control of the power supply path from battery module 100 to processor 400 is achieved. This is achieved through resistor R... pull The first restart module 310, which is configured to directly convert the level signal output from the control interface GPIO of the charging management chip 210 into a signal used to control the battery switch transistor Q. bat The gate voltage is low, the circuit structure is simple, the response is fast, and the reliability is high. When the processor 400 crashes, the control interface GPIO outputs a trigger signal to instantly turn off the battery switch transistor Q. bat This completely shuts down the processor 400; after the trigger signal is released, the battery switch Q... bat Automatic power-on restoration enables the processor 400 to restart. This achieves automatic power-off and reset after a processor 400 crashes, while effectively reducing hardware costs and circuit complexity.

[0041] In some embodiments of this application, in order to utilize the existing battery protection function inside the charging management chip to achieve automatic disconnection of the power supply path without the need for additional control logic, further simplifying the circuit design and improving the reliability of system integration, this application may also adopt a scheme of triggering the battery protection unit through a level conversion element, so that the battery protection unit controls the battery switch unit to turn off.

[0042] For example, such as Figure 3As shown, the first restart module 310 includes a level conversion element 311, and the charging management chip 210 also includes a battery protection unit 212. The control interface GPIO of the charging management chip 210 is connected to the trigger terminal of the battery protection unit through the level conversion element 311, and the output terminal of the battery protection unit is coupled to the control terminal of the battery switch unit. The level conversion element 311 is used to: switch the voltage of the trigger terminal of the battery protection unit 212 from the first voltage value to the second voltage value when the output state of the control interface GPIO of the charging management chip 210 switches from the first level state to the second level state, so as to generate a first control signal; The battery protection unit 212 is used to: trigger the third control signal of the battery protection unit 212 according to the first control signal, and output the third control signal to the control terminal of the battery switch unit 211 to put the battery switch unit 211 in the off state.

[0043] For example, refer to Figure 4 When the first restart module 310 includes a level conversion element 311, the level conversion element 311 may specifically be a resistor element R. pull The control interface GPIO of the charging management chip 210 is connected via a resistor R. pull It is connected to the trigger terminal of the battery protection unit 212.

[0044] In this embodiment, the battery protection unit 212 is a battery protection circuit integrated within the charging management chip 210, including but not limited to a high-temperature protection circuit, an overvoltage protection circuit, an undervoltage protection circuit, or an overcurrent protection circuit. The battery protection unit 212 has a trigger terminal (e.g., a high-temperature detection terminal or an undervoltage detection terminal). When the voltage at the trigger terminal reaches a preset threshold, the battery protection unit 212 is triggered and outputs a third control signal, such as pulling down the control terminal of the battery switch unit 211, causing the battery switch unit 211 to turn off and cutting off the power supply path from the battery module 100 to the processor 400.

[0045] Level conversion element 311 is a resistive element R pull Its first end is connected to the control interface GPIO of the charging management chip 210, and its second end is connected to the trigger end of the battery protection unit 212. The trigger end of the battery protection unit 212 is also grounded through an external thermistor (such as an NTC thermistor), forming a voltage divider network.

[0046] When the processor 400 is running normally and has not crashed, the control interface GPIO of the charging management chip 210 maintains a first level state (e.g., high level), and the trigger terminal is connected to the resistor element R. pullWhen the voltage is pulled to a high level, if the voltage does not reach the protection trigger threshold of the battery protection unit 212, the battery protection unit 212 will not activate, the battery switch unit 211 will remain on, and the battery module 100 will supply power to the processor 400 normally.

[0047] When the processor 400 crashes, the output state of the control interface GPIO of the charging management chip 210 switches from a first level state to a second level state, for example, from a high level to a low level. The voltage at the trigger terminal is controlled by the resistor R. pull The voltage is pulled low, switching from the first voltage value (high voltage) to the second voltage value (low voltage). When the voltage at the trigger terminal drops below the trigger threshold of the battery protection unit 212, the battery protection unit 212 is triggered and outputs a third control signal to control the battery switch unit 211 to turn off, thereby cutting off the power supply from the battery module 100 to the processor 400.

[0048] Thus, in this embodiment of the application, a level conversion element 311 (e.g., a resistor element R) is provided. pull The control interface GPIO of the charging management chip 210 is connected to the trigger terminal of the battery protection unit 212. Utilizing the existing battery protection mechanism within the charging management chip 210, the battery protection unit 212 can be triggered simply by changing the output level of the control interface GPIO, thereby controlling the battery switch unit 211 to automatically shut down and cutting off the power supply path to the processor 400. This solution eliminates the need for an additional independent switch control circuit, fully utilizing the existing hardware resources and protection functions of the charging management chip 210. The circuit structure is more streamlined, and the system integration is higher. At the same time, the mature protection mechanism of the battery protection unit 212 ensures the reliability and safety of power supply cutoff, further reducing hardware costs and design complexity.

[0049] In this embodiment, the battery protection unit 212 may be an existing protection unit of the charging management chip 210, including but not limited to high temperature protection circuit, overvoltage protection circuit, undervoltage protection circuit or overcurrent protection circuit, etc.

[0050] For example, such as Figure 4 As shown, the battery protection unit 212 may include a battery temperature detection unit 2121, and the trigger terminal of the battery protection unit 212 is the temperature detection terminal of the battery temperature detection unit 2121.

[0051] The temperature detection terminal of the battery temperature detection unit 2121 is used to connect to an external temperature detection element (such as a thermistor NTC) to detect the temperature of the battery module 100. The temperature detection terminal is connected to a level conversion element 311 (such as a resistor R). pullThe temperature detection terminal is connected to the control interface GPIO of the charging management chip 210, and is also grounded through a thermistor NTC, forming a voltage divider network. When the battery module 100 temperature is normal, the voltage at the temperature detection terminal is within the normal operating voltage range, and the battery temperature detection unit 2121 does not trigger protection. When the output state of the control interface GPIO of the charging management chip 210 switches from the first level state to the second level state (e.g., from high level to low level), the voltage at the temperature detection terminal is connected to the resistor R. pull If the temperature is pulled down below the high-temperature protection trigger threshold of the battery temperature detection unit 2121, the battery temperature detection unit 2121 determines that the battery temperature is abnormal (simulating a high-temperature state), triggers a high-temperature protection signal, and outputs the protection signal to the control terminal of the battery switch unit 211, causing the battery switch unit 211 to turn off and cut off the power supply path from the battery module 100 to the processor 400.

[0052] Thus, this embodiment of the application utilizes the existing battery temperature detection unit 2121 inside the charging management chip 210 to transmit the control interface GPIO through the resistor element R. pull Connected to the temperature detection terminal, the system simulates high-temperature protection trigger conditions by changing the GPIO level state when the processor 400 crashes, achieving automatic power supply cutoff without the need for additional dedicated protection circuitry. This solution fully utilizes the existing temperature detection hardware resources of the charging management chip 210, resulting in a simple and low-cost circuit structure. Simultaneously, it leverages the mature and reliable high-temperature protection mechanism of the battery temperature detection unit 2121 to ensure the stability and safety of power supply cutoff.

[0053] For example, such as Figure 5 As shown, the battery protection unit 212 includes a battery undervoltage protection unit 2122; the trigger terminal of the battery protection unit 212 is the voltage detection terminal of the battery undervoltage protection unit 2122.

[0054] The voltage detection terminal of the battery undervoltage protection unit 2122 is used to detect the voltage of the battery module 100. When the voltage of the battery module 100 is lower than a preset undervoltage protection threshold, the battery undervoltage protection unit 2122 triggers an undervoltage protection signal, controlling the battery switch unit 211 to turn off, thereby preventing the battery module 100 from being damaged due to over-discharge. The voltage detection terminal is connected to a level conversion element 311 (e.g., a resistor R). pull The voltage detection terminal is connected to the control interface GPIO of the charging management chip 210, and is also connected to the positive terminal of the battery module 100 through a voltage divider resistor to obtain the battery voltage sampling signal. When the output state of the control interface GPIO of the charging management chip 210 switches from the first level state to the second level state (e.g., from high level to low level), the voltage at the voltage detection terminal is transmitted through the resistor element R. pullIf the voltage is pulled down below the undervoltage protection trigger threshold of the battery undervoltage protection unit 2122, the battery undervoltage protection unit 2122 determines that the battery voltage is too low, triggers the undervoltage protection signal, and outputs the protection signal to the control terminal of the battery switch unit 211, causing the battery switch unit 211 to turn off and cut off the power supply path from the battery module 100 to the processor 400.

[0055] Thus, this embodiment utilizes the existing battery undervoltage protection unit 2122 within the charging management chip 210, connecting the control interface GPIO to the voltage detection terminal via a resistor Rpull. When the processor 400 crashes, the undervoltage protection trigger condition is simulated by changing the GPIO level, thereby achieving automatic power supply disconnection. This solution also fully utilizes the existing undervoltage protection hardware resources of the charging management chip 210, completing the power-off reset function without adding extra components. The circuit design is simple and highly reliable. Furthermore, the mature undervoltage protection mechanism of the battery undervoltage protection unit 2122 ensures the accuracy and timeliness of power supply disconnection.

[0056] In some embodiments of this application, in order to provide sufficient reset time after the processor is powered off, ensure that the residual charge on the processor's internal registers and capacitors is completely released, and enable the processor to restart in a clean state, avoiding startup abnormalities caused by incomplete reset, this application may also adopt a scheme of setting a delay module to automatically restore power supply after a preset delay time after power failure.

[0057] For example, such as Figure 2 As shown, the power management circuit 200 also includes a delay module 220, and the restart circuit 300 may also include a second restart module 320. The output terminal of the battery switch unit 211 is connected to the second restart module 320 through the delay module 220, and the second restart module 320 is coupled to the control terminal of the battery switch unit 211. The delay module 220 is used to: generate an enable signal after the battery switch unit 211 is in the off state and after a preset delay, and output the enable signal to the second restart module 320; The second restart module 320 is used to: generate a second control signal according to the enable signal, and output the second control signal to the control terminal of the battery switch unit 211 to turn on the battery switch unit 211 so that the battery module 100 can supply power to the processor 400 again.

[0058] In this embodiment, the delay module 220 is connected between the output of the battery switch unit 211 and the input of the second restart module 320. When the battery switch unit 211 is turned off, the voltage at its output (i.e., the voltage input of the processor 400) begins to drop; the delay module 220 detects this voltage drop or directly detects the off state of the battery switch unit 211 and starts timing. The delay module 220 includes a timing circuit for setting a preset duration, such as 2 to 5 seconds. This preset duration is sufficient for all registers, caches, and filter capacitors on the power lines inside the processor 400 to discharge, ensuring that the processor 400 is completely powered off. When the preset duration is reached, the delay module 220 generates an enable signal and outputs it to the second restart module 320.

[0059] The second restart module 320 includes a switch control circuit, whose input is connected to the output of the delay module 220, and whose output is connected to the control terminal of the battery switch unit 211. When the second restart module 320 receives an enable signal, it generates a second control signal (e.g., pulls the control terminal of the battery switch unit 211 high), causing the battery switch unit 211 to turn on again and restoring the power supply from the battery module 100 to the processor 400.

[0060] Thus, this embodiment of the application, by setting a delay module 220 and a second restart module 320, automatically delays for a preset time after the battery switch unit 211 is turned off, and automatically controls the battery switch unit 211 to turn back on and restore power supply after the processor 400 has completely lost power. This scheme ensures that the processor 400 is in a completely zero-potential state before being powered on again, avoiding problems such as incomplete reset or abnormal startup caused by residual charge. At the same time, the delay module 220 uses the voltage change at the output of the battery switch unit 211 as a trigger condition, without the need for additional control signals, realizing the function of automatic delay after power failure. The circuit structure is simple and reliable, providing sufficient time for the stable restart of the processor 400, further improving the success rate of self-recovery from crashes and the operational stability of the system.

[0061] In some embodiments of this application, in order to achieve automatic delayed power restoration while retaining the physical path for manual restart by the user, and to ensure that the system can still be restarted by button operation when automatic restoration fails or the user needs to actively intervene, thereby improving the reliability of the system and the flexibility of user operation, this application may also adopt a scheme that combines the power button with a toggle switch, so that the delay module and the power button jointly control the battery switching unit.

[0062] For example, such as Figure 3 As shown, the second restart module 320 includes a switch 321; the power supply circuit also includes a power button 500. The output terminal of the battery switch unit 211 is connected to the enable terminal of the switch 321 through the delay module 220. The power button 500 is connected to the first input terminal of the switch 321. The second input terminal of the switch 321 is grounded. The output terminal of the switch 321 is coupled to the control terminal of the battery switch unit 211. The switching switch 321 is used to: connect the second input terminal and the output terminal of the switching switch 321 according to the enable signal output by the delay module 220, so that the output state of the switching switch 321 is switched from the third level state to the fourth level state to generate the second control signal.

[0063] In this embodiment, the switch 321 is a single-pole double-throw switch or an analog switch, having at least an enable terminal EN, a first input terminal A1, a second input terminal A2, and an output terminal B. The enable terminal EN of the switch 321 is connected to the output terminal of the delay module 220 to receive the enable signal generated by the delay module 220; the first input terminal A1 of the switch 321 is connected to the power button 500, and the other end of the power button 500 is grounded; the second input terminal A2 of the switch 321 is grounded; and the output terminal B of the switch 321 is connected to the control terminal of the battery switch unit 211.

[0064] The switch 321 may also have a power interface VDD, which is connected to the positive terminal of the battery module 100. The switch 321 can obtain the battery voltage Vbat from the battery module 100 through the power interface VDD.

[0065] The switch 321 may also have an integrated circuit bus interface (I2C). The I2C interface of the switch 321 is connected to the I2C interface of the processor 400 via the data line I2C_SDA and the clock line I2C_CLK. The switch 321 can obtain control commands output by the processor 400 through the integrated circuit bus (Inter-Integrated Circuit) via the I2C interface to configure the default mode of the switch 321 (such as turning on the first input terminal A1 and the output terminal B).

[0066] When the delay module 220 does not output an enable signal (i.e., the preset delay duration has not been reached), the switch 321 is in the default state, and its output is connected to the first input. At this time, the battery switch unit 211 remains in the off state, and the processor 400 continues to be in the power-off state.

[0067] When the delay module 220 reaches the preset delay duration, it generates an enable signal and outputs it to the enable terminal of the switch 321. The switch 321 responds to the enable signal by switching its state, connecting its output terminal to the second input terminal, thus changing the output state of the switch 321 from the third level state to the fourth level state, thereby generating a second control signal. For example, the switch from the third level state to the fourth level state can be a switch from a high level state to a low level state. The second control signal can be a low-level signal output by the switch 321 to the constant power unit 213. At this time, the power button signal is forcibly pulled low, simulating the user pressing the power button 500. The control signal output by the constant power unit 213 is transmitted to the control terminal of the battery switch unit 211 via the switch control unit 214, turning on the battery switch unit 211 and restoring power supply from the battery module 100 to the processor 400.

[0068] Thus, this embodiment combines the automatic recovery control of the delay module 220 with the manual control of the power button 500 by setting a switch 321. After a preset power outage time, the delay module 220 controls the switch 321 to switch to the second input terminal, simulating the state of the user pressing the power button 500. This provides a path for automatic recovery while retaining the user's ability to manually start the system via the power button 500.

[0069] In some embodiments of this application, in order to achieve precise and reliable delay control while taking into account the flexibility and integration of circuit design, enabling the delay module to be flexibly configured with delay time according to actual needs and adapt to different chip architectures and design cost requirements, this application may also adopt a scheme in which the delay module is composed of a clock unit and a timing capacitor. For example, as Figure 3 As shown, the delay module 220 includes a clock unit 221 and a timing capacitor 222. The output terminal of the battery switch unit 211 is connected to the input terminal of the clock unit 221, the output terminal of the clock unit 221 is connected to the timing capacitor 222, and the output terminal of the clock unit 221 is also connected to the enable terminal of the switch 321.

[0070] In this embodiment, the clock unit 221 is a timing circuit. Its input terminal (i.e., power supply terminal or trigger terminal) is connected to the output terminal of the battery switch unit 211 to detect the off state of the battery switch unit 211 and obtain the working power. The output terminal (i.e., timing terminal) of the clock unit 221 is connected to the timing capacitor 222 to set the delay time constant through the timing capacitor 222. The output terminal of the clock unit 221 is also connected to the enable terminal of the switch 321 to output an enable signal for controlling the switch 321 after the delay reaches the preset duration.

[0071] The timing capacitor 222 is an external capacitor, and its capacitance value determines the delay time of the clock unit 221. Specifically, the delay time is positively correlated with the capacitance value of the timing capacitor 222; the larger the capacitance value, the longer the delay time. By selecting timing capacitors 222 with different capacitance values, the preset duration of the delay module 220 (e.g., 5 seconds, 10 seconds, etc.) can be flexibly configured to adapt to the power-down reset time requirements of different processors 400.

[0072] When the battery switch unit 211 is turned off, its output voltage begins to drop. The clock unit 221 detects this state change and starts timing. The clock unit 221 controls the timing cycle through the charging and discharging process of the timing capacitor 222. When the timing reaches the preset duration set by the timing capacitor 222, the second terminal of the clock unit 221 outputs an enable signal to the enable terminal of the switching switch 321, triggering the switching switch 321 to switch channels.

[0073] Clock unit 221 can be an independent clock unit located outside the discharge management chip 230, or it can be a clock unit RTC located inside the discharge management chip 230. For example, refer to... Figure 3 Clock unit 221 can be an independent clock unit located outside the discharge management chip 230. For example, see reference... Figure 4 The power management circuit 200 also includes a discharge management chip 230. The clock unit 221 can be a clock unit RTC located inside the discharge management chip 230, and the timing capacitor 222 can be a capacitor Crtc located outside the discharge management chip 230.

[0074] In one implementation, such as Figure 3 As shown, the clock unit 221 uses an independent discrete timing chip or RC delay circuit, located around the discharge management chip 230. This solution has an intuitive circuit structure, flexible component selection, and facilitates adjustment of delay parameters according to different product requirements.

[0075] In another implementation, such as Figure 4As shown, the clock unit 221 is integrated inside the discharge management chip 230 and is the Real-Time Clock (RTC) unit built into the discharge management chip 230. The RTC unit of the discharge management chip 230 is typically used for functions such as system timed wake-up and time maintenance. It is externally connected to a timing capacitor Crtc to set the timing reference of the RTC. In this embodiment, the existing RTC unit and the external timing capacitor Crtc are used to form a delay module 220. The output terminal of the battery switch unit 211 is connected to the trigger terminal of the RTC unit. When the battery switch unit 211 is turned off, the RTC unit starts timing. After the timing reaches the duration set by the Crtc capacitor, the RTC unit outputs an enable signal. This solution makes full use of the existing hardware resources of the discharge management chip 230, without the need to add an additional timing chip. It has high circuit integration and low cost. At the same time, the RTC unit has high timing accuracy and stability, which can ensure the accuracy of delay control.

[0076] Thus, this embodiment of the application achieves precise control over the power restoration time after a power outage by using a delay module 220 composed of a clock unit 221 and a timing capacitor 222. The clock unit 221 detects the off state of the battery switch unit 211 and starts timing. The timing capacitor 222 is used to set the delay time constant. By selecting different values ​​of the timing capacitor 222, the delay time can be flexibly configured to meet the power-down reset time requirements of different processors 400. Simultaneously, this embodiment of the application provides two implementation methods: a peripheral solution using an independent clock unit, which offers flexible design and free component selection; and an integrated solution using the internal RTC unit of the discharge management chip 230, which fully utilizes existing hardware resources, has high integration, and low cost. Both solutions can achieve precise and reliable delay control, providing sufficient power-down reset time for the processor 400, ensuring that the system can restart in a clean state, significantly improving the success rate of self-recovery from crashes and the operational stability of the system.

[0077] In some embodiments of this application, in order to achieve automatic power-off reset after the processor 400 crashes under the architecture of separate charging management chip 210 and discharging management chip 230, and to make full use of the hardware resources and control interfaces of the two chips to improve the flexibility and compatibility of system design, this application may also adopt a scheme of triggering hardware reset of discharging management chip 230 through third restart module 330 to stop power supply, and triggering constant power unit 213 through fourth restart module 340 to restore power supply.

[0078] For example, such as Figure 6 As shown, the power management circuit 200 also includes a discharge management chip 230; the battery module 100 is connected to the voltage input terminal of the discharge management chip 230 through the charging management chip 210, and the voltage output terminal of the discharge management chip 230 is connected to the voltage input terminal of the processor 400. The restart circuit 300 includes a third restart module 330 and a fourth restart module 340; the charging management chip 210 includes a constant power unit 213; the control interface GPIO of the charging management chip 210 is connected to the reset terminal RESET_N of the discharge management chip 230 through the third restart module 330; the control interface GPIO of the charging management chip 210 is connected to the constant power unit 213 through the fourth restart module 340, and the constant power unit 213 is connected to the control terminal of the discharge management chip 230 through the control terminal of the charging management chip 210; The third restart module 330 is used to: generate a first control signal according to the trigger signal, and output the first control signal to the reset terminal RESET_N of the discharge management chip 230 to trigger the discharge management chip 230 to reset, so that the battery module 100 stops supplying power to the processor 400; The fourth restart module 340 is used to: generate a second control signal according to the trigger signal, and output the second control signal to the charging management chip 210, so that the charging management chip 210 triggers the discharge management chip 230 to power on according to the second control signal, so that the battery module 100 re-supply the processor 400.

[0079] In this embodiment, the third restart module 330 generates a first control signal based on the trigger signal and outputs the first control signal to the reset terminal RESET_N of the discharge management chip 230, triggering a hardware reset of the discharge management chip 230. The reset terminal RESET_N of the discharge management chip 230 can use the reset signal as an enable signal for the voltage adjustment unit 231, turning off the voltage adjustment unit 231, thereby stopping the battery module 100 from supplying power to the processor 400.

[0080] In this embodiment, the fourth restart module 340 generates a second control signal based on the trigger signal and outputs the second control signal to the constant power unit 231 inside the charging management chip 210. After receiving the second control signal, the constant power unit 231 follows the power-on sequence to restore power supply from the battery module 100 to the processor 400. That is, after the constant power unit 231 receives the second control signal, the charging management chip 210 outputs a power-on command to the discharge management chip 230 via the SPMI bus. According to the power-on command, the discharge management chip 230 reopens the voltage adjustment unit 231, thereby restoring power supply from the battery module 100 to the processor 400.

[0081] In this embodiment, the charging management chip 210 is a charging management integrated circuit (Charger PMIC), which integrates a constant power unit 213. The constant power unit 213 is an Always On Domain module that maintains power supply even in system standby or power-off states, maintaining the basic functions of the charging management chip 210, including the SPMI / I2C communication interface, wake-up logic, and power-on timing control. The constant power unit 213 is connected to the control terminal of the discharge management chip 230 via the SPMI bus or I2C bus, and is used to send power-on commands to the discharge management chip 230.

[0082] In this embodiment, the discharge management chip 230 is a system power management integrated circuit (System PMIC), which integrates a voltage adjustment unit 231. The voltage adjustment unit 231 includes, but is not limited to, a DC-DC converter and an LDO, used to convert the voltage provided by the battery module 100 into various operating voltages required by the processor 400. The discharge management chip 230 has a reset pin RESET_N, which is active low. When the RESET_N pin is pulled low, the discharge management chip 230 performs a hardware reset operation, shuts down the voltage adjustment unit 231, and stops supplying power to the processor 400.

[0083] The third restart module 330 has its input connected to the control interface GPIO of the charging management chip 210, and its output connected to the reset terminal RESET_N of the discharging management chip 230. When the control interface GPIO of the charging management chip 210 outputs a trigger signal (e.g., switching from low to high), the third restart module 330 generates a first control signal (e.g., a low-level signal) to pull the reset terminal RESET_N of the discharging management chip 230 low, triggering a hardware reset of the discharging management chip 230. After performing a hardware reset, the discharging management chip 230 shuts down the voltage adjustment unit 231 and stops supplying power to the processor 400.

[0084] The fourth restart module 340 has its input connected to the control interface GPIO of the charging management chip 210, and its output connected to the trigger terminal of the constant power unit 213. When the control interface GPIO of the charging management chip 210 outputs a trigger signal, the fourth restart module 340 generates a second control signal (such as a low-level signal) and outputs the second control signal to the constant power unit 213. After receiving the second control signal, the constant power unit 213 triggers a power-on sequence: the constant power unit 213 sends a power-on command to the discharge management chip 230 via the SPMI bus, and the discharge management chip 230 reopens the voltage adjustment unit 231 according to the power-on command, restoring power supply to the processor 400.

[0085] The third restart module 330 generates a first control signal based on the trigger signal and outputs the first control signal to the RESET_N terminal of the discharge management chip 230, triggering a hardware reset of the discharge management chip 230. The RESET_N terminal of the discharge management chip 230 can use the reset signal as an enable signal for the voltage adjustment unit 231, turning off the voltage adjustment unit 231, thereby stopping the battery module 100 from supplying power to the processor 400.

[0086] The fourth restart module 340 generates a second control signal based on the trigger signal and outputs the second control signal to the constant power unit 231 inside the charging management chip 210. After receiving the second control signal, the constant power unit 231 follows the power-on sequence to restore power supply from the battery module 100 to the processor 400. That is, after the constant power unit 231 receives the second control signal, the charging management chip 210 outputs a power-on command to the discharge management chip 230 via the SPMI bus. According to the power-on command, the discharge management chip 230 reopens the voltage adjustment unit 231, thereby restoring power supply from the battery module 100 to the processor 400.

[0087] Thus, this embodiment of the application, by setting up a third restart module 330 and a fourth restart module 340, achieves an automatic power-off reset function after the processor 400 crashes, under a hardware architecture where the charging management chip 210 and the discharging management chip 230 are separate. The third restart module 330 utilizes the RESET_N pin of the discharging management chip 230 to trigger a hardware reset by pulling this pin low, quickly shutting down the voltage adjustment unit 231 and cutting off the power supply path. The fourth restart module 340 utilizes the constant power unit 213 inside the charging management chip 210 to trigger the constant power unit 213 to start a power-on sequence, sending a power-on command to the discharging management chip 230 via the SPMI bus, thereby restoring the power supply path. This solution fully adapts to the hardware characteristics of the dual-chip architecture, utilizing the hardware reset mechanism of the discharging management chip 230 and the constant power unit control capability of the charging management chip 210 respectively. It achieves a complete power-off reset process without adding additional complex control circuits, exhibiting good architectural compatibility and design flexibility, and providing a feasible implementation path for self-recovery solutions after crashes on different hardware platforms.

[0088] In some embodiments of this application, in order to realize the functions of the third restart module and the fourth restart module with the simplest circuit structure, the switching characteristics of the switching elements are utilized to directly control the reset signal and the trigger signal of the constant power unit through the control interface, thereby further reducing hardware costs and circuit complexity. This application may also adopt a scheme in which the fourth restart module is composed of the first switching element and the third restart module is composed of the second switching element.

[0089] For example, such as Figure 7As shown, the fourth restart module 340 includes a first switching element Q1; the output terminal of the first switching element Q1 is coupled to the constant power unit 213, the input terminal of the first switching element Q1 is grounded, and the control terminal of the first switching element Q1 is connected to the control interface GPIO of the charging management chip 210. The third restart module 330 includes a second switching element Q2; the output terminal of the second switching element Q2 is connected to the reset terminal of the discharge management chip 230, the input terminal of the second switching element Q2 is grounded, and the control terminal of the second switching element Q2 is connected to the control interface GPIO of the charging management chip 210. The first switching element Q1 is used to: enter the conducting state under the drive of the trigger signal, so that the output state of the first switching element Q1 switches from the fifth level state to the sixth level state to generate the second control signal; The second switching element Q2 is used to: enter the conducting state under the drive of the trigger signal, so that the output state of the second switching element Q2 switches from the seventh level state to the eighth level state, so as to generate the first control signal.

[0090] In the embodiments of this application, both the first switching element Q1 and the second switching element Q2 can be metal-oxide-semiconductor field-effect transistors (MOSFETs) or bipolar junction transistors (BJTs), including but not limited to N-channel MOSFETs and NPN transistors. Taking an N-channel MOSFET as an example, the output terminal of the switching element is the drain, the input terminal is the source, and the control terminal is the gate.

[0091] The drain of the second switching element Q2 is connected to the reset terminal RESET_N of the discharge management chip 230, its source is grounded, and its gate is connected to the control interface GPIO of the charging management chip 210. When the output state of the control interface GPIO of the charging management chip 210 switches from a first level state (e.g., low level) to a second level state (e.g., high level), the second switching element Q2 is turned on, causing its output state to switch from a seventh level state (e.g., high level) to an eighth level state (e.g., low level), thereby generating a first control signal. The first control signal can be a low-level signal. The drain of the second switching element Q2 is pulled low to ground, and the reset terminal RESET_N of the discharge management chip 230 is pulled low, triggering a hardware reset of the discharge management chip 230, turning off the voltage adjustment unit 231, and stopping the power supply to the processor 400.

[0092] The drain of the first switching element Q1 is coupled to the constant power unit 213, the source of the first switching element Q1 is grounded, and the gate of the first switching element Q1 is connected to the control interface GPIO of the charging management chip 210. When the output state of the control interface GPIO of the charging management chip 210 switches from the fifth level state (e.g., low level) to the sixth level state (e.g., high level), the first switching element Q1 is turned on, causing the output state of the first switching element Q1 to switch from the fifth level state (e.g., high level) to the sixth level state (e.g., low level) to generate a second control signal. The second control signal can be a low level signal. The drain of the first switching element Q1 is pulled low to ground, and the second control signal (e.g., low level signal) is output to the constant power unit 231, triggering the power-on sequence and causing the battery module 100 to power the processor 400 again. That is, after the constant power unit 231 receives the second control signal (such as a low level signal), the control terminal of the charging management chip 210 outputs a power-on command to the control terminal of the discharge management chip 230 through the SPMI bus. According to the power-on command, the discharge management chip 230 reopens the voltage adjustment unit 231, thereby enabling the battery module 100 to supply power to the processor 400 again.

[0093] In the specific operating sequence, when the charging management chip 210 detects that the processor 400 has crashed, the control interface GPIO outputs a high-level trigger signal. This high-level signal simultaneously turns on the first switching element Q1 and the second switching element Q2: the second switching element Q2 pulls down the RESET_N terminal of the discharge management chip 230, triggering a hardware reset of the discharge management chip 230 and shutting down the voltage adjustment unit 231; the first switching element Q1 turns on, outputting a low-level signal to the constant power unit 231, initiating the power-on sequence, and allowing the battery module 100 to resume power supply to the processor 400. The two control paths work together to ensure that the processor 400 is completely powered off.

[0094] Thus, this embodiment of the application achieves automatic power-off reset after the processor 400 crashes by using a first switching element Q1 to form the fourth restart module 340 and a second switching element Q2 to form the third restart module 330, with a very simple circuit structure. Both switching elements are standard MOSFETs or transistors, which are characterized by low cost, fast switching speed, and simple control. A single trigger signal output from the GPIO control interface of the charging management chip 210 can simultaneously control the two switching elements, realizing hardware reset (controlled by the second switching element Q2 to control the RESET_N terminal of the discharge management chip 230) and power-on (controlled by the first switching element Q1 to control the constant power unit 231 to follow the power-on timing sequence). The two control paths work together to ensure that the processor 400 is completely powered off and reset. This solution does not require additional complex control logic or dedicated chips, the circuit structure is simple and clear, the number of components is small, the PCB area occupied is small, significantly reducing hardware costs and design complexity, while ensuring the reliability and response speed of the power-off reset operation.

[0095] In some embodiments of this application, in order to achieve the automatic reset function in case of system crash while retaining the original path of manual forced restart by the user through physical buttons, and to ensure that the system can still be restarted through traditional button operation when the automatic reset function fails or the user needs to actively intervene, thus achieving seamless compatibility between automatic reset and manual reset, this application may also adopt a scheme of connecting the first switching element in parallel with the power button and the second switching element in parallel with the combination button.

[0096] For example, such as Figure 7 As shown, the power supply circuit 10 also includes a power button 500 and a combination button 600. The power button 500 is coupled to the constant power unit 213, and the combination button 600 is coupled to the reset terminal of the discharge management chip 230. The output terminal of the first switching element Q1 is connected to the power button 500 and is located between the power button 500 and the constant power unit 213. The output terminal of the second switching element Q2 is connected to the combination button 600 and is located between the combination button 600 and the reset terminal of the discharge management chip 230.

[0097] In this embodiment, the power button 500 is a physical button switch. One end of the power button 500 is grounded, and the other end is coupled to the control terminal of the battery switch unit 211 through the constant power unit 213. When the user presses the power button 500, the power button 500 is turned on, transmitting the power button signal to the constant power unit 213. Then, the control terminal of the charging management chip 210 outputs a power-on command to the control terminal of the discharge management chip 230 via the SPMI bus. According to the power-on command, the discharge management chip 230 reopens the voltage adjustment unit 231, thereby allowing the battery module 100 to resume power supply to the processor 400. Furthermore, the constant power unit 213 can also control the control terminal of the battery switch unit 211 based on the power button signal, turning on the battery switch unit 211 to achieve the power-on or power-restoration function.

[0098] The combination button 600 is a physical button switch (such as the volume up or volume down button), with one end grounded and the other end coupled to the reset terminal RESET_N of the discharge management chip 230. When the user presses the power button 500 and the combination button 600 simultaneously, the reset terminal RESET_N is pulled low to ground, triggering a hardware reset of the discharge management chip 230 and performing a forced restart operation.

[0099] The output terminal (drain) of the first switching element Q1 is connected to the connection node between the power button 500 and the constant power unit 213, so that the first switching element Q1 and the power button 500 are electrically connected in parallel. When the first switching element Q1 is turned on, it achieves the same power-on effect as pressing the power button 500. The two share the same control path, do not interfere with each other, and serve as backups for each other.

[0100] The output terminal (drain) of the second switching element Q2 is connected to the connection node between the combination button 600 and the reset terminal RESET_N of the discharge management chip 230, thus forming an electrical parallel connection between the second switching element Q2 and the combination button 600. When the second switching element Q2 is turned on, it pulls the reset terminal RESET_N low to ground, achieving the same hardware reset effect as when the user presses the combination button 600. Both share the same reset path, do not interfere with each other, and serve as backups for each other.

[0101] In automatic reset mode, when the charging management chip 210 detects that the processor 400 has crashed, the control interface GPIO outputs a high-level trigger signal, and simultaneously turns on the first switch element Q1 and the second switch element Q2: the second switch element Q2 turns on, simulating the reset effect of pressing the combination button 600, pulling the reset terminal RESET_N low, and powering off the processor; the first switch element Q1 turns on, simulating the power-on effect of pressing the power button 500, and the system automatically restores power supply and completes automatic restart.

[0102] In manual reset mode, when a user needs to force a restart, they can press the power button 500 and the combination button 600 simultaneously to complete the forced restart operation. This manual operation path is independent of the automatic reset path and does not affect each other.

[0103] Thus, this embodiment of the application achieves the organic integration of automatic and manual reset circuits by connecting the first switching element Q1 in parallel between the power button 500 and the constant power unit 213, and connecting the second switching element Q2 in parallel between the combination button 600 and the reset terminal RESET_N of the discharge management chip 230. When the processor 400 crashes, the charging management chip 210 controls the first switching element Q1 and the second switching element Q2 to conduct through the control interface GPIO, simulating the electrical effect of the user simultaneously pressing the power button 500 and the combination button 600, and completing the automatic power-off reset. When the automatic reset function fails or the user needs to actively intervene, the user can still complete the forced restart through the traditional physical button operation. This solution retains the original function of manual operation by the user and adds the new function of automatic reset. Both share the same control path, without adding additional hardware interfaces or changing user habits, achieving seamless compatibility between automatic and manual reset, and significantly improving the reliability, compatibility and user experience of the system.

[0104] In some embodiments of this application, in order to combine the hardware reset function of the discharge management chip with the enable control of the voltage adjustment unit, so that the hardware reset signal can directly control the output state of the voltage adjustment unit, simplify the internal control logic of the chip, and improve the speed and reliability of the reset response, this application may also adopt a scheme of connecting the enable terminal of the voltage adjustment unit with the reset terminal, so that the hardware reset signal is used as the output enable control of the voltage adjustment unit.

[0105] For example, such as Figure 7 As shown, the discharge management chip 230 includes a voltage adjustment unit 231; the input terminal of the voltage adjustment unit 231 is the voltage input terminal of the discharge management chip 230, the output terminal of the voltage adjustment unit 231 is the voltage output terminal of the discharge management chip 230, and the enable terminal of the voltage adjustment unit 231 is connected to the reset terminal of the discharge management chip 230. The voltage adjustment unit 231 includes at least one of the following: a DC-DC converter and a low-dropout linear regulator.

[0106] In this embodiment, the discharge management chip 230 integrates a voltage adjustment unit 231, which converts the input voltage (e.g., 3.7V to 4.4V) provided by the battery module 100 into various operating voltages required by the processor 400 (e.g., core voltage 0.8V to 1.2V, I / O voltage 1.8V to 3.3V, analog circuit voltage 3.3V, etc.). The voltage adjustment unit 231 includes, but is not limited to, a DC-DC converter (DCDC converter) and a low-dropout linear regulator (LDO). The DCDC converter is used for high-efficiency voltage conversion and is suitable for high-current power supply scenarios; the LDO is used for low-noise voltage conversion and is suitable for powering noise-sensitive analog and radio frequency circuits.

[0107] The voltage adjustment unit 231 has an enable terminal (EN), which is directly connected to the reset terminal RESET_N of the discharge management chip 230. The reset terminal RESET_N is active low. When the RESET_N pin is pulled low, the enable terminal of the voltage adjustment unit 231 receives a low-level signal, the voltage adjustment unit 231 is disabled, its output is turned off, and power supply to the processor 400 is stopped. When the RESET_N pin returns to a high level, the enable terminal of the voltage adjustment unit 231 receives a high-level signal, the voltage adjustment unit 231 is enabled, its output voltage is re-established, and power supply to the processor 400 is resumed.

[0108] By connecting the enable terminal of the voltage adjustment unit 231 to the reset terminal RESET_N, the discharge management chip 230 does not require additional reset control logic; the hardware reset signal directly serves as the output enable control signal for the voltage adjustment unit 231. When the reset terminal RESET_N is pulled low by an external circuit (such as the second switching element Q2 or the combination button 600), the voltage adjustment unit 231 immediately shuts off its output; when the enable terminal EN of the voltage adjustment unit 231 returns to a high level, the voltage adjustment unit 231 immediately resumes its output. This direct connection method achieves synchronous control of the reset signal and the power output, with minimal delay in the reset response.

[0109] In practical operation, when the processor 400 crashes, the GPIO control interface of the charging management chip 210 outputs a high-level trigger signal, turning on the second switching element Q2 and pulling the reset pin RESET_N of the discharge management chip 230 low. After the reset pin RESET_N is pulled low, the enable pin of the voltage adjustment unit 231 receives a low-level signal, and the voltage adjustment unit 231 immediately shuts off its output, causing the processor 400 to lose power and completing the power-off operation. The first switching element Q1 turns on, outputting a low-level signal to the constant power unit 231, initiating the power-on sequence. The charging management chip 210 outputs a power-on command (e.g., a high-level signal) to the discharge management chip 230 via the SPMI bus. The enable pin of the voltage adjustment unit 231 receives the high-level signal, the voltage adjustment unit 231 re-establishes its output, the processor 400 is powered back, and the restart operation is completed.

[0110] Thus, this embodiment of the application directly connects the enable terminal of the voltage adjustment unit 231 inside the discharge management chip 230 to the reset terminal RESET_N, realizing direct control of the output state of the voltage adjustment unit 231 by the hardware reset signal. When the reset terminal RESET_N is pulled low, the enable terminal of the voltage adjustment unit 231 is simultaneously pulled low, and the voltage adjustment unit 231 immediately shuts off its output, stopping power supply to the processor 400; when the enable terminal of the voltage adjustment unit 231 returns to a high level, the voltage adjustment unit 231 immediately resumes its output, resuming power supply to the processor 400. This solution eliminates the need for a complex reset state machine or additional control logic inside the discharge management chip 230, resulting in the shortest control path between the reset signal and the power output and the fastest response speed, effectively shortening the power-off reset time of the processor 400. Simultaneously, the voltage adjustment unit 231 employs a combination of a DC-DC converter and an LDO, enabling it to efficiently and stably provide multiple operating voltages to the processor 400, meeting the power supply requirements of the processor 400 in different operating modes, and ensuring power quality and stability of the system in both normal operation and reset / restart states.

[0111] Furthermore, based on a concept similar to the power supply circuit provided in the above embodiments of this application, this application also provides an electronic device.

[0112] like Figure 8 As shown, this application embodiment also provides an electronic device 800, including the power supply circuit provided in any embodiment of this application.

[0113] It should be noted that the electronic device 800 provided in the embodiments of this application may include the power supply circuit provided in any embodiment of this application and implement all the functions of the power supply circuit. To avoid repetition, it will not be described again here.

[0114] In this embodiment, the electronic device 800 can be a device with communication capabilities. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a smartwatch, mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), etc., and this embodiment does not specifically limit the functionality.

[0115] In practical applications, the electronic device provided in the embodiments of this application includes Figure 4 Taking the power supply circuit shown as an example, the charging PMIC detects a system crash and forcibly disconnects the system power supply, while simultaneously triggering a power-on restart to achieve automatic restart of the processor after power failure. Specifically, when the processor is active, the processor's watchdog timer expires, and the processor automatically feeds the watchdog. The processor sends a command to the charging PMIC via the SPMI bus, using the charging PMIC's own GPIO (default PD pull-down state) to pull the output high as an external pull-up for the battery temperature signal. When the processor's watchdog is not fed, the system has crashed, and the PMIC has not received an SPMI command within a preset time period. The charging PMIC's GPIO returns to the default low level state, at which point the battery temperature signal is pulled low, forcibly triggering the PMIC's high-temperature protection function and disconnecting Q. bat (Same as ship mode operation) Disconnect Vbat and VPH power supplies. The system will power down directly. At the same time, the VPH delay module acts as the enable control for the switching switch. When VPH drops to 0V, the power button is pulled low, triggering Q. bat Turn on (same as exiting ship mode operation), power on VPH, and set the delay module's delay to more than 2 seconds, which is just enough to meet the system restart time, allowing the system to restart and enter the system desktop.

[0116] In this embodiment, the processor 400 may be a central processing unit (CPU). The CPU controls the register configuration of the switching switch 321 via the I2C bus. The CPU's SPMI bus is connected to the power PMIC and charging PMIC for mutual instruction control and data transmission. The CPU has a watchdog module that is responsible for feeding the system to ensure normal system operation. The CPU has a power module that is responsible for receiving power from the power PMIC to power the various modules inside the CPU. The CPU has a GPIO module that serves as an interface for instruction and data interaction with peripherals.

[0117] In this embodiment, the charging management chip 210 can be a charging PMIC, and the discharging management chip 230 can be a power supply PMIC. The power supply PMIC's SPMI bus connects to the CPU and the charging PMIC for mutual instruction control and data transmission. The real-time clock (RTC) unit inside the power supply PMIC maintains functions such as a timer alarm and is powered by the internal VPH. When the VPH is de-energized, an external timer capacitor Crtc provides a brief power supply; the power supply time is strongly correlated with the Crtc's capacity and can last from a few seconds to tens of seconds. The voltage signal of the timer capacitor Crtc also serves as the enable (EN) signal for the switching switch 321. The voltage adjustment unit (e.g., DC-DC & LDO) is the power conversion unit inside the power supply PMIC, with VPH as input, outputting power to the CPU to supply power to various modules within the CPU.

[0118] In this embodiment, the SPMI bus of the charging PMIC is connected to the CPU and the power PMIC for mutual instruction control and data transmission. The charging PMIC has a constant-power unit 213, such as an Always-on domain unit, which can act as the execution module for the power key signal. Internally, it is powered by the battery voltage Vbat to maintain continuous operation. For example, the constant-power unit 213 can specifically be used to: respond to the power key signal in the power-off state and send a power-on timing signal to the power PMIC and CPU via the SPMI signal; when the power key is pressed, it initiates the complete power-on timing process; the battery module, as the energy source of the electronic device, outputs the battery voltage Vbat, which is controlled by the battery switch Q inside the charging PMIC. bat It supplies power to all power inputs of the backend system; in low-power mode (e.g., ship mode), in response to the user pressing the power button, it internally sends an interrupt command to the switch control unit 214, which then turns on the battery switch transistor Q. bat It provides the system voltage Vsys to the back-end circuitry.

[0119] Low-power mode (such as ship mode) refers to disconnecting the power supply from the battery to the phone after factory testing and before packaging. The purpose is to enable a low-power mode when the phone is manufactured, transported, or stored for a long time, so that the battery can still power the phone after several months.

[0120] In this embodiment, the switch control unit 214 acts as the battery switch Q between the battery voltage Vbat and the system voltage Vsys. bat The switch control module, when detecting an abnormal event, sends a signal to shut down the battery switch transistor Q. bat Disconnect the battery voltage Vbat and the system voltage Vsys.

[0121] In this embodiment, the battery temperature detection unit 2121 can be a temperature analog-to-digital converter (TADC) connected to an external battery temperature sensor. The battery temperature sensor can be a thermistor, such as an NTC thermistor, used to detect the battery temperature (by mapping the voltage value of the battery temperature signal output by the NTC thermistor to the corresponding temperature value). The TADC converts the analog voltage signal from the battery temperature sensor into a digital signal, allowing the system to read the battery temperature and implement corresponding temperature control strategies. For example, when the temperature exceeds a certain value, it may shut down the MOS switch Q between the battery voltage Vbat and the system voltage Vsys. bat Disconnect the electrical load to ensure the battery temperature drops below safety limits. The TADC internally includes numerous register-writable pull-up resistors Rpu, each with a different resistance value (e.g., Rpu1 / Rpu2 / Rpu3, etc.). These pull-up resistors are connected to the Vref_vadc voltage, which is provided by the LDO inside the charging PMIC. The LDO input is provided by Vsys. Simultaneously, the external thermistor NTC is connected via a resistor element R. pull The control interface GPIO is connected to the charging PMIC. The control interface GPIO is connected to the internal pull-up resistor (PULL-UP) and pull-down resistor (PULL-DOWN) of the charging PMIC. The pull-up resistor (PULL-UP) is pulled up to the voltage Vsys. The default state of the GPIO can be pulled down to PULL-DOWN (logic "0", equivalent level pulled to 0V).

[0122] Specifically, for the GPIO of the charging PMIC, when the charging PMIC receives the control command sent by the CPU through SPMI, the GPIO is configured as an input PULL-UP pull-up resistor and the GPIO is set to a high level (logic "1", the signal voltage is pulled up to Vsys); when the charging PMIC does not receive the control command sent by the CPU through SPMI within a preset time period, the GPIO defaults to a PULL-DOWN low level state.

[0123] In this embodiment, the corresponding temperature value is mapped by detecting the voltage value of the battery temperature signal (BAT_therm signal) output by the thermistor NTC, and the voltage of the battery temperature signal output by the thermistor NTC is determined in the following way: When the GPIO of the charging PMIC is set to a high level (i.e., the pull-down resistor is disconnected, the pull-up resistor is connected, and the GPIO level is pulled high equal to Vsys), the voltage of the battery temperature signal output by the thermistor NTC is controlled by the NTC resistor and the external resistor R. pull The voltage is divided to a primitive state. At this time, the voltage change of the battery temperature signal is determined by the voltage division of the NTC resistor and the pull-up resistor Rpu inside the TADC, thereby realizing the original high temperature protection function of the charging PMIC. When the charging PMIC does not receive a control command from the CPU via SPMI within a preset time period, the GPIO of the charging PMIC is set to low. The voltage of the battery temperature signal is determined by the voltage division between the PULL-DWON pull-down resistor and the pull-up resistor Rpu connected to the TADC within the charging PMIC. The NTC resistor is 100K ohms at room temperature, while the PULL-DWON pull-down resistor is in the 10K ohm range. With the 10K ohm pull-down resistor, the equivalent NTC resistor is pulled down below the 10K ohm resistor, and the voltage division is close to or above 60°C. That is, after the voltage division by the PULL-DWON pull-down resistor and the NTC resistor, the voltage of the battery temperature signal is greater than the voltage threshold, so the TADC outputs a temperature protection signal to the switch control unit 214, causing the battery switch Q to activate. bat The circuit is shut down, thus stopping the battery module 100 from supplying power to the processor 400.

[0124] In the embodiment of the present application, the switching switch 321 can be powered by the battery voltage Vbat. The first input terminal A1 of the switching switch 321 is connected to the power-on mechanical key, the second input terminal A2 of the switching switch 321 is directly shorted to the ground, and the output terminal of the switching switch 321 is connected to the constant power unit 213 of the charging PMIC and outputs a power-on key signal (power key signal); the enable (EN) signal of the switching switch 321 is provided by the voltage signal output by the timing capacitor Crtc of the power supply PMIC. Set the threshold high and low levels of EN of the switching switch 321: If Vbat = 4V, VPH = Vbat = Crtc = 4V, set the EN signal level Vth H> 2V as the high level, and set the EN signal level Vth L <1V as the low level.

[0125] Among them, when the electronic device is in the normal shutdown state, at this time the EN signal of the switching switch 321 is set to the high level state (normal shutdown state, VPH = Vbat = 4V, Crtc is powered by VPH), the I2C signal output by the CPU to the switching switch 321 is low level. Based on the level states of EN and I2C, as the default initial state, it is written to the Reg1 register. This state controls the default conduction of the first input terminal A1 of the switching switch 321. At this time, pressing the power-on key by default can trigger the power-on process; Among them, when the EN signal of the switching switch 321 is at the high level, while writing to the internal Reg2 register of I2C, even if the EN signal drops to the low level later, the switch can be configured in advance to conduct the first input terminal A1; Among them, when I2C has no instruction to configure the Reg2 register, and the EN signal level <Vth L (when Q bat In the off state, VPH = 0, the Crtc voltage will gradually drop until it drops to 0V), then the switching switch 321 switches to the second input terminal A2, and the power-on key signal (power key signal) is forced to be pulled low, so as to simulate the process of the user pressing the power-on key to exit the ship mode. When the charging PMIC receives that the powerkey signal is pulled low, it opens the battery switch tube Q through the constant power unit 213 and the switch control unit 214 bat , and re-provides the VPH voltage to the RTC module, and the RTC module recharges Crtc again. When the Crtc voltage > Vth H, the EN signal returns to the high level state, and the switching switch 321 switches back to the first input terminal A1 again, and the power key signal exits the forced pull-down state.

[0126] In addition, based on the similar concept of the power supply circuit provided in the above embodiment of the present application, the embodiment of the present application also provides a control method for an electronic device. In order to achieve automatic restart after the system crashes, while avoiding the impact on normal shutdown and low-power modes (such as ship mode), the electronic device includes Figure 4 Taking the power supply circuit shown as an example, this application embodiment provides a control method for an electronic device. Figure 9 As shown, the control method includes: Determine if the electronic device is powered off; When the electronic device is in a normal off state, the charging PMIC is in a micro-activated state, and the constant power unit 213 can respond to the power key signal to perform the power-on process; the battery voltage Vbat output by the battery module 100 is controlled by the battery switch transistor Q. bat The backend system is supplied with voltage Vsys, where Vsys = VPH. At this time, the RTC module of the power supply PMIC is powered by VPH, and the voltage Vrtc supplied to the external timing capacitor Crtc is maintained at approximately equal to VPH. The output voltage signal Vrtc of Crtc serves as the EN enable signal of the switch 321. At this time, the EN signal is greater than Vth H and is at a high level. Since the power is not yet on, the I2C signals are still at a low level. The switch is in its default initial state, and the I2C signals are written to the Reg1 register. This state controls the switch to be on by default at the first input terminal A1. At this time, pressing the power button will trigger the power-on process.

[0127] If the electronic device is not in a normal shutdown state, it continues to determine whether the electronic device is in a normal power-on state and detects whether the system has crashed; if the system has not crashed, it continues to determine whether the electronic device is ready to enter ship mode.

[0128] When an electronic device is preparing to enter ship mode, the current ship mode entry process includes: the CPU first writes to the Reg2 register inside the switch 321 via the I2C bus, configuring the switch 321 to switch to the first input terminal A1. At the same time, the CPU sends out the normal shutdown procedure via the SPMI bus. All modules of the system first stop working, then the power supply PMIC goes through the power-down sequence procedure, and finally the charging PMIC turns off the battery switch transistor Q. bat Disconnect the power supply to Vbat and Vsys, causing VPH to drop to 0V. To exit ship mode, simply press the power button. bat First, the circuit is turned on to supply the Vsys voltage to the backend system. At the same time, the charging PMIC will initiate a power-on process to boot up and exit ship mode normally.

[0129] When the system of the electronic device is in a frozen state, the CPU cannot send any instructions and data through the SPMI and I2C buses, and the GPIO of the CPU is in an unknown pull-up / pull-down state. At this time, the charging PMIC does not receive the voltage regulation instruction and other instructions sent by the CPU within a preset time period, and the GPIO of the charging PMIC returns to the default configuration state (i.e., the low-level state), and the power supply still maintains output, and the voltage at this time is the default level; Among them, for the temperature protection function of the TADC of the charging PMIC, when the software-set temperature > Tth, the temperature protection function is triggered and Q is turned off bat , to prevent the battery from continuing to discharge and further increasing the battery temperature, and to improve the safety of the battery.

[0130] Among them, when the system of the electronic device is in a frozen state, because the charging PMIC does not receive the SPMI instruction sent by the CPU within a preset time period, the GPIO that originally externally pulled up the battery temperature signal switches back to the default PULL-DOWN state (i.e., the low-level state). At this time, the battery NTC on BAT_Therm is bypassed to the ground by the PULL-DOWN pull-down resistor connected by the GPIO. Also, because the resistance value of the PULL-DOWN pull-down resistor is much smaller than the resistance value of the NTC, which is 100K ohms, the temperature mapped by the divided voltage level > the set temperature for turning off Q bat At this time, Q is triggered bat to turn off; Q bat is turned off, the Vsys output is turned off, and the VPH output to the power PMIC also drops to 0V. The RTC inside the power PMIC is now powered by VPH and switches to being briefly powered by an external Crtc. The voltage of the Crtc will gradually decrease; when the voltage of the Crtc drops to Vcrtc < Vth L (Vth L is the voltage threshold for setting the EN signal of the switching switch to the low-level state), the switching switch switches to the second input terminal A2, and the power key signal is forced to be pulled low. The charging PMIC receives that the powerkey signal is pulled low, and Q bat will exit the off state and conduct Q bat , and re-provide the VPH voltage to the RTC, and the Crtc recharges. When the Crtc voltage > Vth H, the EN enable signal of the switching switch returns to the high-level state, and the switching switch switches back to the first input terminal A1 again, and the power key signal exits the forced pull-down state; Among them, select the capacity of the Crtc to meet the time required for the re-power-on timing process. For example, from the power key being pulled low to Q bat being turned on and then completing the power-on timing process, it takes at least 3 seconds. Based on this, select the capacity of the Crtc such that the time required for the voltage Vcrtc of the Crtc to rise from Vth L to Vth H is greater than 3 seconds.

[0131] After completing the above process, the system will officially restart and return to the operating interface, completing the process from system crash to automatic reset and boot.

[0132] In practical applications, besides utilizing the existing high-temperature battery protection function of the charging PMIC to automatically power off and restart the processor, the existing low-voltage battery protection function of the charging PMIC can also be used. For example, the electronic device provided in the embodiments of this application includes... Figure 5 Taking the power supply circuit shown as an example, after the system crashes, the first reset unit 310 creates conditions to trigger the battery undervoltage protection function, and sets the V value at the battery undervoltage trigger terminal. SENSE A GPIO of the charging PMIC is connected in parallel to the signal (selecting a GPIO with an internal pull-up level of Vsys to prevent the GPIO from burning out due to different levels). The default state of this GPIO is PD pull-down (i.e., low level). When the system is alive, the system sends a command to the PMIC through the SPMI bus to control this GPIO to be high, with the level equal to Vsys. At this time, the battery undervoltage protection function will not be triggered, and the system is in normal state. When the system crashes, if the charging PMIC does not receive the SPMI command sent by the processor within a preset time period, the GPIO returns to the default PD pull-down state. At this time, it will pull down the third control signal (i.e., protection trigger signal) of the trigger terminal of the battery undervoltage protection unit. The charging PMIC will think that the battery voltage is too low at this time, and the PMIC will trigger the restart protection of the battery undervoltage protection function. After restarting, because the GPIO is pulled high again under control, the system returns to normal state.

[0133] In practical applications, besides utilizing the original battery protection functions of the charging PMIV, such as high-temperature protection and low-voltage protection, to automatically restart the processor after power failure, the original method of forced restart via key combination can also be used to achieve automatic power failure and restart of the processor. For example, the electronic device provided in the embodiments of this application includes... Figure 7Taking the power supply circuit shown as an example, the GPIO in the charging PMIC's default PU high state is selected to automatically trigger a hard reset using the combination key after a system crash: When the processor is active, the watchdog timer inside the processor expires, and the processor automatically feeds the watchdog. The processor sends a control command to the charging PMIC via the SPMI bus to set the charging PMIC's GPIO (default PU high state) to PD pull-down state, preventing the first switch element Q1 and the second switch element Q2 from being turned on and pulling the combination key signal to ground, thus erroneously triggering a forced restart. When the processor's watchdog is not fed, the processor has crashed. If the charging PMIC does not receive the SPMI command from the processor within a preset time period, the charging PMIC controls the GPIO to return to the default PU high state, and simultaneously controls the first switch element Q1 and the second switch element Q2 to be turned on, pulling the combination key signal low and maintaining it for a certain period of time (satisfying the time required for a forced system restart), allowing the system to restart and enter the system desktop.

[0134] In this embodiment, the processor 400 may be a CPU. The CPU is connected to the power PMIC and the charging PMIC via the SPMI bus for mutual instruction control and data transmission. The CPU has a watchdog module that is responsible for feeding the system to ensure normal system operation. The CPU has a power module that is responsible for receiving power from the power PMIC to power the various modules inside the CPU. The CPU has GPIO, which serves as an interface for instruction and data interaction with peripherals.

[0135] In this embodiment, the SPMI bus of the power supply PMIC is connected to the CPU and the charging PMIC for mutual instruction control and data transmission. The voltage regulation unit (e.g., DC-DC & LDO) is the power conversion unit inside the power supply PMIC, with VPH as input and output power to the CPU to supply power to various modules within the CPU. The RESET_N signal of the power supply PMIC is connected to an existing combination button (multiplexed as either a volume up or volume down button), which, together with the power button, forms a forced restart button combination.

[0136] In this embodiment, the SPMI bus of the charging PMIC is connected to the CPU and the power PMIC for mutual instruction control and data transmission. The charging PMIC has a constant-power unit 213, such as an Always-on domain unit, which can act as the execution module for the power key signal. Internally, it is powered by the battery voltage Vbat to maintain continuous operation. For example, the constant-power unit 213 can specifically be used to: respond to the power key signal in the power-off state and send a power-on timing signal to the power PMIC and CPU via the SPMI signal; when the power key is pressed, it initiates the complete power-on timing process; the battery module, as the energy source of the electronic device, outputs the battery voltage Vbat, which is controlled by the battery switch Q inside the charging PMIC. bat It supplies power to all power inputs of the backend system; in low-power mode (e.g., ship mode), in response to the user pressing the power button, it internally sends an interrupt command to the switch control unit 214, which then turns on the battery switch transistor Q. bat It provides the system voltage Vsys to the back-end circuitry.

[0137] In this embodiment, the default state of the charging PMIC's GPIO is selected as the PU high state. The PMIC's GPIO simultaneously controls the NMOS of the power button signal and the RESET_N signal to ground (first switching element Q1 and second switching element Q2). When the processor is in normal operation, the processor sends a control command to the charging PMIC through the SPMI bus to set the charging PMIC's GPIO to the PD pull-down state. The first switching element Q1 and the second switching element Q2 are simultaneously turned off to prevent the first switching element Q1 and the second switching element Q2 from being turned on and pulling the combination button signal to ground, thus erroneously triggering a forced restart. When the processor is in a frozen state, the charging PMIC's GPIO returns to the default PU high state. When the GPIO is in a high level state, the first switching element Q1 and the second switching element Q2 are simultaneously turned on, pulling the power button signal input by the charging PMIC and the hardware reset signal input by the RESET_N terminal of the power PMIC low at the same time, simulating the user pressing the combination button and the power button simultaneously to achieve a forced restart of the processor.

[0138] To achieve automatic restart after a system crash, while avoiding impact on normal shutdown, ship mode, and normal startup, the electronic device includes... Figure 7 Taking the power supply circuit shown as an example, this application embodiment provides a control method for an electronic device. Figure 10 As shown, the control method includes: Determine whether the electronic device is in a power-off state or a low-power state (such as ship mode). When the electronic device is in a normal power-off state or a low-power state (such as ship mode), the GPIO of the charging PMIC is set to PD pull-down state. When any state switching action is performed, the first switching element Q1 and the second switching element Q2 remain in the off state; the power key signal and the reset signal remain at a high level. If the electronic device is not in a normal shutdown state or a low power state (such as ship mode), continue to determine whether the charging PMIC receives CPU instructions normally. If the charging PMIC receives the SPMI instruction sent by the processor within a preset time period, the charging PMIC determines that the processor is in a normal state. If the charging PMIC does not receive the SPMI instruction sent by the processor within the preset time period, the charging PMIC determines that the processor is in a frozen state.

[0139] When the processor is in a frozen state, the CPU cannot send any instructions or data through the SPMI bus, and the CPU's GPIO is in an unknown pull-up / pull-down state. At this time, if the charging PMIC does not receive any SPMI instructions from the processor within a preset time period, such as voltage adjustment instructions and watchdog timer feeding instructions, the charging PMIC determines that the processor is in a frozen state. The MCU inside the charging PMIC controls the charging PMIC's GPIO to switch to the PU high state, and at the same time turns on the first switch element Q1 and the second switch element Q2. The first switch element Q1 and the second switch element Q2 are simultaneously grounded, pulling the power button and the combination button low at the same time. After maintaining this for a certain period of time, the power PMIC is forced to restart, and the power-down and power-on reset actions are performed.

[0140] For example, the hardware reset time of the power PMIC can be set to 10 seconds via a register, simulating a forced restart triggered by pressing a combination of keys. Specifically, the power button and the combination of keys can be pulled low simultaneously for a certain period. The logic for a forced restart by holding down the combination of keys is as follows: holding down a specific key combination triggers a forced power-down of the power PMIC. After power-down, the charging PMIC detects that the key combination is still pressed and restarts the power-on sequence. After completing this process, the system officially restarts and returns to the user interface, completing the process from a system crash to automatic reset and restart.

[0141] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0142] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A power supply circuit, characterized in that, include: The system includes a battery module, a power management circuit, a restart circuit, and a processor. The battery module is connected to the voltage input terminal of the processor via the power management circuit, and the control terminal of the processor is connected to the control terminal of the power management circuit. The restart circuit is connected to the power management circuit. The power management circuit is used to: output a trigger signal to the restart circuit if no control command is received from the processor within a preset time period; The restart circuit is used to: generate a first control signal and a second control signal according to the trigger signal, and output the first control signal and the second control signal to the power management circuit; The power management circuit is used to: control the battery module to stop supplying power to the processor according to the first control signal, and control the battery module to supply power to the processor again according to the second control signal, so as to restart the processor.

2. The power supply circuit according to claim 1, characterized in that, The power management circuit includes a charging management chip, which has a control interface. The charging management chip is used to: switch the output state of the control interface of the charging management chip from a first level state to a second level state to generate a trigger signal when no control instruction is received from the processor within a preset time period; and output the trigger signal to the restart circuit through the control interface of the charging management chip.

3. The power supply circuit according to claim 2, characterized in that, The charging management chip includes a battery switch unit, and the output terminal of the battery module is coupled to the voltage input terminal of the processor through the battery switch unit; The restart circuit includes a first restart module, and the control interface of the charging management chip is coupled to the control terminal of the battery switch unit through the first restart module; The first restart module is used to: generate a first control signal according to the trigger signal, and output the first control signal to the control terminal of the battery switch unit to turn off the battery switch unit and stop the battery module from supplying power to the processor.

4. The power supply circuit according to claim 3, characterized in that, The battery switch unit includes a battery switch transistor. The input terminal of the battery switch transistor is connected to the battery module, and the output terminal of the battery switch transistor is coupled to the voltage input terminal of the processor. The control terminal of the battery switch transistor is coupled to the control interface of the charging management chip through the first restart module.

5. The power supply circuit according to claim 3, characterized in that, The first restart module includes a level conversion element, and the charging management chip also includes a battery protection unit. The control interface of the charging management chip is connected to the trigger terminal of the battery protection unit through the level conversion element, and the output terminal of the battery protection unit is coupled to the control terminal of the battery switch unit. The level conversion element is used to: when the output state of the control interface of the charging management chip switches from a first level state to a second level state, switch the voltage of the trigger terminal of the battery protection unit from a first voltage value to a second voltage value, so as to generate a first control signal; The battery protection unit is used to: trigger a third control signal of the battery protection unit according to the first control signal, and output the third control signal to the control terminal of the battery switch unit to put the battery switch unit in the off state; The level conversion element includes a resistor, and the control interface of the charging management chip is connected to the trigger terminal of the battery protection unit through the resistor.

6. The power supply circuit according to claim 5, characterized in that, The battery protection unit includes a battery temperature detection unit, and the trigger terminal of the battery protection unit is the temperature detection terminal of the battery temperature detection unit.

7. The power supply circuit according to claim 5, characterized in that, The battery protection unit includes a battery undervoltage protection unit; the trigger terminal of the battery protection unit is the voltage detection terminal of the battery undervoltage protection unit.

8. The power supply circuit according to claim 3, characterized in that, The power management circuit further includes a delay module, the restart circuit includes a second restart module, the output terminal of the battery switch unit is connected to the second restart module through the delay module, and the second restart module is coupled to the control terminal of the battery switch unit; The delay module is used to: generate an enable signal after the battery switch unit is in the off state and after a preset delay, and output the enable signal to the second restart module; The second restart module is used to: generate a second control signal according to the enable signal, and output the second control signal to the control terminal of the battery switch unit to turn on the battery switch unit so that the battery module can re-supply the processor.

9. The power supply circuit according to claim 8, characterized in that, The second restart module includes a toggle switch; the power supply circuit also includes a power button; The output terminal of the battery switch unit is connected to the enable terminal of the switching switch through the delay module; the power button is connected to the first input terminal of the switching switch; the second input terminal of the switching switch is grounded; and the output terminal of the switching switch is coupled to the control terminal of the battery switch unit. The switching switch is used to: connect the second input terminal and the output terminal of the switching switch according to the enable signal output by the delay module, so that the output state of the switching switch is switched from the third level state to the fourth level state to generate a second control signal.

10. The power supply circuit according to claim 9, characterized in that, The delay module includes a clock unit and a timing capacitor. The output terminal of the battery switch unit is connected to the input terminal of the clock unit, the output terminal of the clock unit is connected to the timing capacitor, and the output terminal of the clock unit is also connected to the enable terminal of the switching switch. The power management circuit further includes a discharge management chip, and the clock unit is located inside the discharge management chip.

11. The power supply circuit according to claim 2, characterized in that, The power management circuit also includes a discharge management chip; the battery module is connected to the voltage input terminal of the discharge management chip through the charging management chip, and the voltage output terminal of the discharge management chip is connected to the voltage input terminal of the processor. The restart circuit includes a third restart module and a fourth restart module; The charging management chip includes a constant power unit; the control interface of the charging management chip is connected to the reset terminal of the discharging management chip through the third restart module; the control interface of the charging management chip is connected to the constant power unit through the fourth restart module, and the constant power unit is connected to the control terminal of the discharging management chip through the control terminal of the charging management chip; The third restart module is used to: generate a first control signal according to the trigger signal, and output the first control signal to the reset terminal of the discharge management chip to trigger the discharge management chip to reset, so that the battery module stops supplying power to the processor; The fourth restart module is used to: generate a second control signal according to the trigger signal, and output the second control signal to the charging management chip, so that the charging management chip triggers the discharge management chip to power on according to the second control signal, so that the battery module can re-supply the processor.

12. The power supply circuit according to claim 11, characterized in that, The fourth restart module includes a first switching element; the output terminal of the first switching element is coupled to the constant power unit, the input terminal of the first switching element is grounded, and the control terminal of the first switching element is connected to the control interface of the charging management chip. The third restart module includes a second switching element; the output terminal of the second switching element is connected to the reset terminal of the discharge management chip, the input terminal of the second switching element is grounded, and the control terminal of the second switching element is connected to the control interface of the charging management chip. The first switching element is used to: enter the conducting state under the drive of the trigger signal, so that the output state of the first switching element switches from the fifth level state to the sixth level state, so as to generate the second control signal; The second switching element is used to: enter the conducting state under the drive of the trigger signal, so that the output state of the second switching element switches from the seventh level state to the eighth level state, so as to generate the first control signal.

13. The power supply circuit according to claim 12, characterized in that, The power supply circuit also includes a power button and a combination button. The power button is coupled to the constant power unit, and the combination button is coupled to the reset terminal of the discharge management chip. The output terminal of the first switching element is connected to the power button and is located between the power button and the constant power unit; The output terminal of the second switching element is connected to the combination button and is located between the combination button and the reset terminal of the discharge management chip.

14. The power supply circuit according to claim 11, characterized in that, The discharge management chip includes a voltage adjustment unit; the input terminal of the voltage adjustment unit is the voltage input terminal of the discharge management chip, the output terminal of the voltage adjustment unit is the voltage output terminal of the discharge management chip, and the enable terminal of the voltage adjustment unit is connected to the reset terminal of the discharge management chip. The voltage adjustment unit includes at least one of the following: a DC-DC converter and a low-dropout linear regulator.

15. An electronic device, characterized in that, Includes the power supply circuit as described in any one of claims 1-14.

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