A feeder terminal device for improving device performance based on data compression

Abstract

The application provides a kind of based on data compression improves the performance of feeder terminal equipment, including voltage acquisition circuit, current acquisition circuit, remote signaling acquisition circuit, main CPU, communication interface circuit etc.;Wherein, main CPU is triggered when recording wave event, compresses data and saves to memory;Communication interface circuit is used to obtain recording wave data or recording wave event trigger in remote background master station, and compressed data is sent to remote background master station according to self-defined communication protocol;Self-defined communication protocol uses data compression algorithm based on adaptive arithmetic coding, and data compression algorithm realizes data compression by dynamically adjusting symbol probability distribution;Remote background master station is used to receive compressed data, and according to self-defined communication protocol, compressed data is parsed, and original data is processed by decompression and restoration.The application realizes efficient transmission and anti-interference processing under large data volume through self-defined compression algorithm, multi-channel parallel processing and dynamic probability model.

Description

Technical Field

[0001] This invention relates to the field of power system distribution automation technology, specifically to a feeder terminal device that improves equipment performance based on data compression. Through a custom data compression algorithm and multi-channel parallel processing technology, it achieves efficient transmission and anti-interference processing under large data volumes, and is suitable for scenarios such as power fault recording and real-time monitoring. Background Technology

[0002] In power system distribution automation, distribution terminal equipment (such as FTUs) needs to collect and transmit data such as voltage, current, and switching quantities to a remote master station in real time. According to Section 7.2 of the "Implementation Rules of the State Grid Corporation of China DL / T 634.5101-2002 Protocol," fault recording data is exchanged using the Comtrade format. However, this format suffers from problems such as excessive redundant information and low transmission efficiency, specifically manifested in the following ways: Bandwidth limitation: The data transmission channel has a fixed bandwidth, and the large size of Comtrade files results in a long transmission cycle; Complex interaction: Redundant information requires multiple interactions for confirmation, increasing the risk of communication instability; High hardware costs: To transmit large amounts of data, high-bandwidth communication modules and large-capacity storage devices are required.

[0003] Existing technologies partially alleviate the problem through hardware upgrades (such as increasing communication speed) or software optimizations (such as simplifying data formats), but cannot simultaneously address efficiency, cost, and compatibility. Therefore, there is an urgent need to develop a feeder terminal device based on data compression. Summary of the Invention

[0004] To address the various shortcomings of existing technologies, this invention provides a feeder terminal device that improves device performance based on data compression. Through a custom compression algorithm, multi-channel parallel processing, and dynamic probability model, it achieves efficient transmission and anti-interference processing under large data volumes.

[0005] The present invention achieves the above objectives through the following technical solutions: A feeder terminal device for improving equipment performance based on data compression, comprising: Voltage acquisition circuit, used to acquire analog voltage transmitted from primary equipment and convert it into digital signal; The current acquisition circuit is used to acquire the analog current transmitted from the primary equipment and convert it into a digital signal; Remote signaling acquisition circuit is used to acquire switch signals transmitted from primary equipment and convert them into digital signals; The main CPU, connected to the voltage acquisition circuit, current acquisition circuit and remote signaling acquisition circuit, is used to receive the converted digital signal and store the acquired data in the buffer area. When the waveform recording event is triggered, the data is compressed and saved to the memory. The communication interface circuit, connected to the main CPU, is used to send compressed data to the remote backend master station according to a custom communication protocol when the remote backend master station acquires waveform data or when a waveform event is triggered. The remote backend master station is used to receive the compressed data, parse the compressed data according to the custom communication protocol, decompress and restore the original data for processing. The custom communication protocol adopts a data compression algorithm based on adaptive arithmetic coding, which achieves data compression by dynamically adjusting the symbol probability distribution.

[0006] According to the present invention, a feeder terminal device for improving device performance based on data compression is provided. The data compression algorithm based on adaptive arithmetic coding achieves data compression by dynamically adjusting the symbol probability distribution, including: Symbol frequency statistics: The main CPU performs real-time symbol frequency statistics on the collected voltage, current, and remote signaling data, and establishes a dynamic probability model; Adaptive coding engine: Dynamically allocates coding bit width according to symbol frequency, using short bit width coding for high-frequency symbols and long bit width coding for low-frequency symbols; Multi-channel parallel processing: Independent modeling and encoding of three data streams—voltage, current, and remote signaling—improves compression efficiency through parallel computing; Compressed data encapsulation: The encoded data stream, along with parameters such as compression bit width, data length, and timestamp, is processed according to a custom communication protocol to form a compressed data packet with encryption and verification.

[0007] According to the present invention, a feeder terminal device for improving device performance based on data compression includes data compression processing comprising various compression bit-width marker compression methods, specifically: 4-bit compression width, compression rate of 75%; 8-bit compressed bit width, compression rate of 50%; 12-bit compressed bit width, compression rate of 25%; A 16-bit compression width indicates no compression.

[0008] According to the present invention, a feeder terminal device for improving device performance based on data compression, wherein the main CPU performs data compression and parameter framing through the following steps when a waveform recording event is triggered: The main CPU reads the preset compression configuration table from the memory to determine the compression bit width, data sampling rate and cycle length parameters applicable to the current waveform data; The main CPU performs layered compression on the acquired voltage, current, and telemetry data according to the compression bit width: For analog voltage / current data, differential coding combined with adaptive arithmetic coding is used to eliminate periodic redundancy; For remote signaling switch data, run-length encoding is used to compress consecutive identical states; Calculate the length of the compressed data in real time and mark the number of valid data points; The main CPU frames the compressed data with the following parameters according to the communication protocol format: Frame header: Fixed identifier + device ID; Compression parameter area: 4-bit compression width marker, 16-bit data length, 8-bit cycle number, 16-bit data point number; Compressed data area: Encoded data stream encapsulated by bit width; Verification area: CRC16 checksum; The main CPU writes the framed data packets to a designated area of ​​memory and updates the data index table, recording the timestamps and data addresses of the waveform events.

[0009] According to the feeder terminal device for improving device performance based on data compression provided by the present invention, after receiving compressed data, the remote back-end master station performs parsing and decompression processing based on adaptive arithmetic coding through the following steps: After receiving the data packet, the communication interface module of the remote back-end master station parses the frame header according to the communication protocol format, verifies the device ID and the CRC16 check code in the check area, and confirms the data integrity. Extract the 4-bit compression bit width marker, 16-bit data length, 8-bit cycle number, and 16-bit data point number from the compression parameter area to determine the bit width configuration and data range required for decompression. Initialize the decoding engine based on the compressed bit width and perform the following operations: Dynamic probability model reconstruction: Based on the symbol frequency statistics in the compression parameters, reconstruct a symbol probability distribution table consistent with the terminal device; For analog voltage / current data, differential decoding combined with adaptive arithmetic decoding is used to restore periodic waveforms; For remote signaling switch data, run-length decoding is used to restore continuous state changes; After decoding each data block, the length of the decoded data is checked to see if it matches the length of the data declared in the compression parameter area. If they do not match, a retransmission mechanism is triggered. The decoded voltage, current, and remote signaling data are rearranged according to the timestamp and the number of data points to generate a time-series data stream that matches the original data collected by the terminal device, thus restoring the original data.

[0010] According to the present invention, a feeder terminal device for improving equipment performance based on data compression, wherein the main CPU performs real-time symbol frequency statistics on the collected voltage, current, and remote signaling data and establishes a dynamic probability model, specifically through the following steps: The main CPU converts the collected analog voltage and current data into discrete symbol sequences according to a preset compressed bit width, and the remote signaling switch data is directly mapped into binary symbols to form the raw symbol stream to be statistically analyzed. The main CPU uses a sliding window mechanism to perform real-time statistics on the raw symbol stream. The window length L is dynamically adjusted according to the data sampling rate, satisfying the following conditions: Voltage / current data window: L = N×T, where N is the number of sampling points per cycle and T is the fundamental period, ensuring full coverage of the waveform characteristics of the cycle; Remote signaling data window: L = M × Δt, where M is the threshold for the number of state changes and Δt is the minimum statistical time interval, capturing the switching quantity jump pattern; Within each window, the main CPU counts the frequency f(s) of each symbol and calculates the relative frequency P(s) = f(s) / L to form an initial symbol frequency table; The main CPU updates the symbol probability model in real time according to the following rules: Exponentially weighted average smoothing: the sign frequency P of the current window statistics t (s) and historical model probability P {t-1} (s) performs weighted fusion, and the updated formula is: P t (s) = α × P t (s) + (1-α) × P {t-1} (s) Where α is the smoothing factor; Threshold-triggered update: When the frequency change of a certain symbol in the new window |P t (s)-P {t-1} When (s)| exceeds the preset threshold ΔP, the probability of the symbol is forcibly updated, and the association probability of adjacent symbols is reset.

[0011] According to the present invention, a feeder terminal device for improving device performance based on data compression has an adaptive coding engine that dynamically allocates the coding bit width according to the symbol frequency, which is specifically achieved through the following steps: The main CPU divides symbols into K levels based on the real-time statistical symbol frequency P(s) and establishes a frequency-bit width mapping table, satisfying the following conditions: The lower frequency threshold T of the i-th level symbol i This can be expressed as the following formula: T i = P max × (β) (i-1) Among them, P max The highest frequency among all symbols, β is the attenuation coefficient; The encoding bit width B of the i-th level symbol allocation isatisfy:

[0012] And restrict B i ∈[B min B max ], where B min For minimum bit width, B max This represents the maximum bit width.

[0013] According to the present invention, a feeder terminal device for improving device performance based on data compression, wherein the main CPU updates the symbol encoding bit width according to the following strategy in each compression cycle: Calculate the symbol frequency P of the current period t (s) and the frequency P of the previous cycle {t-1} The relative rate of change of (s): ΔP(s) = |P t (s) - P {t-1} (s)| / P {t-1} (s) If ΔP(s) exceeds the preset threshold ΔP th (e.g., 10%), then bit width adjustment is triggered; When it is necessary to increase the bit width, a step-by-step adjustment strategy is adopted: B new = B old + ΔB step Where, ΔB step This is a step value to avoid sudden changes in bit width that could cause a sharp drop in coding efficiency. When the bit width needs to be reduced, update to the target bit width immediately; The main CPU pre-stores the bit width mapping table to the hardware lookup unit, and directly obtains the corresponding bit width through the symbol index, reducing real-time calculation latency.

[0014] According to the present invention, a feeder terminal device based on data compression to improve device performance is provided. The main CPU uses a hardware parallel computing unit to independently perform modeling and encoding of three data streams: voltage, current, and remote signaling. An independent dynamic probability model storage area is allocated for each data stream and stored in the high-speed static random access memory of the main CPU. The main CPU dynamically allocates computing resources through a hardware task scheduler: Voltage / current path: Prioritize allocation to dual-core ARM Cortex-M7 processors, utilizing single-instruction multiple-data instruction set to process periodic analog quantities in parallel; Remote signaling channel: Equipped with a single-core ARM Cortex-M3 processor, using interrupt-driven mode to respond to switch quantity changes in real time; When the remote signaling status changes, the model of the voltage / current channel is synchronously updated, and the corresponding encoding engine is notified to pause the calculation via a hardware signal line. The calculation will resume after the model update is completed.

[0015] According to the present invention, a feeder terminal device based on data compression to improve device performance is provided. The main CPU frames the encoded three data streams and metadata according to a custom communication protocol to form a compressed data packet with encryption and verification. When implementing encryption and verification, the main CPU calls the AES-128 engine in the hardware security module and uses a preset key to encrypt the plaintext of the three data streams from the frame header to the channel. The key is rotated every 24 hours. Calculate the CRC32 check value for the plaintext before encryption, then encrypt the check value with AES to generate a 32-bit encrypted check field. The decompression end needs to decrypt the check value before verifying the data integrity. If the encoding engine of a certain channel times out, the main CPU automatically marks the channel as faulty, skips its data encapsulation, and sets the error flag of the corresponding channel in the frame header; the faulty channel data is retransmitted in the next cycle, the version identifier of the retransmitted data frame header is upgraded to v1.1, and a retransmission sequence number is added; When the decompression end detects that the encryption verification has failed, it sends a retransmission request to the main CPU. The main CPU then retransmits the three most recent historical data packets through the reserved emergency communication channel. If remote signaling channel data is lost, the decompression end will default to the state of the previous cycle and trigger an alarm signal.

[0016] Therefore, compared with the prior art, the feeder terminal device based on data compression to improve equipment performance proposed in this invention has the following beneficial effects: 1. The dynamic compression technology used in this invention dynamically allocates the encoding bit width according to the symbol frequency. High-frequency symbols are encoded with short bit width to reduce redundancy, while low-frequency symbols are encoded with long bit width to retain accuracy. This significantly reduces the amount of data transmitted, making more efficient use of limited bandwidth resources. At the same time, it avoids the transmission delay problem caused by excessive data volume and improves the overall communication efficiency of the system.

[0017] 2. This invention utilizes multi-channel parallel processing technology to independently model and encode voltage, current, and remote signaling data. Combined with hardware-accelerated computing, it significantly reduces data processing time, enabling conventionally configured hardware resources to handle higher-load data processing tasks. This avoids the cost of upgrading hardware due to insufficient performance, while also reducing device power consumption and heat dissipation requirements, and extending the lifespan of the hardware.

[0018] 3. This invention employs the AES-128 encryption algorithm and CRC32 verification mechanism to perform high-strength encryption and integrity verification on transmitted data, effectively preventing data from being stolen or tampered with during transmission and ensuring the security of sensitive power information. Simultaneously, the deep integration of the encryption algorithm with a custom protocol further increases the difficulty of data cracking, providing a reliable security barrier for power system data communication.

[0019] 4. To address the data corruption problem that may be caused by sudden changes in remote signaling status, this invention achieves precise timing alignment and adaptive model adjustment of multi-channel data through hardware synchronization signals and dynamic model update mechanisms. This enables the equipment to maintain the stability of data acquisition and transmission in complex electromagnetic environments, avoids malfunctions or data loss caused by interference, and improves the reliability of power system operation.

[0020] 5. In terms of technical implementation, this invention takes into account both protocol compatibility and parameter configurability, supports seamless integration with existing power system standards, and allows for flexible adjustment of parameters such as compression algorithms and channel configurations via a remote master station, enabling the equipment to quickly adapt to the needs of different voltage levels and application scenarios, and reducing the complexity of system upgrades and maintenance.

[0021] 6. This invention provides technical support for advanced applications in smart grids, such as distributed energy management and demand response, by improving data transmission and processing efficiency. Efficient data communication capabilities enable real-time monitoring and optimization of grid operation, reducing energy waste caused by information lag and facilitating the transformation of the power system towards low-carbon and high-efficiency operation.

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0023] Figure 1 This is a schematic diagram illustrating the implementation principle of a feeder terminal device embodiment of the present invention, which improves device performance based on data compression.

[0024] Figure 2 This is a schematic diagram of a feeder terminal device embodiment of the present invention, which improves device performance based on data compression.

[0025] Figure 3 This is a schematic diagram illustrating the process of achieving data compression by dynamically adjusting the symbol probability distribution in an embodiment of a feeder terminal device for improving device performance based on data compression according to the present invention.

[0026] Figure 4 This is a schematic diagram of the compression bit width marking in an embodiment of a feeder terminal device for improving device performance based on data compression according to the present invention.

[0027] Figure 5This is a schematic diagram illustrating the process of implementing data compression and parameter framing in an embodiment of a feeder terminal device for improving device performance based on data compression according to the present invention.

[0028] Figure 6 This is a schematic diagram of the communication protocol format framing in an embodiment of a feeder terminal device for improving device performance based on data compression according to the present invention.

[0029] Figure 7 This is a schematic diagram of the parsing and decompression process of adaptive arithmetic coding in an embodiment of a feeder terminal device for improving device performance based on data compression according to the present invention.

[0030] Figure 8 This is a flowchart illustrating the process of establishing a dynamic probability model in an embodiment of a feeder terminal device for improving device performance based on data compression according to the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] See Figures 1 to 8 This embodiment provides a feeder terminal device for improving device performance based on data compression, including: Voltage acquisition circuit, used to acquire analog voltage transmitted from primary equipment and convert it into digital signal; The current acquisition circuit is used to acquire the analog current transmitted from the primary equipment and convert it into a digital signal; Remote signaling acquisition circuit is used to acquire switch signals transmitted from primary equipment and convert them into digital signals; The main CPU, connected to the voltage acquisition circuit, current acquisition circuit and remote signaling acquisition circuit, is used to receive the converted digital signal and store the acquired data in the buffer area. When the waveform recording event is triggered, the data is compressed and saved to the memory. The communication interface circuit, connected to the main CPU, is used to send compressed data to the remote backend master station according to a custom communication protocol when the remote backend master station acquires waveform data or when a waveform event is triggered. The remote backend master station is used to receive the compressed data, parse the compressed data according to the custom communication protocol, decompress and restore the original data for processing. The custom communication protocol adopts a data compression algorithm based on adaptive arithmetic coding, which achieves data compression by dynamically adjusting the symbol probability distribution. The power supply circuit and other circuits provide auxiliary power and other necessary functions for the feeder terminal equipment.

[0034] In this embodiment, as Figure 3 As shown, the data compression algorithm based on adaptive arithmetic coding achieves data compression by dynamically adjusting the symbol probability distribution, including: Symbol frequency statistics: The main CPU performs real-time symbol frequency statistics on the collected voltage, current, and remote signaling data, and establishes a dynamic probability model; Adaptive coding engine: Dynamically allocates coding bit width according to symbol frequency, using short bit width coding for high-frequency symbols and long bit width coding for low-frequency symbols; Multi-channel parallel processing: Independent modeling and encoding of three data streams—voltage, current, and remote signaling—improves compression efficiency through parallel computing; Compressed data encapsulation: The encoded data stream, along with parameters such as compression bit width (4 / 8 / 12 / 16 bits), data length, and timestamp, is processed according to a custom communication protocol to form a compressed data packet with encryption verification.

[0035] Data compression processing includes various compression methods for compression bit-width markers, such as... Figure 4 As shown, specifically: 4-bit compression width, compression rate of 75%; 8-bit compressed bit width, compression rate of 50%; 12-bit compressed bit width, compression rate of 25%; A 16-bit compression width indicates no compression.

[0036] In this embodiment, when the waveform recording event is triggered, the main CPU, such as Figure 5 As shown, data compression and parameter framing are achieved through the following steps: The main CPU reads the preset compression configuration table from the memory to determine the compression bit width (4 / 8 / 12 / 16 bits), data sampling rate, and cycle length parameters applicable to the current waveform data; The main CPU performs layered compression on the acquired voltage, current, and telemetry data according to the compression bit width: For analog voltage / current data, differential coding combined with adaptive arithmetic coding is used to eliminate periodic redundancy; For remote signaling switch data, run-length encoding (RLE) is used to compress consecutive identical states; Calculate the length of the compressed data in real time and mark the number of valid data points; Among them, such as Figure 6 As shown, the main CPU frames the compressed data with the following parameters according to the communication protocol format: Frame header: Fixed identifier + device ID; Compression parameter area: 4-bit compression width marker, 16-bit data length, 8-bit cycle number, 16-bit data point number; Compressed data area: Encoded data stream encapsulated by bit width; Verification area: CRC16 checksum to ensure data integrity; The main CPU writes the framed data packets to a designated area of ​​memory and updates the data index table, recording the timestamps and data addresses of the waveform events.

[0037] In this embodiment, after receiving the compressed data, the remote backend master station, as follows: Figure 7 As shown, the parsing and decompression processing based on adaptive arithmetic coding is achieved through the following steps: After receiving the data packet, the communication interface module of the remote back-end master station parses the frame header according to the communication protocol format, verifies the device ID and the CRC16 check code in the check area, and confirms the data integrity. Extract the 4-bit compression bit width marker, 16-bit data length, 8-bit cycle number, and 16-bit data point number from the compression parameter area to determine the bit width configuration and data range required for decompression. Initialize the decoding engine based on the compressed bit width and perform the following operations: Dynamic probability model reconstruction: Based on the symbol frequency statistics in the compression parameters, reconstruct a symbol probability distribution table consistent with the terminal device; For analog voltage / current data, differential decoding combined with adaptive arithmetic decoding is used to restore periodic waveforms; For remote signaling switch data, run-length decoding (RLE) is used to reconstruct continuous state changes; After decoding each data block, the length of the decoded data is checked to see if it matches the length of the data declared in the compression parameter area. If they do not match, a retransmission mechanism is triggered. The decoded voltage, current, and remote signaling data are rearranged according to the timestamp and the number of data points to generate a time-series data stream that matches the original data collected by the terminal device, thus restoring the original data.

[0038] In this embodiment, the main CPU performs real-time symbol frequency statistics on the collected voltage, current, and remote signaling data and establishes a dynamic probability model, such as... Figure 8 As shown, this is achieved through the following steps: The main CPU converts the collected analog voltage and current data into discrete symbol sequences according to the preset compression bit width (4 / 8 / 12 / 16 bits), and the remote signaling switch data is directly mapped into binary symbols (0 / 1), forming the raw symbol stream to be statistically analyzed; The main CPU uses a sliding window mechanism to perform real-time statistics on the raw symbol stream. The window length L is dynamically adjusted according to the data sampling rate, satisfying the following conditions: Voltage / current data window: L = N×T, where N is the number of sampling points per cycle and T is the fundamental frequency period, such as 20ms for 50Hz, to ensure full coverage of the waveform characteristics of the cycle; Remote signaling data window: L = M × Δt, where M is the threshold for the number of state changes and Δt is the minimum statistical time interval, such as 10ms, to capture the switching quantity jump pattern; Within each window, the main CPU counts the frequency f(s) of each symbol and calculates the relative frequency P(s) = f(s) / L to form an initial symbol frequency table; The main CPU updates the symbol probability model in real time according to the following rules: Exponentially weighted average (EMA) smoothing: the sign frequency P of the current window statistics. t (s) and historical model probability P {t-1} (s) performs weighted fusion, and the updated formula is: P t (s) = α × P t (s) + (1-α) × P {t-1} (s) Wherein, α is a smoothing factor (0<α≤1), with α=0.3 for voltage / current data to preserve periodicity, and α=0.7 for remote signaling data to respond quickly to state changes; Threshold-triggered update: When the frequency change of a certain symbol in the new window |P t (s)-P {t-1} When (s)| exceeds a preset threshold ΔP (e.g., 5%), the probability of the symbol is forcibly updated, and the association probability of adjacent symbols is reset.

[0039] In this embodiment, the main CPU independently establishes probabilistic models for the three data streams: voltage, current, and remote signaling, and maintains timing synchronization through the following steps: A timestamp is appended to the end of each sliding window to ensure that the updates of the three models are aligned with the data sampling time; A joint probability table is established for the amplitude symbols of voltage / current and the remote signaling status symbols. When the remote signaling status changes, the initial probability distribution of the corresponding voltage / current symbols is adjusted synchronously. The main CPU performs lightweight processing on the dynamic probability model: Sparse storage: Only symbols with a frequency higher than a minimum threshold (e.g., 1%) and their probabilities are retained; zero-frequency symbols are marked as the default value. Differential encoding: Stores the probability change ΔP(s) between adjacent time windows instead of the absolute value, reducing the amount of model data; The optimized model parameters are stored in channels-by-channel blocks in the main CPU's fast cache for the adaptive arithmetic coding engine to access in real time.

[0040] In this embodiment, the adaptive coding engine dynamically allocates the coding bit width according to the symbol frequency, which is specifically achieved through the following steps: The main CPU divides symbols into K levels (K≥3) based on the real-time statistical symbol frequency P(s) and establishes a frequency-bit width mapping table that satisfies the following conditions: The lower frequency threshold T of the i-th level symbol i This can be expressed as the following formula: T i = P max × (β) (i-1) Among them, P max The highest frequency among all symbols is β, which is the attenuation coefficient (0 < β < 1). For voltage / current data, β = 0.5 is used to retain high-frequency components, and for remote signaling data, β = 0.7 is used to balance abrupt changes in state and stability. The encoding bit width B of the i-th level symbol allocation i satisfy:

[0041] And restrict B i ∈[B min B max ], where B min For the minimum bit width (e.g., 2 bits), B max To achieve the maximum bit width (e.g., 16 bits), ensure a balance between encoding efficiency and hardware resources; In each compression cycle, the main CPU updates the symbol encoding bit width according to the following strategy: Calculate the symbol frequency P of the current period t (s) and the frequency P of the previous cycle {t-1} The relative rate of change of (s): ΔP(s) = |P t (s) - P {t-1} (s)| / P {t-1} (s) If ΔP(s) exceeds the preset threshold ΔP th (e.g., 10%), then bit width adjustment is triggered; When a bit width increase is required (e.g., due to a sudden increase in low-frequency symbols), a step-by-step adjustment strategy is adopted: B new = B old + ΔB step Where, ΔB step Use a step value (e.g., 1 bit) to avoid sudden changes in bit width that could cause a sharp drop in coding efficiency. When a reduction in bit width is required, such as when high-frequency symbols continue to dominate, immediately update to the target bit width; The main CPU pre-stores the bit width mapping table into the hardware lookup unit (LUT), and directly obtains the corresponding bit width through the symbolic index, reducing real-time calculation latency; As a preferred approach, the main CPU jointly optimizes the encoding bit width of the three data streams: voltage, current, and remote signaling. Total bit width budget allocation: According to the maximum data length L of a single frame specified in the communication protocol max Dynamically allocate the bit width budget for each channel: L v + L i + L x ≤ L max Among them, L v L i L x The compressed data lengths for voltage, current, and remote signaling channels are respectively, prioritizing the bit width requirements of high-frequency data (such as voltage). Bit-width borrowing mechanism: When the data volume of a certain channel exceeds the budget due to a sudden low-frequency symbol, the remaining bit width of other channels is temporarily borrowed and returned in the next cycle to ensure data integrity.

[0042] In this embodiment, the main CPU handles abnormal symbols, such as symbols that are not counted or have a frequency of zero, through the following measures: Default bit width allocation: For new symbols that do not appear in the frequency statistics table, allocate the maximum bit width B_max to ensure codeability; Zero-frequency symbol compression: For symbols with a frequency of zero, escape coding is used: Reserve 1 bit as an escape flag (e.g., "1"); The original value followed by the sign, such as an 8-bit unsigned integer, sacrifices a small amount of compression ratio for versatility; After each data block is encoded, the deviation between the actual bit width and the budgeted bit width is checked. If the deviation exceeds 5%, the system rolls back to the previous stable state and the bit width is reallocated. The main CPU embeds the encoding bit width parameter into the compressed data frame header, as shown in Table 1, for synchronous decompression by the remote backend master station. The bit width adjustment time is marked by a global timestamp to ensure that the model state of the decompression end and the compression end is consistent.

[0043] Table 1: Frame Header Field Design

[0044] In this embodiment, the main CPU achieves efficient data transmission through multi-channel parallel processing and compressed data encapsulation, specifically including the following steps: The main CPU uses a hardware parallel computing unit (PCU) to independently perform modeling and encoding of the three data streams: voltage, current, and remote signaling. The specific implementation is as follows: Each data stream is allocated an independent dynamic probability model storage area, such as 4KB each for voltage and current, and 1KB for remote signaling, stored in the main CPU's high-speed static random access memory (SRAM) to avoid model cross-interference; each channel is equipped with a dedicated arithmetic coding engine ACE, supporting 4 / 8 / 12 / 16-bit adaptive bit width coding; The main CPU dynamically allocates computing resources through the hardware task scheduler (TS): Voltage / current path: Prioritize allocation to dual-core ARM Cortex-M7 processors, utilizing the Single Instruction Multiple Data (SIMD) instruction set to process periodic analog quantities in parallel; Remote signaling channel: Equipped with a single-core ARM Cortex-M3 processor, using interrupt-driven mode to respond to switch quantity changes in real time; Each channel's encoding task is synchronized with the main CPU's clock frequency via a first-in-first-out (FIFO) queue to ensure timing consistency; The global timestamp generator (TSG) inserts a 64-bit nanosecond-level timestamp at each data sampling time of each channel; When the remote signaling status changes, the model synchronization update of the voltage / current channel is triggered, and the corresponding encoding engine is notified to pause the calculation through the hardware signal line (INT_SYNC). The calculation will resume after the model update is completed. In this embodiment, the main CPU frames the encoded three data streams and metadata according to a custom communication protocol to form a compressed data packet with encryption and verification. The specific encapsulation rules are shown in Tables 2 and 3: Table 2: Data Packet Structure

[0045] Table 3: Channel data subframe format (taking voltage channel as an example)

[0046] When implementing encryption and verification, the main CPU calls the AES-128 engine in the Hardware Security Module (HSM) to encrypt the plaintext of the three data streams from the frame header to the channel using a preset key. The key is rotated every 24 hours. Calculate the CRC32 check value for the plaintext before encryption, then encrypt the check value with AES to generate a 32-bit encrypted check field. The decompression end needs to decrypt the check value before verifying the data integrity. If the encoding engine of a certain channel times out (e.g., no response for more than 1ms), the main CPU automatically marks the channel as "faulty", skips its data encapsulation, and sets the corresponding channel's error flag in the frame header, such as voltage channel fault = 0b100; the faulty channel data is retransmitted in the next cycle, the retransmitted data frame header version identifier is upgraded to v1.1, and a retransmission sequence number is added; When the decompression end detects that the encryption verification has failed, it sends a retransmission request (RTR) to the main CPU. The main CPU then retransmits the three most recent historical data packets through a reserved emergency communication channel (such as RS-485). If remote signaling channel data is lost, the decompression end will default to the state of the previous cycle and trigger an alarm signal (such as LED flashing). In practical applications, this method is implemented using the following hardware configuration in a certain type of feeder terminal equipment: The main CPU is an NXP MPC5748G (dual-core M7 + single-core M3, 200MHz). Its multi-core architecture and high clock speed provide ample computing resources for dynamic compression algorithms (symbol frequency statistics, bit width allocation) and multi-channel parallel scheduling. The dual-core M7 can process complex calculations of voltage and current channels in parallel, while the single-core M3 focuses on fast response of remote signaling channels, ensuring algorithm execution efficiency and real-time performance, and avoiding data backlog caused by computational delays. Parallel computing unit: Xilinx Spartan-7 FPGA (implementing 3-channel ACE and TSG), whose programmable logic resources directly implement the three-channel adaptive arithmetic coding engine (ACE) and global timestamp generator (TSG). The FPGA hardware-level parallel computing capability enables the synchronous execution of three-channel coding tasks, reducing latency from milliseconds in traditional software to microseconds, while consuming far less power than multi-core CPU expansion solutions, balancing efficiency and energy efficiency; Memory: IS61LV25616AL SRAM (256KB, for model storage), with its high-speed read / write characteristics and large capacity design, can store and quickly recall the three-channel dynamic probabilistic model in real time. When the remote signaling state changes abruptly, the main CPU can quickly update the model parameters and write them to the SRAM, and the FPGA synchronously loads the new model, ensuring that the encoding engine always runs based on the latest data features and avoiding the decrease in compression efficiency caused by model lag; Communication Interface: TI TJA1051 CAN transceiver, supporting 1Mbps high-speed communication and compliant with the IEC 61850-9-2 LE protocol standard, seamlessly compatible with existing power system communication networks. Its strong anti-interference capability (common-mode rejection ratio ≥20kV / μs) and fault protection mechanisms (such as bus short-circuit protection) ensure stable data transmission in complex electromagnetic environments, reducing bit error rate and retransmission frequency, and improving overall communication efficiency.

[0047] Therefore, the feeder terminal equipment proposed in this invention, which improves equipment performance based on data compression, provides an efficient, reliable, and secure solution for the field of power system distribution automation through the collaborative innovation of dynamic compression, multi-channel parallel processing, encrypted transmission, and anti-interference design. It has broad application prospects and promotional value.

[0048] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A feeder terminal device for improving equipment performance based on data compression, characterized in that, include: Voltage acquisition circuit, used to acquire analog voltage transmitted from primary equipment and convert it into digital signal; The current acquisition circuit is used to acquire the analog current transmitted from the primary equipment and convert it into a digital signal; Remote signaling acquisition circuit is used to acquire switch signals transmitted from primary equipment and convert them into digital signals; The main CPU, connected to the voltage acquisition circuit, current acquisition circuit and remote signaling acquisition circuit, is used to receive the converted digital signal and store the acquired data in the buffer area. When the waveform recording event is triggered, the data is compressed and saved to the memory. The communication interface circuit is connected to the main CPU and is used to send the compressed data to the remote back-end main station according to a custom communication protocol when the remote back-end main station obtains waveform data or when a waveform event is triggered. The remote backend master station is used to receive compressed data, parse the compressed data according to a custom communication protocol, decompress and restore the original data for processing; the custom communication protocol adopts a data compression algorithm based on adaptive arithmetic coding, which achieves data compression by dynamically adjusting the symbol probability distribution.

2. The feeder terminal equipment according to claim 1, characterized in that, Data compression algorithms based on adaptive arithmetic coding achieve data compression by dynamically adjusting the symbol probability distribution, including: Symbol frequency statistics: The main CPU performs real-time symbol frequency statistics on the collected voltage, current, and remote signaling data, and establishes a dynamic probability model; Adaptive coding engine: Dynamically allocates coding bit width according to symbol frequency, using short bit width coding for high-frequency symbols and long bit width coding for low-frequency symbols; Multi-channel parallel processing: Independent modeling and encoding of three data streams—voltage, current, and remote signaling—improves compression efficiency through parallel computing; Compressed data encapsulation: The encoded data stream, along with parameters such as compression bit width, data length, and timestamp, is processed according to a custom communication protocol to form a compressed data packet with encryption and verification.

3. The feeder terminal equipment according to claim 1, characterized in that, Data compression processing includes various compression methods based on compression bit width markers, specifically: 4-bit compression width, compression rate of 75%; 8-bit compressed bit width, compression rate of 50%; 12-bit compressed bit width, compression rate of 25%; A 16-bit compression width indicates no compression.

4. The feeder terminal equipment according to claim 1, characterized in that, When a waveform recording event is triggered, the main CPU performs data compression and parameter framing through the following steps: The main CPU reads the preset compression configuration table from the memory to determine the compression bit width, data sampling rate and cycle length parameters applicable to the current waveform data; The main CPU performs layered compression on the acquired voltage, current, and telemetry data according to the compression bit width: For analog voltage / current data, differential coding combined with adaptive arithmetic coding is used to eliminate periodic redundancy; For remote signaling switch data, run-length encoding is used to compress consecutive identical states; Calculate the length of the compressed data in real time and mark the number of valid data points; The main CPU frames the compressed data with the following parameters according to the communication protocol format: Frame header: Fixed identifier + device ID; Compression parameter area: 4-bit compression width marker, 16-bit data length, 8-bit cycle number, 16-bit data point number; Compressed data area: Encoded data stream encapsulated by bit width; Verification area: CRC16 checksum; The main CPU writes the framed data packets to a designated area of ​​memory and updates the data index table, recording the timestamps and data addresses of the waveform events.

5. The feeder terminal equipment according to claim 4, characterized in that, After receiving the compressed data, the remote backend master station performs parsing and decompression based on adaptive arithmetic coding through the following steps: After receiving the data packet, the communication interface module of the remote back-end master station parses the frame header according to the communication protocol format, verifies the device ID and the CRC16 check code in the check area, and confirms the data integrity. Extract the 4-bit compression bit width marker, 16-bit data length, 8-bit cycle number, and 16-bit data point number from the compression parameter area to determine the bit width configuration and data range required for decompression. Initialize the decoding engine based on the compressed bit width and perform the following operations: Dynamic probability model reconstruction: Based on the symbol frequency statistics in the compression parameters, reconstruct a symbol probability distribution table consistent with the terminal device; For analog voltage / current data, differential decoding combined with adaptive arithmetic decoding is used to restore periodic waveforms; For remote signaling switch data, run-length decoding is used to restore continuous state changes; After decoding each data block, the length of the decoded data is checked to see if it matches the length of the data declared in the compression parameter area. If they do not match, a retransmission mechanism is triggered. The decoded voltage, current, and remote signaling data are rearranged according to the timestamp and the number of data points to generate a time-series data stream that matches the original data collected by the terminal device, thus restoring the original data.

6. The feeder terminal equipment according to claim 1, characterized in that, The main CPU performs real-time symbol frequency statistics on the collected voltage, current, and remote signaling data and establishes a dynamic probability model, which is achieved through the following steps: The main CPU converts the collected analog voltage and current data into discrete symbol sequences according to a preset compressed bit width, and the remote signaling switch data is directly mapped into binary symbols to form the raw symbol stream to be statistically analyzed. The main CPU uses a sliding window mechanism to perform real-time statistics on the raw symbol stream. The window length L is dynamically adjusted according to the data sampling rate, satisfying the following conditions: Voltage / current data window: L = N×T, where N is the number of sampling points per cycle and T is the fundamental period, ensuring full coverage of the waveform characteristics of the cycle; Remote signaling data window: L = M × Δt, where M is the threshold for the number of state changes and Δt is the minimum statistical time interval, capturing the switching quantity jump pattern; Within each window, the main CPU counts the frequency f(s) of each symbol and calculates the relative frequency P(s) = f(s) / L to form an initial symbol frequency table; The main CPU updates the symbol probability model in real time according to the following rules: Exponentially weighted average smoothing: the sign frequency P of the current window statistics t (s) and historical model probability P {t-1} (s) performs weighted fusion, and the updated formula is: P t (s) = α × P t (s) + (1-a) × P {t-1} (s) Where α is the smoothing factor; Threshold-triggered update: When the frequency change of a certain symbol in the new window |P t (s)-P {t-1} When (s)| exceeds the preset threshold ΔP, the probability of the symbol is forcibly updated, and the association probability of adjacent symbols is reset.

7. The feeder terminal equipment according to claim 6, characterized in that, The adaptive coding engine dynamically allocates the coding bit width based on the symbol frequency, which is achieved through the following steps: The main CPU divides symbols into K levels based on the real-time statistical symbol frequency P(s) and establishes a frequency-bit width mapping table, satisfying the following conditions: The lower frequency threshold T of the i-th level symbol i This can be expressed as the following formula: T i =P max × (b) (i-1) Among them, P max The highest frequency among all symbols, β is the attenuation coefficient; The encoding bit width B of the i-th level symbol allocation i satisfy: And restrict B i ∈[B min B max ], where B min For minimum bit width, B max This represents the maximum bit width.

8. The feeder terminal equipment according to claim 7, characterized in that, During each compression cycle, the main CPU updates the symbol encoding bit width according to the following strategy: Calculate the symbol frequency P of the current period t (s) and the frequency P of the previous cycle {t-1} The relative rate of change of (s): ΔP(s) = |P t (s) - P {t-1} (s)| / P {t-1} (s) If ΔP(s) exceeds the preset threshold ΔP th (e.g., 10%), then bit width adjustment is triggered; When it is necessary to increase the bit width, a step-by-step adjustment strategy is adopted: B new = B old + ΔB step Where, ΔB step This is a step value to avoid sudden changes in bit width that could cause a sharp drop in coding efficiency. When the bit width needs to be reduced, update to the target bit width immediately; The main CPU pre-stores the bit width mapping table to the hardware lookup unit, and directly obtains the corresponding bit width through the symbol index, reducing real-time calculation latency.

9. The feeder terminal equipment according to claim 2, characterized in that: The main CPU uses a hardware parallel computing unit to independently perform modeling and encoding of the three data streams: voltage, current, and remote signaling. It allocates an independent dynamic probability model storage area for each data stream and stores it in the main CPU's high-speed static random access memory. The main CPU dynamically allocates computing resources through a hardware task scheduler: Voltage / current path: Prioritize allocation to dual-core ARM Cortex-M7 processors, utilizing single-instruction multiple-data instruction set to process periodic analog quantities in parallel; Remote signaling channel: Equipped with a single-core ARM Cortex-M3 processor, using interrupt-driven mode to respond to switch quantity changes in real time; When the remote signaling status changes, the model of the voltage / current channel is synchronously updated, and the corresponding encoding engine is notified to pause the calculation via a hardware signal line. The calculation will resume after the model update is completed.

10. The feeder terminal equipment according to claim 2, characterized in that: The main CPU frames the encoded three data streams and metadata according to a custom communication protocol to form a compressed data packet with encryption and verification. When implementing encryption and verification, the main CPU calls the AES-128 engine in the hardware security module and uses a preset key to encrypt the plaintext of the three data streams from the frame header to the channel. The key is rotated every 24 hours. Calculate the CRC32 check value for the plaintext before encryption, then encrypt the check value with AES to generate a 32-bit encrypted check field. The decompression end needs to decrypt the check value before verifying the data integrity. If the encoding engine of a certain channel times out, the main CPU automatically marks the channel as faulty, skips its data encapsulation, and sets the error flag of the corresponding channel in the frame header; the faulty channel data is retransmitted in the next cycle, the version identifier of the retransmitted data frame header is upgraded to v1.1, and a retransmission sequence number is added; When the decompression end detects that the encryption verification has failed, it sends a retransmission request to the main CPU. The main CPU then retransmits the three most recent historical data packets through the reserved emergency communication channel. If remote signaling channel data is lost, the decompression end will default to the state of the previous cycle and trigger an alarm signal.

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