Pole-mounted circuit breaker logic control system based on intelligent distribution network protocol

Abstract

The present application relates to the control and regulation field of power distribution network relay protection control, and proposes a pole-mounted circuit breaker logic control system based on an intelligent distribution network protocol. A protocol analysis engine extracts a topology change identifier and an adjacent node operating state frame from an intelligent distribution network message; a topology reconfigurator constructs a dynamic logic topology matrix accordingly; a cascading calculator inputs the dynamic logic topology matrix into a protection cascading depth calculation model to obtain hierarchical characteristic values; a logic controller maps the hierarchical characteristic values into an adaptive delay coefficient and writes the adaptive delay coefficient into a closing and opening timing register; and when a fault current characteristic quantity exceeds a limit, a delay trip control logic is executed according to the adaptive delay coefficient. The present application overcomes the defect of protection time limit coordination failure caused by dynamic changes in the distribution network topology, eliminates overstep tripping, and improves the selectivity of relay protection.

Description

Technical Field

[0001] This invention relates to the field of distribution network relay protection control in the field of control and regulation technology, and proposes a logic control system for pole-mounted circuit breakers based on smart distribution network protocols. Background Technology

[0002] Existing pole-mounted circuit breaker logic control systems in distribution network relay protection primarily employ a tiered time-delay coordination principle to achieve fault isolation. In this conventional approach, the circuit breaker at the substation's outlet is set with the longest delay setting, while the delay settings of downstream pole-mounted circuit breakers decrease sequentially according to their distance from the power source. When a short-circuit fault occurs, all circuit breakers along the fault current path will activate their protection logic. The circuit breaker closest to the fault point, with the shortest delay setting, will act first to isolate the fault, while upstream circuit breakers will return before their delay expires, thus achieving selective protection. The core of this control logic lies in the strict matching and fixed consistency of the operating delay time differences of each circuit breaker. The delay settings are permanently stored in memory before the system leaves the factory or is put into operation, remaining unchanged during operation.

[0003] With the increasing automation of distribution networks, smart distribution network protocols are widely used for data interaction between distribution master stations and terminal equipment. In current conventional implementations, smart distribution network protocols mainly undertake basic communication functions such as issuing remote control commands, uploading remote signaling data, and setting value calls. In actual operation of distribution networks, to optimize power supply reliability, load transfer, automatic power supply switching, or power restoration to non-faulty sections due to front-end faults are frequently performed. These operations cause frequent dynamic changes in the physical topology of the distribution network. After a topology change, the existing system only updates the topology graphic screen of the master station. The local logic control system of the pole-mounted circuit breaker still uses the fixed delay setting value set at the initial commissioning, failing to establish a data flow and logical mapping relationship between the topology change information in the protocol message and the local protection control timing.

[0004] Existing pole-mounted circuit breaker logic control systems employ a fixed delay coordination strategy. When the distribution network topology changes due to load transfer or fault reconfiguration, the original fixed delay settings cannot match the new cascading relationships. In loop transfer or multi-source interconnection scenarios, changes in power flow direction cause circuit breakers that were originally upstream to become downstream, but the delay settings are not adjusted accordingly. This results in circuit breakers closer to the power source tripping before downstream circuit breakers due to their shorter delays when a fault occurs, leading to cascading tripping and expanding the power outage area. The mismatch between delay settings and dynamic topology cascading relationships constitutes the core problem of existing technology, stemming from the lack of technical means to convert the dynamic topology characteristics in protocol messages into local delay control parameters for circuit breakers in real time. Summary of the Invention

[0005] The purpose of this invention is to provide a logic control system for pole-mounted circuit breakers based on a smart distribution network protocol, which can effectively solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] The pole-mounted circuit breaker logic control system based on the smart distribution network protocol includes a protocol parsing engine that extracts topology change identifiers and adjacent node operating status frames from smart distribution network messages; a topology reconfigurator that constructs a dynamic logical topology matrix based on the topology change identifiers and adjacent node operating status frames; a cascading calculator that inputs the dynamic logical topology matrix into a protection cascading depth calculation model to obtain the hierarchical feature values ​​of the current pole-mounted circuit breaker in the topology; and a logic controller that maps the hierarchical feature values ​​to adaptive delay coefficients and writes them into the opening and closing timing register. When the fault current feature exceeds the limit, the delayed tripping control logic is executed according to the adaptive delay coefficients.

[0008] Preferably, the process by which the protocol parsing engine extracts the topology change identifier and the adjacent node operating status frame from the smart distribution network message includes: decrypting and verifying the frame header of the received smart distribution network message, stripping the message transmission encapsulation layer to obtain the application layer payload; identifying the service primitive type identifier in the application layer payload; when the service primitive type identifier is a topology announcement type, extracting the node identifier list and link state vector in the application layer payload as the topology change identifier; when the service primitive type identifier is a status upload type, extracting the switch position dual-point information and protection action soft pressure plate status in the application layer payload as the adjacent node operating status frame.

[0009] Preferably, the process by which the topology reconfigurator constructs a dynamic logical topology matrix based on the topology change identifier and the adjacent node operating status frame includes: initializing a zero-based matrix using each pole-mounted circuit breaker node in the distribution network as the matrix row and column indices; traversing the node identifier list and link status vector in the topology change identifier, and writing link connectivity weight values ​​at the corresponding row and column positions in the zero-based matrix; combining the switch position dual-point information and protection action soft-pressurization state in the adjacent node operating status frame, performing availability correction on the link connectivity weight values, setting the weight values ​​corresponding to unavailable links to zero, and generating a dynamic logical topology matrix characterizing the dual attributes of physical connectivity and electrical availability of the current distribution network.

[0010] Preferably, the process by which the cascade calculator inputs the dynamic logic topology matrix into the protection cascade depth calculation model to obtain the hierarchical feature value of the current pole-mounted circuit breaker in the topology includes: taking the power supply side root node as the search starting point, performing a depth-first search traversal on the dynamic logic topology matrix, recording the number of node hops with non-zero available link weights traversed from the power supply side root node to the current pole-mounted circuit breaker node; performing a weighted fusion operation on the number of node hops and the number of downstream branches associated with the current pole-mounted circuit breaker node in the dynamic logic topology matrix, and using the operation result as the hierarchical feature value of the current pole-mounted circuit breaker in the topology.

[0011] Preferably, the logic controller maps the hierarchical feature value to an adaptive delay coefficient and writes it into the trip timing register. When the fault current feature value exceeds the limit, the process of executing the delayed trip control logic based on the adaptive delay coefficient includes: calculating the delay time difference uniquely corresponding to the hierarchical feature value according to the preset hierarchical feature value and time ladder mapping function; adding the basic protection action delay setting value to the delay time difference to obtain the adaptive delay coefficient, and writing the adaptive delay coefficient into the comparison register in the trip timing register; when the fault current feature value exceeds the limit and the internal timer count value reaches the adaptive delay coefficient in the comparison register, outputting the trip drive level.

[0012] Preferably, the process of modifying the availability of the link connectivity weight value by combining the switch position dual-point information and the protection action soft pressure plate status in the adjacent node operation status frame includes: extracting the switch position dual-point information of the corresponding node in the adjacent node operation status frame; when the switch position dual-point information is in the open state, cutting off the weight assignment path of the link corresponding to the switch position in the dynamic logic topology matrix; extracting the protection action soft pressure plate status; when the protection action soft pressure plate status is in the exit state, setting the protection blocking flag of the node corresponding to the soft pressure plate; and downgrading the path weight of the path passing through the node in the dynamic logic topology matrix according to the protection blocking flag, thereby completing the availability modification of the link connectivity weight value.

[0013] Preferably, the process of performing a depth-first search traversal of the dynamic logical topology matrix with the power supply-side root node as the search starting point includes: locating the row index of the power supply-side root node in the dynamic logical topology matrix, searching downstream along the non-zero weight column index, and recording the node sequence and cumulative hop count of the current search path; when the search reaches the final leaf node or encounters a weight downgrade node, backtracking to the previous branch node and continuing to search along other non-zero weight column indices until all connected paths starting from the power supply-side root node are traversed; if the current pole-mounted circuit breaker node exists in multiple connected paths, the hop count corresponding to the path with the largest cumulative hop count is selected as the effective traversal hop count of the current node to participate in the subsequent weighted fusion calculation.

[0014] Preferably, the process of outputting a trip drive level when the fault current characteristic exceeds the limit and the internal timer count reaches the adaptive delay coefficient in the comparison register includes: real-time sampling of the instantaneous values ​​of the three-phase current and calculation of the current mutation; activating the fault detection state when the current mutation exceeds the steady-state fluctuation threshold; calculating the effective value of the phase current and the effective value of the zero-sequence current in the fault detection state; triggering a hardware interrupt signal when the effective value of the phase current or the effective value of the zero-sequence current exceeds the corresponding adaptive current setting value; starting the internal timer in response to the hardware interrupt signal; and outputting the trip drive level to the circuit breaker operating mechanism when the current count value of the internal timer matches the adaptive delay coefficient stored in the comparison register.

[0015] Preferably, the protocol link monitor counts the number of consecutive frame drops and the number of cyclic redundancy check errors in the smart distribution network messages; when the number of consecutive frame drops exceeds the frame count threshold or the number of cyclic redundancy check errors exceeds the error count threshold, it determines that the communication link is interrupted and generates a protocol failure flag; the protocol failure flag is sent to the logic controller, and the logic controller responds to the protocol failure flag by blocking the channel for writing the adaptive delay coefficient into the circuit breaker timing register, and reading the fixed backup delay setting value pre-stored in the non-volatile memory to overwrite the contents of the current circuit breaker timing register, and controlling the circuit breaker to enter a degraded operation mode based on the locally fixed setting value.

[0016] Preferably, the adaptive current setting adjuster obtains the hierarchical feature value of the current pole-mounted circuit breaker in the topology output by the cascade calculator and the load aggregation capacity downstream of the current pole-mounted circuit breaker in the dynamic logic topology matrix; determines the protection sensitivity coefficient of the current node based on the hierarchical feature value, and calculates the expected maximum load current based on the load aggregation capacity; uses the product of the protection sensitivity coefficient and the expected maximum load current as the adaptive current setting value, and sends the adaptive current setting value to the fault current feature quantity over-limit judgment comparator to replace the initial default current setting value in the fault judgment logic.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0018] 1. This invention extracts topology change identifiers and adjacent node operating status frames from intelligent distribution network messages, and constructs a dynamic logical topology matrix accordingly. The matrix is ​​then input into a protection cascade depth calculation model to obtain hierarchical feature values, which are then mapped to adaptive delay coefficients and written into the opening and closing timing register to execute delayed tripping control logic, enabling the opening and closing timing to adapt to changes in the distribution network topology. The protocol parsing engine identifies service primitive type identifiers, extracts a list of node identifiers and link status vectors from the topology announcement type payload as topology change identifiers, and extracts switch position dual-point information and protection action soft-plate status from the status quantity upload type payload as operating status frames, providing multi-dimensional data sources for dynamic topology construction. The topology reconfigurator constructs an all-zero matrix using each node as an index, writes link connectivity weight values ​​based on the link status vectors, and performs availability correction on the weight values ​​by combining switch position dual-point information and protection action soft-plate status, setting unusable links to zero, generating a dynamic logical topology matrix with both physical connectivity and electrical availability attributes.

[0019] 2. The cascade calculator performs a depth-first search traversal of the matrix starting from the root node on the power supply side to obtain the node hop count. The node hop count is then weighted and fused with the number of associated downstream branches to obtain a hierarchical feature value. The logic controller calculates the delay time difference according to a preset mapping function and adds it to the basic setpoint to obtain an adaptive delay coefficient. This mechanism overcomes the defect of protection time-delay coordination failure caused by dynamic changes in the distribution network topology, eliminates cascading tripping, and improves the selectivity and reliability of relay protection actions.

[0020] 3. During the construction of the dynamic logic topology matrix, when the switch position double-point information is in the open state, the weight assignment path is cut off; when the protection action soft pressure plate state is in the exit state, the corresponding path weight is downgraded. This eliminates the interference of physically connected but electrically disconnected nodes and protection function exit nodes on the hierarchical calculation, improving the consistency between the topology matrix and the actual operating state. In the depth-first search traversal, if the current node exists in multiple connected paths, the path with the largest cumulative jump count is selected as the effective traversal jump count, ensuring that the hierarchical feature value reflects the most stringent cascading depth and avoiding false tripping caused by the protection setting being too small in multi-path scenarios.

[0021] 4. In the delayed trip execution phase, fault detection is activated based on sudden current changes. A hardware interrupt is triggered to start timing by comparing the effective values ​​of the phase current and zero-sequence current with the adaptive setting value. When the count value matches the adaptive delay coefficient in the comparison register, a trip drive level is output, ensuring the determinism and real-time performance of the adaptive delay logic at the underlying hardware execution level. When the number of consecutive frame drops or cyclic redundancy check errors counted by the protocol link monitor exceeds the threshold and generates a protocol failure flag, the logic controller blocks the adaptive delay coefficient writing channel and reads the solidified backup delay setting value overwrite register, causing the system to enter a degraded operation mode and preventing control logic disorder during communication interruptions. The adaptive setting value adjuster determines the sensitivity coefficient based on hierarchical characteristic values, calculates the expected maximum load current in conjunction with the downstream load aggregation capacity, and generates an adaptive current setting value to replace the default setting value in the judgment. This allows the fault identification threshold to dynamically adjust with the topology cascade location and load level, enhancing the accuracy of fault identification under different operating conditions. Attached Figure Description

[0022] Figure 1 Flowchart for intelligent distribution network message parsing and topology data extraction;

[0023] Figure 2 Flowchart for dynamic logical topology matrix construction and availability correction;

[0024] Figure 3 Flowchart for protecting cascade depth calculation and hierarchical feature value generation;

[0025] Figure 4 The flowchart for adaptive delay coefficient mapping and delay trip control is shown below;

[0026] Figure 5 Flowchart for protocol link monitoring and system degradation operation;

[0027] Figure 6 Flowchart for adaptive adjustment of setpoints and update of fault judgment parameters. Detailed Implementation

[0028] In a preferred embodiment, the pole-mounted circuit breaker logic control system based on the smart distribution network protocol includes a protocol parsing engine, a topology reconfigurator, a cascading calculator, and a logic controller. The protocol parsing engine is electrically connected to the smart distribution network communication interface and receives smart distribution network messages from the distribution master station or adjacent pole-mounted circuit breaker nodes.

[0029] The input of the topology reconfigurator is electrically connected to the output of the protocol parsing engine, receiving the topology change identifier and adjacent node running status frames output by the protocol parsing engine. The input of the cascade calculator is electrically connected to the output of the topology reconfigurator, receiving the dynamic logical topology matrix output by the topology reconfigurator. The input of the logic controller is electrically connected to the output of the cascade calculator, receiving the hierarchical characteristic values ​​output by the cascade calculator. The output of the logic controller is electrically connected to the opening and closing timing register and operating mechanism of the pole-mounted circuit breaker.

[0030] Reference Figure 1 In this embodiment, the protocol parsing engine extracts the topology change identifier and adjacent node operating status frames from the smart distribution network (SDN) message. The SDN message adopts the manufacturing message specification format of the IEC 61850 standard, and its structure includes a frame header, transmission control field, application layer payload, and checksum field. The protocol parsing engine preprocesses the received SDN message, extracting the source address, destination address, and application identifier fields to determine the sending node and message type.

[0031] The topology reconfigurator constructs a dynamic logical topology matrix based on the topology change identifiers output by the protocol parsing engine and the operating status frames of adjacent nodes. The dynamic logical topology matrix is ​​an n×n square matrix, where n is the total number of pole-mounted circuit breaker nodes in the distribution network, and each element in the matrix represents the link connectivity and electrical availability between the corresponding two nodes.

[0032] The cascading calculator inputs the dynamic logic topology matrix into the protection cascading depth calculation model to obtain the hierarchical characteristic value of the current pole-mounted circuit breaker in the topology. The protection cascading depth calculation model is constructed based on the shortest path algorithm and node importance evaluation method in graph theory, and can quantitatively characterize the cascading depth of the current pole-mounted circuit breaker relative to the power source side in the distribution network topology.

[0033] The logic controller maps hierarchical feature values ​​to adaptive delay coefficients and writes them into the trip / close timing register. The trip / close timing register includes a counting register and a comparison register. The counting register is used to accumulate the number of timing pulses in real time, and the comparison register is used to store the delay threshold. When the fault current feature exceeds the limit, the logic controller executes the delayed trip control logic based on the adaptive delay coefficient. The fault current feature includes current surges, phase current RMS values, and zero-sequence current RMS values, which are acquired by current transformers and input to the logic controller after analog-to-digital conversion.

[0034] Specifically, when a topology change occurs in the distribution network, the distribution master station or adjacent nodes send a topology announcement message to this node via the smart distribution network protocol. The protocol parsing engine identifies this message as a topology change-related message and extracts the topology change identifier. Simultaneously, the protocol parsing engine receives status upload messages periodically sent by adjacent nodes and extracts the adjacent node operating status frames from them.

[0035] The topology reconfigurator updates the element values ​​of the dynamic logical topology matrix based on the latest topology change identifier and the operating status frames of adjacent nodes. The cascade calculator recalculates the hierarchical characteristic values ​​of the current node based on the updated dynamic logical topology matrix. The logic controller updates the adaptive delay coefficient in the trip / close timing register based on the new hierarchical characteristic values. When a short-circuit fault occurs on the line, if the fault current characteristic exceeds a preset threshold, the logic controller starts an internal timer. When the timer count reaches the adaptive delay coefficient, it outputs a trip drive level to the circuit breaker operating mechanism, causing the circuit breaker to trip and clear the fault.

[0036] In this embodiment, the elements of the dynamic logical topology matrix are defined as follows:

[0037] When there is a usable link between node i and node . When there is no available link between node i and node i, .in, Let be the element in the i-th row and j-th column of the dynamic logical topology matrix. This represents the link connectivity weight between node i and node j. The link connectivity weight is preset based on the link's impedance characteristics and transmission capacity, and its value is a real number between 0 and 1.

[0038] The input to the protection cascaded deep computation model is the dynamic logical topology matrix A and the current node number k, and the output is the hierarchical feature value of the current node. The calculation process of hierarchical feature values ​​is based on a depth-first search algorithm. Starting from the root node on the power supply side, it traverses all reachable paths, calculates the maximum number of hops for the current node, and performs weighted fusion by combining the number of downstream branches.

[0039] The mapping relationship of the adaptive delay coefficient is determined by a preset hierarchical characteristic value and a time ladder mapping function. The mapping function adopts a piecewise linear function form, mapping hierarchical characteristic values ​​of different ranges to corresponding delay time differences. The delay time difference is added to the basic protection action delay setting to obtain the final adaptive delay coefficient. The basic protection action delay setting is preset according to the overall protection coordination requirements of the distribution network and stored in non-volatile memory.

[0040] This embodiment extracts dynamic topology information by parsing smart distribution network messages, constructs a dynamic logical topology matrix that reflects the actual operating status of the distribution network in real time, calculates the hierarchical feature values ​​of nodes based on the topology matrix and maps them to adaptive delay coefficients, so that the protection action sequence of pole-mounted circuit breakers can adapt to changes in the distribution network topology.

[0041] In a preferred embodiment, the process by which the protocol parsing engine extracts the topology change identifier and adjacent node operating status frames from the smart distribution network (SDN) message includes decrypting the received SDN message and verifying its frame header. The SDN message is encrypted using an Advanced Encryption Standard (AES), and the protocol parsing engine decrypts the message using a pre-configured session key.

[0042] After decryption, the protocol parsing engine verifies the packet header to check if the version number, packet length, and control fields in the header conform to the protocol specifications. If the header verification fails, the protocol parsing engine discards the packet and records the verification error information. If the header verification passes, the protocol parsing engine strips the packet's transport encapsulation layer to obtain the application layer payload data.

[0043] In this embodiment, the application layer payload includes a service primitive type identifier, a parameter length field, and a parameter data field. The protocol parsing engine identifies the service primitive type identifier in the application layer payload. The service primitive type identifier is a 1-byte unsigned integer, and different values ​​correspond to different service primitive types. When the service primitive type identifier is 0x01, it indicates that the message is a topology advertisement type message.

[0044] The protocol parsing engine extracts a list of node identifiers and a link state vector from the parameter data fields of the application layer payload as topology change identifiers. The node identifier list contains unique identifiers for all pole-mounted circuit breaker nodes involved in this topology change; each node identifier is a 2-byte unsigned integer. The link state vector is a binary vector, where each bit corresponds to the link state between two nodes in the node identifier list; a bit value of 1 indicates a connected link, and a bit value of 0 indicates a disconnected link.

[0045] When the service primitive type identifier is 0x02, it indicates that the message is a status upload type message. The protocol parsing engine extracts the switch position dual-point information and the protection action soft pressure plate status from the parameter data field of the application layer payload as the operating status frame of the adjacent node.

[0046] The switch position information is 2-bit binary data, used to indicate the current position status of the circuit breaker, where 00 indicates the open state, 01 indicates the closed state, 10 indicates the intermediate state, and 11 indicates the fault state. The protection action soft switch status is 1-bit binary data, with a bit value of 1 indicating that the protection action soft switch is engaged and a bit value of 0 indicating that the protection action soft switch is disengaged.

[0047] Specifically, the protocol parsing engine maintains a message receiving buffer to store received smart distribution network messages. When a complete message is available in the buffer, the protocol parsing engine initiates the message processing flow. First, the protocol parsing engine calls a decryption function to decrypt the message. The input to the decryption function is the encrypted message data and the session key, and the output is the decrypted plaintext data. The decryption function uses an electronic codebook mode, decrypting the plaintext data in blocks, with each block being 128 bits long.

[0048] After decryption, the protocol parsing engine verifies the frame header. Frame header verification includes version number verification, message length verification, and control field verification. Version number verification verifies whether the protocol version used in the message is compatible with the version supported by this node. Message length verification verifies whether the actual message length matches the length indicated in the frame header.

[0049] Control field validation verifies whether the reserved bits in the control field are 0 and whether the message type is valid. If any validation fails, the protocol parsing engine generates a validation error event, records the error type and message source address in the error log, and discards the message.

[0050] If the frame header verification passes, the protocol parsing engine strips the transport encapsulation layer of the packet. The transport encapsulation layer includes the Ethernet frame header, IP header, and TCP header. The protocol parsing engine sequentially strips these header information according to the protocol format of each layer to obtain the application layer payload data. The starting position of the application layer payload data is determined by the data offset field in the TCP header.

[0051] The protocol parsing engine parses the first byte of the application layer payload to obtain the service primitive type identifier. Depending on the service primitive type identifier, the protocol parsing engine executes different parsing procedures. For topology advertisement type messages, the protocol parsing engine first reads the parameter length field to determine the length of the parameter data field. Then, the protocol parsing engine reads the length of the node identifier list from the beginning of the parameter data field. This length is a 1-byte unsigned integer representing the number of nodes contained in the node identifier list.

[0052] Next, the protocol parsing engine reads the identifier of each node sequentially and stores it in a node identifier list array. Finally, the protocol parsing engine reads the link state vector, the length of which is... bytes, where m is the number of combinations of the number of nodes in the node identifier list, i.e. , where n is the number of nodes.

[0053] For status upload type messages, the protocol parsing engine also first reads the parameter length field. Then, the protocol parsing engine sequentially reads the switch position dual-point information and protection action soft pressure plate status of each adjacent node from the parameter data field.

[0054] The status information of each adjacent node occupies 1 byte, where the high 2 bits are the switch position information, the 3rd bit is the status of the protection action soft pressure plate, and the low 5 bits are reserved. The protocol parsing engine stores the parsed status information in the adjacent node status table. The adjacent node status table is indexed by the node identifier and stores the latest operating status of each adjacent node. The application layer payload format of the smart distribution network message is shown in Table 1.

[0055] Table 1. Description of Application Layer Payload Format for Smart Distribution Network Messages

[0056] Service primitive type identifier 1 The type of the service primitive is identified: 0x01 for topology announcement, 0x02 for state upload, and other values ​​are reserved. Parameter length 2 This indicates the total length of the parameter data field, in bytes. Parameter data variable Depending on the type of service primitive, it contains different parameter contents. Checksum 2 Cyclic redundancy check (CRC) values ​​of application layer payloads are used to verify the integrity of application layer data.

[0057] Table 1 illustrates the format of the application layer payload in smart distribution network messages. The service primitive type identifier field distinguishes different types of messages, the parameter length field indicates the length of the parameter data field, the parameter data field contains the actual message content, and the checksum field verifies the integrity of the application layer data.

[0058] When parsing the application layer payload, the protocol parsing engine first calculates the cyclic redundancy check (CRC) value in the parameter data field and compares it with the value in the checksum field. If the two are not equal, it indicates that the application layer data has been corrupted during transmission. The protocol parsing engine then discards the packet and records the checksum error.

[0059] This embodiment details the processing of smart distribution network messages by the protocol parsing engine, including decryption, frame header verification, transport encapsulation layer stripping, and application layer payload parsing. By identifying different types of service primitives, the protocol parsing engine can accurately extract topology change identifiers and adjacent node operating status frames, providing a reliable data source for subsequent dynamic topology construction.

[0060] Reference Figure 2 In a preferred embodiment, the process by which the topology reconfigurer constructs a dynamic logical topology matrix based on topology change identifiers and adjacent node operating status frames includes initializing a matrix of all zeros using each pole-mounted circuit breaker node in the distribution network as the matrix's row and column indices. The total number of pole-mounted circuit breaker nodes in the distribution network is n, therefore the dynamic logical topology matrix is ​​an n×n square matrix.

[0061] Both the row and column indices of the matrix correspond to unique identifiers of the nodes. The mapping between node identifiers and matrix indices is stored in the node index mapping table. The node index mapping table is established during system initialization, and the topology refactoring device updates the node index mapping table when a new node is added or an old node is removed.

[0062] In this embodiment, the topology reconfigurator traverses the node identifier list and link state vector in the topology change identifier, and writes the link connectivity weight value at the corresponding row and column position in the all-zero matrix. For each pair of nodes (i,j) in the node identifier list, the topology reconfigurator determines the link state between the two nodes based on the value of the corresponding bit in the link state vector.

[0063] If the value of the corresponding bit in the link state vector is 1, it indicates that there is a physical link between node i and node j. The topology reconfigurator writes the preset link connectivity weight value at the i-th row and j-th column and the j-th row and i-th column positions of the matrix. If the value of the corresponding bit in the link state vector is 0, it means that there is no physically connected link between node i and node j, and the topology reconfigurator keeps the value of the corresponding position in the matrix at 0.

[0064] The topology reconfigurator combines the switch position information and protection action soft-switch status from the adjacent node's operating status frame to perform availability correction on the link connectivity weight value. The purpose of availability correction is to eliminate the impact of physically connected but electrically disconnected or protection-disconnected links on the topology matrix. For each non-zero element in the matrix, the topology reconfigurator checks the switch position information of node i and node j. If the switch position information of node i or node j is in the open state, it indicates that the link is electrically disconnected, and the topology reconfigurator sets the element value at the corresponding position in the matrix to zero. If the switch position information of node i and node j is in the closed state, the topology reconfigurator further checks the protection action soft-switch status of node i and node j. If the protection action soft-switch status of node i or node j is in the disconnected state, it indicates that the protection function of that node is unavailable, and the topology reconfigurator multiplies the element value at the corresponding position in the matrix by a weight degradation coefficient. The weight degradation coefficient is a positive number less than 1, used to reduce the priority of paths passing through nodes whose protection functions have been disconnected.

[0065] Specifically, when the topology reconfigurator receives a new topology change identifier, it first creates a temporary all-zero matrix. Then, the topology reconfigurator parses the node identifier list in the topology change identifier to obtain all nodes involved in this topology change. For each node i in the node identifier list, the topology reconfigurator traverses all other nodes j in the node identifier list and calculates the corresponding positions of node i and node j in the link state vector. The calculation formula is:

[0066]

[0067] in, Let i be the position in the link state vector, and j be the node identifiers, where i is the node identifier and j is the node identifier. <j。

[0068] The topology reconfigurator reads the link state vector. The bit value at the location. If the bit value is 1, the topology reconfigurator writes the link connectivity weight value at the i-th row, j-th column and the j-th row, i-th column positions of the temporary matrix. Link connectivity weight value Based on the impedance characteristics of the link, the weight value is usually set to 0.8 for overhead lines and 0.9 for cable lines.

[0069] After writing the link connectivity weights, the topology refactorer performs availability correction on the temporary matrix. The topology refactorer iterates through all non-zero elements in the temporary matrix. For each non-zero element, the topology refactorer reads the node from the neighbor node state table. and nodes The two-point information of the switch position. The process of reading the two-point information of the switch position is as follows:

[0070]

[0071]

[0072] in, and These are the switch position information for nodes i and j, respectively. This is a state table for adjacent nodes. These are attribute fields for the node status table.

[0073] like 00 or A value of 00 indicates that node i or node j is in a tripped state, and the link is electrically unavailable. The topology reconfigurator performs the following operations:

[0074]

[0075]

[0076] The element in the j-th row and i-th column of the dynamic logical topology matrix;

[0077] like and Both values ​​are 0 or 1, indicating that both node i and node j are in the closed state, and the link is electrically available. The topology reconfigurator further reads the protection action soft switch status of node i and node j:

[0078]

[0079]

[0080] in, and These represent the soft pressure plate states of the protection actions for nodes i and j, respectively. This is a dedicated attribute field for the node status table.

[0081] like 0 or A value of 0 indicates that the protection action soft pressure plate of node i or node j is in the deactivated state. The topology reconfigurator performs the following operations:

[0082]

[0083]

[0084] in, This is the weighting downgrade coefficient, which ranges from 0.1 to 0.5. In this embodiment, it is set to 0.3.

[0085] After completing the availability correction for all non-zero elements, the topology refactorer copies the temporary matrix to the dynamic logical topology matrix, thus updating the dynamic logical topology matrix. The dynamic logical topology matrix is ​​stored in random access memory for fast access by the cascaded calculator.

[0086] This embodiment details the construction process of the dynamic logic topology matrix, including matrix initialization, writing link connectivity weight values, and availability correction. By combining the two-point information of switch positions and the soft-plate status of protection actions to correct the link connectivity weight values, the generated dynamic logic topology matrix can simultaneously reflect the physical connectivity and electrical availability status of the distribution network, providing an accurate topology basis for subsequent protection cascading depth calculations.

[0087] Reference Figure 3 In a preferred embodiment, the cascade calculator inputs the dynamic logic topology matrix into the protection cascade depth calculation model to obtain the hierarchical feature value of the current pole-mounted circuit breaker in the topology. This process includes performing a depth-first search traversal on the dynamic logic topology matrix, starting from the power supply side root node. The power supply side root node refers to the pole-mounted circuit breaker node directly connected to the substation busbar, and its node identifier is configured and stored in non-volatile memory during system initialization. The purpose of the depth-first search traversal is to find all possible paths from the power supply side root node to the current pole-mounted circuit breaker node and record the node hop count for each path.

[0088] In this embodiment, the cascading calculator records the number of node hops with non-zero weights on the available links traversed from the root node on the power supply side to the current pole-mounted circuit breaker node. The node hop count refers to the number of links traversed from the root node on the power supply side to the current node. For example, if it takes 3 available links to get from the root node on the power supply side to the current node, the node hop count is 3. If the current node exists in multiple connected paths, the cascading calculator selects the hop count corresponding to the path with the largest cumulative hop count as the effective traversal hop count for the current node. The purpose of selecting the maximum hop count is to ensure that the hierarchical feature value reflects the most stringent cascading depth and avoids false tripping caused by insufficient protection settings in multi-path scenarios.

[0089] The cascade calculator performs a weighted fusion calculation on the node hop count and the number of downstream branches associated with the current pole-mounted circuit breaker node in the dynamic logic topology matrix. The result is used as the hierarchical feature value of the current pole-mounted circuit breaker in the topology. The number of downstream branches refers to the number of available links originating from the current node without passing through the power supply side. The weighted fusion calculation uses a linear weighting method, multiplying the node hop count and the number of downstream branches by their respective weight coefficients and then summing them.

[0090] Specifically, after receiving the updated dynamic logic topology matrix, the cascade calculator initiates the protection cascade depth calculation process. First, the cascade calculator reads the identifier of the power-side root node from non-volatile memory. Then, the cascading calculator initializes a visit flag array `visited`, with a size of `n`, where `n` is the total number of nodes. Each element of the array is initialized to a boolean value of `false`, indicating that the corresponding node has not yet been visited. The cascading calculator also initializes a maximum hop count variable. The initial value is 0.

[0091] The cascade calculator calls a depth-first search function, with the current node identifier as the input parameter. Current hop count and access marker array The execution process of the depth-first search function is as follows:

[0092] Mark the access status of the currently processed power grid node. Setting it to the boolean value true indicates that the current node has been visited.

[0093] like Equal to the identifier of the current pole-mounted circuit breaker node ,Compare and ,like Greater than Then update for .

[0094] Traversing the dynamic logic topology matrix For the corresponding row, find all elements that satisfy the dynamic logical topology matrix. And the access status flags of the current node's neighboring candidate nodes. Adjacent nodes that are false .

[0095] For each adjacent node that meets the condition The depth-first search function is called recursively, with the following input parameters: hop count from the power source root node to the next adjacent node and .

[0096] After the recursion returns, Set as This is so that other paths can access the node.

[0097] After the depth-first search function completes its execution, This is the effective traversal jump count of the current node.

[0098] The cascade calculator calculates the number of downstream branches associated with the current node. The calculation process for the number of downstream branches is as follows:

[0099]

[0100] in, This is the identifier of the parent node of the current node on the shortest path, that is, the identifier of the upstream node directly connected to the current node in the path from the root node on the power supply side to the current node. In the dynamic logical topology matrix, the row number is The element with column number j. This is an indicator function that takes the value 1 when the condition is true, and 0 otherwise.

[0101] The cascade calculator performs a weighted fusion calculation on the effective traversal hop count and the number of downstream branches to obtain the hierarchical feature value of the current node. : .

[0102] in, This is the hop count weighting coefficient. This is the weighting coefficient for the number of branches. and The value is preset based on the structural characteristics of the distribution network and the protection coordination requirements. In this embodiment, Set to 0.7, The value is set to 0.3. The calculation of hierarchical eigenvalues ​​under different topologies is shown in Table 2.

[0103] Table 2 Examples of hierarchical eigenvalue calculation under different topologies

[0104] Single-power radiation type S1 C3 3 2 2.7 Single-power ring network type S1 C5 4 1 3.1 Dual power interconnect type S1,S2 C7 5 3 4.4 Multi-branch radial type S1 C9 2 4 2.6

[0105] Table 2 shows examples of hierarchical eigenvalue calculations under different topologies. As can be seen from the table, the hierarchical eigenvalues ​​comprehensively consider the cascading depth of nodes and the number of downstream branches, accurately reflecting the importance of nodes in the distribution network topology. For nodes with deeper cascading depths and more downstream branches, their hierarchical eigenvalues ​​are larger, and the corresponding protection action delays are also longer, meeting the selectivity requirements of relay protection.

[0106] This embodiment details the working process of the protection cascading depth calculation model, including depth-first search traversal, determination of the effective traversal hop count, and weighted fusion calculation. By selecting the maximum hop count as the effective traversal hop count and combining it with the number of downstream branches for weighted fusion, the calculated hierarchical feature values ​​can accurately reflect the cascading depth and importance of nodes in the distribution network topology, providing a reliable basis for the mapping of adaptive delay coefficients.

[0107] Reference Figure 4 In a preferred embodiment, the logic controller maps hierarchical feature values ​​to adaptive delay coefficients and writes them into the tripping and closing timing register. When the fault current feature exceeds the limit, the process of executing the delayed tripping control logic based on the adaptive delay coefficient includes calculating the delay time difference uniquely corresponding to the hierarchical feature value according to a preset hierarchical feature value and time ladder mapping function. The hierarchical feature value and time ladder mapping function adopts a piecewise linear function form, dividing the value range of the hierarchical feature value into multiple intervals, each interval corresponding to a fixed delay time difference. The parameters of the mapping function are preset according to the protection coordination requirements of the distribution network and stored in non-volatile memory.

[0108] In this embodiment, the logic controller adds the basic protection action delay setting to the delay time difference to obtain the adaptive delay coefficient. The basic protection action delay setting refers to the protection action delay setting of the current node under the initial topology of the distribution network. This value is set and stored in non-volatile memory before the system is put into operation. The logic controller writes the calculated adaptive delay coefficient into the comparison register in the opening and closing timing register. The opening and closing timing register includes a counting register and a comparison register. The counting register is driven by the system clock and is used to accumulate the number of timing pulses in real time. The comparison register is used to store the delay threshold.

[0109] When the fault current characteristic exceeds the limit, the logic controller starts the internal timer, that is, the counting register starts counting from zero. When the count value of the counting register reaches the adaptive delay coefficient stored in the comparison register, the logic controller outputs a trip drive level to the circuit breaker operating mechanism, causing the circuit breaker to operate and clear the fault.

[0110] Specifically, the logic controller receives the hierarchical feature values ​​output by the cascaded calculator. Then, the mapping function is called to calculate the delay time difference. The mapping function is defined as follows:

[0111]

[0112] in, These are the interval boundaries for the eigenvalues ​​at each level. Let be the slope of each interval. These are the intercepts for each interval. These parameters are set before the system is put into operation according to the protection coordination requirements of the distribution network.

[0113] For example, in this embodiment, the parameters of the mapping function are set as follows:

[0114] , ,

[0115] , ,

[0116] , ,

[0117] , ,

[0118] If the current node's hierarchical feature value Then the value lies in the interval Within, the corresponding delay time difference Second.

[0119] The logic controller reads the basic protection action delay setting stored in the non-volatile memory. Calculate the adaptive delay coefficient :

[0120]

[0121] If the basic protection action delay setting is... If the time is seconds, then the adaptive delay coefficient is:

[0122] Second.

[0123] The logic controller converts the calculated adaptive delay coefficient into a number of timing pulses and writes it to the comparison register in the opening and closing timing register. The frequency of the timing pulses is determined by the system clock; in this embodiment, the system clock frequency is 1kHz, therefore the period of each timing pulse is 1 millisecond. The number of timing pulses corresponding to the adaptive delay coefficient... for:

[0124]

[0125] For the example above, One pulse.

[0126] When a short-circuit fault occurs on the line, the fault current characteristic exceeds a preset threshold, triggering a hardware interrupt signal from the logic controller. In response to this hardware interrupt signal, the logic controller clears the counter register in the opening and closing timing register and starts counting. The counter register increments by 1 with each system clock pulse. The count value in the counter register is compared with the value stored in the comparison register. When the values ​​are equal, the comparison circuit of the logic controller outputs a matching signal. This matching signal triggers the trip drive circuit, which outputs a trip drive level to the circuit breaker operating mechanism.

[0127] The trip drive level is a high-level signal that lasts for a certain period of time; in this embodiment, the duration is 100 milliseconds. After receiving the trip drive level, the circuit breaker operating mechanism drives the moving contact of the circuit breaker to separate from the stationary contact, thus interrupting the fault current.

[0128] This embodiment details the mapping process of the adaptive delay coefficient and the execution process of the delay trip control logic. Through a preset piecewise linear mapping function, hierarchical feature values ​​are converted into corresponding delay time differences, which are then added to the basic protection action delay setting to obtain the adaptive delay coefficient. When a fault occurs, the logic controller executes delay trip control based on the adaptive delay coefficient, ensuring the selectivity and reliability of the protection action.

[0129] In a preferred embodiment, the process of adjusting the availability of the link connectivity weight value by combining the two-point information of the switch positions and the soft-plate status of the protection action in the adjacent node operation status frame includes extracting the two-point information of the switch positions of the corresponding node in the adjacent node operation status frame. The adjacent node operation status frame contains the two-point information of the switch positions and the soft-plate status of the protection action of all adjacent nodes in the distribution network. This information is periodically sent by the adjacent nodes through the smart distribution network protocol. The protocol parsing engine stores the parsed adjacent node operation status frames in the adjacent node status table, and the topology reconfigurator reads the required status information from the adjacent node status table.

[0130] In this embodiment, when the switch position double-point information is in the open state, the weight assignment path of the link corresponding to the switch position in the dynamic logic topology matrix is ​​cut off. A switch position double-point information of 00 indicates that the circuit breaker is in the open state; at this time, the link containing the circuit breaker is electrically disconnected and cannot transmit current. Therefore, the topology reconfigurator sets the weight values ​​of all links related to this node in the dynamic logic topology matrix to zero, cutting off the weight assignment path of these links in the topology matrix.

[0131] The topology reconfigurator extracts the status of the protection action soft switch. When the protection action soft switch status is in the "out" state, it sets the protection lockout flag of the corresponding node. A protection action soft switch status of 0 indicates that the protection action soft switch is in the "out" state; at this time, the protection function of the node is locked, and protection actions cannot be performed. The topology reconfigurator sets the protection lockout flag for this node in the node status table; a flag of 1 indicates that the protection function of the node is locked.

[0132] The topology reconfigurer downgrades the weights of paths passing through a node in the dynamic logical topology matrix based on the protection blocking flag. For all non-zero link weights associated with that node in the dynamic logical topology matrix, the topology reconfigurer multiplies them by a weight downgrade factor, reducing the weight values ​​of these links. The purpose of weight downgrading is to reduce the priority of paths passing through protection function blocking nodes during protection cascading depth calculation, ensuring the selectivity of protection actions.

[0133] Specifically, when performing availability correction, the topology reconfigurator first iterates through the switch position information of all nodes. For each node... The topology reconfigurator reads the two-point information of the switching positions from the state tables of adjacent nodes. .like A value of 00 indicates that node i is in a tripped state. The topology reconfigurator performs the following operations:

[0134]

[0135]

[0136] This will cut the node Links between nodes and all other nodes enable nodes to... It becomes an isolated node in the dynamic logical topology matrix.

[0137] like A value of 0 or 1 indicates a node. The circuit is in the closed state. The topology reconfigurator further reads the status of the protection action soft switch of node i. .like A value of 0 indicates a node. The protection action soft pressure plate is in the disengaged state. The topology reconfigurator will update the node status table. Protection lockout flag Set: .

[0138] Then, the topology refactorer traverses all nodes in the dynamic logical topology matrix. Related non-zero elements and Perform a weight downgrade operation:

[0139]

[0140]

[0141] in, This is the weight downgrade factor, which is set to 0.3 in this embodiment.

[0142] like A value of 1 indicates a node. The protective action soft pressure plate is in the engaged state. The topology reconfigurator will update the node status table. Protection lockout flag Reset: .

[0143] At this point, it is not necessary to work with the nodes. The relevant link weight values ​​are downgraded.

[0144] After completing the dual-point information of switch positions and the status check of protection action soft pressure plates for all nodes, the topology reconfigurer updates the dynamic logical topology matrix. The updated dynamic logical topology matrix will reflect the latest link availability status.

[0145] This embodiment details the availability correction process for link connectivity weight values, including the handling of switch position open state and protection action soft pressure plate exit state. By cutting off the weight assignment path of the electrically disconnected link and the path weight of the degraded protection function blocking node, the interference of unavailable links and protection function exit nodes on the protection cascade depth calculation is eliminated, improving the consistency between the topology matrix and the actual operating state.

[0146] In a preferred embodiment, the process of performing a depth-first search traversal of the dynamic logical topology matrix, starting from the power-side root node, includes locating the row index of the power-side root node within the dynamic logical topology matrix. The identifier of the power-side root node is configured during system initialization, and the topology refactorer maintains a mapping table between node identifiers and matrix row indices. The cascade calculator retrieves the corresponding row index from the mapping table based on the identifier of the power-side root node. .

[0147] In this embodiment, the cascade calculator searches downstream along the non-zero weight column indices, recording the node sequence and cumulative hop count of the current search path. The cascade calculator starts from the row index of the root node on the power supply side and traverses all column indices of that row. For each column index j, if the dynamic logic topology matrix... This indicates the root node and node on the power supply side. Available links exist between them. The cascading calculator will connect the nodes. Add the node sequence of the current search path and increment the cumulative hop count by 1.

[0148] Cascade calculator continues from node Starting with the row index, the search proceeds downstream along the non-zero weight column index. This process is repeated until a terminal leaf node is reached or a weight-degraded node is encountered. A terminal leaf node is a node with no downstream available links; that is, all elements in the row corresponding to this node are 0, except for elements connected to upstream nodes. A weight-degraded node is a node where the protection latch flag is set. The node.

[0149] When the retrieval reaches a terminal leaf node or encounters a node with a weight downgrade, the cascading calculator backtracks to the previous branch node and continues searching for other non-zero weight column indices. During backtracking, the cascading calculator removes the current node from the node sequence of the search path and decrements the cumulative hop count by 1. The cascading calculator continues to traverse other non-zero weight column indices of the branch nodes until all connected paths originating from the power-side root node have been traversed.

[0150] If the current pole-mounted circuit breaker node exists in multiple connected paths, the cascading calculator selects the path with the largest cumulative hop count as the effective traversal hop count for the current node to participate in subsequent weighted fusion calculations. The purpose of selecting the maximum hop count is to ensure that the hierarchical feature value reflects the most stringent cascading depth and avoid false tripping caused by insufficient protection settings in multi-path scenarios.

[0151] Specifically, the cascade calculator uses a recursive approach to implement a depth-first search traversal. The cascade calculator defines a recursive function `dfs`, whose input parameters include the current node index. Current cumulative jump count The function executes as follows: `path` represents the current path node sequence, and `visited` represents the visit flag array.

[0152] Access the array indexed by elements Setting it to true indicates that the current node has been visited.

[0153] Will Add to the end of the path.

[0154] like Equal to the index of the current pole-mounted circuit breaker node ,Compare and .like Greater than Then update for And copy the path to middle.

[0155] Initialize a flag variable The initial value is false.

[0156] Traversing the dynamic logic topology matrix For the corresponding row, for each column index j:

[0157] If in the dynamic logic topology matrix A, the row number is The element with column number j, and The value is false.

[0158] Will Set to true.

[0159] The dfs function is called recursively, with the following input parameters: , path, and visited.

[0160] like If false, it means that the current node is a terminal leaf node or a node that has experienced a weight downgrade.

[0161] Remove the last element of the path.

[0162] Will Set to false.

[0163] After the recursive function finishes executing, This is the effective traversal jump count of the current node. This is the longest path from the root node on the power supply side to the current node. Table 3 shows the selection of the effective traversal hop count in multi-path scenarios.

[0164] Table 3. Examples of effective traversal hop count selection in multipath scenarios.

[0165] 1 S1→C1→C3→C5 3 no 4 2 S1→C2→C4→C5 3 no 4 3 S1→C1→C2→C4→C5 4 yes 4 4 S1→C2→C1→C3→C5 4 yes 4

[0166] Table 3 shows an example of selecting the effective hop count in a multi-path scenario. In this example, the current node C5 has 4 connected paths originating from the root node S1 on the power supply side. Among them, the cumulative hop count of paths 3 and 4 is 4, which is the largest among all paths. Therefore, the cascade calculator selects 4 as the effective hop count for the current node.

[0167] This embodiment details the execution process of depth-first search traversal, including path retrieval, backtracking, and longest path selection. Depth-first search is implemented recursively, enabling traversal of all connected paths originating from the root node on the power supply side. The path with the highest cumulative hop count is selected as the valid path, ensuring that the hierarchical feature values ​​reflect the most stringent cascading depth and avoiding false trips caused by undersized protection settings in multi-path scenarios.

[0168] In a preferred embodiment, the process of outputting a trip drive level when the fault current characteristic exceeds the limit and the internal timer count reaches the adaptive delay coefficient in the comparison register includes real-time sampling of the instantaneous values ​​of the three-phase current and calculation of the current surge. The current transformer collects the current signal of the three-phase line, processes it through a signal conditioning circuit, and then inputs it to the analog-to-digital converter (ADC). The ADC samples the current signal at a fixed sampling frequency, converting the analog current signal into a digital instantaneous current value. The logic controller reads the digital instantaneous current value output by the ADC in real time and calculates the current surge.

[0169] In this embodiment, the fault detection state is activated when the current surge exceeds the steady-state fluctuation threshold. The steady-state fluctuation threshold refers to the maximum fluctuation value of the current during normal operation of the distribution network. This value is set according to the load characteristics of the distribution network and stored in non-volatile memory before the system is put into operation. The current surge is calculated using the differential method, which is the difference between the instantaneous current value at the current sampling moment and the instantaneous current value at the corresponding sampling moment in the previous cycle.

[0170] In fault detection mode, the logic controller calculates the RMS values ​​of the phase current and the zero-sequence current. The RMS value of the phase current is calculated using the root mean square (RMS) method, performing a RMS operation on the instantaneous current values ​​within one cycle. The RMS value of the zero-sequence current is calculated using the RMS method of the sum of the instantaneous values ​​of the three-phase currents. The logic controller then compares the RMS values ​​of the phase current and the zero-sequence current with the corresponding adaptive current setting values.

[0171] When the effective value of the phase current or the effective value of the zero-sequence current exceeds the corresponding adaptive current setting value, a hardware interrupt signal is triggered. The hardware interrupt signal is generated by the comparator circuit inside the logic controller and is directly connected to the interrupt pin of the central processing unit. In response to this hardware interrupt signal, the central processing unit starts its internal timer, that is, the count register in the opening and closing timer register starts counting from zero.

[0172] When the current count value of the internal timer matches the adaptive delay coefficient stored in the comparison register, the logic controller outputs a trip drive level to the circuit breaker operating mechanism. The trip drive level is generated by the trip drive circuit inside the logic controller and can drive the trip coil of the circuit breaker operating mechanism.

[0173] Specifically, the logic controller samples the instantaneous values ​​of the three-phase currents A, B, and C in real time at a sampling frequency of 10kHz. , and The logic controller calculates the abrupt changes in the three-phase currents A, B, and C. , and :

[0174]

[0175]

[0176]

[0177] in, , , These represent the instantaneous values ​​of the three-phase currents A, B, and C at the kNth sampling time, where N is the number of sampling points within one power frequency cycle. In this embodiment, the power frequency is 50Hz, and the sampling frequency is 10kHz. =200.

[0178] The logic controller calculates the maximum value of the three-phase current surge. :

[0179] like ,in To determine the steady-state fluctuation threshold, the logic controller activates fault detection mode. In fault detection mode, the logic controller calculates the effective values ​​of the three-phase currents A, B, and C. , and :

[0180]

[0181]

[0182]

[0183] The logic controller calculates the effective value of the zero-sequence current. : .

[0184] The logic controller compares the effective value of the phase current with the adaptive set value of the phase current. The effective value of the zero-sequence current is compared with the adaptive setting value of the zero-sequence current. Compare them. If one of the following conditions is met: or or or .

[0185] The logic controller triggers a hardware interrupt signal.

[0186] In response to a hardware interrupt signal, the CPU executes the interrupt service routine. The interrupt service routine first clears the counter register in the gate opening / closing timer register to zero, and then starts counting. The counter register increments by 1 with each system clock pulse. The system clock frequency is 1kHz, so the counting unit of the counter register is milliseconds.

[0187] When the count value of the counter register The count value corresponding to the adaptive delay coefficient stored in the comparison register When they are equal: .

[0188] The logic controller's comparator circuit outputs a matching signal. This matching signal triggers the trip drive circuit, which outputs a trip drive level to the circuit breaker operating mechanism. The trip drive level lasts for 100 milliseconds to ensure reliable operation of the circuit breaker operating mechanism.

[0189] This embodiment details the execution process of fault current characteristic quantity detection and delayed trip control. Activating the fault detection state through sudden current changes improves the speed of fault detection. Triggering a hardware interrupt by comparing the effective values ​​of the phase current and zero-sequence current with the adaptive setting ensures the accuracy of fault determination. Delay control based on a hardware timer guarantees the accuracy and real-time performance of the delayed trip.

[0190] Reference Figure 5 In a preferred embodiment, the protocol link monitor counts the number of consecutive frame drops and cyclic redundancy check (CRC) errors in smart distribution network (SDP) messages. The protocol link monitor is electrically connected to the SDP communication interface and monitors the SDP messages received by the communication interface in real time. The protocol link monitor maintains a message reception counter and an error counter, used to count the total number of received messages and the number of erroneous messages, respectively.

[0191] In this embodiment, when the number of consecutive lost frames exceeds the frame count threshold or the number of cyclic redundancy check (CRC) errors exceeds the error count threshold, the protocol link monitor determines that the communication link is interrupted and generates a protocol failure flag. The number of consecutive lost frames refers to the number of consecutive missed expected messages. The frame count threshold is preset according to the reliability requirements of the communication link; in this embodiment, it is set to 5. The number of CRC errors refers to the number of CRC-erroneous messages received within a certain time period. The error count threshold is preset according to the bit error rate requirements of the communication link; in this embodiment, it is set to 10.

[0192] The protocol link monitor sends a protocol failure flag to the logic controller. In response to the protocol failure flag, the logic controller blocks the channel for writing the adaptive delay coefficient to the circuit breaker timing register. Blocking the write channel prevents incorrect adaptive delay coefficients from being written to the circuit breaker timing register during communication interruptions, which could lead to protection logic malfunction.

[0193] The logic controller reads the pre-stored backup delay setting in non-volatile memory and overwrites the contents of the current opening / closing timing register. The pre-stored backup delay setting refers to the protection action delay setting of the current node under the initial topology of the distribution network. This value is set and stored in non-volatile memory before the system is put into operation. The logic controller converts the pre-stored backup delay setting into a number of timing pulses and writes it into the comparison register in the opening / closing timing register.

[0194] The logic controller controls the circuit breaker to enter a degraded operation mode based on locally fixed settings. In degraded operation mode, the protection action delay of the pole-mounted circuit breaker adopts the fixed backup delay setting and no longer adaptively adjusts according to changes in the distribution network topology. When the communication link returns to normal, the protocol link monitor clears the protocol failure flag, the logic controller releases the block on the adaptive delay coefficient writing channel, and the system returns to normal operation mode.

[0195] Specifically, the protocol link monitor monitors the message reception status of the smart distribution network communication interface in real time. For each expected message, if it is not received within the timeout period, the protocol link monitor increments the consecutive frame loss count by 1. If the message is received, the protocol link monitor resets the consecutive frame loss count to zero. When the consecutive frame loss count exceeds the frame count threshold... hour:

[0196]

[0197] The protocol link monitor determines that the communication link is interrupted. The number of consecutive frame drops.

[0198] Meanwhile, the protocol link monitor performs cyclic redundancy check (CRUD) on each received packet. If the check fails, the protocol link monitor increments the CRUD error count by 1. The protocol link monitor uses a sliding time window to count CRUD errors, with the sliding time window having a length of 1 minute. When the number of CRUD errors within the sliding time window exceeds the error count threshold... Time: Total number of cyclic redundancy check errors within the sliding time window .

[0199] The protocol link monitor determines that the communication link is interrupted.

[0200] When the protocol link monitor determines that the communication link is interrupted, it generates a protocol failure flag. And set bit: .

[0201] The logic controller monitors the status of the protocol failure flag in real time. When a failure flag is detected... When this happens, the logic controller performs the following operations:

[0202] Block the channel for writing the adaptive delay coefficient to the opening and closing timing register. The logic controller sets a write enable flag. Clear it to zero: .

[0203] when At this time, any write operation to the opening and closing timer register will be ignored.

[0204] Read the hardened backup delay setting from non-volatile memory. .

[0205] Convert the solidified backup delay setting into a number of timing pulses. .

[0206] Will Write the comparison register into the opening and closing timing register.

[0207] Set the system operating mode flag to degraded operating mode: System operating mode flag .

[0208] Where 0 represents normal operation mode and 1 represents degraded operation mode.

[0209] In degraded operation mode, the logic controller continues to execute fault detection and delayed trip control logic, but uses a fixed backup delay setting as the delay threshold. Once the communication link returns to normal, the protocol link monitor resets the number of consecutive lost frames and cyclic redundancy check errors to zero, and clears the protocol failure flag.

[0210] The logic controller detected When this happens, perform the following operations:

[0211] Unblock the adaptive delay coefficient write channel and set the write enable flag: .

[0212] Trigger the cascade calculator to recalculate the hierarchical feature values ​​of the current node.

[0213] The adaptive delay coefficient is calculated based on the new hierarchical feature value and written into the comparison register in the opening and closing timing register.

[0214] Set the system operating mode flag to normal operating mode: .

[0215] This embodiment details the implementation process of protocol link monitoring and degraded operation mode. By counting the number of consecutive frame drops and cyclic redundancy check (CRC) errors, the protocol link monitor can promptly detect communication link interruptions. During a communication interruption, the system automatically switches to a degraded operation mode based on locally fixed settings to ensure the reliability of the protection function. When communication is restored, the system automatically returns to normal operation mode and continues to provide adaptive delay protection.

[0216] Reference Figure 6 In a preferred embodiment, the adaptive setpoint adjuster acquires the hierarchical characteristic value of the current pole-mounted circuit breaker in the topology, output by the cascade calculator, and the load aggregation capacity downstream of the current pole-mounted circuit breaker in the dynamic logic topology matrix. The input of the adaptive setpoint adjuster is electrically connected to the outputs of the cascade calculator and the topology reconfigurator, and receives the hierarchical characteristic value and the dynamic logic topology matrix, respectively.

[0217] In this embodiment, the adaptive setpoint adjuster determines the protection sensitivity coefficient of the current node based on the hierarchical characteristic value. The protection sensitivity coefficient is used to adjust the current setting value for protection operation. A larger hierarchical characteristic value indicates a deeper cascading depth of the node in the topology, resulting in a smaller protection sensitivity coefficient to avoid maloperation. The mapping relationship between the protection sensitivity coefficient and the hierarchical characteristic value is a linear function.

[0218] The adaptive setpoint regulator calculates the expected maximum load current based on the load aggregation capacity. The load aggregation capacity refers to the total capacity of all loads downstream of the current node; this value is periodically sent by the distribution master station via the smart distribution network protocol, or calculated by the current node based on the operating status of each downstream load node. The expected maximum load current is calculated based on the load aggregation capacity and the system rated voltage.

[0219] The adaptive current regulator uses the product of the protection sensitivity coefficient and the expected maximum load current as the adaptive current setting value. The adaptive current setting value includes both phase current adaptive setting value and zero-sequence current adaptive setting value. The adaptive current regulator then sends the adaptive current setting value to the fault current characteristic over-limit judgment comparator, replacing the initial default current setting value in the fault judgment logic.

[0220] Specifically, the adaptive tuner receives the hierarchical feature values ​​output by the cascaded calculator. Then, calculate the protection sensitivity coefficient. :

[0221]

[0222] in, Basic sensitivity coefficient, This is the sensitivity adjustment coefficient. and The value is preset according to the protection requirements of the distribution network. In this embodiment... Set to 1.5. Set it to 0.1.

[0223] For example, if the hierarchical feature value of the current node Then the protection sensitivity coefficient is:

[0224]

[0225] The adaptive setpoint adjuster obtains the identifiers of all load nodes downstream of the current node from the dynamic logical topology matrix. For each load node, the adaptive setpoint adjuster reads its current load capacity from the load status table. The load status table is maintained by the protocol parsing engine and stores the operating status information of each load node sent by the power distribution master station.

[0226] The adaptive setpoint adjuster calculates the load aggregation capacity downstream of the current node. :

[0227]

[0228] Where m is the total number of load nodes downstream of the current node.

[0229] The adaptive setpoint regulator calculates the expected maximum load current based on the aggregated load capacity. :

[0230]

[0231] in, The system's rated voltage. This is the load power factor. In this embodiment... Set to 10kV, Set it to 0.85.

[0232] For example, if the load aggregation capacity downstream of the current node If the current is kVA, then the expected maximum load current is:

[0233]

[0234] The adaptive regulator calculates the adaptive setting value of the phase current. :

[0235]

[0236] For the example above, the phase current adaptive setting value is:

[0237]

[0238] The adaptive regulator calculates the zero-sequence current adaptive setting value. The zero-sequence current adaptive setting value is usually a certain proportion of the phase current adaptive setting value.

[0239]

[0240] in, The zero-sequence current proportionality coefficient is set to 0.2 in this embodiment.

[0241] For the example above, the zero-sequence current adaptive setting value is:

[0242]

[0243] The calculation of adaptive current setting values ​​under different operating conditions is shown in Table 4.

[0244] Table 4 Examples of Adaptive Current Setting Values ​​under Different Operating Conditions

[0245] 1.5 1.35 2000 135.9 183.5 36.7 2.7 1.23 5000 339.7 417.8 83.6 3.2 1.18 8000 543.5 641.3 128.3 4.1 1.09 12000 815.3 888.7 177.7

[0246] Table 4 shows examples of adaptive current setting values ​​calculated under different operating conditions. As can be seen from the table, the adaptive current setting value decreases with increasing hierarchical characteristic values ​​and increases with increasing load aggregation capacity. This adjustment mechanism allows the fault identification threshold to dynamically change with the topology cascade location and load level, enhancing the accuracy of fault identification under different operating conditions.

[0247] The adaptive setpoint regulator sends the calculated adaptive setpoints for phase current and zero-sequence current to the fault current characteristic over-limit judgment comparator. The fault current characteristic over-limit judgment comparator replaces the initial default setpoint with the new setpoint and participates in the subsequent fault judgment logic.

[0248] This embodiment details the implementation process of adaptive current setting adjustment. By determining the protection sensitivity coefficient based on hierarchical characteristic values ​​and calculating the expected maximum load current in conjunction with the downstream load aggregation capacity, an adaptive current setting value is generated. This adjustment mechanism enables the fault discrimination threshold to dynamically change with the distribution network topology and load level, improving the accuracy of fault identification and the reliability of protection actions.

Claims

1. A logic control system for pole-mounted circuit breakers based on intelligent distribution network protocols, characterized in that, The protocol parsing engine extracts topology change identifiers and adjacent node operating status frames from smart distribution network messages; The topology reconfigurator constructs a dynamic logical topology matrix based on the topology change identifier and the running status frames of the adjacent nodes; The cascade calculator inputs the dynamic logic topology matrix into the protection cascade depth calculation model to obtain the hierarchical feature value of the current pole-mounted circuit breaker in the topology. The logic controller maps the hierarchical feature values ​​to adaptive delay coefficients and writes them into the opening and closing timing register. When the fault current feature value exceeds the limit, the delayed trip control logic is executed according to the adaptive delay coefficient.

2. The pole-mounted circuit breaker logic control system based on intelligent distribution network protocol according to claim 1, characterized in that, The process by which the protocol parsing engine extracts the topology change identifier and the adjacent node running status frame from the smart distribution network message includes: decrypting the received smart distribution network message and verifying the frame header, and stripping the message transmission encapsulation layer to obtain the application layer payload. Identify the service primitive type identifier in the application layer payload. When the service primitive type identifier is a topology announcement type, extract the node identifier list and link state vector in the application layer payload as the topology change identifier. When the service primitive type identifier is a status quantity upload type, the switch position dual-point information and the protection action soft pressure plate status in the application layer load are extracted as the running status frame of the adjacent node.

3. The pole-mounted circuit breaker logic control system based on intelligent distribution network protocol according to claim 1, characterized in that, The process by which the topology reconfigurator constructs a dynamic logical topology matrix based on the topology change identifier and the adjacent node running status frame includes: initializing an all-zero matrix using each pole-mounted circuit breaker node in the distribution network as the matrix row index and column index; Traverse the node identifier list and link state vector in the topology change identifier, and write the link connectivity weight value in the corresponding row and column position of the all-zero matrix; Combining the switch position information and the protection action soft pressure plate status in the adjacent node operation status frame, the availability correction is performed on the link connectivity weight value, the weight value corresponding to the unavailable link is set to zero, and a dynamic logical topology matrix representing the dual attributes of physical connectivity and electrical availability of the current distribution network is generated.

4. The pole-mounted circuit breaker logic control system based on intelligent distribution network protocol according to claim 1, characterized in that, The process by which the cascade calculator inputs the dynamic logic topology matrix into the protection cascade depth calculation model and obtains the hierarchical feature value of the current pole-mounted circuit breaker in the topology includes: taking the power supply side root node as the search starting point, performing a depth-first search traversal on the dynamic logic topology matrix, and recording the number of hops of nodes with non-zero available link weights traversed from the power supply side root node to the current pole-mounted circuit breaker node; The node hop count is weighted and fused with the number of downstream branches associated with the current pole-mounted circuit breaker node in the dynamic logic topology matrix, and the result is used as the hierarchical feature value of the current pole-mounted circuit breaker in the topology.

5. The pole-mounted circuit breaker logic control system based on intelligent distribution network protocol according to claim 1, characterized in that, The logic controller maps the hierarchical feature value to an adaptive delay coefficient and writes it into the opening and closing timing register. When the fault current feature value exceeds the limit, the process of executing the delayed trip control logic according to the adaptive delay coefficient includes: calculating the delay time difference that uniquely corresponds to the hierarchical feature value according to the preset hierarchical feature value and time ladder mapping function. The adaptive delay coefficient is obtained by adding the basic protection action delay setting value to the delay time difference value, and the adaptive delay coefficient is written into the comparison register in the opening and closing timing register; When the fault current characteristic exceeds the limit and the internal timer count reaches the adaptive delay coefficient in the comparison register, the trip drive level is output.

6. The pole-mounted circuit breaker logic control system based on intelligent distribution network protocol according to claim 3, characterized in that, The process of modifying the availability of the link connectivity weight value by combining the switch position dual-point information and the protection action soft pressure plate status in the adjacent node operation status frame includes: extracting the switch position dual-point information of the corresponding node in the adjacent node operation status frame; when the switch position dual-point information is in the open state, cutting off the weight assignment path of the link corresponding to the switch position in the dynamic logic topology matrix. Extract the status of the protection action soft pressure plate. When the status of the protection action soft pressure plate is in the exit state, set the protection blocking flag of the corresponding node of the soft pressure plate. Based on the protection blocking flag, downgrade the path weight of the node in the dynamic logic topology matrix to complete the availability correction of the link connectivity weight value.

7. The pole-mounted circuit breaker logic control system based on intelligent distribution network protocol according to claim 4, characterized in that, The process of performing a depth-first search traversal of the dynamic logical topology matrix with the power supply side root node as the search starting point includes: locating the row index of the power supply side root node in the dynamic logical topology matrix, searching downstream along the non-zero weight column index, and recording the node sequence and cumulative hop count of the current search path. When the retrieval reaches the final leaf node or encounters a weight downgrade node, backtrack to the previous branch node and continue to search for other non-zero weight columns until all connected paths originating from the power supply root node have been traversed. If the current pole-mounted circuit breaker node exists in multiple connected paths, the hop count corresponding to the path with the largest cumulative hop count is selected as the effective traversal hop count of the current node and used in subsequent weighted fusion calculations.

8. The pole-mounted circuit breaker logic control system based on intelligent distribution network protocol according to claim 5, characterized in that, The process of outputting a trip drive level when the fault current characteristic exceeds the limit and the internal timer count reaches the adaptive delay coefficient in the comparison register includes: real-time sampling of the instantaneous value of the three-phase current and calculation of the current mutation amount; when the current mutation amount exceeds the steady-state fluctuation threshold, the fault detection state is activated. In the fault detection state, the effective value of the phase current and the effective value of the zero-sequence current are calculated. When the effective value of the phase current or the effective value of the zero-sequence current exceeds the corresponding adaptive current setting value, a hardware interrupt signal is triggered. In response to the hardware interrupt signal, the internal timer is started. When the current count value of the internal timer matches the adaptive delay coefficient stored in the comparison register, the trip drive level is output to the circuit breaker operating mechanism.

9. The pole-mounted circuit breaker logic control system based on intelligent distribution network protocol according to claim 1, characterized in that, The protocol link monitor counts the number of consecutive frame drops and cyclic redundancy check errors in smart distribution network packets; When the number of consecutive lost frames exceeds the frame count threshold or the number of cyclic redundancy check errors exceeds the error count threshold, the communication link is determined to be interrupted and a protocol failure flag is generated. The protocol failure flag is sent to the logic controller. In response to the protocol failure flag, the logic controller blocks the channel for writing the adaptive delay coefficient into the opening and closing timing register, and reads the solidified backup delay setting value pre-stored in the non-volatile memory to overwrite the contents of the current opening and closing timing register, and controls the circuit breaker to enter the degraded operation mode based on the local solidified setting value.

10. The pole-mounted circuit breaker logic control system based on intelligent distribution network protocol according to claim 1, characterized in that, The adaptive setpoint adjuster obtains the hierarchical characteristic value of the current pole-mounted circuit breaker in the topology output by the cascade calculator and the load aggregation capacity downstream of the current pole-mounted circuit breaker in the dynamic logic topology matrix; The protection sensitivity coefficient of the current node is determined based on the hierarchical feature values, and the expected maximum load current is calculated based on the load aggregation capacity. The product of the protection sensitivity coefficient and the expected maximum load current is used as the adaptive current setting value. The adaptive current setting value is sent to the fault current characteristic quantity over-limit judgment comparator to replace the initial default current setting value in the fault judgment logic.

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