A method for harmonic optimization of five-level ANPC converter under capacitor voltage unbalance

Abstract

The application discloses a harmonic optimization method of a five-level ANPC converter under capacitor voltage imbalance. Firstly, according to a current modulation wave signal and a capacitor voltage value, a selected key redundant switch state in a current switch period is determined. Secondly, according to a geometric relation of a carrier layering PWM and a similar triangle principle, an action time of the key redundant state under ideal capacitor voltage and an action time of the key redundant state under actual capacitor voltage are calculated. Then, according to a volt-second balance principle, an output voltage integral area under the actual capacitor voltage is equal to an integral area under an ideal condition, and an optimized modulation wave amplitude capable of compensating capacitor voltage fluctuation is calculated. Finally, the optimized modulation wave signal is compared with a carrier to generate a switch signal for driving the five-level ANPC converter. The application has the advantages of simple implementation, remarkable current harmonic suppression effect under capacitor voltage imbalance and basically fixed switch frequency.

Description

Technical Field

[0001] This invention relates to a harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance, belonging to the field of multilevel converter control technology. Background Technology

[0002] In recent years, my country's demand for power conversion has been rapidly developing towards higher voltage and higher power. To meet this demand, multilevel converters have been widely used in medium- and high-voltage, high-power power conversion fields due to their advantages such as low output voltage harmonics, low electromagnetic interference, and fast dynamic response. Among them, the five-level active neutral-point clamp converter, as a typical topology, shows significant advantages in terms of the number of output levels, device voltage stress, and control flexibility by introducing active switching devices to replace the clamping diodes in the traditional NPC topology.

[0003] Traditional research on capacitor control and harmonic optimization focuses on improving capacitor voltage balancing capabilities, neglecting converter control issues under conditions of significant capacitor voltage fluctuations. However, when the system operates under extreme conditions or experiences severe disturbances, such as reduced operating frequency or capacitor capacity decay, capacitor voltage fluctuations in five-level active neutral-point clamped converters are difficult to limit to a low range, failing to effectively achieve capacitor voltage balance and thus affecting the power quality of the output waveform. Therefore, a PWM optimization control method suitable for capacitor voltage imbalance needs to be developed to reduce current harmonic distortion in such situations. Summary of the Invention

[0004] The problem this invention aims to solve is that, under traditional 5L-ANPC capacitor control and harmonic optimization, the total harmonic distortion rate of the output current increases when the capacitor voltage deviates or fluctuates significantly. This invention proposes a harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance, comprising the following steps:

[0006] S1) Sample and obtain the voltage values ​​of the DC-side bus capacitor and floating capacitor of the converter;

[0007] S2) Based on the sampled capacitor voltage value in S1) and the current modulation wave signal, determine the key redundant switch state selected in the current switching cycle;

[0008] S3) Based on the geometric relationship of the carrier-layered PWM and the principle of similar triangles, calculate the duration t of the selected critical redundant state in S2) under the ideal capacitor voltage. x ;

[0009] S4) Based on the actual capacitor voltage that generates the offset, correct the duration t' of the critical redundant state selected in S2) under actual conditions. x ;

[0010] S5) Based on the duration of the critical redundant states selected in S3) and S4) and their corresponding output levels, calculate the volt-second integral area S1 under ideal conditions and the volt-second integral area S2 under actual conditions.

[0011] S6) Based on the volt-second balance principle, determine the equation for the modulation wave correction: S1 = S2;

[0012] S7) Based on the modulation wave correction equation S1 = S2 in S6), the optimized modulation wave amplitude v' that can compensate for capacitor voltage fluctuations is calculated. x Thus, the original modulated wave v x The signal amplitude is adjusted in real time;

[0013] S8) Compare the optimized modulation wave signal from S7) with the carrier wave to generate a switching signal that drives the five-level ANPC converter.

[0014] In a five-level ANPC converter bridge arm topology, the DC input voltage V dc The upper DC capacitor voltage V is divided into equal voltages. p and the voltage V of the lower DC capacitor n Each phase arm has a floating capacitor C. fx Where x represents phases a, b, and c, and the voltage of the floating capacitor is stable at V. dc Around 4. Assuming the bus capacitor voltage is 4E, then the floating capacitor voltage V fx The amplitude should be stable at E, where x represents the three phases a, b, and c, and the amplitude of the DC bus capacitor voltage on the upper and lower sides should be stable at 2E.

[0015] In step S2), the five-level ANPC output levels are 2E, E, 0, -E, and -2E. Each phase arm has eight switching states, named V0-V7. V7 corresponds to an output level of 2E, V5 and V6 both correspond to an output level of E, V3 and V4 both correspond to an output level of 0, V1 and V2 both correspond to an output level of -E, and V0 corresponds to an output level of -2E. Therefore, V1 and V2, V3 and V4, and V5 and V6 are redundant switching states corresponding to output levels -E, 0, and E, respectively. Taking phase a as an example, determining the key redundant switching state selected in the current switching cycle includes three steps:

[0016] Step S2-1) Calculate the voltage V of the floating capacitor in phase a. fa Its rated value V dc / 4 absolute value of deviation V dc The input voltage is a DC voltage, and the absolute value of this deviation is compared with a preset voltage tolerance threshold Δu. f Compare them. If the absolute value of the expression is greater than Δu... f If the voltage is unbalanced, the floating capacitor voltage is determined to be unbalanced, and the floating capacitor voltage control process is entered (step S2-2); otherwise, the bus capacitor voltage control process is entered (step S2-3).

[0017] Step S2-2) Calculate the expression for the direction of voltage regulation. , where i a This represents the instantaneous value of the output current of phase a. If the value of this formula is greater than 0, then switch state combination V2 or V6 is selected; if the value of this formula is less than or equal to 0, then switch state combination V1 or V5 is selected.

[0018] Step S2-3) Calculate the expression for the direction of voltage regulation. V n The value of the equation is the DC capacitor voltage on the lower side. If the value of this equation is greater than 0, then switch state combination V2 or V5 is selected; if the value of this equation is less than or equal to 0, then switch state combination V1 or V6 is selected.

[0019] In step S3), the piecewise expression for the duration of the selected critical redundant switch state under the ideal capacitor voltage is as follows:

[0020] , among which, T s The PWM carrier period is the switching period, v x This is the original modulation amplitude value.

[0021] In step S4), the optimized modulation wave v' x Substituting the expression for the duration of the selected critical redundant state under the ideal capacitor voltage, the piecewise expression for the duration of the critical redundant switch state under the actual capacitor voltage is as follows:

[0022] , where v' x This is the optimized modulation amplitude value.

[0023] In step S5), when E ≤ v x When < 2E, taking the critical redundant switch state V5 as an example, the ideal output voltage value for this cycle is 2E – E – 2E, and the actual output voltage value is V. p – V f – V p Then, in the ideal case, the area S1 of the volt-second integral is: In practice, the volt-second integral area S2 is: .

[0024] The principle of volt-second balance in step S6) requires that: in any PWM switching cycle T s Within this timeframe, the integral of the actual output pulse voltage sequence of the converter over time should be equal to the volt-second product of the desired ideal output voltage sequence, i.e., ... .

[0025] In step S7), when E ≤ v x When the voltage is less than 2E, taking the critical redundant switch state V5 as an example, by combining the expressions for the duration of the selected critical redundant state in S3) and S4), and the equation for the modulation wave correction in S6), the optimized modulation wave amplitude that can compensate for capacitor voltage fluctuations can be calculated. In other cases, v' x Similarly, the derivation process can yield a set of optimized modulation waves v' x The unified calculation formula.

[0026] This invention has the following features and advantages:

[0027] (1) Based on the volt-second balance principle, the optimized modulation wave required to offset the capacitor voltage deviation under large capacitor voltage fluctuation is calculated in real time and accurately, and the suppression effect on current harmonics is significant.

[0028] (2) This method directly acts on the modulated wave, does not depend on the load model or complex system parameters, and only requires sampling the capacitor voltage. It is simple to implement and has a small amount of computation.

[0029] (3) The switching frequency is basically fixed, and there are no instantaneous high switching frequencies, so the system has high reliability;

[0030] (4) The renovation cost is small and the practicality is high. Attached Figure Description

[0031] Figure 1 This is a schematic diagram illustrating the principle of the present invention;

[0032] Figure 2 This is a diagram of a five-level ANPC topology.

[0033] Figure 3 Flowchart for selecting capacitor voltage control for critical redundant switch states;

[0034] Figure 4 The modulated wave and carrier wave are plotted as an integral area diagram.

[0035] Figure 5 To select the optimized modulation wave v' under different critical redundancy switching states x A unified calculation formula table;

[0036] Figure 6The current waveform and its THD modulated using traditional methods under capacitance attenuation conditions;

[0037] Figure 7 The current waveform modulated by the method of the present invention and its THD under capacitance attenuation conditions;

[0038] Figure 8 The current waveform and its THD modulated using conventional methods under frequency reduction conditions;

[0039] Figure 9 The current waveform modulated using the method of this invention under frequency reduction conditions and its THD are shown. Detailed Implementation

[0040] To better understand the technical advantages of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The specific embodiments described are only used to explain the present invention and are not limited to the present invention.

[0041] This invention relates to a harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance. For its core control flow, please refer to [link / reference needed]. Figure 1 This includes the following steps:

[0042] S1) Sample and obtain the voltage values ​​of the DC-side bus capacitor and floating capacitor of the converter;

[0043] S2) Based on the sampled capacitor voltage value and the current modulation wave signal in S1), determine the key redundant switch state selected in the current switching cycle. In step S2), the five-level ANPC output levels are 2E, E, 0, -E, and -2E. Each phase arm has 8 switching states, named V0-V7 respectively. V7 corresponds to an output level of 2E, V5 and V6 both correspond to an output level of E, V3 and V4 both correspond to an output level of 0, V1 and V2 both correspond to an output level of -E, and V0 corresponds to an output level of -2E. Therefore, V1 and V2, V3 and V4, and V5 and V6 are redundant switch states corresponding to output levels of -E, 0, and E, respectively. Taking phase a as an example, the flowchart for determining the key redundant switch state selected in the current switching cycle is as follows: Figure 3 As shown, it includes three steps:

[0044] Step S2-1) Calculate the voltage V of the floating capacitor in phase a. fa Its rated value V dc / 4 absolute value of deviation V dc The input voltage is a DC voltage, and the absolute value of this deviation is compared with a preset voltage tolerance threshold Δu. f Compare them. If the absolute value of the expression is greater than Δu... fIf the voltage is unbalanced, the floating capacitor voltage is determined to be unbalanced, and the floating capacitor voltage control process is entered (step S2-2); otherwise, the bus capacitor voltage control process is entered (step S2-3).

[0045] Step S2-2) Calculate the expression for the direction of voltage regulation. , where i a This represents the instantaneous value of the output current of phase a. If the value of this formula is greater than 0, then switch state combination V2 or V6 is selected; if the value of this formula is less than or equal to 0, then switch state combination V1 or V5 is selected.

[0046] Step S2-3) Calculate the expression for the direction of voltage regulation. V n This represents the voltage of the DC capacitor on the lower side. If the value of this formula is greater than 0, then select switch state combination V2 or V5; if the value of this formula is less than or equal to 0, then select switch state combination V1 or V6.

[0047] S3) Based on the geometric relationship of the carrier-layered PWM and the principle of similar triangles, calculate the duration t of the selected critical redundant state in S2) under the ideal capacitor voltage. x In step S3), the duration t of the selected critical redundant switch state under the ideal capacitor voltage is... x The piecewise expression is:

[0048] T s The PWM carrier period is the switching period, v x This is the original modulation amplitude value;

[0049] S4) Based on the actual capacitor voltage that generates the offset, correct the duration t' of the critical redundant state selected in S2) under actual conditions. x In step S4), the optimized modulation wave v' x Substituting the expression for the duration of the selected critical redundant state under the ideal capacitor voltage, the piecewise expression for the duration of the selected critical redundant switch state under the actual capacitor voltage is as follows:

[0050] , where v' x The optimized modulation amplitude value;

[0051] S5) Based on the duration of the critical redundancy states selected in S3) and S4) and their corresponding output levels, calculate the volt-second integral area S1 under ideal conditions and the volt-second integral area S2 under actual conditions, respectively; in step S5), when E ≤ v x When the value is less than 2E, taking the critical redundant switch state V5 as an example, such as... Figure 4As shown, the ideal output voltage value for this cycle is 2E – E – 2E, and the actual output voltage value is V. p – V f – V p The ideal volt-second integral area S1 is calculated to be: In practice, the volt-second integral area S2 is: ;

[0052] S6) Based on the volt-second balance principle, determine the equation S1 = S2 for the modulation wave correction; in step S6), the volt-second balance principle requires that: in any PWM switching cycle T s Within this timeframe, the integral of the actual output pulse voltage sequence of the converter over time should be equal to the volt-second product of the desired ideal output voltage sequence, i.e. ;

[0053] S7) Based on the modulation wave correction equation S1 = S2 in S6), the optimized modulation wave amplitude v' that can compensate for capacitor voltage fluctuations is calculated. x Thus, the original modulated wave v x The signal undergoes real-time amplitude adjustment; in step S7), when E ≤ v x When the voltage is less than 2E, taking the critical redundant switch state V5 as an example, by combining the expressions for the duration of the selected critical redundant state in S3) and S4), and the equation for the modulation wave correction in S6), the optimized modulation wave amplitude that can compensate for capacitor voltage fluctuations can be calculated. In other cases, v' x Similarly, the derivation process can yield a set of optimized modulation waves v' x The unified calculation formula, such as Figure 5 As shown;

[0054] S8) Compare the optimized modulation wave signal from S7) with the carrier wave to generate a switching signal that drives the five-level ANPC converter.

[0055] This invention takes a five-level ANPC as an example, and its topology is as follows: Figure 2 As shown, the DC side consists of two energy storage capacitors C up and C down Composition, DC input voltage V dc The upper DC capacitor voltage V is divided into equal voltages. p and the voltage V of the lower DC capacitor n Each phase arm has 12 switching power transistors and one floating capacitor C. fx Where x represents phases a, b, and c, and the voltage of the floating capacitor is stable at V. dcNear / 4, R and L are the load resistance and inductance, respectively. This invention simulates the voltage fluctuation of a large capacitor caused by both capacitance decay and frequency reduction. Multi-dimensional simulation verification is performed using both traditional control methods and the control method of this invention.

[0056] from Figure 6 and Figure 7 The comparison shows that the lower capacitance value limits its ability to store charge, resulting in higher voltage fluctuations and more severe distortion of the output voltage, which in turn affects the sinusoidal characteristics of the output current. In this case, the THD value of the output current is 4.77% under the conventional method, while the THD value of the output current is 2.97% under the method of this invention, effectively reducing the harmonic content by 37.7%.

[0057] from Figure 8 and Figure 9 The comparison shows that the reduction in sampling frequency leads to a longer carrier period, which reduces the tracking accuracy of the control algorithm on the reference voltage. This not only limits the control capability of the capacitor but also affects the sinusoidal characteristics of the output waveform. In this case, the THD value of the output current is 6.44% under the traditional method, while the THD value of the output current is 4.34% under the method of this invention, effectively reducing the harmonic content by 32.6%.

[0058] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance, comprising the following steps: S1) Sample and obtain the voltage values ​​of the DC-side bus capacitor and floating capacitor of the converter; S2) Based on the sampled capacitor voltage value in S1) and the current modulation wave signal, determine the key redundant switch state selected in the current switching cycle; S3) Based on the geometric relationship of the carrier-layered PWM and the principle of similar triangles, calculate the duration t of the selected critical redundant state in S2) under the ideal capacitor voltage. x ; S4) Based on the actual capacitor voltage that generates the offset, correct the duration t' of the critical redundant state selected in S2) under actual conditions. x ; S5) Based on the duration of the critical redundant states selected in S3) and S4) and their corresponding output levels, calculate the volt-second integral area S1 under ideal conditions and the volt-second integral area S2 under actual conditions. S6) Based on the volt-second balance principle, determine the equation for the modulation wave correction: S1 = S2; S7) Based on the modulation wave correction equation S1 = S2 in S6), the optimized modulation wave amplitude v' that can compensate for capacitor voltage fluctuations is calculated. x Thus, the original modulated wave v x The signal amplitude is adjusted in real time; S8) Compare the optimized modulation wave signal from S7) with the carrier wave to generate a switching signal that drives the five-level ANPC converter.

2. The harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance according to claim 1, characterized in that: In step S2), the five-level ANPC output levels are 2E, E, 0, -E, and -2E. Each phase arm has eight switching states, named V0-V7. V7 corresponds to an output level of 2E, V5 and V6 both correspond to an output level of E, V3 and V4 both correspond to an output level of 0, V1 and V2 both correspond to an output level of -E, and V0 corresponds to an output level of -2E. Therefore, V1 and V2, V3 and V4, and V5 and V6 are redundant switching states corresponding to output levels -E, 0, and E, respectively. Taking phase a as an example, determining the key redundant switching state selected in the current switching cycle includes three steps: Step S2-1) Calculate the voltage V of the floating capacitor in phase a. fa Its rated value V dc / 4 absolute value of deviation V dc The input voltage is a DC voltage, and the absolute value of this deviation is compared with a preset voltage tolerance threshold Δu. f Compare them. If the absolute value of the expression is greater than Δu... f If the voltage is unbalanced, the floating capacitor voltage is determined to be unbalanced, and the floating capacitor voltage control process is entered (step S2-2); otherwise, the bus capacitor voltage control process is entered (step S2-3). Step S2-2) Calculate the expression for the direction of voltage regulation. , where i a This represents the instantaneous value of the output current of phase a. If the value of this formula is greater than 0, then switch state combination V2 or V6 is selected; if the value of this formula is less than or equal to 0, then switch state combination V1 or V5 is selected. Step S2-3) Calculate the expression for the direction of voltage regulation. V n This represents the voltage of the DC capacitor on the lower side. If the value of this formula is greater than 0, then switch state combination V2 or V5 is selected; if the value of this formula is less than or equal to 0, then switch state combination V1 or V6 is selected.

3. The harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance according to claim 1, characterized in that: In step S3), the piecewise expression for the duration of the selected critical redundant switch state under the ideal capacitor voltage is as follows: , among which, T s The PWM carrier period is the switching period, v x This is the original modulation amplitude value.

4. The harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance according to claim 1, characterized in that: In step S4), the optimized modulation wave v' x Substituting the expression for the duration of the selected critical redundant switch state under the ideal capacitor voltage, the piecewise expression for the duration of the critical redundant switch state under the actual capacitor voltage is as follows: , where v' x This is the optimized modulation amplitude value.

5. The harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance according to claim 1, characterized in that: In step S5), when E ≤ v x When < 2E, taking the critical redundant switch state V5 as an example, the ideal output voltage value for this cycle is 2E – E – 2E, and the actual output voltage value is V. p – V f – V p Then, in the ideal case, the area S1 of the volt-second integral is: In practice, the volt-second integral area S2 is: .

6. The harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance according to claim 1, characterized in that: The principle of volt-second balance in step S6) requires that: in any PWM switching cycle T s Within this timeframe, the integral of the actual output pulse voltage sequence of the converter over time should be equal to the volt-second product of the desired ideal output voltage sequence. .

7. The harmonic optimization method for a five-level ANPC converter under capacitor voltage imbalance according to claim 1, characterized in that: In step S7), when E ≤ v x When the threshold is < 2E, taking V5 as the critical redundant switch state as an example, by combining the expressions for the duration of the critical redundant state selected in S3) and S4), and the equation for the modulation wave correction in S6), the optimized modulation wave amplitude that can compensate for capacitor voltage fluctuations can be calculated. In other cases, v' x Similarly, the derivation process can yield a set of optimized modulation waves v' x The unified calculation formula.

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