A bootstrap diode simulator circuit suitable for high voltage half bridge gate drive chips

Abstract

The present application belongs to the technical field of integrated circuits, and particularly relates to a bootstrap diode simulator circuit suitable for a high-voltage half-bridge gate drive chip. The present application adopts a first high-voltage switch tube NLDMOS and a first low-voltage switch tube NMOS to form a controlled bootstrap charging path, and then combines a charge pump, a level shift circuit and a drive circuit to generate a drive signal for controlling the on and off of the bootstrap charging path according to the output of a logic judgment circuit, so as to realize the functions of turning on the charging path, charging the bootstrap capacitor when the half-bridge gate drive circuit works at the low side, turning off the charging path, and supplying power for the high-side gate drive with the bootstrap capacitor when the half-bridge gate drive circuit works at the high side. Meanwhile, the present application can be integrated in a chip, can avoid the negative effects such as higher on-voltage drop, reverse recovery and parasitic effect of the traditional bootstrap diode, can enhance the driving capacity of the half-bridge gate drive chip, and can improve the reliability of the bootstrap charging. Furthermore, the circuit of the present application is simple to realize, is suitable for various bootstrap charging occasions, and can meet the application requirements of the bootstrap charging of the high-speed half-bridge gate drive.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a bootstrap diode simulator circuit suitable for high-voltage half-bridge gate driver chips. Background Technology

[0002] Half-bridge gate driver chips are widely used in power conversion, motor drives, and power control systems. Their core task is to achieve reliable and efficient gate driving between the high-side and low-side power transistors. Because the high-side power transistor operates in a floating environment that varies with the load node voltage, a bootstrap charging circuit is necessary to generate a floating power rail. With increasing system voltage and faster switching speeds, half-bridge gate driver chips place more stringent performance demands on their bootstrap charging structures.

[0003] Traditional bootstrap power supply solutions mainly include external high-voltage bootstrap diode solutions and on-chip integrated high-voltage bootstrap diode solutions. While external high-voltage bootstrap diode solutions are simple to implement, they require additional components and wiring, increasing area costs. External circuitry can also introduce parasitic parameters, hindering system integration and switching performance. Furthermore, the high forward voltage drop and reverse recovery issues of diodes can lead to insufficient high-side drive capability, increased losses, and voltage spikes in the driver chip. In contrast, while on-chip integrated high-voltage bootstrap diode solutions reduce the number of external components and simplify application design, integrating the high-voltage diode within the chip often requires a larger chip area, increasing manufacturing complexity and cost. Additionally, on-chip integrated diodes also suffer from fixed forward voltage drops and limited charging paths, potentially resulting in insufficient charging of the bootstrap capacitor and limiting reliable high-side drive operation. Summary of the Invention

[0004] To address the aforementioned problems and shortcomings, and to overcome the various deficiencies of traditional bootstrap power supply schemes, this invention provides a bootstrap diode simulator circuit suitable for high-voltage half-bridge gate driver chips. This invention utilizes a controlled switching path to simulate the unidirectional conduction characteristics of a diode, effectively avoiding a series of problems caused by conduction voltage drop, reverse recovery, and parasitic effects in traditional bootstrap power supply schemes while achieving bootstrap charging functionality. This enhances driving capability and improves the reliability of the bootstrap charging process, and is of great significance in the application of high-voltage half-bridge gate driver chips.

[0005] A bootstrap diode simulator circuit suitable for high-voltage half-bridge gate driver chips includes: a first high-voltage switch NLDMOS, a first low-voltage switch NMOS, a logic judgment circuit, a level shifting circuit, a charge pump, and a drive circuit.

[0006] The gate of the first high-voltage switch NLDMOS is connected to the output VG of the driving circuit, the drain of the first high-voltage switch NLDMOS is connected to the upper plate of the bootstrap capacitor CBST, and the source of the first high-voltage switch NLDMOS is connected to the source of the first low-voltage switch NMOS.

[0007] The gate of the first low-voltage switching transistor NMOS is connected to the output VG of the driving circuit, the source of the first low-voltage switching transistor NMOS is connected to the source of the first high-voltage switching transistor NLDMOS, and the drain of the first low-voltage switching transistor NMOS is connected to the low-voltage voltage source VCC.

[0008] The logic judgment circuit includes a first inverter INV1 and a second inverter INV2. The input terminal of the first inverter INV1 is connected to the low-side gate drive signal GL, and the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2. The output of the first inverter INV1 serves as the first output of the logic judgment circuit, generating a first control signal VCTRL1. The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and the output of the second inverter INV2 serves as the second output of the logic judgment circuit, generating a second control signal VCTRL2.

[0009] The first input of the charge pump is connected to the low-voltage source VCC, the second input of the charge pump is connected to ground GND, and the output voltage VCC_H of the charge pump is connected to the input of the level shifting circuit and the driving circuit.

[0010] The first input of the level shift circuit is connected to the first control signal VCTRL1, the second output is connected to the second control signal VCTRL2, the third input is connected to the low-voltage source VCC, the fourth input is connected to the output VCC_H of the charge pump, the fifth input is connected to ground GND, and the output voltage VLS is connected to the input of the drive circuit. The level shift circuit generates voltage signals to control the first high-voltage switch NLDMOS and the first low-voltage switch NMOS to turn on or off: when the first control signal VCTRL1 is low and the second control signal VCTRL2 is high, the output VLS of the level shift circuit is pulled up to VCC_H; when the first control signal VCTRL1 is high and the second control signal VCTRL2 is low, the output VLS of the level shift circuit is pulled down to VCC.

[0011] The first input of the driving circuit is connected to the low-voltage source VCC, the second input of the driving circuit is connected to the output VCC_H of the charge pump, the third input of the driving circuit is connected to the output VLS of the level shift circuit, and the output VG of the driving circuit is connected to the gates of the first high-voltage switch NLDMOS and the first low-voltage switch NMOS.

[0012] In this invention, the entire bootstrap diode simulator circuit consists of a first high-voltage switch NLDMOS and a first low-voltage switch NMOS forming a controlled charging path. The logic judgment circuit determines whether the charging conditions are met, and the charge pump, level shift circuit and driving circuit generate driving signals to control the conduction and turn-off of the first high-voltage switch NLDMOS and the first low-voltage switch NMOS.

[0013] Specifically, the first high-voltage switch NLDMOS and the first low-voltage switch NMOS are interconnected at their sources to form a bootstrap charging path. The first high-voltage switch NLDMOS is located at the output of the bootstrap diode simulator circuit, providing withstand voltage to withstand the floating high voltage of the bootstrap voltage VBST. The first low-voltage switch NMOS is located on the low-voltage side of the charging path, with faster switching speed and stronger instantaneous current conduction capability, which is beneficial to improving the bootstrap charging rate and enhancing the bootstrap charging capability. At the same time, the first high-voltage switch NLDMOS and the first low-voltage switch NMOS are connected by source interconnection, and the body diodes of the two switches are in opposite directions. This can structurally ensure bidirectional blocking of the charging path when the controlled charging path is off, avoiding the formation of an uncontrolled charging path through the body diodes of the switches during the high-side operation stage and the dead-zone negative voltage stage of the half-bridge gate drive circuit, and preventing overcharging of the bootstrap capacitor. In addition, the bootstrap charging path is composed of the first high-voltage switch NLDMOS and the first low-voltage switch NMOS, which can significantly reduce the on-state voltage drop loss during the bootstrap charging process and enhance the high-side driving capability of the half-bridge gate drive circuit.

[0014] Furthermore, the level shifting circuit adopts an asymmetric circuit structure, including a first low-voltage NMOS transistor N1, a second low-voltage NMOS transistor N2, a third low-voltage NMOS transistor N3, a fourth low-voltage NMOS transistor N4, a first high-voltage NMOS transistor N5, a second high-voltage NMOS transistor N6, a first low-voltage PMOS transistor P1, a second low-voltage PMOS transistor P2, a third low-voltage PMOS transistor P3, a fourth low-voltage PMOS transistor P4, a first resistor R1, and a second resistor R2.

[0015] In this configuration, the source of the first low-voltage NMOS transistor N1 is interconnected with the source of the second low-voltage NMOS transistor N2 and connected to ground (GND). The gate of the first low-voltage NMOS transistor N1 is connected to the second control signal VCTRL2, the gate of the second low-voltage NMOS transistor N2 is connected to the first control signal VCTRL1, the drain of the first low-voltage NMOS transistor N1 is connected to the source of the first high-voltage NMOS transistor N5, and the drain of the second low-voltage NMOS transistor N2 is connected to the source of the second high-voltage NMOS transistor N6.

[0016] The gates of the first high-voltage NMOS transistor N5 and the second high-voltage NMOS transistor N6 are interconnected and connected to the low-voltage voltage source VCC. The drain of the first high-voltage NMOS transistor N5 is connected to the lower end of the first resistor R1, and the drain of the second high-voltage NMOS transistor N6 is connected to the lower end of the second resistor R2. The upper end of the first resistor R1 is connected to the gate and drain of the first low-voltage PMOS transistor P1 and the gate of the second low-voltage PMOS transistor P2. The upper end of the second resistor R2 is connected to the gate and drain of the fourth low-voltage PMOS transistor P4 and the gate of the third low-voltage PMOS transistor P3.

[0017] The sources of the first low-voltage PMOS transistor P1, the second low-voltage PMOS transistor P2, the third low-voltage PMOS transistor P3, and the fourth low-voltage PMOS transistor P4 are interconnected and connected to the charge pump output VCC_H. The drain of the second low-voltage PMOS transistor P2 is connected to the drain of the third low-voltage NMOS transistor N3. The drain of the third low-voltage PMOS transistor P3 is connected to the gate and drain of the fourth low-voltage NMOS transistor N4 and the gate of the third low-voltage NMOS transistor N3. The sources of the third low-voltage NMOS transistor N3 and the fourth low-voltage NMOS transistor N4 are interconnected and connected to the low-voltage voltage source VCC.

[0018] The connection point between the drain of the second low-voltage PMOS transistor P2 and the drain of the third low-voltage NMOS transistor N3 is the output VLS of the level shifting circuit.

[0019] In the input transistors of the level shift circuit, the width-to-length ratio of the first low-voltage NMOS transistor N1 to the second low-voltage NMOS transistor N2 is 1:N, where N is a real number greater than 1, and its upper limit is limited by the chip area and power consumption required by the actual application. The width-to-length ratio of the second low-voltage NMOS transistor N2 is greater than that of the first low-voltage NMOS transistor N2. This is to ensure that when the first control signal VCTRL1 is high and the second control signal VCTRL2 is low, the delay of the output VLS of the level shift circuit being pulled down to VCC is significantly shortened, thereby avoiding a series of stability problems such as current spikes and additional power consumption caused by the high turn-off delay of the bootstrap diode simulator circuit in the bootstrap charging path.

[0020] Furthermore, the output VCC_H of the charge pump is a voltage with a value of VCC + Vgs_on, where Vgs_on is the gate-source voltage required for the switching transistor of the applicable process to be fully turned on.

[0021] Furthermore, the driving circuit consists of a multi-stage inverter buffer chain.

[0022] The bootstrap diode simulator circuit of the present invention forms a controlled charging path through a first high-voltage switch NLDMOS and a first low-voltage switch NMOS; a logic judgment circuit generates low-voltage logic signals VCTRL1 and VCTRL2 according to the low-side operating state of the half-bridge gate drive circuit; a charge pump generates a drive power supply VCC_H higher than VCC to solve the problem that the gate drive voltages of the first high-voltage switch NLDMOS and the first low-voltage switch NMOS rise with the bootstrap voltage VBST during bootstrap charging and cannot be effectively driven directly by the low-voltage signal; a level shifting circuit converts the low-voltage logic signals VCTRL1 and VCTRL2 into a control signal VLS in the VCC-VCC_H voltage domain; a drive circuit further amplifies the level-converted control signal VLS into a gate drive signal VG with sufficient pull-in and pull-out current capability, ensuring that the first high-voltage switch NLDMOS and the first low-voltage switch NMOS can still be quickly and reliably turned on and off when the bootstrap voltage VBST is at a floating potential. This circuit structure combines the controlled switching transistor with the control circuit, completely simulating the unidirectional conduction characteristics of a diode. It realizes the function of the charging path being turned on when the low-side power transistor of the half-bridge gate drive circuit is turned on, and the bootstrap capacitor being charged. When the high-side power transistor is turned on, the charging path is turned off, and the bootstrap capacitor supplies power to the high-side gate drive.

[0023] The beneficial effects of this invention are as follows: This invention can achieve on-chip integration and avoid parasitic effects; This invention can reduce the on-state voltage drop on the bootstrap charging path, increase the high-side drive voltage margin, and improve the driving capability; This invention uses an asymmetric level shift circuit to control the state of the switching transistor, reduce the turn-off delay, and improve the reliability of the bootstrap charging path; This invention can prevent the risk of overcharging during the dead time of the bootstrap capacitor; This invention is suitable for high-speed half-bridge gate drive applications. Attached Figure Description

[0024] Figure 1 This is a traditional bootstrap charging circuit for a half-bridge gate driver chip.

[0025] Figure 2 This is a schematic block diagram of the circuit of the present invention;

[0026] Figure 3 This is a schematic diagram of the level shifting circuit structure in an embodiment;

[0027] Figure 4 The waveform diagram shows the relevant signals of the bootstrap charging circuit using the bootstrap diode simulator of this invention. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0029] contrast Figure 1The traditional half-bridge gate driver chip bootstrap charging circuit shown in this invention uses a controlled switching path to simulate the unidirectional conduction characteristics of a diode. The bootstrap diode simulator circuit replaces the traditional bootstrap diode. The bootstrap charging path is controlled by a switching structure composed of a first high-voltage switch NLDMOS and a first low-voltage switch NMOS. The control circuit composed of a logic judgment circuit, a level shifting circuit, a charge pump, and a driving circuit controls the turning on and off of the first high-voltage switch NLDMOS and the first low-voltage switch NMOS, thereby replacing the bootstrap diode in the traditional bootstrap charging circuit.

[0030] The bootstrap voltage of a traditional bootstrap charging circuit can be expressed by equation (1-1):

[0031] VCBST = VCC - VF (1-1)

[0032] In the formula, VCBST is the bootstrap voltage, and VF is the forward voltage drop of the bootstrap diode. If a common high-voltage diode is used, VF can reach 0.7V; if a Schottky diode is used, VF can reach 0.3~0.4V.

[0033] The bootstrap voltage of the bootstrap diode simulator circuit of this invention can be expressed by equation (1-2):

[0034] VCBST=VCC-Vds,NMOS-Vds,NLDMOS (1-2)

[0035] In the formula, Vds,NMOS is the on-state voltage drop of the first low-voltage switch NMOS; Vds,NLDMOS is the on-state voltage drop of the first high-voltage switch NLDMOS, and its value depends on the on-resistance and operating current of the switch. In this embodiment, the sum of the on-state voltages of the first low-voltage switch NMOS and the first high-voltage switch NLDMOS is only 0.2V under a charging current of 100mA. The reduction in on-state voltage will further improve the driving capability of the half-bridge gate drive.

[0036] The bootstrap diode simulator circuit proposed in this invention is as follows: Figure 2 As shown, it includes a first high-voltage switching transistor NLDMOS, a first low-voltage switching transistor NMOS, a logic judgment circuit, a level shifting circuit, a charge pump, and a drive circuit.

[0037] In this invention, the first high-voltage switch NLDMOS and the first low-voltage switch NMOS form a controlled bootstrap charging path. The gate of the first high-voltage switch NLDMOS is connected to the control signal VG, its source is connected to the source of the first low-voltage switch NMOS, and its drain is connected to the upper plate of the bootstrap capacitor CBST. The gate of the first low-voltage switch NMOS is connected to the control signal VG, its source is connected to the source of the first high-voltage switch NLDMOS, and its drain is connected to the low-voltage voltage source VCC.

[0038] The first high-voltage switch NLDMOS meets the requirement of withstanding the high-voltage bootstrap voltage VBST at the output of the bootstrap diode simulator circuit, while the first low-voltage switch NMOS ensures a strong overcurrent capability during the bootstrap charging process. At the same time, the sources of the first high-voltage switch NLDMOS and the first low-voltage switch NMOS are connected, and when both are turned off, their two body diodes are in opposite directions, ensuring that the charging path can be completely blocked.

[0039] In this invention, the logic judgment circuit is used to generate low-voltage logic signals based on the low-side gate drive signal GL: a first control signal VCTRL1 and a second control signal VCTRL2. The level shifting circuit, charge pump, and drive circuit are used to generate control signals VG for the first high-voltage switch NLDMOS and the first low-voltage switch NMOS based on the first control signal VCTRL1 and the second control signal VCTRL2.

[0040] In this invention, the high-side power rail of the level shifting circuit is provided by a charge pump. The output VCC_H of the charge pump is the low-voltage voltage source VCC plus the voltage that can turn on the first high-voltage switch NLDMOS and the first low-voltage switch NMOS. In this embodiment, VCC_H is set to twice the value of VCC to meet the requirement of fully turning on the switch.

[0041] In this invention, the generation of gate control signals for the first high-voltage switch NLDMOS and the first low-voltage switch NMOS depends on a level shifting circuit. The specific circuit structure of the level shifting circuit in this embodiment is as follows: Figure 3 As shown: including a first low-voltage NMOS transistor N1, a second low-voltage NMOS transistor N2, a third low-voltage NMOS transistor N3, a fourth low-voltage NMOS transistor N4, a first high-voltage NMOS transistor N5, a second high-voltage NMOS transistor N6, a first low-voltage PMOS transistor P1, a second low-voltage PMOS transistor P2, a third low-voltage PMOS transistor P3, a fourth low-voltage PMOS transistor P4, a first resistor R1, and a second resistor R2.

[0042] In this configuration, the source of the first low-voltage NMOS transistor N1 is interconnected with the source of the second low-voltage NMOS transistor N2 and connected to ground (GND). The gate of the first low-voltage NMOS transistor N1 is connected to the second control signal VCTRL2, and the gate of the second low-voltage NMOS transistor N2 is connected to the first control signal VCTRL1. The drain of the first low-voltage NMOS transistor N1 is connected to the source of the first high-voltage NMOS transistor N5, and the drain of the second low-voltage NMOS transistor N2 is connected to the source of the second high-voltage NMOS transistor N6. The gates of the first high-voltage NMOS transistor N5 and the second high-voltage NMOS transistor N6 are interconnected and connected to a low-voltage voltage source VCC. The drain of the first high-voltage NMOS transistor N5 is connected to the lower end of the first resistor R1, and the drain of the second high-voltage NMOS transistor N6 is connected to the lower end of the second resistor R2. The upper end of the first resistor R1 is connected to the gate and drain of the first low-voltage PMOS transistor P1 and the second low-voltage PMOS transistor P6. The gate of MOSFET P2 is connected to the gate and drain of the fourth low-voltage PMOS transistor P4 and the gate of the third low-voltage PMOS transistor P3. The sources of the first low-voltage PMOS transistor P1, the second low-voltage PMOS transistor P2, the third low-voltage PMOS transistor P3 and the fourth low-voltage PMOS transistor P4 are interconnected and connected to the charge pump output VCC_H. The drain of the second low-voltage PMOS transistor P2 is connected to the drain of the third low-voltage NMOS transistor N3. The drain of the third low-voltage PMOS transistor P3 is connected to the gate and drain of the fourth low-voltage NMOS transistor N4 and the gate of the third low-voltage NMOS transistor N3. The sources of the third low-voltage NMOS transistor N3 and the fourth low-voltage NMOS transistor N4 are interconnected and connected to the low-voltage voltage source VCC. The connection node between the drain of the second low-voltage PMOS transistor P2 and the drain of the third low-voltage NMOS transistor N3 is the output VLS of the level shifting circuit.

[0043] In the level shifting circuit, when the first control signal VCTRL1 is low and the second control signal VCTRL2 is high, the first low-voltage NMOS transistor N1 in the input transistors of the level shifting circuit is turned on and the second low-voltage NMOS transistor N2 is turned off. The branch containing the first low-voltage NMOS transistor N1 generates current and ultimately pulls the output VLS of the level shifting circuit up to VCC_H. When the first control signal VCTRL1 is high and the second control signal VCTRL2 is low, the first low-voltage NMOS transistor N1 in the input transistors of the level shifting circuit is turned off and the second low-voltage NMOS transistor N2 is turned on. The branch containing the second low-voltage NMOS transistor N2 generates current and pulls the output VLS of the level shifting circuit down to VCC.

[0044] In this embodiment, the level shifting circuit is designed as an asymmetric level shifting circuit structure. The width-to-length ratio of the first low-voltage NMOS transistor N1 to the second low-voltage NMOS transistor N2 in the input transistors of the level shifting circuit is designed to be 1:2. This ensures that when the first control signal VCTRL1 is high and the second control signal VCTRL2 is low, the delay of pulling down the output VLS of the level shifting circuit to VCC is minimized, thereby minimizing the turn-off delay of the bootstrap diode simulator circuit.

[0045] Compared to traditional bootstrap charging circuits where the high-voltage bootstrap diode exhibits a severe reverse recovery effect at a charging current of hundreds of mA, failing to immediately cut off during the switch from the low-side power transistor ML to the high-side power transistor MH in the half-bridge gate drive, instead continuing to conduct a reverse recovery current for a short period. This generates a large current spike during the rise of the floating voltage VSW, leading to voltage fluctuations on the bootstrap capacitor CBST, causing additional power consumption and heat generation, and ultimately affecting the stability of the high-side drive and the reliability of the device. The bootstrap diode simulator of this invention, with its extremely low turn-off delay, rapidly cuts off the charging path at the moment of switching, ensuring a stable bootstrap voltage VBST, and better meeting the application requirements of high-speed half-bridge gate drive bootstrap charging circuits.

[0046] refer to Figure 4 , Figure 2 The working principle of the bootstrap charging circuit using the bootstrap diode simulator is as follows: In the initial stage, the low voltage source VCC inside the half-bridge gate driver chip is powered on, and the output VCC_H of the charge pump also rises with the power-on of VCC. At this time, the chip power stage circuit is not working.

[0047] In the normal operating mode of the half-bridge gate driver chip, when the low-side power transistor ML is turned on and the high-side power transistor MH is turned off, the floating voltage VSW is pulled down to ground GND, the low-side gate drive signal GL is high, the logic judgment circuit generates a first control signal VCTRL1 low and a second control signal VCTRL2 high, the first low-voltage NMOS transistor N1 in the level shift circuit is turned on, the second low-voltage NMOS transistor N2 is turned off, and the branch containing the first low-voltage NMOS transistor N1 generates a pull-down current, which passes through the first high-voltage NMOS transistor N5 and the first resistor R1 to connect the first low-voltage PMOS transistor P1 and... The gate voltage of the second low-voltage PMOS transistor P2 is pulled low, thereby turning on the first low-voltage PMOS transistor P1 and the second low-voltage PMOS transistor P2. The branch containing the second low-voltage PMOS transistor P2 generates a pull-up current, which pulls up the output VLS of the level shift circuit to VCC_H. After passing through the driving circuit, a VG signal with a voltage of VCC_H is obtained. At this time, the gate-source voltage Vgs of the first high-voltage switch transistor NLDMOS and the first low-voltage switch transistor NMOS is VCC. The switch transistors are turned on, the bootstrap diode simulator is forward-biased, and the voltage on the upper plate of the bootstrap capacitor CBST is charged to VCC. The bootstrap voltage VBST is VCC.

[0048] When the low-side power transistor ML is turned off and the high-side power transistor MH is turned on in the half-bridge drive, the floating voltage VSW is pulled up to the high voltage VS, the low-side gate drive signal GL is low, and the logic judgment circuit generates the first control signal VCTRL1 as high and the second control signal VCTRL2 as low. In the level shifting circuit, the second low-voltage NMOS transistor N2 is turned on, the first low-voltage NMOS transistor N1 is turned off, and the branch containing the second low-voltage NMOS transistor N2 generates a pull-down current. Through the second high-voltage NMOS transistor N6 and the second resistor R2, the gate voltages of the third low-voltage PMOS transistor P3 and the fourth low-voltage PMOS transistor P4 are pulled low, thereby turning on the third low-voltage PMOS transistor P3 and the fourth low-voltage PMOS transistor P4. The branch containing the low-voltage PMOS transistor P3 generates a pull-up current, which pulls up the gate voltages of the third low-voltage NMOS transistor N3 and the fourth low-voltage NMOS transistor N4, thereby turning on the third low-voltage NMOS transistor N3 and the fourth low-voltage NMOS transistor N4. The branch containing the third low-voltage NMOS transistor N3 generates a pull-down current, which pulls down the output VLS of the level shift circuit to VCC. After passing through the driving circuit, a VG signal with a voltage of VCC is obtained. At this time, the gate-source voltage Vgs of the first high-voltage switch transistor NLDMOS and the first low-voltage switch transistor NMOS is 0, the switch transistors are turned off, the bootstrap diode simulator is reverse cut off, the voltage difference between the upper and lower plates of the bootstrap capacitor CBST is maintained at VCC, and the bootstrap voltage VBST is raised to VS+VCC.

[0049] During the dead time, the half-bridge gate drive causes the floating voltage VSW to drop to a negative voltage due to reverse freewheeling. At this time, both the first high-voltage switch NLDMOS and the first low-voltage switch NMOS are turned off, and the bootstrap diode simulator is reverse-cut off to prevent the bootstrap voltage VBST from overcharging during the dead time.

[0050] Because the sources of the first high-voltage switch NLDMOS and the first low-voltage switch NMOS are interconnected, that is, the anodes of the body diodes of the first high-voltage switch NLDMOS and the first low-voltage switch NMOS are interconnected, the charging path can be blocked when both switches are turned off, thus ensuring the reliability of the half-bridge gate driver chip.

[0051] As can be seen from the above embodiments, the bootstrap diode simulator circuit of the present invention utilizes a controlled charging path composed of a first high-voltage switch NLDMOS and a first low-voltage switch NMOS, and combines a logic judgment circuit, a level shifting circuit, a charge pump, and a driving circuit to control the conduction and turn-off of the switch transistors according to the low-side gate drive signal of the half-bridge gate driver chip; the bootstrap charging path is opened during the low-side power transistor turn-on stage to charge the bootstrap capacitor CBST, and the bootstrap charging path is blocked during the high-side power transistor turn-on stage. The charging path formed by the first high-voltage switch NLDMOS and the first low-voltage switch NMOS not only meets the requirements of withstanding the VBST high voltage, but also ensures the overcurrent capability of the bootstrap charging path, reducing the forward conduction voltage drop loss caused by traditional bootstrap diodes. At the same time, the two switches adopt a source-interconnected connection method to ensure that the charging path is completely blocked when the switches are turned off, avoiding the problem of overcharging of the bootstrap capacitor CBST during the dead time. The asymmetric level shifting circuit design minimizes the pull-down delay of the switch control voltage, enabling it to quickly cut off the bootstrap charging path when the half-bridge gate driver chip switches from the low side to the high side, thereby avoiding possible bootstrap voltage fluctuations, current spikes and other problems.

[0052] This invention uses a bootstrap diode simulator circuit to replace the traditional bootstrap diode. This not only enables on-chip circuit integration and avoids the negative effects of parasitic effects of traditional bootstrap diodes, but also avoids the additional losses and reliability problems caused by the forward voltage drop and reverse recovery process of traditional bootstrap diodes. It can enhance the high-side driving capability of the half-bridge gate driver chip and enable the half-bridge gate driver chip to operate at a higher frequency. Moreover, the circuit of this invention is simple to implement and suitable for various occasions that require bootstrap charging, meeting the application requirements of high-speed half-bridge gate driver bootstrap charging circuits.

Claims

1. A bootstrap diode simulator circuit suitable for high-voltage half-bridge gate driver chips, characterized in that: It includes a first high-voltage switching transistor NLDMOS, a first low-voltage switching transistor NMOS, a logic judgment circuit, a level shifting circuit, a charge pump, and a drive circuit; The gate of the first high-voltage switch NLDMOS is connected to the output VG of the driving circuit, the drain of the first high-voltage switch NLDMOS is connected to the upper plate of the bootstrap capacitor CBST, and the source of the first high-voltage switch NLDMOS is connected to the source of the first low-voltage switch NMOS. The gate of the first low-voltage switching transistor NMOS is connected to the output VG of the driving circuit, the source of the first low-voltage switching transistor NMOS is connected to the source of the first high-voltage switching transistor NLDMOS, and the drain of the first low-voltage switching transistor NMOS is connected to the low-voltage voltage source VCC. The logic judgment circuit includes a first inverter INV1 and a second inverter INV2; wherein, the input terminal of the first inverter INV1 is connected to the low-side gate drive signal GL, the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, and the output of the first inverter INV1 serves as the first output of the logic judgment circuit, generating a first control signal VCTRL1; the input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and the output of the second inverter INV2 serves as the second output of the logic judgment circuit, generating a second control signal VCTRL2; The first input of the charge pump is connected to the low-voltage source VCC, the second input of the charge pump is connected to ground GND, and the output voltage VCC_H of the charge pump is connected to the input of the level shifting circuit and the driving circuit. The first input of the level shift circuit is connected to the first control signal VCTRL1, the second output of the level shift circuit is connected to the second control signal VCTRL2, the third input of the level shift circuit is connected to the low-voltage source VCC, the fourth input of the level shift circuit is connected to the output VCC_H of the charge pump, the fifth input of the level shift circuit is connected to ground GND, and the output voltage VLS of the level shift circuit is connected to the input terminal of the drive circuit. The level shift circuit is used to generate voltage signals to control the first high-voltage switch NLDMOS and the first low-voltage switch NMOS to turn on or off: when the first control signal VCTRL1 is low and the second control signal VCTRL2 is high, the output VLS of the level shift circuit is pulled up to VCC_H; when the first control signal VCTRL1 is high and the second control signal VCTRL2 is low, the output VLS of the level shift circuit is pulled down to VCC. The first input of the driving circuit is connected to the low-voltage source VCC, the second input of the driving circuit is connected to the output VCC_H of the charge pump, the third input of the driving circuit is connected to the output VLS of the level shift circuit, and the output VG of the driving circuit is connected to the gates of the first high-voltage switch NLDMOS and the first low-voltage switch NMOS.

2. The bootstrap diode simulator circuit for high-voltage half-bridge gate driver chips as described in claim 1, characterized in that: The level shifting circuit adopts an asymmetric circuit structure, including a first low-voltage NMOS transistor N1, a second low-voltage NMOS transistor N2, a third low-voltage NMOS transistor N3, a fourth low-voltage NMOS transistor N4, a first high-voltage NMOS transistor N5, a second high-voltage NMOS transistor N6, a first low-voltage PMOS transistor P1, a second low-voltage PMOS transistor P2, a third low-voltage PMOS transistor P3, a fourth low-voltage PMOS transistor P4, a first resistor R1, and a second resistor R2; In this configuration, the source of the first low-voltage NMOS transistor N1 is interconnected with the source of the second low-voltage NMOS transistor N2 and connected to ground GND. The gate of the first low-voltage NMOS transistor N1 is connected to the second control signal VCTRL2, the gate of the second low-voltage NMOS transistor N2 is connected to the first control signal VCTRL1, the drain of the first low-voltage NMOS transistor N1 is connected to the source of the first high-voltage NMOS transistor N5, and the drain of the second low-voltage NMOS transistor N2 is connected to the source of the second high-voltage NMOS transistor N6. The gates of the first high-voltage NMOS transistor N5 and the second high-voltage NMOS transistor N6 are interconnected and connected to the low-voltage voltage source VCC. The drain of the first high-voltage NMOS transistor N5 is connected to the lower end of the first resistor R1, and the drain of the second high-voltage NMOS transistor N6 is connected to the lower end of the second resistor R2. The upper end of the first resistor R1 is connected to the gate and drain of the first low-voltage PMOS transistor P1 and the gate of the second low-voltage PMOS transistor P2. The upper end of the second resistor R2 is connected to the gate and drain of the fourth low-voltage PMOS transistor P4 and the gate of the third low-voltage PMOS transistor P3. The sources of the first low-voltage PMOS transistor P1, the second low-voltage PMOS transistor P2, the third low-voltage PMOS transistor P3, and the fourth low-voltage PMOS transistor P4 are interconnected and connected to the charge pump output VCC_H. The drain of the second low-voltage PMOS transistor P2 is connected to the drain of the third low-voltage NMOS transistor N3. The drain of the third low-voltage PMOS transistor P3 is connected to the gate and drain of the fourth low-voltage NMOS transistor N4 and the gate of the third low-voltage NMOS transistor N3. The sources of the third low-voltage NMOS transistor N3 and the fourth low-voltage NMOS transistor N4 are interconnected and connected to the low-voltage voltage source VCC. The connection point between the drain of the second low-voltage PMOS transistor P2 and the drain of the third low-voltage NMOS transistor N3 is the output VLS of the level shift circuit; and the width-to-length ratio of the first low-voltage NMOS transistor N1 to the second low-voltage NMOS transistor N2 is 1:N, where N is a real number greater than 1.

3. The bootstrap diode simulator circuit for high-voltage half-bridge gate driver chips as described in claim 1, characterized in that: The output VCC_H of the charge pump is a voltage of VCC + Vgs_on, where Vgs_on is the gate-source voltage required for the switching transistor of the applicable process to be fully turned on.

4. The bootstrap diode simulator circuit for high-voltage half-bridge gate driver chips as described in claim 1, characterized in that: The driving circuit consists of a multi-stage inverter buffer chain.

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