Bridge inverter circuit and driving circuit thereof

Abstract

The application belongs to the technical field of inverter circuit structure, and particularly relates to a bridge type inverter circuit and a driving circuit thereof. The driving circuit comprises a signal input module and a delay control module. The delay control module comprises a first delay branch and a second delay branch. The outputs of the first delay branch and the second delay branch are connected to the high side switch and the low side switch of the bridge arm of the bridge type inverter circuit respectively. When the input signal of the driving circuit is converted, the signal needs to pass through the delay time of the first delay branch and the second delay branch respectively to reach the output end. The delay time is used as the transition state inclusive time of the high side switch and the low side switch, so that the simultaneous conduction of the high side switch and the low side switch is effectively avoided, the bridge arm direct through is avoided, and the circuit is protected.

Description

Technical Field

[0001] This invention belongs to the technical field of inverter circuit structure, specifically relating to a bridge inverter circuit and its driving circuit. Background Technology

[0002] Each arm of a bridge inverter circuit consists of two switches: a high-side switch and a low-side switch. The two switches in each arm of the bridge inverter circuit alternately turn on and off, converting DC input to AC output. If both the high-side and low-side switches are on at the same time, a direct path is formed from the positive to the negative terminal of the DC power supply, i.e., the bridge arm is shoot-through.

[0003] When the high-side and low-side switches of the same bridge arm are turned on simultaneously, the DC power supply will be directly short-circuited, causing the current through the switching devices to increase sharply and instantaneously. The short-circuit current will not only cause serious damage to the switching devices, but may also damage other circuit components, resulting in economic losses.

[0004] In existing technologies, dead time is typically set directly in the controller's control signal, inserting a delay to ensure that one switch is completely turned off before another is turned on, thus preventing bridge arm shoot-through. However, this method can still lead to bridge arm shoot-through in the event of controller failure or unstable output signal, causing circuit damage and insufficient reliability. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the low reliability of existing methods for avoiding bridge arm shoot-through in bridge inverter circuits, thereby providing a bridge inverter circuit and its driving circuit.

[0006] A driving circuit for a bridge inverter includes a signal input module and a delay control module; the output terminal of the signal input module is connected to the input terminal of the delay control module to form a logic signal output; the delay control module includes a first delay branch and a second delay branch. The first delay branch includes a first AND gate and a first delay module. The first input terminal of the first AND gate is connected to the output terminal of the first delay module, and the second input terminal of the first AND gate and the input terminal of the first delay module are connected to the output terminal of the signal input module. The second delay branch includes a first inverter, a second AND gate, and a second delay module. The first input of the second AND gate is connected to the output of the second delay module. The second input of the second AND gate and the input of the second delay module are connected to the output of the first inverter. The input of the first inverter is connected to the output of the signal input module.

[0007] Furthermore, it also includes multiple resonant circuits, with the input terminals of the first delay module and the second delay module respectively connected in series with one of the resonant circuits.

[0008] Furthermore, the resonant circuit is an RC resonant circuit.

[0009] Furthermore, the first delay module and the second delay module include at least one delay device.

[0010] Furthermore, the delay device is at least one of a gate, an AND gate, and an OR gate.

[0011] Furthermore, the signal input module is one of an in-phase buffer and a gate buffer.

[0012] Furthermore, the signal input module includes at least one of an inverter, an AND gate, and an OR gate.

[0013] A bridge inverter circuit includes a first driving circuit and a first half-bridge circuit. The structure of the first driving circuit is as described above. The first half-bridge circuit includes a first switching transistor and a second switching transistor. The drain of the first switching transistor is connected to a DC power supply. The source of the first switching transistor and the drain of the second switching transistor are connected to form the output terminal of the first half-bridge circuit. The source of the second switching transistor is grounded. The output terminal of the first delay branch is connected to the gate of the first switching transistor, and the output terminal of the second delay branch is connected to the gate of the second switching transistor.

[0014] Furthermore, it also includes a first transformer, the output terminals of the first delay branch and the second delay branch are respectively connected to the same-name terminal and the opposite-name terminal of the primary coil of the first transformer; the same-name terminal of the primary coil of the first transformer is connected to the gate of the first switching transistor, and the opposite-name terminal of the primary coil of the first transformer is connected to the output terminal of the first half-bridge circuit; the opposite-name terminal of the secondary coil of the first transformer is connected to the gate of the second switching transistor, and the same-name terminal of the secondary coil is grounded.

[0015] Furthermore, there are multiple first half-bridge circuits configured in parallel, and the output terminals of each first half-bridge circuit are connected to a resonant filter circuit.

[0016] Furthermore, there are multiple first driving circuits, which are configured in pairs with the first half-bridge circuit, and each first driving circuit receives the same input signal.

[0017] Furthermore, it also includes a switching module, which is selectively configured at some or all of the input or output terminals of the first driving circuit, so that the selected first driving circuit is enabled or disabled.

[0018] Furthermore, it also includes a second half-bridge circuit and a second driving circuit. The architecture of the second driving circuit is the same as that of the driving circuit described above. The second half-bridge circuit includes a third switch and a fourth switch. The drain of the third switch is connected to a DC source. The source of the third switch and the drain of the fourth switch are connected to form the output terminal of the second half-bridge circuit. The source of the fourth switch is grounded. The output of the first delay branch of the second driving circuit is connected to the gate of the fourth switch, and the output of the second delay branch of the second driving circuit is connected to the gate of the third switch. The first driving circuit and the second driving circuit acquire input signals with opposite phases.

[0019] Furthermore, it also includes a second transformer; the output terminals of the first delay branch and the second delay branch of the second driving circuit are respectively connected to the same-name terminal and the opposite-name terminal of the primary coil of the second transformer; the same-name terminal of the first primary coil of the second transformer is connected to the gate of the third switching transistor, and the opposite-name terminal of the first primary coil of the second transformer is connected to the output terminal of the second half-bridge circuit; the opposite-name terminal of the second secondary coil of the second transformer is connected to the gate of the fourth switching transistor, and the same-name terminal of the second secondary coil is grounded.

[0020] Furthermore, it also includes a signal amplification module, which includes multiple signal amplifiers, two of which are a first signal amplifier and a second signal amplifier; the output of the AND gate of the first delay branch is connected to the input of the first signal amplifier through a resistor; the output of the AND gate of the second delay branch is connected to the input of the second signal amplifier through a resistor. The signal output terminals of the first signal amplifier and the second signal amplifier are respectively connected to the gates of the first and second switching transistors via the first transformer. The grounding terminal of the signal amplifier is grounded; the power supply terminal of the signal amplifier is connected to a DC power supply and a polarized capacitor is connected to ground.

[0021] Furthermore, the signal amplification module also includes a filtering module, which includes four filtering capacitors. The first end of the four filtering capacitors is connected to the power supply terminal of the signal amplifier, and the second end is grounded.

[0022] Beneficial effects: This invention discloses a driving circuit for a bridge inverter circuit, including a signal input module and a delay control module. The delay control module includes a first delay branch and a second delay branch. The outputs of the first delay branch and the second delay branch are respectively connected to the high-side switch and the low-side switch of the bridge arm of the bridge inverter circuit. When the input signal of the driving circuit changes, the signal needs to pass through the delay time of the first delay branch and the second delay branch to reach the output terminal. The delay time serves as the transition envelope time of the high-side switch and the low-side switch, effectively preventing the high-side switch and the low-side switch from conducting simultaneously, avoiding the bridge arm from shoot-through, and thus protecting the circuit. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic block diagram of the overall structure of the driving circuit of the present invention; Figure 2 This is a schematic diagram of the driving circuit of the present invention; Figure 3 This is a schematic diagram of the connection circuit between the first half-bridge circuit and the first transformer of the present invention; Figure 4 This is a schematic diagram of the second half-bridge circuit and the connection circuit of the second transformer of the present invention. Figure 5 This is a schematic diagram of the signal amplification module connection circuit of the present invention; Figure 6 This is a schematic diagram of another signal amplification module connection circuit according to the present invention; Figure 7 This is a schematic block diagram of a bridge inverter circuit structure according to the present invention; Figure 8 This is a schematic block diagram of another bridge inverter circuit structure of the present invention.

[0025] Explanation of reference numerals in the attached figures: ① First delay module; ② Second delay module; ③ First resonant circuit; ④ Second resonant circuit; ⑤ Signal input module; ⑥ First half-bridge circuit; ⑦ Second half-bridge circuit; U1, First AND gate; U2, Second AND gate; U3, Third AND gate; U4, First inverter; U5, Fourth inverter; U6, Fifth inverter; U7, Second inverter; U8, Third inverter; U9, First signal amplifier; U10, Second signal amplifier; R1, First resistor; R2, Second resistor; C1, First capacitor; C2, Second capacitor; Q1, First switch transistor; Q2, Second switch transistor; Q3, Third switch transistor; Q4, Fourth switch transistor; T1, First transformer; T2, Second transformer. Detailed Implementation

[0026] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0027] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0028] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0029] Example 1: Reference Figure 1 and Figure 2 As shown, this embodiment discloses a driving circuit for a bridge inverter circuit, including a signal input module ⑤ and a delay control module; the output terminal of the signal input module ⑤ is connected to the input terminal of the delay control module to form a logic signal output; the delay control module includes a first delay branch and a second delay branch; The first delay branch includes a first AND gate U1 and a first delay module ①. The first input terminal of the first AND gate U1 is connected to the output terminal of the first delay module ①, and the second input terminal of the first AND gate U1 and the input terminal of the first delay module ① are connected to the output terminal of the signal input module ⑤. The second delay branch includes a first inverter U4, a second AND gate U2, and a second delay module ②. The first input terminal of the second AND gate U2 is connected to the output terminal of the second delay module ②. The second input terminal of the second AND gate U2 and the input terminal of the second delay module ② are connected to the output terminal of the first inverter U4. The input terminal of the first inverter U4 is connected to the output terminal of the signal input module ⑤.

[0030] This embodiment provides a driving circuit for a bridge inverter circuit, including a signal input module ⑤ and a delay control module. The delay control module includes a first delay branch and a second delay branch. The outputs of the first delay branch and the second delay branch are respectively connected to the high-side switch and the low-side switch of the bridge arm of the bridge inverter circuit. When the input signal of the driving circuit changes, the signal needs to pass through the delay time of the first delay branch and the second delay branch to reach the output terminal. The delay time serves as the transition envelope time of the high-side switch and the low-side switch, effectively preventing the high-side switch and the low-side switch from conducting simultaneously, preventing the bridge arm from shoot-through, and thus protecting the circuit.

[0031] As a further improvement to this embodiment, multiple resonant circuits are also included, with the input terminals of the first delay module ① and the second delay module ② respectively connected in series with a resonant circuit. Preferably, the resonant circuit in this embodiment is an RC resonant circuit. In this embodiment, the resonant circuit of the first delay branch is denoted as the first resonant circuit ③, including a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is connected to the output terminal of the signal input module ⑤, and the second end is connected to the input terminal of the first delay module ①. The first end of the first capacitor C1 is connected to the second end of the first resistor R1, and the second end of the first capacitor C1 is grounded. The resonant circuit of the second delay branch is denoted as the second resonant circuit ④, including a second resistor R2 and a second capacitor C2. The first end of the second resistor R2 is connected to the output terminal of the first inverter U4, and the second end is connected to the input terminal of the second delay module ②. The first end of the second capacitor C2 is connected to the second end of the second resistor R2, and the second end of the second capacitor C2 is grounded.

[0032] In this embodiment, the first delay module ① and the second delay module ② each include at least one delay device. Preferably, the delay device is at least one of a gate, an AND gate, and an OR gate. In one implementation of this embodiment, the delay device is two inverters connected in series: a second inverter U7 and a third inverter U8 in the first delay module ①, and a fourth inverter U5 and a fifth inverter U6 in the second delay module ②. Preferably, the inverters in the delay modules are low-latency Schmitt-N gates.

[0033] In this embodiment, when the input signal changes from a low bit to a high bit, it passes through the resonant circuit of the first delay branch and the first delay module ① in sequence before being output to the first AND gate U1, causing the output of the first AND gate U1 to change from a low bit to a high bit; the first inverter U4 of the second delay branch outputs a low bit, directly causing the output of the second AND gate U2 to change from a low bit to a high bit. When the input signal changes from a high bit to a low bit, the first AND gate U1 of the first delay branch outputs a low bit; the first inverter U4 of the second delay branch outputs a high bit, and passes through the resonant circuit of the first delay module ① and the first delay module ① in sequence before being output to the second AND gate U2, causing the output of the second AND gate U2 to change from a low bit to a high bit. Thus, when the input signal changes from a high bit to a low bit or from a low bit to a high bit, the first AND gate U1 and the second AND gate U2 can be prevented from simultaneously outputting high bits, avoiding bridge arm shoot-through.

[0034] Specifically, the signal input module ⑤ is either an in-phase buffer or a gate buffer. Preferably, in this embodiment, the signal input module ⑤ is a gate buffer.

[0035] As a further improvement to this embodiment, the signal input module ⑤ includes at least one of an inverter, an AND gate, and an OR gate. Preferably, the signal input module ⑤ is a third AND gate U3.

[0036] Example 2: Reference Figure 3 As shown, this embodiment provides a bridge inverter circuit, which includes a first driving circuit and a first half-bridge circuit ⑥. The structure of the first driving circuit is as described in Embodiment 1. The first half-bridge circuit ⑥ includes a first switching transistor Q1 and a second switching transistor Q2. The drain of the first switching transistor Q1 is connected to a DC power supply. The source of the first switching transistor Q1 and the drain of the second switching transistor Q2 are connected to form the output terminal of the first half-bridge circuit ⑥. The source of the second switching transistor Q2 is grounded. The output terminal of the first delay branch is connected to the gate of the first switching transistor Q1, and the output terminal of the second delay branch is connected to the gate of the second switching transistor Q2. The output terminal of the first delay branch of the first driving circuit is denoted as OUT11, and the output terminal of the second delay branch of the first driving circuit is denoted as OUT12.

[0037] As a further improvement to this embodiment, it also includes a first transformer T1, with the output terminals of the first delay branch and the second delay branch respectively connected to the same-name terminal and the opposite-name terminal of the primary coil of the first transformer T1; the same-name terminal of the primary coil of the first transformer T1 is connected to the gate of the first switching transistor Q1, and the opposite-name terminal of the primary coil of the first transformer T1 is connected to the output terminal of the first half-bridge circuit ⑥; the opposite-name terminal of the secondary coil of the first transformer T1 is connected to the gate of the second switching transistor Q2, and the same-name terminal of the secondary coil is grounded.

[0038] Reference Figure 7As shown, in this embodiment, there are multiple first half-bridge circuits ⑥ connected in parallel, and the output terminals of each first half-bridge circuit ⑥ are connected to the resonant filter circuit.

[0039] Specifically, there are multiple first driving circuits, which are configured in pairs with the first half-bridge circuit ⑥, and each first driving circuit receives the same input signal.

[0040] As a further improvement to this embodiment, a switching module is also included, which is selectively configured at some or all of the input or output terminals of the first driving circuit, enabling or disabling the selected first driving circuit. In some embodiments of this embodiment, the switching module is a series-connected switching transistor.

[0041] Reference Figure 4 and Figure 8 As shown, in some other embodiments of the present invention, a second half-bridge circuit ⑦ and a second driving circuit are also included. The architecture of the second driving circuit is the same as that of the driving circuit in the embodiment. The second half-bridge circuit ⑦ includes a third switch Q3 and a fourth switch Q4. The drain of the third switch Q3 is connected to a DC source. The source of the third switch Q3 and the drain of the fourth switch Q4 are connected to form the output terminal of the second half-bridge circuit ⑦. The source of the fourth switch Q4 is grounded. The output of the first delay branch of the second driving circuit is connected to the gate of the fourth switch Q4, and the output of the second delay branch of the second driving circuit is connected to the gate of the third switch Q3. The first driving circuit and the second driving circuit acquire input signals with opposite phases. The output terminal of the first delay branch of the second driving circuit is denoted as OUT21, and the output terminal of the second delay branch of the second driving circuit is denoted as OUT22.

[0042] In these embodiments, a second transformer T2 is also included; the output terminals of the first delay branch and the second delay branch of the second drive circuit are respectively connected to the same-name terminal and the opposite-name terminal of the primary coil of the second transformer T2; the same-name terminal of the primary coil of the second transformer T2 is connected to the gate of the third switch Q3, and the opposite-name terminal of the primary coil of the second transformer T2 is connected to the output terminal of the second half-bridge circuit ⑦; the opposite-name terminal of the secondary coil of the second transformer T2 is connected to the gate of the fourth switch Q4, and the same-name terminal of the secondary coil is grounded.

[0043] Reference Figure 5 As shown, as a further improvement of this embodiment, a signal amplification module is also included. The signal amplification module includes multiple signal amplifiers, two of which are a first signal amplifier U9 and a second signal amplifier U10. The output terminal of the AND gate of the first delay branch is connected to the input terminal of the first signal amplifier U9 through a resistor. The output terminal of the AND gate of the second delay branch is connected to the input terminal of the second signal amplifier U10 through a resistor. In some embodiments of this example, the signal output terminal of the first signal amplifier U9 is connected to the gate of the first switching transistor Q1, and the signal output terminal of the second signal amplifier U10 is connected to the gate of the second switching transistor Q2. Reference Figure 6 As shown, in some other embodiments of this example, the signal output terminal of the first signal amplifier U9 and the signal output terminal of the second signal amplifier U10 are respectively connected to the gates of the first switch Q1 and the second switch Q2 via the first transformer T1.

[0044] The grounding terminal of the signal amplifier is grounded; the power supply terminal of the signal amplifier is connected to a DC power supply and a polarized capacitor is connected to ground.

[0045] As a further improvement to this embodiment, the signal amplification module also includes a filtering module, which includes four filtering capacitors. The first end of the four filtering capacitors is connected to the power supply terminal of the signal amplifier, and the second end is grounded.

[0046] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0047] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A drive circuit for a bridge inverter circuit, characterized by It includes a signal input module and a delay control module; the output terminal of the signal input module is connected to the input terminal of the delay control module to form a logic signal output; the delay control module includes a first delay branch and a second delay branch; The first delay branch includes a first AND gate and a first delay module. The first input terminal of the first AND gate is connected to the output terminal of the first delay module, and the second input terminal of the first AND gate and the input terminal of the first delay module are connected to the output terminal of the signal input module. The second delay branch includes a first inverter, a second AND gate, and a second delay module. The first input of the second AND gate is connected to the output of the second delay module. The second input of the second AND gate and the input of the second delay module are connected to the output of the first inverter. The input of the first inverter is connected to the output of the signal input module.

2. The driving circuit of a bridge inverter circuit according to claim 1, characterized in that, It also includes multiple resonant circuits, with the input terminals of the first delay module and the second delay module respectively connected in series with one of the resonant circuits.

3. The driving circuit of a bridge inverter circuit according to claim 2, characterized in that, The resonant circuit is an RC resonant circuit.

4. The driving circuit of a bridge inverter circuit according to claim 1, characterized in that, The first delay module and the second delay module each include at least one delay device.

5. The driving circuit of a bridge inverter circuit according to claim 4, characterized in that, The delay device is at least one of a gate, an AND gate, and an OR gate.

6. The driving circuit of a bridge inverter circuit according to claim 1, characterized in that, The signal input module is one of an in-phase buffer and a gate buffer.

7. The driving circuit of a bridge inverter circuit according to claim 1, characterized in that, The signal input module includes at least one of an inverter, an AND gate, and an OR gate.

8. A bridge inverter circuit, characterized in that, It includes a first driving circuit and a first half-bridge circuit. The structure of the first driving circuit is as described in any one of claims 1 to 7. The first half-bridge circuit includes a first switching transistor and a second switching transistor. The drain of the first switching transistor is connected to a DC power supply. The source of the first switching transistor and the drain of the second switching transistor are connected to form the output terminal of the first half-bridge circuit. The source of the second switching transistor is grounded. The output terminal of the first delay branch is connected to the gate of the first switching transistor, and the output terminal of the second delay branch is connected to the gate of the second switching transistor.

9. A bridge inverter circuit according to claim 8, characterized in that, It also includes a first transformer, the output terminals of the first delay branch and the second delay branch are respectively connected to the same-name terminal and the opposite-name terminal of the primary coil of the first transformer; the same-name terminal of the primary coil of the first transformer is connected to the gate of the first switching transistor, and the opposite-name terminal of the primary coil of the first transformer is connected to the output terminal of the first half-bridge circuit; the opposite-name terminal of the secondary coil of the first transformer is connected to the gate of the second switching transistor, and the same-name terminal of the secondary coil is grounded.

10. A bridge inverter circuit according to claim 8, characterized in that, The number of first half-bridge circuits is multiple and they are configured in parallel, and the output terminals of each first half-bridge circuit are connected to a resonant filter circuit.

11. A bridge inverter circuit according to claim 10, characterized in that, There are multiple first driving circuits, which are configured in pairs with the first half-bridge circuit, and each first driving circuit receives the same input signal.

12. A bridge inverter circuit according to claim 10, characterized in that, It also includes a switching module, which is selectively configured at some or all of the input or output terminals of the first drive circuit, so that the selected first drive circuit is enabled or disabled.

13. A bridge inverter circuit according to claim 8, characterized in that, It also includes a second half-bridge circuit and a second driving circuit, the architecture of which is the same as that of the driving circuit described in any one of claims 1 to 7; the second half-bridge circuit includes a third switch and a fourth switch; the drain of the third switch is connected to a DC source; the source of the third switch and the drain of the fourth switch are connected to form the output terminal of the second half-bridge circuit; the source of the fourth switch is grounded; the output of the first delay branch of the second driving circuit is connected to the gate of the fourth switch, and the output of the second delay branch of the second driving circuit is connected to the gate of the third switch; the first driving circuit and the second driving circuit acquire input signals with opposite phase.

14. A bridge inverter circuit according to claim 13, characterized in that, It also includes a second transformer; the output terminals of the first delay branch and the second delay branch of the second drive circuit are respectively connected to the same-name terminal and the opposite-name terminal of the primary coil of the second transformer; the same-name terminal of the first primary coil of the second transformer is connected to the gate of the third switch, and the opposite-name terminal of the first primary coil of the second transformer is connected to the output terminal of the second half-bridge circuit; the opposite-name terminal of the second secondary coil of the second transformer is connected to the gate of the fourth switch, and the same-name terminal of the second secondary coil is grounded.

15. A bridge inverter circuit according to claim 9, characterized in that, It also includes a signal amplification module, which includes multiple signal amplifiers, two of which are a first signal amplifier and a second signal amplifier; the output of the AND gate of the first delay branch is connected to the input of the first signal amplifier through a resistor; the output of the AND gate of the second delay branch is connected to the input of the second signal amplifier through a resistor. The signal output terminals of the first signal amplifier and the second signal amplifier are respectively connected to the gates of the first and second switching transistors via the first transformer. The grounding terminal of the signal amplifier is grounded; the power supply terminal of the signal amplifier is connected to a DC power supply and a polarized capacitor is connected to ground.

16. A bridge inverter circuit according to claim 15, characterized in that, The signal amplification module also includes a filtering module, which includes four filtering capacitors. The first end of the four filtering capacitors is connected to the power supply terminal of the signal amplifier, and the second end is grounded.

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