A negative voltage output circuit, a radio frequency switch and a radio frequency chip

Abstract

The application relates to the technical field of radio frequency switches, and discloses a negative pressure output circuit, a radio frequency switch and a radio frequency chip, wherein the negative pressure output circuit comprises a negative pressure identification circuit, a negative pressure generation circuit and a negative pressure selection circuit; in use, the negative pressure identification circuit is arranged to detect whether external negative pressure input exists; if external negative pressure input exists, an enable signal is not input to the negative pressure generation circuit, so that the negative pressure generation circuit does not output internal negative pressure; finally, the negative pressure selection circuit is used to output negative pressure; when no external negative pressure input exists, the negative pressure identification circuit inputs the enable signal to the negative pressure generation circuit, so that the negative pressure generation circuit outputs internal negative pressure; then, the negative pressure selection circuit is used to output negative pressure; therefore, the application can be compatible with internal negative pressure output and can accept external negative pressure input.

Description

Technical Field

[0001] This invention relates to the field of radio frequency switch technology, specifically to a negative voltage output circuit, a radio frequency switch, and a radio frequency chip. Background Technology

[0002] Radio frequency (RF) switches are key components in RF front-end circuits, primarily responsible for switching RF signal paths. By multiplexing components across multiple RF links, system costs can be effectively reduced and the RF front-end architecture simplified.

[0003] During use, the noise introduced by the RF switch itself directly affects the overall receiving performance of the device, so it must be fully considered during the design phase. To meet the application requirements of mainstream RF communication systems, the noise floor of the RF switch typically needs to be controlled below -150 dBm / Hz.

[0004] Currently, the design of RF switch chips is mainly based on SOI (Silicon-on-Insulator) technology, and their functionality requires biasing using a negative voltage circuit. The application circuit diagram of a commonly used negative voltage circuit in existing RF switches is shown below. Figure 1 As shown, in Figure 1 In the circuit, the negative voltage circuit includes a voltage converter, an oscillator, and a negative voltage charge pump. The voltage converter is used to convert the voltage VDD into a bias voltage Vreg_ana. The oscillator outputs a clock CLK based on the bias voltage Vreg_ana. The negative voltage charge pump outputs a negative voltage Vneg_int based on the clock CLK. The drive circuit generates drive voltages Vg and Vb that are input to the RF switch branch based on the negative voltage Vneg_int and the control signal CTRL.

[0005] for Figure 1 The circuit, during normal operation, relies on the coordinated action of an oscillator and a negative charge pump. It cannot simultaneously handle externally input negative voltage. The oscillator and charge pump generate periodic high-low level switching during operation, resulting in periodic noise. This periodic noise severely degrades the receiving sensitivity of the entire RF front-end link, significantly negatively impacting system performance. Particularly noteworthy is that in low-frequency (down to 10MHz) narrowband (2.5kHz) communication systems, due to narrow bandwidth and weak anti-interference capabilities, the periodic noise introduced by the internal clock circuit becomes a core bottleneck restricting system sensitivity improvement, directly determining whether the system can meet the preset communication performance requirements. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the present invention provides a negative voltage output circuit, an RF switch and an RF chip. The technical problem to be solved is that the negative voltage circuit in the existing RF switch is not compatible with the external input negative voltage.

[0007] To solve the above technical problems, in a first aspect, the present invention provides the following technical solution: a negative pressure output circuit, comprising a negative pressure identification circuit, a negative pressure generation circuit, and a negative pressure selection circuit; both the negative pressure identification circuit and the negative pressure selection circuit include an external negative pressure input terminal, and the external negative pressure input terminal of the negative pressure identification circuit is electrically connected to the external negative pressure input terminal of the negative pressure selection circuit; the negative pressure selection circuit further includes an internal negative pressure input terminal;

[0008] The negative pressure recognition circuit stops inputting an enable signal to the negative pressure generating circuit when an external negative pressure is input to the external negative pressure input terminal, and inputs an enable signal to the negative pressure generating circuit when no external negative pressure is input to the external negative pressure input terminal. When an enable signal is input, the negative pressure generating circuit inputs an internal negative pressure to the internal negative pressure input terminal of the negative pressure selection circuit. The negative pressure selection circuit selects the external negative pressure for output when an external negative pressure is input, and selects the internal negative pressure for output when an internal negative pressure is input.

[0009] In one embodiment of the first aspect, the negative voltage identification circuit includes a resistor R1, a MOSFET P1, a MOSFET N1, an inverter INV1, and an inverter INV2; one end of the resistor R1 is used to input the operating voltage. The other end of the resistor R1 is electrically connected to the source of the MOS transistor P1 and the input of the inverter INV1, respectively. The gate of MOS transistor P1 and the gate of MOS transistor N1 are electrically connected for grounding; the drain of MOS transistor P1 and the drain of MOS transistor N1 are electrically connected, and the source of MOS transistor N1 is the external negative voltage input terminal of the negative voltage recognition circuit. The output terminal of inverter INV1 is electrically connected to the input terminal of inverter INV2, and the output terminal of inverter INV2 is used to output an enable signal.

[0010] In one embodiment of the first aspect, the negative pressure generating circuit includes an oscillator and a negative pressure charge pump; an enable signal is input to the oscillator, which inputs a clock signal to the negative pressure charge pump when the enable signal is input, and the negative pressure charge pump inputs an internal negative pressure to the negative pressure selection circuit based on the input clock signal.

[0011] In one embodiment of the first aspect, the internal negative pressure is -2.5V.

[0012] In one embodiment of the first aspect, the negative voltage selection circuit includes MOSFET N2 and MOSFET N3. The drain of MOSFET N2 is the internal negative voltage input terminal and is also electrically connected to the gate of MOSFET N3. The source of MOSFET N2 is electrically connected to the source of MOSFET N3 for outputting negative voltage. The drain of MOSFET N3 is the external negative voltage input terminal and is electrically connected to the gate of MOSFET N2.

[0013] In one embodiment of the first aspect, a voltage converter is also included, which is used to convert the input power supply voltage into an operating voltage input to the negative voltage identification circuit and the negative voltage generation circuit.

[0014] Secondly, the present invention also provides a radio frequency switch, including the aforementioned negative voltage output circuit, and further including a driving circuit and a switching circuit. The negative voltage output by the negative voltage selection circuit is input to the driving circuit, and the driving circuit inputs a driving voltage to the switching circuit based on the input negative voltage and a control signal.

[0015] In one embodiment of the second aspect, the switching circuit includes a first switching branch and a second switching branch, a first connection terminal of the first switching branch is electrically connected to a first connection terminal of the second switching branch, a second connection terminal of the first switching branch and a second connection terminal of the second switching branch are used to connect an antenna, and the driving voltage is input to the control terminal of the first switching branch and the control terminal of the second switching branch to control the on / off state of the first switching branch and the second switching branch.

[0016] Thirdly, the present invention also provides an RF chip, including a chip body, on which the aforementioned RF switch is provided. The chip body also includes an RFC pin, an RF1 pin, an RF2 pin, a VSS pin, a CTRL pin, and a VDD pin. The RFC pin is electrically connected to a first connection terminal of a first switch branch. The RF1 pin is electrically connected to a second connection terminal of the first switch branch. The RF2 pin is electrically connected to a second connection terminal of a second switch branch. The VSS pin is electrically connected to the external negative voltage input terminal of the negative voltage identification circuit and the external negative voltage input terminal of the negative voltage selection circuit, respectively. The CTRL pin is electrically connected to a driving circuit for inputting a control signal to the driving circuit. The VDD pin is electrically connected to a voltage converter for inputting a power supply voltage to the voltage converter.

[0017] In one embodiment of the third aspect, the RFC pin is located on the left side of the chip body, the RF1 pin is located on the upper side of the chip body, the RF2 pin is located on the lower side of the chip body, and the VSS pin, CTRL pin, and VDD pin are located on the right side of the chip body.

[0018] The advantages of this invention compared to existing technologies are as follows: This invention uses a negative pressure recognition circuit to detect whether there is an external negative pressure input. If there is an external negative pressure input, no enable signal is input to the negative pressure generating circuit, thus preventing the negative pressure generating circuit from outputting internal negative pressure. Finally, the negative pressure is output through the negative pressure selection circuit. When there is no external negative pressure input, the negative pressure recognition circuit inputs an enable signal to the negative pressure generating circuit, causing the negative pressure generating circuit to output internal negative pressure, which is then output through the negative pressure selection circuit. Therefore, this invention can accept both internal negative pressure output and external negative pressure input. Attached Figure Description

[0019] Figure 1 This is a schematic diagram illustrating the application of a negative voltage circuit in an existing radio frequency switch. Figure 2 This is a schematic diagram of the negative voltage output circuit in Example 1; Figure 3 for Figure 2 The circuit diagram of the negative pressure recognition circuit in the image; Figure 4 for Figure 2 The circuit diagram of the negative voltage selection circuit in the middle; Figure 5 This is a structural diagram of the radio frequency switch in Embodiment 2; Figure 6 This is a structural diagram of the radio frequency chip in Example 3. Detailed Implementation

[0020] The illustrative embodiments of this application include, but are not limited to, a negative voltage output circuit, an RF switch, and an RF chip.

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0022] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. Words such as “comprising” or “including” mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and does not exclude other elements or objects. Words such as “connected” or “linked” are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0023] Example 1 like Figure 2 As shown, in order to be compatible with external negative pressure input while being able to output negative pressure itself, this embodiment provides a negative pressure output circuit, including a negative pressure identification circuit 1, a negative pressure generation circuit 2, and a negative pressure selection circuit 3; both the negative pressure identification circuit 1 and the negative pressure selection circuit 3 include an external negative pressure input terminal, and the external negative pressure input terminal of the negative pressure identification circuit 1 is electrically connected to the external negative pressure input terminal of the negative pressure selection circuit 3; the negative pressure selection circuit 3 also includes an internal negative pressure input terminal; When an external negative pressure is input at the external negative pressure input terminal, the negative pressure recognition circuit 1 stops inputting the enable signal EN to the negative pressure generating circuit 2, and inputs the enable signal EN to the negative pressure generating circuit 2 when no external negative pressure is input at the external negative pressure input terminal. When the enable signal EN is input, the negative pressure generating circuit 2 inputs the internal negative pressure V2 to the internal negative pressure input terminal of the negative pressure selection circuit 3; The negative pressure selection circuit 3 selects the external negative pressure for output when an external negative pressure is input, and selects the internal negative pressure for output when an internal negative pressure V2 is input.

[0024] In practical use, this invention uses a negative pressure recognition circuit 1 to detect whether there is an external negative pressure input. If there is an external negative pressure input, the enable signal EN is not input to the negative pressure generating circuit 2, thus preventing the negative pressure generating circuit 2 from outputting the internal negative pressure. Finally, the negative pressure is output through the negative pressure selection circuit 3. When there is no external negative pressure input, the negative pressure recognition circuit 1 inputs an enable signal to the negative pressure generating circuit 2, causing the negative pressure generating circuit 2 to output the internal negative pressure V2. Then, the negative pressure is output through the negative pressure selection circuit 3. Therefore, this invention can be compatible with both internal negative pressure output and external negative pressure input, thereby meeting the diversified use of RF switches.

[0025] Specifically, in this embodiment, the circuit of the negative pressure recognition circuit 1 is as follows: Figure 3As shown, it includes resistor R1, MOSFET P1, MOSFET N1, inverter INV1 and inverter INV2; one end of resistor R1 is used to input the operating voltage V1; The other end of resistor R1 is electrically connected to the source of MOSFET P1 and the input of inverter INV1, respectively. The gates of MOSFET P1 and N1 are electrically connected for grounding; the drains of MOSFET P1 and N1 are electrically connected, and the source of MOSFET N1 is the external negative voltage input terminal of the negative voltage recognition circuit. The output terminal of inverter INV1 is electrically connected to the input terminal of inverter INV2, and the output terminal of inverter INV2 is used to output the enable signal EN.

[0026] In practical use, when the source of MOSFET N1 is floating or grounded, the input terminal of inverter INV1 is pulled up to the working voltage V1 through resistor R1. Therefore, a high-level signal is input to the input terminal of inverter INV1, which in turn causes the output terminal of inverter INV2 to output a high-level enable signal EN, ultimately causing the negative voltage generating circuit 2 to generate an internal negative voltage V2. When an external negative voltage is input to MOSFET N1, the input terminal of inverter INV1 is pulled down to the external negative voltage through MOSFET P1 and MOSFET N1. At this time, a low-level signal is input to the input terminal of inverter INV1, which in turn causes inverter INV2 to output a low-level signal, that is, there is no output enable signal EN. Therefore, the negative voltage generating circuit does not output the internal negative voltage V2.

[0027] Specifically, in this embodiment, in Figure 2 In the circuit, the negative pressure generating circuit 2 includes an oscillator 20 and a negative pressure charge pump 21; an enable signal EN is input to the oscillator 20, and the oscillator 20 inputs a clock signal CLK to the negative pressure charge pump 21 when the enable signal EN is input. The negative pressure charge pump 21 inputs an internal negative pressure V2 to the negative pressure selection circuit 3 based on the input clock signal CLK.

[0028] In addition, in this embodiment, the internal negative pressure V2 is -2.5V. In some implementations, the internal negative pressure V2 can also be set to other magnitudes according to actual needs.

[0029] Specifically, in this embodiment, the negative voltage selection circuit 3 includes MOSFET N2 and MOSFET N3. The drain of MOSFET N2 is the internal negative voltage input terminal and is also electrically connected to the gate of MOSFET N3. The source of MOSFET N2 is electrically connected to the source of MOSFET N3 for outputting negative voltage. The drain of MOSFET N3 is the external negative voltage input terminal and is electrically connected to the gate of MOSFET N2.

[0030] In actual use, when the external negative voltage is -2.5V and the internal negative voltage V2 is 0V, MOSFET N3 is turned on and MOSFET N2 is turned off. The negative voltage Vneg output by the negative voltage selection circuit 3 is the external negative voltage. When MOSFET N3 is grounded or floating, the internal negative voltage V2 output by negative voltage selection circuit 2 is -2.5V. At this time, MOSFET N2 is turned on and MOSFET N3 is turned off. The negative voltage Vneg output by negative voltage selection circuit 3 is the internal negative voltage V1.

[0031] Specifically, in this embodiment, as Figure 2 As shown, the present invention also includes a voltage converter 4, which is used to convert the input power supply voltage VDD into an operating voltage V1 input to the negative voltage identification circuit 1 and the negative voltage generation circuit 2.

[0032] Example 2 like Figure 5 As shown, this embodiment also provides a radio frequency switch, including the negative voltage output circuit in Embodiment 1, and further including a driving circuit 4 and a switching circuit 5. The negative voltage Vneg output by the negative voltage selection circuit 3 is input to the driving circuit 4, and the driving circuit 4 inputs a driving voltage to the switching circuit 5 based on the input negative voltage Vneg and the control signal CTRL.

[0033] Furthermore, in this embodiment, the switching circuit includes a first switching branch and a second switching branch. The first connection terminal of the first switching branch is electrically connected to the first connection terminal of the second switching branch. The second connection terminal of the first switching branch and the second connection terminal of the second switching branch are used to connect the antenna. The driving voltage is input to the control terminal of the first switching branch and the control terminal of the second switching branch to control the on / off state of the first switching branch and the second switching branch.

[0034] In practical use, the RF channel is selected by controlling the on / off state of the first and second switch branches.

[0035] Furthermore, since the control implementation of the drive circuit 4 and the switch circuit 5 is a prior art, it will not be described in detail here. Those skilled in the art can select whether the first or second switch branch is turned on based on the level of the control signal CTRL. For example, when the control signal CTRL is high, the first switch branch is turned on, and when the control signal CTRL is low, the second switch branch is turned on. Alternatively, the second switch branch can be turned on when the control signal CTRL is high, and the first switch branch can be turned on when the control signal CTRL is low.

[0036] Example 3 like Figure 6As shown, this embodiment also provides an RF chip, including a chip body 100. The chip body 100 is provided with the RF switch in Embodiment 2. The chip body is also provided with an RFC pin, an RF1 pin, an RF2 pin, a VSS pin, a CTRL pin, and a VDD pin. The RFC pin is electrically connected to the first connection terminal of the first switch branch; the RF1 pin is electrically connected to the second connection terminal of the first switch branch; the RF2 pin is electrically connected to the second connection terminal of the second switch branch; the VSS pin is electrically connected to the external negative voltage input terminal of the negative voltage identification circuit 1 and the external negative voltage input terminal of the negative voltage selection circuit 3, respectively; the CTRL pin is electrically connected to the driving circuit 5 and is used to input a control signal to the driving circuit 5; the VDD pin is electrically connected to the voltage converter 4 and is used to input the power supply voltage VDD to the voltage converter.

[0037] Furthermore, in this embodiment, the RFC pin is located on the left side of the chip body 100, the RF1 pin is located on the upper side of the chip body 100, the RF2 pin is located on the lower side of the chip body 100, and the VSS pin, CTRL pin, and VDD pin are located on the right side of the chip body 100.

[0038] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A negative voltage output circuit, characterized in that, It includes a negative pressure identification circuit, a negative pressure generation circuit, and a negative pressure selection circuit; both the negative pressure identification circuit and the negative pressure selection circuit include an external negative pressure input terminal, and the external negative pressure input terminal of the negative pressure identification circuit is electrically connected to the external negative pressure input terminal of the negative pressure selection circuit; the negative pressure selection circuit also includes an internal negative pressure input terminal; The negative pressure recognition circuit stops inputting an enable signal to the negative pressure generating circuit when an external negative pressure is input to the external negative pressure input terminal, and inputs an enable signal to the negative pressure generating circuit when no external negative pressure is input to the external negative pressure input terminal. When an enable signal is input, the negative pressure generating circuit inputs an internal negative pressure to the internal negative pressure input terminal of the negative pressure selection circuit. The negative pressure selection circuit selects the external negative pressure for output when an external negative pressure is input, and selects the internal negative pressure for output when an internal negative pressure is input.

2. The negative voltage output circuit according to claim 1, characterized in that, The negative voltage identification circuit includes a resistor R1, a MOSFET P1, a MOSFET N1, an inverter INV1, and an inverter INV2; one end of the resistor R1 is used to input the operating voltage. The other end of the resistor R1 is electrically connected to the source of the MOS transistor P1 and the input of the inverter INV1, respectively. The gate of MOS transistor P1 and the gate of MOS transistor N1 are electrically connected for grounding; the drain of MOS transistor P1 and the drain of MOS transistor N1 are electrically connected, and the source of MOS transistor N1 is the external negative voltage input terminal of the negative voltage recognition circuit. The output terminal of inverter INV1 is electrically connected to the input terminal of inverter INV2, and the output terminal of inverter INV2 is used to output an enable signal.

3. The negative voltage output circuit according to claim 1, characterized in that, The negative pressure generating circuit includes an oscillator and a negative pressure charge pump; the enable signal is input to the oscillator, and the oscillator inputs a clock signal to the negative pressure charge pump when the enable signal is input, and the negative pressure charge pump inputs internal negative pressure to the negative pressure selection circuit based on the input clock signal.

4. The negative voltage output circuit according to claim 3, characterized in that, The internal negative pressure is -2.5V.

5. A negative voltage output circuit according to claim 1, characterized in that, The negative voltage selection circuit includes MOSFET N2 and MOSFET N3. The drain of MOSFET N2 is the internal negative voltage input terminal and is also electrically connected to the gate of MOSFET N3. The source of MOSFET N2 is electrically connected to the source of MOSFET N3 for outputting negative voltage. The drain of MOSFET N3 is the external negative voltage input terminal and is electrically connected to the gate of MOSFET N2.

6. A negative voltage output circuit according to any one of claims 1-5, characterized in that, It also includes a voltage converter for converting the input power supply voltage into an operating voltage that is input to the negative voltage identification circuit and the negative voltage generation circuit.

7. A radio frequency switch, characterized in that, The negative pressure output circuit according to any one of claims 1-6 further includes a driving circuit and a switching circuit, wherein the negative pressure output by the negative pressure selection circuit is input to the driving circuit, and the driving circuit inputs a driving voltage to the switching circuit based on the input negative pressure and a control signal.

8. The radio frequency switch according to claim 7, characterized in that, The switching circuit includes a first switching branch and a second switching branch. The first connection terminal of the first switching branch is electrically connected to the first connection terminal of the second switching branch. The second connection terminals of the first and second switching branches are used to connect an antenna. The driving voltage is input to the control terminals of the first and second switching branches to control the on / off state of the first and second switching branches.

9. A radio frequency chip, characterized in that, The device includes a chip body, on which the radio frequency switch of claim 8 is provided. The chip body also includes an RFC pin, an RF1 pin, an RF2 pin, a VSS pin, a CTRL pin, and a VDD pin. The RFC pin is electrically connected to the first connection terminal of the first switch branch. The RF1 pin is electrically connected to the second connection terminal of the first switch branch. The RF2 pin is electrically connected to the second connection terminal of the second switch branch. The VSS pin is electrically connected to the external negative voltage input terminal of the negative voltage identification circuit and the external negative voltage input terminal of the negative voltage selection circuit, respectively. The CTRL pin is electrically connected to the drive circuit and is used to input a control signal to the drive circuit. The VDD pin is electrically connected to the voltage converter and is used to input a power supply voltage to the voltage converter.

10. The radio frequency chip according to claim 9, characterized in that, The RFC pin is located on the left side of the chip body, the RF1 pin is located on the upper side of the chip body, the RF2 pin is located on the lower side of the chip body, and the VSS pin, CTRL pin, and VDD pin are located on the right side of the chip body.

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