Linear voltage stabilizing circuit, linear voltage stabilizing chip and electronic device

Abstract

The application belongs to the field of electronic circuits and provides a linear voltage stabilizing circuit, a linear voltage stabilizing chip and an electronic device. The circuit comprises an error amplification module, a current following module, a driving module, a resistance module, a pull-down module, a first power tube, a second power tube and a third power tube. The application splits the power tube of a traditional LDO into three power tubes of different sizes to cope with different loads. Under no load, the first power tube is driven by the error amplification module, and the second power tube, the third power tube and the driving module are turned off to realize low static current; under light load and heavy load, the second power tube and the third power tube are driven by different driving voltages and turned on in turn to provide smooth and fast output current. The current following module is used to realize fast transient response. The gate capacitance of each power tube is smaller than that of the power tube in the traditional LDO, so the response speed of a single power tube is faster, and the response speed of the circuit to load transient changes can be further improved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a linear voltage regulator circuit, a linear voltage regulator chip, and an electronic device. Background Technology

[0002] An LDO (Low Dropout Regulator) is a widely used power management circuit that provides a stable output voltage from a high, unregulated input voltage with significant power supply noise. An LDO used for power supply needs to possess two characteristics: low power consumption in standby mode and fast response speed in operating mode. To achieve low quiescent current while maintaining fast transient response, several current scaling methods exist: one is an adaptive bias scheme, where the bias current is proportional to the load current; although this method achieves good slew rate and large loop bandwidth under heavy load, it still requires additional transient enhancement to handle the transition from light to heavy load due to the low bias current under light load. Another is a dynamic bias scheme, where the slew rate of the power transistor is enhanced only during transients; however, this method is only suitable for LDOs without external capacitors, where the dominant pole is determined by the gate-source capacitance of the power transistor. A third is a hybrid bias scheme, which allows the bias current to scale dynamically during transients and adaptively follow the load current; this scheme can increase bandwidth and has excellent slew rate even under heavy load, but its quiescent current is relatively large. Another approach is to shut down the core circuitry of the error amplifier and buffer under light load conditions. However, this approach increases the transient settling time, which is not suitable for LDOs that require fast transient response.

[0003] Therefore, there is an urgent need for a solution that can meet both the requirements of low quiescent current under no-load mode and rapid transient response from no-load to heavy-load mode. Summary of the Invention

[0004] This application provides a linear voltage regulator circuit, a linear voltage regulator chip, and an electronic device, which can solve the problem that traditional LDOs cannot simultaneously meet the requirements of low quiescent current in no-load mode and fast transient response from no-load to heavy-load.

[0005] In a first aspect, embodiments of this application provide a linear voltage regulator circuit, including an error amplification module, a current follower module, a driving module, a resistor module, a pull-down module, a first power transistor, a second power transistor, and a third power transistor. The first input terminal of the error amplification module is used to receive a reference voltage. The second input terminal of the error amplification module is connected to the sampling terminal of the resistor module. The tail current terminal of the error amplification module is connected to the output terminal of the current follower module. The output terminal of the error amplification module is connected to the input terminal of the current follower module, the gate of the first power transistor, and the input terminal of the driving module, respectively. The sources of the first power transistor, the second power transistor, and the third power transistor all receive... The power supply voltage is specified. The first output terminal of the driving module is connected to the gate of the second power transistor, and the second output terminal of the driving module is connected to the gate of the third power transistor. The drain of the first power transistor is connected to the drain of the second power transistor, the drain of the third power transistor, the first terminal of the resistor module, the first terminal of the pull-down module, the first terminal of the external capacitor, and the first terminal of the load. The second terminal of the pull-down module is connected to the body terminal of the first power transistor. The second terminals of the resistor module, the external capacitor, and the load are all grounded. The size of the first power transistor is smaller than that of the second power transistor, and the size of the second power transistor is smaller than that of the third power transistor. The resistor module is used to sample the output voltage of the linear regulator circuit and output a feedback voltage; the pull-down module is used to provide a pull-down voltage to the body terminal of the first power transistor; the error amplifier module is used to output an error voltage based on the feedback voltage, the reference voltage, and the bias current; the current follower module is used to output a bias current based on the error voltage. When the load current is less than the first threshold, the first power transistor turns on according to the error voltage and outputs the first current; the drive module turns off according to the error voltage, thereby turning off the second power transistor and the third power transistor. When the load current is greater than or equal to the first threshold and less than or equal to the second threshold, the first power transistor remains on and continuously outputs the first current; the driving module outputs a first driving voltage and a second driving voltage according to the error voltage, wherein the first driving voltage is less than the second driving voltage; the second power transistor turns on first according to the first driving voltage and outputs the second current; the third power transistor turns on later according to the second driving voltage and outputs the third current. When the load current is greater than the second threshold, the first power transistor remains in the on state and continuously outputs the first current; the first driving voltage and the second driving voltage begin to decrease and the rate of decrease of the first driving voltage is less than the rate of decrease of the second driving voltage, so that the third current is greater than the second current.

[0006] In one possible implementation of the first aspect, the pull-down module includes a fourth transistor, a fifth transistor, and a sixth transistor. The source of the fourth transistor receives a power supply voltage. The gate of the fourth transistor is connected to the drain of the fourth transistor, the drain of the sixth transistor, and the body of the first power transistor. The gates of the sixth transistor and the fifth transistor both receive a bias voltage. The drain of the fifth transistor is connected to the drain of the first power transistor, the drain of the second power transistor, the drain of the third power transistor, a first terminal of the resistor module, a first terminal of the external capacitor, and a first terminal of the load. The sources of the fifth transistor and the sixth transistor are both grounded.

[0007] In one possible implementation of the first aspect, the fourth transistor is a PMOS transistor, and the fifth and sixth transistors are NMOS transistors.

[0008] In one possible implementation of the first aspect, the driving module includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a first resistor, a second resistor, and a third resistor. The gate of the seventh transistor is connected to the output terminal of the error amplification module, the input terminal of the current follower module, and the gate of the first power transistor. The drain of the seventh transistor is connected to the drain of the eighth transistor, the gate of the eighth transistor, the gate of the ninth transistor, and the gate of the eleventh transistor. The source of the ninth transistor is connected to the first terminal of the first resistor. The drain of the ninth transistor is... The eleventh transistor is connected to the drain of the tenth transistor, the gate of the tenth transistor, the first terminal of the second resistor, and the gate of the second power transistor. The drain of the eleventh transistor is connected to the drain of the twelfth transistor, the gate of the twelfth transistor, the first terminal of the third resistor, and the gate of the third power transistor. The source of the tenth transistor, the second terminal of the second resistor, the source of the twelfth transistor, and the second terminal of the third resistor all receive power supply voltage. The source of the eighth transistor, the second terminal of the first resistor, and the source of the eleventh transistor are all grounded. The ninth transistor is larger than the eleventh transistor.

[0009] In one possible implementation of the first aspect, the current follower module includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The source of the thirteenth transistor receives a power supply voltage. The gate of the thirteenth transistor is connected to the output terminal of the error amplification module, the gate of the first power transistor, and the input terminal of the driving module, respectively. The drain of the thirteenth transistor is connected to the drain of the fourteenth transistor, the gate of the fourteenth transistor, and the gate of the fifteenth transistor, respectively. The drain of the fifteenth transistor is connected to the tail current terminal of the error amplification module. The sources of the fourteenth transistor and the fifteenth transistor are both grounded.

[0010] In one possible implementation of the first aspect, the thirteenth transistor is a PMOS transistor, and the fourteenth and fifteenth transistors are NMOS transistors.

[0011] In one possible implementation of the first aspect, the error amplification module includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor. The gate of the sixteenth transistor is connected to the sampling terminal of the resistor module. The gate of the seventeenth transistor is used to receive a reference voltage. The drain of the sixteenth transistor is connected to the drain of the eighteenth transistor, the gate of the eighteenth transistor, and the gate of the nineteenth transistor. The sources of the eighteenth transistor and the nineteenth transistor both receive a power supply voltage. The drain of the nineteenth transistor is connected to the drain of the seventeenth transistor, the gate of the first power transistor, the input terminal of the current follower module, and the input terminal of the drive module. The source of the sixteenth transistor is connected to the source of the seventeenth transistor, the drain of the twentieth transistor, and the output terminal of the current follower module. The gate of the twentieth transistor receives a bias voltage, and the source of the twentieth transistor is grounded.

[0012] In one possible implementation of the first aspect, the resistor module includes a fourth resistor and a fifth resistor. The first terminal of the fourth resistor is connected to the drain of the first power transistor, the drain of the second power transistor, the drain of the third power transistor, the first terminal of the external capacitor, the first terminal of the load, and the first terminal of the pull-down module. The second terminal of the fourth resistor is connected to the first terminal of the fifth resistor and the second input terminal of the error amplifier module. The second terminal of the fifth resistor is grounded.

[0013] Secondly, embodiments of this application provide a linear voltage regulator chip, including the linear voltage regulator circuit described in any one of the first aspects.

[0014] Thirdly, embodiments of this application provide an electronic device including the linear voltage regulator chip described in any one of the second aspects.

[0015] The beneficial effects of the embodiments of this application compared with the prior art are: This application provides a linear voltage regulator circuit, including an error amplification module, a current follower module, a driver module, a resistor module, a pull-down module, a first power transistor, a second power transistor, and a third power transistor. The first input terminal of the error amplification module is used to receive a reference voltage. The second input terminal of the error amplification module is connected to the sampling terminal of the resistor module. The tail current terminal of the error amplification module is connected to the output terminal of the current follower module. The output terminal of the error amplification module is connected to the input terminal of the current follower module, the gate of the first power transistor, and the input terminal of the driver module. The sources of the first, second, and third power transistors all receive the power supply voltage. The first output terminal of the driver module is connected to the gate of the second power transistor, and the second output terminal of the driver module is connected to the gate of the third power transistor. The drain of the first power transistor is connected to the drain of the second and third power transistors, the first terminal of the resistor module, the first terminal of the pull-down module, the first terminal of the external capacitor, and the first terminal of the load. The second terminal of the pull-down module is connected to the body terminal of the first power transistor. The second terminals of the resistor module, the external capacitor, and the load are all grounded. The size of the first power transistor is smaller than that of the second power transistor, and the size of the second power transistor is smaller than that of the third power transistor.

[0016] The resistor module samples the output voltage of the linear regulator circuit and outputs a feedback voltage. The pull-down module provides a pull-down voltage to the body of the first power transistor, ensuring that the first power transistor conducts before the second and third power transistors when the linear regulator circuit is in no-load mode. The error amplifier module outputs an error voltage based on the feedback voltage, reference voltage, and bias current. The current follower module outputs a bias current based on the error voltage to dynamically adjust its output bias current during load transients, thereby accelerating the response speed of the error amplifier module.

[0017] When the load current is less than the first threshold, the linear regulator circuit is in no-load mode. At this time, the first power transistor turns on based on the error voltage and outputs the first current. The drive module turns off based on the error voltage, thereby turning off the second and third power transistors. That is, the smallest power transistor, the first one, turns on first in no-load mode, and the first current dominates, while the second and third power transistors and the drive module are off to maintain a low quiescent current and reduce circuit power consumption in no-load mode.

[0018] When the load current is greater than or equal to the first threshold and less than or equal to the second threshold, the linear regulator circuit is in light-load mode. In this mode, the first power transistor remains on, continuously outputting the first current. The drive module outputs a first drive voltage and a second drive voltage based on the error voltage, with the first drive voltage being less than the second drive voltage. The second power transistor turns on first based on the first drive voltage and outputs the second current. The third power transistor turns on later based on the second drive voltage and outputs the third current. That is, in light-load mode, the second current dominates.

[0019] When the load current exceeds the second threshold, the linear regulator circuit is in heavy-load mode. In this mode, the first power transistor remains on, continuously outputting the first current. The first and second drive voltages begin to decrease, and the rate of decrease of the first drive voltage is less than that of the second drive voltage, causing the third current to exceed the second current. That is, in heavy-load mode, the third current dominates.

[0020] The linear regulator circuit provided in this application splits the power transistors in a traditional LDO into three power transistors of different sizes to cope with different load conditions. In no-load mode, the smallest power transistor is directly driven by the error amplifier module, while the second and third power transistors and the driver module are in the off state to achieve low quiescent current and thus reduce circuit power consumption. In light-load and heavy-load modes, the medium-sized second power transistor and the largest third power transistor are driven by different drive voltages, causing the second and third power transistors to conduct sequentially to provide a smooth and fast output current. A current follower module is also used to achieve fast transient response. Furthermore, this application splits the power transistors in a traditional LDO into three power transistors of different sizes, and the gate capacitance of each power transistor is smaller than that of the power transistors in a traditional LDO. Therefore, the response speed of a single power transistor is faster, which can further improve the circuit's response speed to transient load changes.

[0021] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a linear voltage regulator circuit provided in an embodiment of this application; Figure 2This is a circuit diagram of a linear voltage regulator circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram showing the relationship between the current of each power transistor and the load current in a linear voltage regulator circuit provided in an embodiment of this application.

[0024] In the diagram: 10, Error Amplification Module; 20, Current Follower Module; 30, Driver Module; 40, Resistor Module; 50, Pull-down Module. Detailed Implementation

[0025] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0026] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0027] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0028] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0029] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0031] To address the issue that traditional LDOs cannot simultaneously meet the requirements of low quiescent current in no-load mode and fast transient response from no-load to heavy-load, this application provides a linear regulator circuit that splits the power transistors in a traditional LDO into three power transistors of different sizes to handle different load conditions. In no-load mode, the smallest power transistor is directly driven by the error amplifier module, while the second and third power transistors and the driver module are in the off state to achieve low quiescent current and thus reduce circuit power consumption. In light-load and heavy-load modes, the medium-sized second power transistor and the largest third power transistor are driven by different drive voltages, causing the second and third power transistors to conduct sequentially to provide a smooth and fast output current. A current follower module is also used to achieve a fast transient response. Furthermore, by splitting the power transistors in a traditional LDO into three power transistors of different sizes, the gate capacitance of each power transistor is smaller than that of the power transistors in a traditional LDO, resulting in a faster response speed for each individual power transistor and further improving the circuit's response speed to transient load changes.

[0032] In summary, the linear regulator circuit provided in this application solves the problem that traditional LDOs cannot simultaneously meet the requirements of low quiescent current in no-load mode and fast transient response from no-load to heavy-load.

[0033] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0034] Figure 1 A schematic diagram of a linear voltage regulator circuit according to an embodiment of this application is shown. Figure 1 As shown, the linear voltage regulator circuit includes an error amplifier module 10, a current follower module 20, a driver module 30, a resistor module 40, a pull-down module 50, a first power transistor M1, a second power transistor M2, and a third power transistor M3. The first input terminal of the error amplifier module 10 is used to receive the reference voltage V. REFThe second input terminal of the error amplifier module 10 is connected to the sampling terminal of the resistor module 40, and the tail current terminal of the error amplifier module 10 is connected to the output terminal of the current follower module 20. The output terminal of the error amplifier module 10 is connected to the input terminal of the current follower module 20, the gate of the first power transistor M1, and the input terminal of the drive module 30, respectively. The sources of the first power transistor M1, the second power transistor M2, and the third power transistor M3 all receive the power supply voltage V. CC The first output terminal of the drive module 30 is connected to the gate of the second power transistor M2, and the second output terminal of the drive module 30 is connected to the gate of the third power transistor M3. The drain of the first power transistor M1 is connected to the drain of the second power transistor M2, the drain of the third power transistor M3, the first terminal of the resistor module 40, the first terminal of the pull-down module 50, and the external capacitor C. L The first terminal of the pull-down module 50 is connected to the first terminal of the load LOAD, the second terminal of the pull-down module 50 is connected to the body terminal of the first power transistor M1, and the second terminal of the resistor module 40 and the external capacitor C are connected. L Both the second terminal of the transistor and the second terminal of the load LOAD are grounded. The size of the first power transistor M1 is smaller than that of the second power transistor M2, and the size of the second power transistor M2 is smaller than that of the third power transistor M3.

[0035] Specifically, resistor module 40 is used to regulate the output voltage V of the linear voltage regulator circuit. OUT Sample the voltage and output the feedback voltage V. FB The pull-down module 50 provides a pull-down voltage to the body terminal of the first power transistor M1, ensuring that the first power transistor M1 can conduct before the second power transistor M2 and the third power transistor M3 when the linear regulator circuit is in no-load mode. The error amplifier module 10 is used to amplify the voltage based on the feedback voltage V. FB Reference voltage V REF and bias current output error voltage V EA The current follower module 20 is used to follow the error voltage V. EA The output bias current (which is a dynamic bias current) is used to dynamically adjust the output bias current when the load load changes transiently, thereby speeding up the response speed of the error amplification module 10.

[0036] When the load current I LOAD When the voltage is less than the first threshold, it indicates that the linear regulator circuit is in no-load mode. At this time, the first power transistor M1 operates according to the error voltage V. EA Turn on and output the first current I. M1 The drive module 30 operates based on the error voltage V. EA The first power transistor M1, being the smallest, is turned on first in no-load mode, causing the second power transistor M2 and the third power transistor M3 to turn off as well. This means the first power transistor M1, being the smallest in size, is turned on first, with the first current I... M1The first power transistor (M2) dominates the current supply, while the second power transistor (M2), the third power transistor (M3), and the drive module 30 are in the off state to maintain a low quiescent current in no-load mode and reduce circuit power consumption. In this embodiment, the first threshold is approximately 100 nA.

[0037] When the load current I LOAD When the voltage is greater than or equal to the first threshold and less than or equal to the second threshold, it indicates that the linear regulator circuit is in light-load mode. At this time, the first power transistor M1 remains on and continuously outputs the first current I. M1 Compared to the no-load mode, the load current I in the light-load mode is... LOAD Increase, causing the error voltage V EA The voltage decreases, at which point the drive module 30 adjusts the voltage according to the error voltage V. EA The system outputs a first drive voltage and a second drive voltage. The first drive voltage is less than the second drive voltage. Therefore, the second power transistor M2 turns on first based on the first drive voltage and outputs a second current I. M2 The third power transistor M3 turns on after receiving the second drive voltage and outputs the third current I. M3 That is, in light load mode, the second current I M2 Dominant. In this embodiment, the second threshold is approximately 10 mA.

[0038] When the load current I LOAD When the current exceeds the second threshold, it indicates that the linear regulator circuit is in heavy-load mode. At this time, the first power transistor M1 remains on and continuously outputs the first current I. M1 Compared to light load mode, the load current I under heavy load mode is... LOAD It becomes larger, causing the error voltage V to... EA As the voltage decreases further, the first and second driving voltages begin to drop, and the rate of decrease of the first driving voltage is less than the rate of decrease of the second driving voltage, causing the third current I... M3 Greater than the second current I M2 That is, in heavy load mode, the third current I M3 Dominant.

[0039] The linear regulator circuit provided in this application splits the power transistors in a traditional LDO into three power transistors of different sizes to cope with different load conditions. In no-load mode, the smallest power transistor, M1, is directly driven by the error amplifier module 10, while the second power transistor, M2, the third power transistor, M3, and the drive module 30 are in the off state to achieve low quiescent current and thus reduce circuit power consumption. In light-load and heavy-load modes, the medium-sized second power transistor, M2, and the largest power transistor, M3, are driven by different drive voltages, causing the second power transistor, M2, and the third power transistor, M3, to conduct sequentially to provide a smooth and fast output current. Simultaneously, a current follower module 20 is used to achieve a fast transient response. Furthermore, this application splits the power transistors in a traditional LDO into three power transistors of different sizes, each with a smaller gate capacitance than the power transistors in a traditional LDO. Therefore, the response speed of a single power transistor is faster, further improving the circuit's response speed to transient load changes.

[0040] In one embodiment of this application, such as Figure 2 As shown, the pull-down module 50 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The source of the fourth transistor M4 receives the power supply voltage V. CC The gate of the fourth transistor M4 is connected to the drain of the fourth transistor M4, the drain of the sixth transistor M6, and the body of the first power transistor M1, respectively. The gates of the sixth transistor M6 and the fifth transistor M5 both receive a bias voltage V. BN The drain of the fifth transistor M5 is connected to the drain of the first power transistor M1, the drain of the second power transistor M2, the drain of the third power transistor M3, the first terminal of the resistor module 40, and the external capacitor C, respectively. L The first terminal of the transistor is connected to the first terminal of the load LOAD, and the source of the fifth transistor M5 and the source of the sixth transistor M6 are both grounded. In this embodiment, the fourth transistor M4 is a PMOS transistor, and the fifth transistor M5 and the sixth transistor M6 are NMOS transistors.

[0041] Specifically, to ensure that the first power transistor M1 can conduct before the second and third power transistors M2 and M3 under no-load conditions, the body terminal potential of the first power transistor M1 is pulled low through a fourth transistor M4 connected in a diode configuration, providing a pull-down voltage to the body terminal potential of the first power transistor M1, thereby reducing the threshold voltage of the first power transistor M1. The threshold voltage of the first power transistor M1 can be adjusted by the current flowing through the fourth transistor M4. It should be noted that the value of the pull-down voltage should ensure that it can reduce the threshold voltage of the first power transistor M1, while preventing the PN junction between the source and body terminals of the first power transistor M1 from conducting.

[0042] In one embodiment of this application, such as Figure 2As shown, the drive module 30 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. 10 11th transistor M 11 Twelfth transistor M 12 The first resistor R1, the second resistor R2, and the third resistor R3, and the gate of the seventh transistor M7 are respectively connected to the output terminal of the error amplifier module 10, the input terminal of the current follower module 20, and the gate of the first power transistor M1. The drain of the seventh transistor M7 is respectively connected to the drain of the eighth transistor M8, the gate of the eighth transistor M8, the gate of the ninth transistor M9, and the gate of the eleventh transistor M1. 11 The gate of the ninth transistor M9 is connected to the first terminal of the first resistor R1, and the drain of the ninth transistor M9 is connected to the tenth transistor M1. 10 The drain of the tenth transistor M 10 The gate of the eleventh transistor M2 is connected to the first terminal of the second resistor R2 and the gate of the second power transistor M2. 11 The drains of the transistors are respectively connected to the twelfth transistor M. 12 The drain of the twelfth transistor M 12 The gate of the third transistor M3, the first terminal of the third resistor R3, and the gate of the third power transistor M3 are connected. The tenth transistor M... 10 The source of the transistor, the second terminal of the second resistor R2, and the twelfth transistor M. 12 The source and the second terminal of the third resistor R3 both receive the power supply voltage V. CC The source of the eighth transistor M8, the second terminal of the first resistor R1, and the eleventh transistor M 11 The sources of all transistors are grounded; among them, the ninth transistor M9 is larger than the eleventh transistor M. 11 The size.

[0043] Specifically, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M 10 The first unity-gain buffer Buffer1 forms the second power transistor M2. The current flowing through the seventh transistor M7 passes through the eighth transistor M8, the ninth transistor M9, and the tenth transistor M1 in the current amplifier. 10 Amplified, and finally injected into the gate of the second power transistor M2, due to I M2 The current flows through the tenth transistor M 10 Current I M10 The buffer is derived from a mirror image, thus allowing for adaptive bias current adjustment to accelerate response speed under load transients. The second resistor R2 reduces the equivalent impedance of the gate of the second power transistor M2 and pushes the gate pole above the unity-gain bandwidth frequency, achieving better loop stability under light load conditions. The seventh transistor M7, the eighth transistor M8, and the eleventh transistor M... 11Twelfth transistor M 12 The second unity-gain buffer Buffer2, which forms the third power transistor M3, allows the current flowing through the seventh transistor M7 to pass through the eighth transistor M8 and the eleventh transistor M1 in the current amplifier. 11 and the twelfth transistor M 12 Amplified, and finally injected into the gate of the third power transistor M3, due to I M3 The current flows through the twelfth transistor M 12 Current I M12 Because it is mirrored, this buffer can be adaptively adjusted by the bias current, thereby accelerating the response speed under load transients. The third resistor R3 is used to reduce the equivalent impedance of the gate of the third power transistor M3 and push the gate pole above the unity-gain bandwidth frequency to achieve better loop stability under light load conditions. The drive capability of the first unity-gain buffer Buffer1 differs from that of the second unity-gain buffer Buffer2.

[0044] In light-load mode, compared to no-load mode, the load current I in light-load mode is... LOAD Increase, causing the error voltage V EA When the current decreases, the seventh transistor M7 turns on, and the current flowing through the seventh transistor M7 is mirrored to the ninth transistor M9 and the eleventh transistor M1. 11 Because the size of the ninth transistor M9 is larger than that of the eleventh transistor M... 11 The size of the transistor is such that the current flowing through the ninth transistor M9 is greater than that through the eleventh transistor M1. 11 The current is such that the first driving voltage is less than the second driving voltage, thus enabling the second power transistor M2 to conduct first, followed by the third power transistor M3. That is, in light load mode, the second power transistor M2 is the main power transistor supplied.

[0045] A first resistor R1 (i.e., the source degradation resistor) is set between the first unity-gain buffer Buffer1 and ground. As the load current I... LOAD The increase, i.e., when switching from light load to heavy load, is due to the error voltage V. EA If the first resistor R1 is further reduced, the rate at which the gate voltage (i.e., the first drive voltage) of the second power transistor M2 decreases will be less than the rate at which the gate voltage (i.e., the second drive voltage) of the third power transistor M3 decreases. This reduces the driving capability of the first unity-gain buffer Buffer1, so that the third power transistor M3 becomes the main power supply transistor under heavy load. Therefore, the first resistor R1 needs to be carefully selected according to transient requirements.

[0046] From the perspective of transient enhancement, the second power transistor M2 and the third power transistor M3 are driven in segments. The second power transistor M2 and the first unity-gain buffer Buffer1 are called the fast channel, and the third power transistor M3 and the second unity-gain buffer Buffer are called the slow channel. Assume that the size ratios of the second power transistor M2 and the third power transistor M3 relative to the overall power transistor (i.e., the combination of the second power transistor M2 and the third power transistor M3) are n and 1-n, respectively. Since the size of the first power transistor M1 is very small, it is omitted. The strength ratios (i.e., the driving capability ratios) of the first unity-gain buffer Buffer1 and the second unity-gain buffer Buffer2 relative to the overall buffer (i.e., the combination of Buffer1 and Buffer2) are k and 1-k, respectively, where n and k are constants, taking values ​​greater than zero and less than one. Therefore, the input capacitors C2 and C3 of the second power transistor M2 and the third power transistor M3, and the output resistance R of the first unity-gain buffer Buffer1 are... B2 The output resistance R of the second unity gain buffer Buffer2 B3 It can be represented as: , , , , where C g and R B These are the input capacitor of the overall power transistor and the output resistor of the overall buffer, respectively.

[0047] In the fast channel, the strength of the first unity-gain buffer Buffer1 is not proportional to the size of the second power transistor M2 it drives; the strength of the first unity-gain buffer Buffer1 is larger than the size of the second power transistor M2 it drives, and this buffer is designed as follows: .

[0048] Therefore, the time constant τ of the fast channel is obtained. M2 (τ M2 =R B ×C g ×n / k), compared to the time constant τ of the unsplit overall power transistor scheme. C (τ C =R B ×C g Smaller. This means that when the load undergoes transient changes, the fast path in this application reacts faster than conventional solutions and provides output current earlier, resulting in smaller output jumps.

[0049] In one embodiment of this application, such as Figure 2 As shown, the current follower module 20 includes a thirteenth transistor M. 13 Fourteenth transistor M 14and the fifteenth transistor M 15 The thirteenth transistor M 13 The source receives the power supply voltage V CC The thirteenth transistor M 13 The gates of the transistors are connected to the output of the error amplifier module 10, the gate of the first power transistor M1, and the input of the drive module 30, respectively. The thirteenth transistor M... 13 The drains of the fourteenth transistor M are respectively connected to the drain of the fourteenth transistor M. 14 The drain of the fourteenth transistor M 14 The gate and the fifteenth transistor M 15 The gate connection of the fifteenth transistor M 15 The drain of the transistor is connected to the tail current terminal of the error amplifier module 10, and the fourteenth transistor M... 14 The source and the fifteenth transistor M 15 The sources of all transistors are grounded. In this embodiment, the thirteenth transistor M... 13 It is a PMOS transistor, the fourteenth transistor M. 14 and the fifteenth transistor M 15 It is an NMOS transistor.

[0050] Specifically, it employs a thirteenth transistor M 13 Fourteenth transistor M 14 and the fifteenth transistor M 15 The current source that is configured to follow the output load current I at any time can follow the output load current I. LOAD This is to enhance the transient response of the circuit.

[0051] In one embodiment of this application, the error amplification module 10 includes a sixteenth transistor M. 16 The seventeenth transistor M 17 The eighteenth transistor M 18 The nineteenth transistor M 19 Twentieth transistor M 20 The sixteenth transistor M 16 The gate of the transistor is connected to the sampling terminal of the resistor module 40, and the seventeenth transistor M... 17 The gate is used to receive the reference voltage V. REF The sixteenth transistor M 16 The drains of the transistors are respectively connected to the eighteenth transistor M. 18 The drain of the eighteenth transistor M 18 The gate and the nineteenth transistor M 19 The gate connection of the eighteenth transistor M 18 The source and the nineteenth transistor M 19 The source terminals all receive the power supply voltage V. CC The nineteenth transistor M 19 The drains of the transistors are respectively connected to the seventeenth transistor M. 17The drain of the transistor, the gate of the first power transistor M1, the input terminal of the current follower module 20, and the input terminal of the drive module 30 are connected. The sixteenth transistor M... 16 The source of each transistor is connected to the seventeenth transistor M. 17 The source of the twentieth transistor M 20 The drain of the transistor is connected to the output of the current follower module 20, and the twentieth transistor M is connected to the output of the current follower module 20. 20 Gate receive bias voltage V BN The twentieth transistor M 20 The source electrode is grounded.

[0052] Specifically, the error amplification module 10 adopts a common-source structure, and the differential input pair is controlled by the sixteenth transistor M. 16 and the seventeenth transistor M 17 The tail current of the error amplification module 10 is composed of a fixed bias current I. M20 (i.e., current flows through the twentieth transistor M) 20 (current) and dynamic bias current I M15 (i.e., current flows through the fifteenth transistor M) 15 The error voltage V output by the error amplifier module 10 during the load current transition is composed of the current. EA With load current I LOAD The dynamic bias current I increases and decreases. M15 Then, depending on the load current I LOAD Increase the speed of the error amplification module 10 to accelerate its response.

[0053] In one embodiment of this application, such as Figure 2 As shown, the resistor module 40 includes a fourth resistor R4 and a fifth resistor R5. The first terminal of the fourth resistor R4 is connected to the drain of the first power transistor M1, the drain of the second power transistor M2, the drain of the third power transistor M3, and the external capacitor C. L The first terminal of the first resistor R4 is connected to the first terminal of the load LOAD and the first terminal of the pull-down module 50. The second terminal of the fourth resistor R4 is connected to the first terminal of the fifth resistor R5 and the second input terminal of the error amplifier module 10, respectively. The second terminal of the fifth resistor R5 is grounded.

[0054] Specifically, the resistor divider network consisting of the fourth resistor R4 and the fifth resistor R5 is used to divide the output voltage V. OUT Voltage divider sampling is performed, and a feedback voltage V is output to the second input terminal of the error amplification module 10. FB This causes the error amplification module 10 to adjust according to the feedback voltage V. FB Perform a loop response.

[0055] Figure 3 The diagram shows the current of each power transistor as a function of the load current I. LOAD The changing relationship. For example... Figure 3As shown, the current of the three power transistors is continuous, and each power transistor operates at a different load current I. LOAD The range dominates. Initially, when the load current I... LOAD When the current is below the first threshold (i.e., the light load threshold, approximately 100 nA), the first current I M1 The dominant current; once the load current I LOAD Exceeding the second threshold (i.e., the overload threshold, approximately 10 mA), the third current I... M3 The dominant current is the second current I between the first and second thresholds. M2 The dominant current is 600 ohms. These power transistors operate smoothly and continuously, eliminating the need for complex current sensing circuits and significantly reducing the circuit's quiescent current.

[0056] In summary, the linear regulator circuit provided in this application divides the power transistors in a traditional LDO into three power transistors of different sizes to handle different loads. In no-load mode, the smallest power transistor M1 is directly driven by the error amplifier module 10 to achieve low quiescent current. In light-load and heavy-load modes, the medium-sized second power transistor M2 and the largest power transistor M3 are driven by buffers with different drive capabilities, combined with the current follower module 20 to achieve fast transient response. Furthermore, this application does not require changes to the external circuitry and does not significantly increase the circuit size and complexity of the chip.

[0057] This application also provides a linear voltage regulator chip, including the linear voltage regulator circuit described above. Since the linear voltage regulator chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0058] This application also provides an electronic device, including the linear voltage regulator chip described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon further here.

[0059] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0060] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A linear voltage regulator circuit, characterized in that, The system includes an error amplification module, a current follower module, a driver module, a resistor module, a pull-down module, a first power transistor, a second power transistor, and a third power transistor. The first input terminal of the error amplification module receives a reference voltage. The second input terminal of the error amplification module is connected to the sampling terminal of the resistor module. The tail current terminal of the error amplification module is connected to the output terminal of the current follower module. The output terminal of the error amplification module is connected to the input terminal of the current follower module, the gate of the first power transistor, and the input terminal of the driver module. The sources of the first, second, and third power transistors all receive a power supply voltage. The driver module... The first output terminal of the first power transistor is connected to the gate of the second power transistor, and the second output terminal of the driving module is connected to the gate of the third power transistor. The drain of the first power transistor is connected to the drain of the second power transistor, the drain of the third power transistor, the first terminal of the resistor module, the first terminal of the pull-down module, the first terminal of the external capacitor, and the first terminal of the load. The second terminal of the pull-down module is connected to the body terminal of the first power transistor. The second terminal of the resistor module, the second terminal of the external capacitor, and the second terminal of the load are all grounded. The size of the first power transistor is smaller than that of the second power transistor, and the size of the second power transistor is smaller than that of the third power transistor. The resistor module is used to sample the output voltage of the linear regulator circuit and output a feedback voltage; the pull-down module is used to provide a pull-down voltage to the body terminal of the first power transistor; the error amplifier module is used to output an error voltage based on the feedback voltage, the reference voltage, and the bias current; the current follower module is used to output a bias current based on the error voltage. When the load current is less than the first threshold, the first power transistor turns on according to the error voltage and outputs the first current; the drive module turns off according to the error voltage, thereby turning off the second power transistor and the third power transistor. When the load current is greater than or equal to the first threshold and less than or equal to the second threshold, the first power transistor remains on and continuously outputs the first current; the driving module outputs a first driving voltage and a second driving voltage according to the error voltage, wherein the first driving voltage is less than the second driving voltage; the second power transistor turns on first according to the first driving voltage and outputs the second current; the third power transistor turns on later according to the second driving voltage and outputs the third current. When the load current is greater than the second threshold, the first power transistor remains in the on state and continuously outputs the first current; the first driving voltage and the second driving voltage begin to decrease and the rate of decrease of the first driving voltage is less than the rate of decrease of the second driving voltage, so that the third current is greater than the second current.

2. The linear voltage regulator circuit according to claim 1, characterized in that, The pull-down module includes a fourth transistor, a fifth transistor, and a sixth transistor. The source of the fourth transistor receives a power supply voltage. The gate of the fourth transistor is connected to the drain of the fourth transistor, the drain of the sixth transistor, and the body of the first power transistor. The gates of the sixth transistor and the fifth transistor both receive a bias voltage. The drain of the fifth transistor is connected to the drain of the first power transistor, the drain of the second power transistor, the drain of the third power transistor, the first terminal of the resistor module, the first terminal of the external capacitor, and the first terminal of the load. The sources of the fifth transistor and the sixth transistor are both grounded.

3. The linear voltage regulator circuit according to claim 2, characterized in that, The fourth transistor is a PMOS transistor, and the fifth and sixth transistors are NMOS transistors.

4. The linear voltage regulator circuit according to any one of claims 1 to 3, characterized in that, The driving module includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a first resistor, a second resistor, and a third resistor. The gate of the seventh transistor is connected to the output terminal of the error amplification module, the input terminal of the current follower module, and the gate of the first power transistor. The drain of the seventh transistor is connected to the drain, gate, ninth, and eleventh transistors. The source of the ninth transistor is connected to the first terminal of the first resistor. The drain of the ninth transistor is connected to the drain, gate, second terminal of the second resistor, and gate of the second power transistor. The drain of the eleventh transistor is connected to the drain, gate, first terminal of the third resistor, and gate of the third power transistor. The source of the tenth transistor, the second terminal of the second resistor, the source of the twelfth transistor, and the second terminal of the third resistor all receive a power supply voltage. The source of the eighth transistor, the second terminal of the first resistor, and the source of the eleventh transistor are all grounded. The ninth transistor is larger than the eleventh transistor.

5. The linear voltage regulator circuit according to any one of claims 1 to 3, characterized in that, The current follower module includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The source of the thirteenth transistor receives the power supply voltage. The gate of the thirteenth transistor is connected to the output terminal of the error amplification module, the gate of the first power transistor, and the input terminal of the driving module. The drain of the thirteenth transistor is connected to the drain of the fourteenth transistor, the gate of the fourteenth transistor, and the gate of the fifteenth transistor. The drain of the fifteenth transistor is connected to the tail current terminal of the error amplification module. The sources of the fourteenth transistor and the fifteenth transistor are both grounded.

6. The linear voltage regulator circuit according to claim 5, characterized in that, The thirteenth transistor is a PMOS transistor, and the fourteenth and fifteenth transistors are NMOS transistors.

7. The linear voltage regulator circuit according to any one of claims 1 to 3, characterized in that, The error amplification module includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor. The gate of the sixteenth transistor is connected to the sampling terminal of the resistor module. The gate of the seventeenth transistor is used to receive a reference voltage. The drain of the sixteenth transistor is connected to the drain of the eighteenth transistor, the gate of the eighteenth transistor, and the gate of the nineteenth transistor. The sources of the eighteenth transistor and the nineteenth transistor both receive power supply voltage. The drain of the nineteenth transistor is connected to the drain of the seventeenth transistor, the gate of the first power transistor, the input terminal of the current follower module, and the input terminal of the drive module. The source of the sixteenth transistor is connected to the source of the seventeenth transistor, the drain of the twentieth transistor, and the output terminal of the current follower module. The gate of the twentieth transistor receives a bias voltage, and the source of the twentieth transistor is grounded.

8. The linear voltage regulator circuit according to any one of claims 1 to 3, characterized in that, The resistor module includes a fourth resistor and a fifth resistor. The first end of the fourth resistor is connected to the drain of the first power transistor, the drain of the second power transistor, the drain of the third power transistor, the first end of the external capacitor, the first end of the load, and the first end of the pull-down module. The second end of the fourth resistor is connected to the first end of the fifth resistor and the second input end of the error amplifier module. The second end of the fifth resistor is grounded.

9. A linear voltage regulator chip, characterized in that, Includes the linear voltage regulator circuit described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the linear voltage regulator chip as described in claim 9.

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