Switching power supply and control method, switching circuit, power supply circuit
By using a cascaded switching circuit structure, the phase of the phase shift is automatically adjusted, which solves the problem of poor adaptability of the PLL method in the existing technology and realizes flexible control and stable power supply when adding or subtracting phases in the switching power supply.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUZHOU POWERON IC DESIGN
- Filing Date
- 2026-06-24
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, phase-locked loop (PLL) methods require pre-setting of phase shifts, cannot be dynamically adjusted, have poor adaptability, and are complex to design, making them unable to flexibly cope with changes in the number of switching circuits.
It adopts a PLL-free approach, using a cascaded switching circuit structure to automatically adjust the phase of the phase difference using a clock signal, thereby achieving parallel control of the phase difference and providing strong adaptability.
It achieves automatic adjustment to the optimal phase interleaving during phase addition and subtraction, has strong applicability, eliminates the need for PLL circuits, simplifies design, and improves system flexibility and stability.
Smart Images
Figure CN122437387A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of switching power supply technology, and in particular to a switching power supply and control method, switching circuit, and power supply circuit. Background Technology
[0002] Switching power supplies use multiple switching circuits connected in parallel to broaden the power supply's load capacity. To reduce input and output ripple current and ripple voltage, staggered parallel connection technology is usually used.
[0003] The main approach in existing technology is to use a phase-locked loop (PLL) to achieve phase-shifted parallel control. The switching circuit outputs a clock signal that is phase-shifted but fixed in phase with its own pulse width modulation (PWM) through the PLL circuit. This clock signal is then used to synchronize another switching circuit, thereby achieving phase-shifted parallel control of at least two switching circuits.
[0004] However, the PLL method has the following disadvantages: the phase shift needs to be set in advance according to the number of parallel switching circuits, and the PLL circuit needs to be specially designed. It cannot be dynamically adjusted according to the number of parallel switching circuits, resulting in poor adaptability. Summary of the Invention
[0005] The purpose of this application is to address the shortcomings of the prior art by providing a switching power supply and control method, switching circuit, and power supply circuit that can automatically adjust to the optimal phase interleaving during phase addition and subtraction, thereby achieving phase-shifted parallel control and having strong applicability.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, the present invention provides a switching power supply, comprising: At least two switching circuits, each of the switching circuits having an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; the input voltage terminals of the at least two switching circuits are connected in parallel to receive an input voltage, and the output voltage terminals of the at least two switching circuits are connected in parallel to generate an output voltage; At least two of the aforementioned switching circuits are cascaded through a clock input terminal and a clock output terminal. The clock output terminal of the preceding switching circuit is electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal. The clock signal includes multiple pulses, and each of the aforementioned switching circuits sequentially generates a PWM control signal based on one pulse of the clock signal to perform power conversion.
[0007] In an optional implementation, the phase shift of at least two of the switching circuits is P683_692P, where M is the number of the switching circuits.
[0008] In an optional implementation, the clock input terminal of the first switching circuit in at least two of the switching circuits receives the clock signal.
[0009] In an optional implementation, the clock input terminal of the first switching circuit and the clock output terminal of the tail switching circuit in at least two of the switching circuits are also connected to the power supply voltage / reference ground via resistors.
[0010] In an optional implementation, the clock output of the tail switch circuit in at least two of the switching circuits is also connected to the power supply voltage / reference ground via a resistor.
[0011] In an optional embodiment, each of the switching circuits further has a reset terminal, and the reset terminals of at least two of the switching circuits are electrically connected; the tail switch circuit in the at least two switching circuits is used to generate a reset signal after receiving a clock signal and send the reset signal to the other switching circuits.
[0012] In an optional implementation, each of the switching circuits includes: a loop control circuit, a phase-controlled triggering circuit, a PWM generation circuit, and a main power circuit; The output terminal of the loop control circuit is electrically connected to the first input terminal and the clock input terminal of the phase-controlled trigger circuit, respectively; the second input terminal of the phase-controlled trigger circuit is electrically connected to the reset terminal; the first output terminal of the phase-controlled trigger circuit is electrically connected to the clock output terminal; the second output terminal of the phase-controlled trigger circuit is electrically connected to the input terminal of the PWM generation circuit; the output terminal of the PWM generation circuit is electrically connected to the control terminal of the main power circuit; the input terminal of the main power circuit is electrically connected to the input voltage terminal; and the output terminal of the main power circuit is electrically connected to the output voltage terminal.
[0013] In an optional implementation, the loop control circuit includes: an error amplifier, a comparator, a first voltage divider resistor, a second voltage divider resistor, and a first switch; The input terminal of the error amplifier is electrically connected to one end of the first voltage divider resistor and one end of the second voltage divider resistor, respectively. The other end of the first voltage divider resistor is electrically connected to the output terminal of the main power circuit, and the other end of the second voltage divider resistor is grounded. The output of the error amplifier is electrically connected to the input of the comparator, the output of the comparator is electrically connected to one end of the first switch, and the other end of the first switch is electrically connected to the clock input.
[0014] In an optional implementation, the phase-controlled trigger circuit includes: an inverter, a D flip-flop, a first AND gate, a second AND gate, a second switch, and a monostable multivibrator; The input terminal of the inverter is electrically connected to the clock input terminal of the switching circuit, the other end of the first switch, the first input terminal of the first AND gate, and the first input terminal of the second AND gate, respectively; the output terminal of the inverter is electrically connected to the data input terminal of the D flip-flop. The clock input terminal of the D flip-flop is electrically connected to the reset terminal of the switching circuit and one end of the second switch, respectively. The non-inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the first AND gate and the input terminal of the monostable multivibrator, respectively. The inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the second AND gate. The other end of the second switch is electrically connected to the output of the monostable multivibrator, the output of the first AND gate is electrically connected to the clock output of the switching circuit, and the output of the second AND gate is electrically connected to the input of the PWM generation circuit.
[0015] Secondly, the present invention provides a switching circuit having an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; wherein at least two of the switching circuits constitute a switching power supply, the input voltage terminals of the at least two switching circuits are connected in parallel to receive an input voltage, and the output voltage terminals of the at least two switching circuits are connected in parallel to generate an output voltage; the at least two switching circuits are cascaded through a clock input terminal and a clock output terminal, and the clock output terminal of the preceding switching circuit is electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal; wherein the clock signal includes multiple pulses, and each of the switching circuits sequentially generates a PWM control signal according to one pulse of the clock signal to perform power conversion.
[0016] In an optional embodiment, the switching circuit further includes a reset terminal, and the reset terminals of at least two of the switching circuits are electrically connected; the tail switch circuit in the at least two switching circuits is used to generate a reset signal after receiving a clock signal and send the reset signal to the other switching circuits.
[0017] In an optional implementation, the switching circuit includes: a loop control circuit, a phase-controlled triggering circuit, a PWM generation circuit, and a main power circuit; The output terminal of the loop control circuit is electrically connected to the first input terminal and the clock input terminal of the phase-controlled trigger circuit, respectively; the second input terminal of the phase-controlled trigger circuit is electrically connected to the reset terminal; the first output terminal of the phase-controlled trigger circuit is electrically connected to the clock output terminal; the second output terminal of the phase-controlled trigger circuit is electrically connected to the input terminal of the PWM generation circuit; the output terminal of the PWM generation circuit is electrically connected to the control terminal of the main power circuit; the input terminal of the main power circuit is electrically connected to the input voltage terminal; and the output terminal of the main power circuit is electrically connected to the output voltage terminal.
[0018] In an optional implementation, the loop control circuit includes: an error amplifier, a comparator, a first voltage divider resistor, a second voltage divider resistor, and a first switch; The input terminal of the error amplifier is electrically connected to one end of the first voltage divider resistor and one end of the second voltage divider resistor, respectively. The other end of the first voltage divider resistor is electrically connected to the output terminal of the main power circuit, and the other end of the second voltage divider resistor is grounded. The output of the error amplifier is electrically connected to the input of the comparator, the output of the comparator is electrically connected to one end of the first switch, and the other end of the first switch is electrically connected to the clock input.
[0019] In an optional implementation, the phase-controlled trigger circuit includes: an inverter, a D flip-flop, a first AND gate, a second AND gate, a second switch, and a monostable multivibrator; The input terminal of the inverter is electrically connected to the clock input terminal of the switching circuit, the other end of the first switch, the first input terminal of the first AND gate, and the first input terminal of the second AND gate, respectively; the output terminal of the inverter is electrically connected to the data input terminal of the D flip-flop. The clock input terminal of the D flip-flop is electrically connected to the reset terminal of the switching circuit and one end of the second switch, respectively. The non-inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the first AND gate and the input terminal of the monostable multivibrator, respectively. The inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the second AND gate. The other end of the second switch is electrically connected to the output of the monostable multivibrator, the output of the first AND gate is electrically connected to the clock output of the switching circuit, and the output of the second AND gate is electrically connected to the input of the PWM generation circuit.
[0020] Thirdly, the present invention provides a control method for a switching power supply, applied to a switching power supply, the switching power supply comprising: at least two switching circuits, each of the switching circuits having an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; the input voltage terminals of the at least two switching circuits are connected in parallel for receiving an input voltage, and the output voltage terminals of the at least two switching circuits are connected in parallel for generating an output voltage; At least two of the aforementioned switching circuits are cascaded through a clock input terminal and a clock output terminal, wherein the clock output terminal of the preceding switching circuit is electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal; wherein the clock signal comprises multiple pulses; The control method includes: Each of the aforementioned switching circuits sequentially generates a PWM control signal based on a pulse of the clock signal to perform power conversion.
[0021] In an optional implementation, the control method further includes: Before the first switching circuit in at least two of the switching circuits receives the clock signal, the first switching circuit generates the clock signal according to the output voltage of the switching power supply.
[0022] In an optional implementation, the control method further includes: After receiving the clock signal, the tail switch circuit in at least two of the switching circuits controls the tail switch circuit to generate a reset signal and sends the reset signal to the other switching circuits.
[0023] Fourthly, the present invention provides a power supply circuit, including a switching power supply and a load as described in any of the foregoing embodiments, wherein the output terminal of the switching power supply and the power supply terminal of the load are electrically connected.
[0024] The beneficial effects of this application are: The switching power supply and control method, switching circuit, and power supply circuit provided in this application include: at least two switching circuits, each with an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; the input voltage terminals of the at least two switching circuits are connected in parallel to receive the input voltage, and the output voltage terminals of the at least two switching circuits are connected in parallel to generate the output voltage; the at least two switching circuits are cascaded through the clock input terminal and the clock output terminal, with the clock output terminal of the preceding switching circuit electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal; wherein, the clock signal includes multiple pulses, and each switching circuit sequentially generates a PWM control signal according to one pulse of the clock signal to perform power conversion, thereby achieving phase-shift synchronization without the introduction of a phase-locked loop (PLL) circuit, and automatically adjusting to the optimal phase interleaving during phase addition and subtraction, making it highly applicable. Attached Figure Description
[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 1 ; Figure 2 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 2 ; Figure 3 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 3 ; Figure 4 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 4 ; Figure 5 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 5 ; Figure 6 A schematic diagram of a signal timing diagram provided in an embodiment of this application; Figure 7 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 6 . Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0028] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0029] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0030] The main approach in existing technology is to use a phase-locked loop (PLL) to achieve phase-shifted parallel control. In this method, each switching circuit in the switching power supply outputs a clock signal with a fixed phase shift from its own pulse-width modulation (PWM) output via the PLL circuit. This clock signal is then used to synchronize another switching circuit, achieving phase-shifted parallel control of at least two switching circuits. Since the optimal phase difference is actually 360 / H degrees, where H is the number of parallel circuits, the phase-shifted clock output by the PLL is typically set to 360 / H degrees.
[0031] However, the PLL method has the following drawbacks: the phase shift needs to be pre-set according to the number of parallel switching circuits, and a special PLL circuit needs to be designed. It cannot be dynamically adjusted according to the number of parallel switching circuits, resulting in poor adaptability. In addition, the PLL requires closed-loop control, and loop compensation can cause stability problems, leading to a complex and unreliable design. For example, in a switching power supply with three units set up with a 120-degree phase shift using a phase-locked loop (PLL), if three phases are removed and only phases 1 and 2 are working, phases 1 and 2 still maintain a 120-degree phase difference. However, ideally, the two phases should work at a 180-degree phase difference. Therefore, the PLL method lacks flexibility in adding or removing phases.
[0032] In view of this, the embodiments of this application provide a switching power supply that can automatically adjust to the optimal phase interleaving when adding or subtracting phases without introducing a phase-locked loop (PLL) circuit, thereby achieving phase-shifted parallel control and having strong adaptability.
[0033] Figure 1 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 1 .like Figure 1 As shown, the switching power supply includes: at least two switching circuits, each switching circuit having an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; the input voltage terminals of the at least two switching circuits are connected in parallel to receive the input voltage, and the output voltage terminals of the at least two switching circuits are connected in parallel to generate the output voltage; the at least two switching circuits are cascaded through a clock input terminal CLK_IN and a clock output terminal CLK_OUT, and the clock output terminal CLK_OUT of the preceding switching circuit is electrically connected to the clock input terminal CLK_IN of the following switching circuit for transmitting a clock signal; wherein, the clock signal includes multiple pulses, and each switching circuit sequentially generates a PWM control signal according to one pulse of the clock signal to perform power conversion.
[0034] The input voltage terminal VIN can be connected to the input voltage Vin, and the output voltage terminal VOUT can supply power to the load. By setting at least two switching circuits with their input voltage terminals connected in parallel and at least two switching circuits with their output voltage terminals connected in parallel, the load can be supplied with power after multi-phase power conversion.
[0035] Among them, such as Figure 1As shown, for each switching circuit, each switching circuit can be configured with a clock input terminal CLK_IN and a clock output terminal CLK_OUT, and a clock signal cascade relationship is established through the clock port. In some implementations, during operation, the first switching circuit of at least two switching circuits can generate a clock signal. Based on a pulse of the clock signal, a PWM control signal can be generated and transmitted to the next switching circuit. Other switching circuits of at least two switching circuits can generate PWM control signals based on a pulse of the received clock signal. The PWM control signals generated by each switching circuit can be used to drive the power stage switches in the switching circuit. After being filtered by the power inductor, they are combined and superimposed at the output terminal, ultimately providing a low-ripple, fast-response stable voltage for the load.
[0036] In some implementations, for each switching circuit, phase addition / subtraction operations can be performed according to the actual scenario to determine whether each switching circuit outputs a PWM control signal. Specifically, for a certain switching circuit, if it is determined that the switching circuit needs to perform a phase subtraction operation, then the switching circuit does not output a PWM control signal after receiving the clock signal, but transmits the clock signal to the next switching circuit; if it is determined that the switching circuit needs to perform a phase addition operation, then the switching circuit generates a PWM control signal based on one pulse of the clock signal after receiving the clock signal, and transmits the clock signal to the next switching circuit.
[0037] Optionally, when determining whether each switching circuit needs to perform a phase reduction operation or a phase addition operation, it can be determined according to a preset phase reduction sequence or a preset phase addition sequence. For example, the preset phase reduction sequence indicates that, except for the first switching circuit in the switching power supply, each switching circuit will be reduced sequentially according to its number from smallest to largest or from largest to smallest.
[0038] Of course, it should be noted that the preset phase subtraction sequence or preset phase addition sequence is not limited to this and can be flexibly set according to the actual application scenario. For example, in some implementations, a random selection switching circuit can be set to perform phase addition or phase subtraction operations.
[0039] For example, a switching power supply includes four switching circuits, numbered 1, 2, 3, and 4 respectively. If a phase reduction is determined, the switching circuit numbered 2 can be subtracted first, then the switching circuit numbered 3 can be subtracted, and finally the switching circuit numbered 4 can be subtracted. If a phase addition is determined, the switching circuit with the highest number can be added. For example, if it is found that switching circuits 2 and 3 are currently in a phase reduction state, then switching circuit 3 can be added first, and then switching circuit 2 can be added.
[0040] It is worth noting that this application does not limit the number of switching circuits added or subtracted each time, and can be flexibly selected according to the actual application scenario. In addition, in some embodiments, it can be limited that all switching circuits except the first switching circuit in the switching power supply can be subtracted.
[0041] By applying the embodiments of this application, multiple switching circuits are cascaded through clock ports, and each switching circuit can generate PWM control signals sequentially according to the clock pulses received in sequence, thereby achieving phase-shifting operation. Furthermore, the phases can be automatically adjusted to achieve optimal phase shifting during phase addition and subtraction, making it highly applicable.
[0042] Of course, this application does not limit the type of each switching circuit. Each switching circuit can be an isolated converter or a non-isolated converter, and is not limited here.
[0043] In summary, this application provides a switching power supply, including: at least two switching circuits, each switching circuit having an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; the input voltage terminals of the at least two switching circuits are connected in parallel to receive the input voltage, and the output voltage terminals of the at least two switching circuits are connected in parallel to generate the output voltage; the at least two switching circuits are cascaded through the clock input terminal and the clock output terminal, with the clock output terminal of the preceding switching circuit electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal; wherein, the clock signal includes multiple pulses, and each switching circuit sequentially generates a PWM control signal according to one pulse of the clock signal to perform power conversion, thereby achieving phase-locked loop (PLL) synchronization without the need for a PLL circuit, and automatically adjusting to the optimal phase interleaving during phase addition and subtraction, making it highly applicable.
[0044] In an optional implementation, the phase shift of at least two switching circuits is... M represents the number of switching circuits.
[0045] In some implementations, if each switching circuit sequentially generates a PWM control signal based on a pulse of the clock signal, then the out-of-phase phase corresponding to the switching power supply is... For example, if the value of M is 2, the corresponding phase misalignment is 180°; if the value of M is 3, the corresponding phase misalignment is 120°.
[0046] To better understand this application, let's take a switching power supply with three switching circuits as an example. In some embodiments, if all three switching circuits generate PWM control signals at the first moment, that is, the current number of phases is 3, and a phase reduction operation is needed at the second moment to reduce the current number of phases to 1, then the aforementioned method can be used to perform a phase reduction operation on the switching circuits other than the first switching circuit in the switching power supply so as not to output PWM control signals. It can be understood that after the phase reduction operation, the corresponding number of phases will be 1, which can realize single-phase control. When a phase addition operation is needed at the third moment to add the current number of phases to 3, then the aforementioned method can be used to adjust the number of switching circuits that output PWM control signals in the switching power supply to 3. It can be understood that after the phase addition operation, the corresponding number of phases will be 3.
[0047] In an optional implementation, the clock input of the first switching circuit in at least two switching circuits receives a clock signal.
[0048] In some implementations, the clock signal of the first switching circuit in at least two switching circuits can be generated internally or externally.
[0049] Optionally, the clock signal of the first switching circuit can be obtained in two ways. In some implementations, the clock signal can be generated autonomously by its internally integrated oscillation circuit or loop control circuit to achieve independent oscillation operation. In other implementations, the clock signal can also be provided by external devices such as external dedicated timing circuits, so that the clock signal is uniformly provided to the first switching circuit from the outside. The choice can be made flexibly according to the actual application scenario to provide a stable and reliable clock for the cascaded transmission of clocks for subsequent switching circuits.
[0050] Of course, this application does not limit the frequency of each cycle signal in the clock signal. It is generated according to the actual application scenario and is not limited here. It can be flexibly set according to the actual application scenario.
[0051] Figure 2 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 2 In an optional implementation, the clock input of the first switching circuit and the clock output of the last switching circuit in at least two switching circuits are also connected to the power supply voltage VCC / reference ground via resistors.
[0052] In an optional implementation, the clock output of the tail switch circuit in at least two switching circuits is also connected to the power supply voltage VCC / reference ground via a resistor.
[0053] Optionally, such as Figure 2As shown, the clock input terminal CLK_IN of the first switch circuit can be connected to the power supply voltage VCC through the first resistor R1, thus fixing the input terminal in a high-level state and avoiding problems such as level indeterminacy, signal reflection, and electromagnetic interference caused by floating pins. Of course, the specific connection method is not limited to this. Depending on the actual application scenario, the clock input terminal of the first switch circuit can also be connected to the reference ground through a resistor.
[0054] In some implementations, the clock output terminal CLK_OUT of the tail switch circuit can be connected to the power supply voltage VCC through a second resistor R2. This allows the clock output terminal CLK_OUT to be clamped at a fixed level, avoiding level instability, signal reflection, and electromagnetic interference problems caused by floating pins. Of course, the specific connection method is not limited to this. Depending on the actual application scenario, the clock output terminal of the tail switch circuit can also be connected to the reference ground through a resistor.
[0055] Figure 3 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 3 In alternative implementations, such as Figure 3 As shown, each switching circuit also has a reset terminal RESET, and the reset terminals RESET of at least two switching circuits are electrically connected; the tail switch circuit in at least two switching circuits is used to generate a reset signal after receiving a clock signal and send a reset signal to other switching circuits.
[0056] The tail switch circuit of the switching power supply also functions as a reset signal generator. Upon receiving the clock signal, it automatically generates a reset signal and sends it to each switch circuit via the RESET pin. This enables each switch circuit to generate the PWM control signal for the next cycle based on the reset signal. Upon receiving the reset signal, each switch circuit synchronously resets its internal timing state, enters the preparation stage for the next working cycle, realigns its phase according to the reset signal, and, as described above, outputs multiple PWM signals for the next cycle, thereby achieving continuous power supply to the load.
[0057] In some implementations, each switching circuit may also include a current-sharing pin. These pins are electrically connected, allowing multiple switching circuits to automatically and evenly share the load current, preventing any single module from overheating or being damaged due to excessive current. Optionally, during operation, each switching circuit can compare its output current with a reference current, fine-tuning the duty cycle of the PWM trigger signal based on the comparison result. This ultimately enables each switching circuit to automatically and evenly share the load current, with the reference current calculated by weighted averaging of the output currents of each switching circuit.
[0058] Figure 4 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 4 In an optional implementation, each switching circuit includes at least: a loop control circuit 250, a phase-controlled triggering circuit 210, a PWM generation circuit 220, and a main power circuit 230, wherein, as... Figure 4 As shown, the output terminal of the loop control circuit 250 is electrically connected to the first input terminal and the clock input terminal CLK_IN of the phase-controlled trigger circuit 210, respectively; the second input terminal of the phase-controlled trigger circuit 210 is electrically connected to the reset terminal RESET; the first output terminal of the phase-controlled trigger circuit 210 is electrically connected to the clock output terminal CLK_OUT; the second output terminal of the phase-controlled trigger circuit 210 is electrically connected to the input terminal of the PWM generation circuit 220; the output terminal of the PWM generation circuit 220 is electrically connected to the control terminal of the main power circuit 230; the input terminal of the main power circuit 230 is electrically connected to the input voltage terminal; and the output terminal of the main power circuit 230 is electrically connected to the output voltage terminal of the switching circuit.
[0059] The loop control circuit 250 is used to generate a clock signal based on the output voltage of the switching power supply; the phase-controlled trigger circuit 210 is used to generate a PWM trigger signal based on the clock signal and the reset signal, and transmit the clock signal through the clock output terminal; the PWM generation circuit 220 is used to generate a PWM control signal based on the PWM trigger signal and send it to the main power circuit 230; the main power circuit 230 is used to perform power conversion based on the PWM control signal.
[0060] Optionally, the working principle of the switching circuit is as follows: If the switching circuit is the first switching circuit in the switching power supply, the loop control circuit 250 in the switching circuit can generate a clock signal according to the output voltage of the switching power supply and send it to the phase-controlled trigger circuit 210; the phase-controlled trigger circuit 210 receives the clock signal from the loop control circuit 250, and generates a PWM trigger signal according to the clock signal and the reset signal and sends it to the PWM generation circuit 220, and transmits the clock signal to the next switching circuit through the clock output terminal CLK_OUT; the PWM generation circuit 220 can obtain the PWM trigger signal sent by the phase-controlled trigger circuit 210 and generate a PWM control signal and send it to the main power circuit 230. The PWM control signal drives the corresponding power stage switch in the main power circuit 230 through the gate driver, and after being filtered by the power inductor, it is superimposed at the output voltage terminal, and finally provides a stable voltage with low ripple and fast response for the load.
[0061] It should be noted that if the switching circuit is a non-first switching circuit in the switching power supply, the phase-controlled trigger circuit 210 can obtain the clock signal from the clock output of the previous switching circuit, generate a PWM trigger signal based on the clock signal and the reset signal, send it to the PWM generation circuit 220, and transmit the clock signal to the next switching circuit through the clock output terminal CLK_OUT. If the switching circuit is the tail switching circuit in the switching power supply, the tail switching circuit does not need to transmit a clock signal. The operation of the PWM generation circuit 220 and the main power circuit 230 can be found in the relevant descriptions above, and will not be repeated here.
[0062] Figure 5 This is a schematic diagram of a switching circuit provided in an embodiment of this application. In optional embodiments, such as... Figure 5 As shown, the loop control circuit 250 may include: an error amplifier EA, a comparator CMP, a first voltage divider resistor R5, a second voltage divider resistor R6, and a first switch S1; wherein, the input terminal of the error amplifier EA is electrically connected to one end of the first voltage divider resistor R5 and one end of the second voltage divider resistor R6, the other end of the first voltage divider resistor R5 is connected to the output terminal of the main power circuit 230, and the other end of the second voltage divider resistor R5 is grounded; the output terminal of the error amplifier EA is electrically connected to the input terminal of the comparator CMP, the output terminal of the comparator CMP is electrically connected to one end of the first switch S1, and the other end of the first switch S1 is electrically connected to the clock input terminal CLK_IN.
[0063] The working principle of the loop control circuit 250 is as follows: The first voltage divider resistor R5 and the second voltage divider resistor R6 form a voltage divider sampling network to perform real-time voltage divider acquisition of the final output voltage. The sampled feedback voltage signal is sent to the error amplifier EA. The error amplifier EA compares the sampled feedback voltage signal with the internal reference voltage, amplifies the voltage difference between the two, and outputs an error voltage. This error voltage is input to the comparator CMP. The comparator CMP compares the error voltage with the reference signal and generates a clock signal CLK based on the comparison result. When the output voltage is too low, the error voltage increases, and the operating frequency of the comparator CMP increases accordingly. When the output voltage is too high, the error voltage decreases, and the operating frequency of the comparator CMP decreases accordingly, thereby generating an adjustable clock signal and transmitting it to the phase-controlled trigger circuit 210.
[0064] Optionally, refer to Figure 5 As shown, the loop control circuit 250 may further include: the first capacitor C1 and the first filter resistor R3 can form an RC integral filter network, which can smooth the error voltage output by the error amplifier EA to filter out loop transient spikes and high-frequency interference from switching.
[0065] In some implementations, refer to Figure 5As shown, the phase-controlled trigger circuit 210 includes: an inverter U1, a D flip-flop U2, a first AND gate AND_1, a second AND gate AND_2, a second switch S2, and a monostable multivibrator one shot.
[0066] Specifically, the input terminal of inverter U1 is electrically connected to the clock input terminal CLK_IN of the switching circuit, one end of the first switch S1, the first input terminal of the first AND gate AND_1, and the first input terminal of the second AND gate AND_2, respectively; the output terminal of inverter U1 is electrically connected to the data input terminal of D flip-flop U2; the clock input terminal CLK_IN of D flip-flop U2 is electrically connected to the reset terminal RESET of the switching circuit and one end of the second switch S2, respectively; the non-inverting output terminal of D flip-flop U2 is electrically connected to the second input terminal of the first AND gate AND_1 and the input terminal of the monostable multivibrator one shot, respectively; the inverting output terminal of D flip-flop U2 is electrically connected to the second input terminal of the second AND gate AND_2; the other end of the second switch S2 is electrically connected to the output terminal of the monostable multivibrator one shot, the output terminal of the first AND gate AND_1 is electrically connected to the clock output terminal CLK_OUT of the switching circuit, and the output terminal of the second AND gate AND_2 is electrically connected to the input terminal of the PWM generation circuit 220.
[0067] Optionally, during the operation of the phase-controlled trigger circuit 210: when this switching circuit is the first switching circuit in the switching power supply, the first switch S1 is closed and the second switch S2 is open, and its clock signal is provided by the internal loop control circuit; when this switching circuit is the tail switching circuit in the switching power supply, the second switch S2 is closed and the first switch S1 is open, the monostable multivibrator One shot generates a reset signal according to the non-inverting output terminal of the D flip-flop, and outputs it through the reset terminal RESET; when this switching circuit is the intermediate switching circuit in the switching power supply, the second switch S2 is open and the first switch S1 is open.
[0068] In addition, inverter U1 can invert the level signal input to the clock input terminal of the switching circuit and transmit it to D flip-flop U2; D flip-flop U2 latches the signal under the action of the clock edge and outputs two complementary logic signals; the two complementary signals are respectively connected to the first AND gate and the second AND gate, and after logical AND operation, two logic control signals with staggered timing and no conflict are generated. One logic control signal is sent to the subsequent PWM generation circuit 220, and the other logic control signal is output through the clock output terminal.
[0069] In some implementations, the PWM generation circuit 220 may include an On timer and an RS flip-flop U3. Its working principle is as follows: a logic control signal output by the phase-controlled trigger circuit 210 is connected to the RS flip-flop U3 to trigger the rising edge of the PWM and control MOS_1 to turn on; after the fixed time of the On timer, the falling edge of the PWM is triggered and control MOS_1 to turn off.
[0070] In some implementations, reference continues. Figure 5 As shown, the main power circuit 230 may include: a gate driver, a first power transistor MOS_1, a second power transistor MOS_2, a fifth inductor L5, and a fifth capacitor C5. Its working principle is as follows: after the PWM control signal output by the PWM generation circuit 220 is input to the gate driver, the gate driver amplifies the PWM control signal and drives the first power transistor MOS_1 and the second power transistor MOS_2 to alternately turn on and off, thereby converting the input voltage; the fifth inductor L5 and the fifth capacitor C5 form an LC filter circuit to smooth the pulsating voltage, filter out high-frequency ripple, and output a stable DC voltage to power the load.
[0071] Based on the above explanation, it can be understood that if the switching power supply outputs multiple PWM control signals, each PWM signal can output a stable DC voltage through the corresponding main power circuit 230, which can ultimately provide a stable voltage with low ripple and fast response for the load.
[0072] Figure 6 This is a schematic diagram of a signal timing diagram provided in an embodiment of this application. To better understand this application, the following description is provided in conjunction with the signal timing diagram. In some embodiments, it is assumed that the number of switching circuits in the switching power supply is three. From top to bottom, these switching circuits are denoted as: the first switching circuit, the second switching circuit, and the last switching circuit (i.e., the third switching circuit). The signal timing of the switching power supply can then be referenced... Figure 6 As shown.
[0073] Among them, such as Figure 6As shown, the first switching circuit can generate a clock signal CLK internally. Based on the first pulse of the clock signal CLK, it generates a first PWM signal PWM1 and transmits the clock signal CLK to the second switching circuit through the clock output terminal of the first switching circuit. The second switching circuit receives the clock signal CLK and generates a second PWM signal PWM2 based on the second pulse of the clock signal CLK. It then transmits the clock signal CLK to the third switching circuit through the clock output terminal of the second switching circuit. The third switching circuit receives the clock signal CLK and generates a third PWM signal PWM3 based on the third pulse of the clock signal CLK. It then sends a reset signal reset to the first switching circuit and the second switching circuit through the reset terminal RESET.
[0074] Where the current phase mode does not change, after the first switch circuit and the second switch circuit receive the reset signal, they can generate multiple PWM control signals for the next cycle based on the clock signal.
[0075] In summary, it can be seen that if the number of phases is 3, the first switching circuit, the second slave switching circuit, and the third switching circuit can respectively output the first PWM signal PWM1, the second PWM signal PWM2, and the third PWM signal PWM3, thereby realizing the output of 3 PWM signals with automatic phase shift of 120°. Referring to the foregoing explanation, each PWM signal can drive the corresponding power stage switch through the gate driver, and after being filtered and stored in the power inductor, they are combined and superimposed at the output terminal, ultimately providing the load with a low-ripple, fast-response stable voltage.
[0076] Continue to refer to Figure 6 As shown, if in certain scenarios it is necessary to reduce the number of phases to 2, then only the first switch circuit and the third switch circuit will work, while the second switch circuit will stop working. The working process of the first switch circuit and the third switch circuit is the same as the above working process, and will not be repeated here.
[0077] In summary, it can be seen that if the number of phases is 2, the first switch circuit and the third switch circuit can output the first PWM signal PWM1 and the third PWM signal PWM3 respectively, thereby realizing the output of 2 PWM signals with automatic phase shift of 180°.
[0078] Continue to refer to Figure 6 As shown, if in certain scenarios it is necessary to reduce the number of phases to 1, then only the first switching circuit works, and the working process is the same as when the number of phases is 2. The third switching circuit stops working, which will not be described in detail here.
[0079] Understandably, if the number of phases is 1, the first switching circuit automatically cycles through the process of phase shifting 360° according to the clock signal, so that the switching power supply can work stably under single-phase operation.
[0080] Figure 7 A schematic diagram of a switching power supply provided in an embodiment of this application. Figure 6 Optionally, refer to Figure 7 As shown, the switching power supply may include four switching circuits. Each switching circuit includes: a power input pin VIN, a clock output pin CLK_OUT, a reset pin RESET, an internal power input pin VCC, a clock input pin CLK_IN, and a power input pin VIN. The input voltage terminals of the four switching circuits are connected in parallel to receive the input voltage, and the output voltage terminals of the four switching circuits are connected in parallel to generate the output voltage. The four switching circuits are cascaded through clock input and clock output terminals, with the clock output terminal of one switching circuit electrically connected to the clock input terminal of the next switching circuit for transmitting a clock signal. The clock signal consists of multiple pulses, and each switching circuit sequentially generates a PWM control signal based on one pulse of the clock signal to perform power conversion.
[0081] In addition, it should be noted that if the clock input terminal CLK_IN of the switching circuit is pulled up to VCC, it is identified as the first switching circuit; if the clock output terminal CLK_OUT of the switching circuit is pulled up to VCC, it is identified as the tail switching circuit; otherwise, it is identified as an intermediate switching circuit cascaded between the first and tail switching circuits.
[0082] Optionally, the present invention also provides a switching circuit having an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; wherein at least two of the switching circuits constitute a switching power supply, the input voltage terminals of the at least two switching circuits are connected in parallel to receive an input voltage, and the output voltage terminals of the at least two switching circuits are connected in parallel to generate an output voltage; the at least two switching circuits are cascaded through a clock input terminal and a clock output terminal, and the clock output terminal of the preceding switching circuit is electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal; wherein the clock signal includes multiple pulses, and each of the switching circuits sequentially generates a PWM control signal according to one pulse of the clock signal to perform power conversion.
[0083] In an optional embodiment, each of the switching circuits further has a reset terminal, and the reset terminals of at least two of the switching circuits are electrically connected; the tail switch circuit in the at least two switching circuits is used to generate a reset signal after receiving a clock signal and send the reset signal to the other switching circuits.
[0084] In an optional implementation, each of the switching circuits includes: a loop control circuit, a phase-controlled triggering circuit, a PWM generation circuit, and a main power circuit; The output terminal of the loop control circuit is electrically connected to the first input terminal and the clock input terminal of the phase-controlled trigger circuit, respectively; the second input terminal of the phase-controlled trigger circuit is electrically connected to the reset terminal; the first output terminal of the phase-controlled trigger circuit is electrically connected to the clock output terminal; the second output terminal of the phase-controlled trigger circuit is electrically connected to the input terminal of the PWM generation circuit; the output terminal of the PWM generation circuit is electrically connected to the control terminal of the main power circuit; the input terminal of the main power circuit is electrically connected to the input voltage terminal; and the output terminal of the main power circuit is electrically connected to the output voltage terminal.
[0085] In an optional implementation, the loop control circuit includes: an error amplifier, a comparator, a first voltage divider resistor, a second voltage divider resistor, and a first switch; The input terminal of the error amplifier is electrically connected to one end of the first voltage divider resistor and one end of the second voltage divider resistor, respectively. The other end of the first voltage divider resistor is electrically connected to the output terminal of the main power circuit, and the other end of the second voltage divider resistor is grounded. The output of the error amplifier is electrically connected to the input of the comparator, the output of the comparator is electrically connected to one end of the first switch, and the other end of the first switch is electrically connected to the clock input.
[0086] In an optional implementation, the phase-controlled trigger circuit includes: an inverter, a D flip-flop, a first AND gate, a second AND gate, a second switch, and a monostable multivibrator; The input terminal of the inverter is electrically connected to the clock input terminal of the switching circuit, the other end of the first switch, the first input terminal of the first AND gate, and the first input terminal of the second AND gate, respectively; the output terminal of the inverter is electrically connected to the data input terminal of the D flip-flop. The clock input terminal of the D flip-flop is electrically connected to the reset terminal of the switching circuit and one end of the second switch, respectively. The non-inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the first AND gate and the input terminal of the monostable multivibrator, respectively. The inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the second AND gate. The other end of the second switch is electrically connected to the output of the monostable multivibrator, the output of the first AND gate is electrically connected to the clock output of the switching circuit, and the output of the second AND gate is electrically connected to the input of the PWM generation circuit.
[0087] Optionally, the present invention provides a control method for a switching power supply, which can be applied to a switching power supply, the switching power supply comprising: at least two switching circuits, each switching circuit having an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; the input voltage terminals of the at least two switching circuits are connected in parallel for receiving an input voltage, and the output voltage terminals of the at least two switching circuits are connected in parallel for generating an output voltage; At least two of the aforementioned switching circuits are cascaded through a clock input terminal and a clock output terminal, wherein the clock output terminal of the preceding switching circuit is electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal; wherein the clock signal comprises multiple pulses; The control method includes: Each of the aforementioned switching circuits sequentially generates a PWM control signal based on a pulse of the clock signal to perform power conversion.
[0088] In an optional implementation, the control method further includes: Before the first switching circuit in at least two of the switching circuits receives the clock signal, the first switching circuit generates the clock signal according to the output voltage of the switching power supply.
[0089] In an optional implementation, the control method further includes: After receiving the clock signal, the tail switch circuit in at least two of the switching circuits controls the tail switch circuit to generate a reset signal and sends the reset signal to the other switching circuits.
[0090] Optionally, the present invention provides a power supply circuit, including a switching power supply and a load as described in any of the foregoing embodiments, wherein the output terminal of the switching power supply and the power supply terminal of the load are electrically connected.
[0091] The load can be an industrial sensor, controller, display, inverter, energy storage system, wearable device, storage load, etc., and is not limited here. It can vary depending on the actual application scenario.
[0092] It should be noted that the working principle of switching power supplies can be found in the aforementioned explanations, as their implementation principles and technical effects are similar and will not be repeated here.
[0093] By applying the embodiments of this application, it is possible to power the load through a switching power supply, and during the power supply process, there is no need to introduce a phase-locked loop (PLL) circuit to automatically adjust to the optimal phase interleaving when adding or subtracting phases, thereby realizing phase-shifted parallel control with strong adaptability.
[0094] In the embodiments provided in this application, the embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.
[0095] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.
[0096] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0097] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. It should be noted that similar reference numerals and letters denote similar items in the accompanying drawings; therefore, once an item is defined in one drawing, it will not be further defined or explained in subsequent drawings.
[0098] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A switching power supply, characterized in that, include: At least two switching circuits, each of the switching circuits having an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; At least two of the switching circuits have their input voltage terminals connected in parallel to receive an input voltage, and at least two of the switching circuits have their output voltage terminals connected in parallel to generate an output voltage. At least two of the aforementioned switching circuits are cascaded through a clock input terminal and a clock output terminal. The clock output terminal of the preceding switching circuit is electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal. The clock signal includes multiple pulses, and each of the aforementioned switching circuits sequentially generates a PWM control signal based on one pulse of the clock signal to perform power conversion.
2. The switching power supply according to claim 1, characterized in that, At least two of the said switching circuits have out-of-phase phases. M represents the number of the switching circuits.
3. The switching power supply according to claim 1, characterized in that, The clock signal is received at the clock input terminal of the first switching circuit in at least two of the aforementioned switching circuits.
4. The switching power supply according to claim 3, characterized in that, In at least two of the aforementioned switching circuits, the clock input terminal of the first switching circuit and the clock output terminal of the last switching circuit are also connected to the power supply voltage / reference ground via resistors.
5. The switching power supply according to claim 3, characterized in that, In at least two of the aforementioned switching circuits, the clock output of the tail switch circuit is also connected to the power supply voltage / reference ground via a resistor.
6. The switching power supply according to any one of claims 1-5, characterized in that, Each of the switching circuits also has a reset terminal, and the reset terminals of at least two of the switching circuits are electrically connected; the tail switch circuit in the at least two switching circuits is used to generate a reset signal after receiving a clock signal and send the reset signal to the other switching circuits.
7. The switching power supply according to claim 6, characterized in that, Each of the aforementioned switching circuits includes: a loop control circuit, a phase-controlled triggering circuit, a PWM generation circuit, and a main power circuit; The output terminal of the loop control circuit is electrically connected to the first input terminal and the clock input terminal of the phase-controlled trigger circuit, respectively; the second input terminal of the phase-controlled trigger circuit is electrically connected to the reset terminal; the first output terminal of the phase-controlled trigger circuit is electrically connected to the clock output terminal; the second output terminal of the phase-controlled trigger circuit is electrically connected to the input terminal of the PWM generation circuit; the output terminal of the PWM generation circuit is electrically connected to the control terminal of the main power circuit; the input terminal of the main power circuit is electrically connected to the input voltage terminal; and the output terminal of the main power circuit is electrically connected to the output voltage terminal.
8. The switching power supply according to claim 7, characterized in that, The loop control circuit includes: an error amplifier, a comparator, a first voltage divider resistor, a second voltage divider resistor, and a first switch; The input terminal of the error amplifier is electrically connected to one end of the first voltage divider resistor and one end of the second voltage divider resistor, respectively. The other end of the first voltage divider resistor is electrically connected to the output terminal of the main power circuit, and the other end of the second voltage divider resistor is grounded. The output of the error amplifier is electrically connected to the input of the comparator, the output of the comparator is electrically connected to one end of the first switch, and the other end of the first switch is electrically connected to the clock input.
9. The switching power supply according to claim 8, characterized in that, The phase-controlled trigger circuit includes: an inverter, a D flip-flop, a first AND gate, a second AND gate, a second switch, and a monostable multivibrator; The input terminal of the inverter is electrically connected to the clock input terminal of the switching circuit, the other end of the first switch, the first input terminal of the first AND gate, and the first input terminal of the second AND gate, respectively; the output terminal of the inverter is electrically connected to the data input terminal of the D flip-flop. The clock input terminal of the D flip-flop is electrically connected to the reset terminal of the switching circuit and one end of the second switch, respectively. The non-inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the first AND gate and the input terminal of the monostable multivibrator, respectively. The inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the second AND gate. The other end of the second switch is electrically connected to the output of the monostable multivibrator, the output of the first AND gate is electrically connected to the clock output of the switching circuit, and the output of the second AND gate is electrically connected to the input of the PWM generation circuit.
10. A switching circuit, characterized in that, The switching circuit has an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; wherein, at least two of the switching circuits constitute a switching power supply, the input voltage terminals of at least two of the switching circuits are connected in parallel to receive the input voltage, and the output voltage terminals of at least two of the switching circuits are connected in parallel to generate the output voltage; at least two of the switching circuits are cascaded through the clock input terminal and the clock output terminal, and the clock output terminal of the preceding switching circuit is electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal; wherein, the clock signal includes multiple pulses, and each of the switching circuits sequentially generates a PWM control signal according to one pulse of the clock signal to perform power conversion.
11. The switching circuit according to claim 10, characterized in that, The switching circuit also has a reset terminal, and the reset terminals of at least two of the switching circuits are electrically connected; the tail switch circuit in the at least two switching circuits is used to generate a reset signal after receiving a clock signal and send the reset signal to the other switching circuits.
12. The switching circuit according to claim 11, characterized in that, The switching circuit includes: a loop control circuit, a phase-controlled triggering circuit, a PWM generation circuit, and a main power circuit; The output terminal of the loop control circuit is electrically connected to the first input terminal and the clock input terminal of the phase-controlled trigger circuit, respectively; the second input terminal of the phase-controlled trigger circuit is electrically connected to the reset terminal; the first output terminal of the phase-controlled trigger circuit is electrically connected to the clock output terminal; the second output terminal of the phase-controlled trigger circuit is electrically connected to the input terminal of the PWM generation circuit; the output terminal of the PWM generation circuit is electrically connected to the control terminal of the main power circuit; the input terminal of the main power circuit is electrically connected to the input voltage terminal; and the output terminal of the main power circuit is electrically connected to the output voltage terminal.
13. The switching circuit according to claim 12, characterized in that, The loop control circuit includes: an error amplifier, a comparator, a first voltage divider resistor, a second voltage divider resistor, and a first switch; The input terminal of the error amplifier is electrically connected to one end of the first voltage divider resistor and one end of the second voltage divider resistor, respectively. The other end of the first voltage divider resistor is electrically connected to the output terminal of the main power circuit, and the other end of the second voltage divider resistor is grounded. The output of the error amplifier is electrically connected to the input of the comparator, the output of the comparator is electrically connected to one end of the first switch, and the other end of the first switch is electrically connected to the clock input.
14. The switching circuit according to claim 13, characterized in that, The phase-controlled trigger circuit includes: an inverter, a D flip-flop, a first AND gate, a second AND gate, a second switch, and a monostable multivibrator; The input terminal of the inverter is electrically connected to the clock input terminal of the switching circuit, the other end of the first switch, the first input terminal of the first AND gate, and the first input terminal of the second AND gate, respectively; the output terminal of the inverter is electrically connected to the data input terminal of the D flip-flop. The clock input terminal of the D flip-flop is electrically connected to the reset terminal of the switching circuit and one end of the second switch, respectively. The non-inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the first AND gate and the input terminal of the monostable multivibrator, respectively. The inverting output terminal of the D flip-flop is electrically connected to the second input terminal of the second AND gate. The other end of the second switch is electrically connected to the output of the monostable multivibrator, the output of the first AND gate is electrically connected to the clock output of the switching circuit, and the output of the second AND gate is electrically connected to the input of the PWM generation circuit.
15. A control method for a switching power supply, characterized in that, The invention is applied to a switching power supply, the switching power supply comprising: at least two switching circuits, each of the switching circuits having an input voltage terminal, an output voltage terminal, a clock input terminal, and a clock output terminal; the input voltage terminals of the at least two switching circuits are connected in parallel to receive an input voltage, and the output voltage terminals of the at least two switching circuits are connected in parallel to generate an output voltage; At least two of the aforementioned switching circuits are cascaded through a clock input terminal and a clock output terminal, wherein the clock output terminal of the preceding switching circuit is electrically connected to the clock input terminal of the following switching circuit for transmitting a clock signal; wherein the clock signal comprises multiple pulses; The control method includes: Each of the aforementioned switching circuits sequentially generates a PWM control signal based on a pulse of the clock signal to perform power conversion.
16. The control method according to claim 15, characterized in that, The control method further includes: Before the first switching circuit in at least two of the switching circuits receives the clock signal, the first switching circuit generates the clock signal according to the output voltage of the switching power supply.
17. The control method according to claim 15 or 16, characterized in that, The control method further includes: After receiving the clock signal, the tail switch circuit in at least two of the switching circuits controls the tail switch circuit to generate a reset signal and sends the reset signal to the other switching circuits.
18. A power supply circuit, characterized in that, The device includes a load and a switching power supply as described in any one of claims 1-9, wherein the output terminal of the switching power supply is electrically connected to the power supply terminal of the load.