A design method for suppressing double-frequency voltage ripple of power electronic transformer

Abstract

The application discloses a kind of power electronic transformer design methods for inhibiting double-frequency voltage ripple, belong to power electronic converter technical field.Aiming at the problem that double-frequency fluctuation power of cascaded power electronic transformer input stage leads to large DC capacitor voltage ripple and low system power density, a design method based on impedance analysis is proposed.The method establishes the parallel impedance model of isolation stage and sub-module DC capacitor, based on impedance shunting principle, through asymmetric inductance parameter configuration or series resonance network configuration, the primary side port of isolation stage is constructed as a low impedance flow channel for double-frequency fluctuation power, guiding multi-phase double-frequency fluctuation power to flow into isolation stage first, superimposed and offset in high-frequency AC path, to suppress the double-frequency voltage ripple of sub-module DC capacitor.The application does not need to increase the capacitance value or complex active control, fundamentally suppresses ripple from the hardware level, while achieving natural balance of sub-module DC capacitor voltage, improving system power density and operation reliability.

Description

Technical Field

[0001] This invention belongs to the field of power electronic converter technology, specifically relating to a design method for suppressing second harmonic voltage ripple based on impedance analysis. Background Technology

[0002] With the rapid development of the energy internet and smart grids, power electronic transformers (PETs), also known as solid-state transformers (SSTs), as key equipment integrating voltage transformation, electrical isolation, and power quality control functions, have shown broad application prospects in fields such as AC / DC hybrid microgrids and rail transit power supply. Among them, the topology using a cascaded H-bridge (CHB) as the high-voltage input stage and achieving multi-port interconnection through a high-frequency isolation stage has become a research hotspot in medium- and high-voltage, high-capacity applications due to its high modularity and ease of expansion.

[0003] However, this type of topology faces an inherent problem in practical applications: since the input stage is usually composed of multiple cascaded single-phase H-bridges, the instantaneous power of the single-phase AC input contains a second harmonic ripple component twice the grid frequency. Because the DC sides of the H-bridges are independent of each other, these ripple powers are difficult to cancel out naturally through inter-phase flow and will eventually flow into the DC support capacitor of the submodule, causing second harmonic ripple in the DC bus voltage, which seriously affects the stable operation of the system.

[0004] To address the above problems, existing technologies mainly employ the following two types of solutions, but both have significant limitations: The first type is the passive suppression solution. Traditional industry typically adopts the "passive suppression" approach, which involves directly selecting large-capacity electrolytic capacitors to buffer fluctuation energy. While this method is simple, it results in large capacitors, often occupying 30%-50% of the total system volume, and the electrolytic capacitors have a short lifespan, severely limiting the improvement of PET power density and long-term reliability.

[0005] The second category is active control schemes. To reduce capacitor values, academia and industry have proposed numerous solutions based on "active control." For example, Chinese patent CN 113629985 B, entitled "A Submodule Capacitor Optimization Control Method for CHB-QAB Topology," proposes a power-balanced control strategy that attempts to achieve forced power distribution by dynamically coordinating the phase shift angles of each submodule. However, this strategy heavily relies on high-precision voltage and current sampling, and the computational burden of the control system increases exponentially with the number of submodules. Furthermore, Chinese patent CN 117155129 A, entitled "A Control Method for Achieving Submodule Power Balancing in a Modular Solid-State Transformer," while enhancing system controllability to some extent, not only consumes valuable control resources and communication bandwidth but also struggles to guarantee robustness when sensor noise interference or communication delays occur.

[0006] In summary, the aforementioned existing technologies all suppress ripple through control algorithms, which are complex and lack a design-based solution to suppress second harmonic voltage ripple. Summary of the Invention

[0007] To address the shortcomings of existing passive suppression schemes, such as large capacitor size, and active control schemes, such as high control complexity and poor robustness, this invention provides a design method for suppressing second-harmonic voltage ripple in power electronic transformers. This method aims to construct a low-impedance flow path for second-harmonic power through systematic design of the impedance domain, guiding the three-phase second-harmonic power to naturally cancel each other out. This achieves suppression of second-harmonic voltage ripple on the DC capacitor of the submodule without introducing complex active control algorithms.

[0008] To address the aforementioned technical problems, this invention provides a design method for suppressing second-harmonic voltage ripple in power electronic transformers. The method is applied to a power electronic transformer, which includes an input stage and an isolation stage. The input stage employs a multi-phase cascaded topology, with each phase containing several sub-modules equipped with DC capacitors. The isolation stage connects the sub-modules of the input stage and achieves electrical coupling between the multiple phases through a high-frequency AC path. The design method includes the following steps: S1: Establish an impedance model for the primary side port of the isolation stage and the DC capacitor of the submodule in parallel; S2: Based on the principle of impedance shunt, the isolation stage is planned and configured as a low-impedance flow channel for second harmonic fluctuation power; S3: Design the circuit parameters of the primary side port of the isolation stage so that the input impedance of the primary side port of the isolation stage at twice the power frequency is significantly less than the capacitive reactance of the DC capacitor of the submodule at twice the power frequency, thereby realizing the hardware construction of the low impedance flow channel. S4: Through the low-impedance flow channel, the multiphase second harmonic fluctuation power generated by the input stage is guided to flow preferentially into the isolation stage, and the multiphase fluctuation power is naturally superimposed and canceled on the high-frequency AC path, suppressing the second harmonic voltage ripple on the DC capacitor of the submodule, and at the same time achieving the natural balance of the DC capacitor voltage of each submodule.

[0009] Furthermore, in step S3, the low-impedance flow channel is constructed in at least one of the following two ways: the asymmetric inductor parameter configuration method and the series resonant network configuration method; The asymmetric inductor parameter configuration method specifically involves: configuring the total equivalent link inductance to meet the system's rated transmission power requirements. L k Under the design constraints, the equivalent high-frequency inductance of the primary-side port of the isolation stage is... L n The values ​​of n=1, 2, 3, etc., are designed to be minimized, retaining only the transformer leakage inductance. L σ The remaining inductance required to satisfy the total equivalent link inductance is allocated to the secondary port loop of the isolation stage, i.e., the secondary equivalent inductance. L 4 This reduces the input impedance component at the primary port, thus constructing the low-impedance flow channel. The specific configuration method of the series resonant network is as follows: a series resonant design is introduced into the AC circuit of the primary side port of the isolation stage; a resonant capacitor is selected. C r Connected in series to the primary side port, and configured with a capacitance value satisfying equation (1): ; Where fs is the system switching frequency. L 1 The inherent equivalent inductance of the primary side port; utilizing the resonant capacitor C r The primary-side port's inherent equivalent inductance resonates in series with the system's switching frequency; the resonant characteristics are used to cancel out the inductive reactance component of the primary-side port at the switching frequency and its sideband, thus constructing the low-impedance flow channel.

[0010] To address voltage ripple suppression, this invention employs a "primary-side synchronous phase-shift control" strategy (e.g., Figure 2 As shown in the diagram, a power balancing mechanism is introduced based on the common phase shift angle φ. Specifically, this involves first using a voltage closed loop to balance the low-voltage DC bus voltage. V LD With a given value V LD_ref The error is adjusted by PI to generate a common phase shift angle. Secondly, the active power of each phase is balanced through a power balancing loop.P x With three-phase average power P avg The deviation is adjusted by PI to generate a correction amount. Finally, by formula The final synthesis command is obtained. This strategy ensures power balance while maintaining synchronous phase shift, and, combined with the low-impedance flow channel design, achieves natural cancellation of three-phase second-harmonic power fluctuations within the isolation stage.

[0011] Furthermore, in S3 above, the input impedance of the primary side port of the isolation stage at twice the power frequency is significantly less than the capacitive reactance of the DC capacitor of the submodule at twice the power frequency. Specifically, the input impedance of the primary side port of the isolation stage at twice the power frequency is 1 / 10 or less of the capacitive reactance of the DC capacitor of the submodule at twice the power frequency.

[0012] Compared with the prior art, the advantages of this invention are: 1. Solving the DC bus voltage ripple problem from a physical perspective and significantly simplifying system design: This invention constructs a low-impedance flow path for second-harmonic power fluctuations through optimized circuit parameter design, allowing them to naturally cancel each other out across multiple phases, thereby suppressing second-harmonic voltage ripple on the DC capacitors of the sub-modules. This hardware-level suppression scheme directly avoids the reliance of traditional active control on complex compensation algorithms, high-precision sensors, and high-bandwidth communication, significantly reducing controller resource requirements while improving system reliability and robustness.

[0013] 2. Significantly improve power density: Since the second harmonic fluctuation power is guided to the high-frequency side for cancellation, the second harmonic fluctuation power flowing into the DC bus capacitor side is greatly reduced. Therefore, under the premise of meeting the same voltage ripple index, the capacitance value of the DC capacitor of the sub-module can be greatly reduced, thereby reducing the system size and creating conditions for replacing the short-life electrolytic capacitor with a long-life film capacitor.

[0014] 3. Wide topology adaptability: The two implementation paths provided by this invention, namely asymmetric inductor configuration and series resonant network, cover different application scenarios of low leakage inductance and high leakage inductance transformers, respectively. They are suitable for transformer structures with different coupling degrees and have high engineering application value.

[0015] 4. Achieve natural voltage equalization: The electrical connection built based on low impedance design forms a "virtual parallel" effect of DC capacitors in each submodule, which enables the system to have natural voltage equalization capability, simplifies the voltage equalization control strategy, and reduces the risk of module overvoltage due to control failure. Attached Figure Description

[0016] Figure 1 This is a topology diagram of an existing three-phase cascaded high-frequency chain power electronic transformer; Figure 2 This is the block diagram of the primary-side synchronous phase-shift control; Figure 3 This is a schematic diagram of the power distribution of second harmonic fluctuations; Figure 4 This is a circuit diagram of the isolation stage of a power electronic transformer based on an asymmetric inductor configuration design. Figure 5 It uses the Bode plot of the open-loop input impedance of the isolation stage under both traditional and asymmetric designs; Figure 6 These are experimental waveforms of DC capacitor voltage and isolation stage inductor current in a common high-frequency chain power electronic transformer submodule under traditional design. Figure 7 These are experimental waveforms of capacitor voltage and isolation stage inductor current in a common high-frequency chain power electronic transformer submodule under asymmetric design. Figure 8 This is a circuit diagram of the isolation stage of a power electronic transformer with a resonant network configuration; Figure 9 These are experimental waveforms of DC capacitor voltage and isolation stage inductor current in a common high-frequency link power electronic transformer submodule without a resonant network. Figure 10 These are experimental waveforms of the capacitor voltage and isolation stage inductor current of a common high-frequency chain power electronic transformer submodule configured with a resonant network. Detailed Implementation

[0017] The steps of the present invention will be further described in detail below with reference to the accompanying drawings and test examples.

[0018] Example 1: This example is for applications where the leakage inductance of the high-frequency transformer is small or controllable. It employs an "asymmetric inductance parameter configuration method" to construct a low-impedance flow path. For example... Figure 1 As shown, the overall topology of the power electronic transformer described in this embodiment includes two parts: an input stage and an isolation stage. The input stage adopts a three-phase cascaded H-bridge structure, with phases A, B, and C each composed of several cascaded power submodules, and connected to a grid-side filter inductor. L g Connected to a medium-voltage AC power grid; each power submodule contains a single-phase H-bridge circuit and an independent DC support capacitor. C m (m=1, 2, 3, 4). The isolation stage adopts a modular multi-active bridge converter structure, such as... Figure 4The schematic diagram of the isolation stage circuit shown is mainly composed of multiple H-bridge converters on the primary side, a high-frequency transformer T, and an H-bridge converter on the secondary side. Specifically, each primary-side port of the isolation stage is connected to a sub-module DC capacitor of the input stage. The primary-side port contains a full-bridge circuit composed of four switching transistors. The AC output of this full-bridge circuit is connected to the primary winding (N1, N2, N3) of the high-frequency transformer. The secondary winding (N4) of the high-frequency transformer is connected to the AC input of the secondary full-bridge circuit. A secondary DC capacitor is connected in parallel on the DC side of the secondary full-bridge circuit. C 4 It also serves as a low-voltage DC bus to supply power to the load.

[0019] Based on the above circuit structure, this embodiment focuses on the specific design of asymmetric inductor parameters. To verify effectiveness, a rated power... P N Taking a 3 kW prototype as an example, the AC mains voltage is 180 V, the frequency is 50 Hz, and the filter inductor... L g 8mH; DC-side primary capacitance C 1 to C 3 The secondary capacitance is 300 μF. C 4 The value is 2400 μF. Based on the transmission power requirements, the total equivalent link inductance of the system is... L k Approximately 360μH. A key improvement in this embodiment lies in the asymmetric configuration of the inductor: in... Figure 4 In the circuit shown, by optimizing the transformer winding structure, the equivalent high-frequency inductance of the primary winding is reduced. L n (i.e., original edge leakage) L 1 , L 2 , L 3 The value is designed to be minimized in this embodiment. L 1 , L 2 , L 3 It has a capacitance of only 3.5 μH, and no additional independent inductor is connected in series in the loop between the primary full-bridge and the primary winding of the transformer; at the same time, all the remaining inductance required to meet the power transfer is transferred to the secondary side, that is, a large equivalent high-frequency inductor is connected in series between the secondary winding of the transformer and the secondary full-bridge circuit. L 4 Its equivalent sensitivity is designed to be 356.5 μH.

[0020] In conjunction with the above hardware circuit, this embodiment employs the following... Figure 2 The control strategy is shown. The control system mainly consists of a voltage loop and a power loop. First, the secondary low-voltage DC bus voltage is acquired. V LD With a given value V LD_ref The error is adjusted by PI to output a common phase shift angle. First, it serves as the reference synchronization signal for all primary-side H-bridge modules; second, it collects the actual active power of each primary-side port. P x With three-phase average power P avg The error is adjusted by PI to generate a correction value. Ultimately, through the formula... The drive signals for each primary-side H-bridge are synthesized. Through this control, the second harmonic ripple power generated by the input stage is guided into the isolation stage via the low-impedance flow channel on the primary side, and then realized in the high-frequency transformer magnetic circuit as... Figure 3 The multiphase superposition and cancellation shown.

[0021] Figure 5 The impedance characteristic comparison diagram shows the asymmetric design (primary side) used in this embodiment. L n After the impedance of the primary side port is reduced to 3.5 μH, the impedance at 100 Hz is significantly reduced. Figure 6 and Figure 7 The waveform diagram shows the experimental waveforms, from top to bottom: three-phase high-frequency inductor current. iL x (x = 1, 2, 3), DC capacitor voltage of the three-phase submodule v m (m = 1, 2, 3). The comparison shows that compared to the traditional design that places the inductor on the primary side (ripple peak-to-peak value)... V 2ω-pp (39.2 V), after adopting the asymmetric circuit architecture of this embodiment, the peak-to-peak value of the second harmonic ripple of the DC capacitor voltage of the submodule is... V 2ω-pp The voltage dropped to 5.5 V, and the voltage of each module achieved natural balancing, verifying the effectiveness of the circuit topology and parameter configuration.

[0022] Example 2: This example addresses an application scenario with high high-voltage insulation requirements and a large, non-reducible transformer leakage inductance. It employs a "series resonant network configuration method" to construct a low-impedance flow path. For example... Figure 8As shown, the circuit structure of this embodiment is basically the same as that of Embodiment 1, also including a primary-side H-bridge converter connecting the input stage submodule, high-frequency transformers T1, T2, and T3, and a secondary-side H-bridge converter. However, unlike Embodiment 1, this embodiment includes a resonant capacitor configured for the primary-side circuit of the high-frequency transformer. C r .exist Figure 8 In the isolation stage circuit shown, due to the limitation of high-voltage insulation distance, the primary winding of the high-frequency transformer itself has a large inherent leakage inductance. L σ (In this embodiment, it is fixed at 30 μH), and cannot be eliminated directly as in Embodiment 1.

[0023] To overcome the inherent large leakage inductance's obstruction of second harmonic ripple absorption, this embodiment connects a resonant capacitor in series between the AC output terminal of the primary-side H-bridge and the primary winding of the transformer in the AC circuit of each primary-side port of the isolation stage. C r The resonant capacitor C r The parameter design process is as follows: The design goal is to make the resonant capacitor C r The inherent leakage inductance of the transformer primary side L σ The series branch formed by the circuit resonates at the switching frequency fs of the system, thus exhibiting zero impedance characteristics at that frequency.

[0024] In this embodiment, the system switching frequency fs is 10kHz, and the transformer primary side has inherent leakage inductance. L σ The value is 30μH. According to the principle of series resonance, resonance occurs when the inductive reactance and capacitive reactance are equal, which satisfies the formula: ; This leads to the derivation of the resonant capacitance. C r The calculation formula is: fs=10kHz and L σ Substitute 30μH into the above formula to calculate: C r = 8.45uF.

[0025] Based on the above calculation results, this embodiment selects a capacitor with a capacitance of 8.45 μF as the resonant capacitor. C r It is connected in series in the primary circuit. Through this design, although the physical inductance... L k It still exists, but at a switching frequency of 10 kHz, it is affected by the inductor. Lk and capacitor C r The branch impedances cancel each other out, resulting in extremely low impedance characteristics, thus artificially creating a low-impedance flow path to the interior of the isolation stage.

[0026] In conjunction with the above-described hardware circuit, this embodiment uses the same hardware as Embodiment 1. Figure 2 The control strategy shown.

[0027] Its implementation effect is as follows Figure 9 and Figure 10 As shown. Without the resonant capacitor connected. C r hour( Figure 9 Due to the transformer's 30 μH leakage inductance, the primary impedance is relatively high, resulting in a high peak-to-peak value of the second-harmonic voltage ripple in the submodule's DC capacitor. V 2ω-pp Up to 16.4 V; and a resonant capacitor is connected in series in the circuit. C r back( Figure 10 The resonant branch successfully counteracted the effect of leakage inductance, breaking through the bottleneck of second harmonic power flow and reducing the peak-to-peak value of the second harmonic voltage ripple. V 2ω-pp The voltage dropped significantly to 4.3 V, a decrease of 73.8%. This indicates that by adding a series resonant network to the circuit, it is also possible to achieve natural voltage balance and ripple suppression for each submodule, making it suitable for applications with high leakage inductance transformers.

[0028] The above embodiments have provided a detailed description of the technical solution of the present invention. Obviously, the present invention is not limited to the described embodiments. Based on the embodiments of the present invention, those skilled in the art can make various modifications, but any modifications that are equivalent to or similar to the present invention fall within the scope of protection of the present invention.

[0029] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

[0030] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A design method for suppressing second-harmonic voltage ripple in power electronic transformers, characterized in that, This design method is applied to power electronic transformers, which include an input stage and an isolation stage. The input stage adopts a multi-phase cascaded topology, with each phase containing several sub-modules equipped with DC capacitors. The isolation stage connects the sub-modules of the input stage and achieves electrical coupling between the multiple phases through a high-frequency AC path. The design method includes the following steps: S1: Establish an impedance model for the primary side port of the isolation stage and the DC capacitor of the submodule in parallel; S2: Based on the principle of impedance shunt, the isolation stage is planned and configured as a low-impedance flow channel for second harmonic fluctuation power; S3: Design the circuit parameters of the primary side port of the isolation stage so that the input impedance of the primary side port of the isolation stage at twice the power frequency is significantly less than the capacitive reactance of the DC capacitor of the submodule at twice the power frequency, thereby realizing the hardware construction of the low impedance flow channel. S4: Through the low-impedance flow channel, the multiphase second harmonic fluctuation power generated by the input stage is guided to flow preferentially into the isolation stage, and the multiphase fluctuation power is naturally superimposed and canceled on the high-frequency AC path, suppressing the second harmonic voltage ripple on the DC capacitor of the submodule, and at the same time achieving the natural balance of the DC capacitor voltage of each submodule.

2. The design method for suppressing second harmonic voltage ripple in power electronic transformers according to claim 1, characterized in that, In step S3, the low-impedance flow channel is constructed in at least one of the following two ways: asymmetric inductor parameter configuration method and series resonant network configuration method; The asymmetric inductor parameter configuration method specifically involves: configuring the total equivalent link inductance to meet the system's rated transmission power requirements. L k Under the design constraints, the equivalent high-frequency inductance of the primary-side port of the isolation stage is... L n The values ​​of n=1, 2, 3, etc., are designed to be minimized, retaining only the transformer leakage inductance. L σ The remaining inductance required to satisfy the total equivalent link inductance is allocated to the secondary port loop of the isolation stage, i.e., the secondary equivalent inductance. L 4 This reduces the input impedance component at the primary port, thus constructing the low-impedance flow channel. The specific configuration method of the series resonant network is as follows: a series resonant design is introduced into the AC circuit of the primary side port of the isolation stage; a resonant element is selected and connected in series with the primary side port, and its parameters are configured to resonate with the inherent equivalent inductance of the primary side port at the switching frequency of the system; the resonant characteristics are used to cancel the input impedance components of the primary side port at the switching frequency and its sideband, thereby constructing the low-impedance flow channel.

3. The design method for suppressing second-harmonic voltage ripple in power electronic transformers according to claim 1, characterized in that, It also includes supporting control steps for suppressing the second harmonic voltage ripple of the submodule: controlling multiple primary-side ports of the isolation stage to use primary-side synchronous phase-shift control, first generating a common phase-shift angle through a voltage closed loop, then correcting the phase-shift angle of each primary-side port through a power balancing loop, configuring the drive signal of each primary-side port based on the same common phase-shift angle and with a power correction amount; through the synchronous phase-shift control in conjunction with the low-impedance flow channel constructed in step S3, guiding the multiphase second harmonic fluctuation power to achieve precise superposition and cancellation in the high-frequency AC path of the isolation stage.

4. The design method for suppressing second harmonic voltage ripple in power electronic transformers according to claim 2, characterized in that, In the series resonant network configuration method, the resonant capacitor Cr The capacitance value and the inherent equivalent inductance of the primary side port L 1 Satisfies the series resonance relation (1): ； Where fs is the switching frequency of the system, and through the resonant capacitor Cr The inductance of the primary side port resonates in series with the inherent equivalent inductance of the primary side port at the switching frequency, thus canceling out the inductive reactance component of the primary side port at the switching frequency and its sideband.

5. The design method for suppressing second-harmonic voltage ripple in power electronic transformers according to claim 3, characterized in that, The primary-side synchronous phase-shift control is specifically implemented as follows: First, through a voltage closed loop, the low-voltage DC bus voltage is controlled. V LD With a given value V LD_ref The error is adjusted by PI to generate a common phase shift angle. Secondly, the active power of each phase is balanced through a power balancing loop. P x With three-phase average power P avg The deviation is adjusted by PI to generate a correction amount. Finally, by formula The final synthesized command achieves power balance across all phases while maintaining phase shift synchronization at each primary-side port.

6. The design method for suppressing second harmonic voltage ripple in power electronic transformers according to claim 1, characterized in that, In S3, the input impedance of the primary side port of the isolation stage at twice the power frequency is significantly less than the capacitive reactance of the DC capacitor of the submodule at twice the power frequency. Specifically, the input impedance of the primary side port of the isolation stage at twice the power frequency is less than 1 / 10 of the capacitive reactance of the DC capacitor of the submodule at twice the power frequency.

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