A redundant drive circuit for motor controllers and limp-home control method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HEFEI JUYI POWER SYST CO LTD
- Filing Date
- 2026-04-27
- Publication Date
- 2026-07-21
Smart Images
Figure CN122437461A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of new energy vehicle motor control technology, and in particular to a redundant drive circuit for a motor controller and a limp-home control method. Background Technology
[0002] With the rapid development of new energy vehicles and drive-by-wire chassis technology, the functional safety requirements for motor controllers, as core drive units, are becoming increasingly stringent, needing to meet international standards for functional safety of road vehicles such as ISO 26262. In three-phase AC motor drive systems, the main control chip typically needs to output six pulse-width modulation signals to control the on / off switching of six power switching devices in the three-phase inverter, thereby achieving precise regulation of motor torque and speed.
[0003] In practical applications, the main control chip may malfunction, such as crashing, abnormal output signals, or complete failure, due to electromagnetic interference, power fluctuations, software glitches, or hardware aging. Once the main control chip fails, the motor will instantly lose torque output, causing a power interruption in the vehicle and easily leading to a safety accident of loss of vehicle control. Therefore, how to achieve emergency safety control of the motor when the main control chip fails, enabling the vehicle to limp home at a low speed, has become a technical problem that urgently needs to be solved in this field.
[0004] Currently, motor safety control solutions for main control chip failures can be mainly divided into the following two categories: One approach is the watchdog reset scheme. This scheme uses a hardware watchdog circuit to monitor the main control chip's operating status in real time. When a fault such as a system crash or software malfunction is detected, a reset operation is triggered to attempt to restore the main control chip to normal operation. However, the watchdog reset scheme has a significant reset time delay problem. During the reset process, the main control chip cannot output a valid pulse width modulation signal, and the motor will instantly lose torque output, resulting in a power interruption. If the vehicle is traveling at high speed at this time, the power interruption will directly cause serious safety hazards. In addition, if the main control chip suffers an unrecoverable hardware failure, repeated resets will not restore it to normal operation, and the motor will remain in an uncontrolled state. Therefore, this scheme is difficult to meet the requirements of high functional safety levels.
[0005] The second approach is a redundant master control chip solution. This solution adds a backup master control chip to the motor controller, forming a dual-chip redundant control architecture with the primary master control chip. When the primary master control chip fails, the backup master control chip takes over the control of the motor, maintaining its basic operation. However, the redundant master control chip solution has higher hardware costs, as adding a backup master control chip directly increases material costs. Furthermore, the backup master control chip still requires the development of complete motor drive control software, increasing the complexity of system development, debugging, and maintenance. In addition, since both the primary and backup master control chips run software programs, there is a risk that both may fail simultaneously due to a shared software failure, making it impossible to completely eliminate the potential for software-level fault propagation.
[0006] More importantly, the overall drive logic of existing technical solutions is highly dependent on the software algorithms of the main control chip. The generation of the three-phase drive timing, the stator winding energization pattern, and torque regulation for a three-phase AC motor all require the main control chip to calculate the rotor position and phase sequence via software. When the main control chip completely fails due to power supply abnormalities or hardware malfunctions, the aforementioned emergency solutions relying on software logic will be completely ineffective. Existing motor controller hardware merely serves as the execution carrier for the main control chip's software instructions; it lacks an independent, purely hardware-based redundant drive circuit designed specifically for the three-phase drive characteristics of the stator windings of a three-phase AC motor. This results in a lack of independent hardware-level emergency drive mechanisms in the event of a complete failure of the main control chip, and insufficient functional safety protection layers.
[0007] Furthermore, existing emergency control schemes do not adequately consider secondary fault protection at the hardware level during fault switching. For example, during drive signal switching or emergency drive signal generation, if there is insufficient dead time between the drive signals of the upper and lower bridge arms, the upper and lower power transistors of the same bridge arm of the inverter may conduct simultaneously, causing a bridge arm shoot-through fault, generating a large instantaneous current, and further damaging the motor controller hardware and the motor itself. Simultaneously, the lack of an effective overcurrent protection mechanism during emergency operation may also lead to overheating of the motor due to abnormal load, causing secondary damage.
[0008] Therefore, how to provide a redundant drive circuit and limp-home control method that is independent of the main control chip software logic, cost-controllable, fast-responding, and has hardware-level security protection has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0009] To address the technical problems existing in the background art, this invention proposes a redundant drive circuit for a motor controller and a limp-home control method.
[0010] The present invention proposes a redundant drive circuit for a motor controller, comprising: The signal monitoring module is used to monitor whether the dog feed signal output by the main control chip is in a transition state, and outputs a fault detection signal when the dog feed signal is not transitioning or is at a fixed level; The fault latching and logic switching module is used to receive and latch fault detection signals to generate limp mode enable signals. A fixed duty cycle oscillator is used to start and generate a fixed carrier signal with a preset frequency and a preset duty cycle when a limp mode enable signal is received. The three-phase timing generator has its enable terminal connected to the output terminal of the fault latch and logic switching module, and its clock input terminal connected to the output terminal of the fixed duty cycle oscillator. It is used to generate six redundant drive signals with a 120-degree phase difference through hardware logic when the limp mode enable signal is valid and a fixed carrier signal is received. The gate driver multiplexer has a first signal input terminal, a second signal input terminal, a control terminal, and an output terminal. Its first signal input terminal is used to receive six main control drive signals output by the main control chip. Its second signal input terminal is connected to the output terminal of the three-phase timing generator to receive six redundant drive signals. Its control terminal is connected to the output terminal of the fault latch and logic switching module, and is used to select six main control drive signals or six redundant drive signals to be output to the subsequent gate driver chip under the control of the limp mode enable signal.
[0011] Preferably, the signal monitoring module includes a window watchdog chip, wherein the watchdog signal input pin of the window watchdog chip serves as the input terminal of the signal monitoring module to receive the watchdog signal, and the reset signal output pin of the window watchdog chip serves as the output terminal of the signal monitoring module to output a fault detection signal.
[0012] Preferably, the fault latching and logic switching module includes an RS flip-flop composed of NAND gates. The set input of the RS flip-flop is connected to the output of the signal monitoring module to receive a fault detection signal. The output of the RS flip-flop serves as the output of the fault latching and logic switching module to output a limp-mode enable signal. The reset input of the RS flip-flop receives a reset signal from the main control chip.
[0013] Preferably, the fixed duty cycle oscillator includes a 555 timer chip configured as an astable multivibrator, the reset terminal of the 555 timer chip serves as the enable terminal of the fixed duty cycle oscillator, and the output terminal of the 555 timer chip serves as the output terminal of the fixed duty cycle oscillator; by configuring the external resistor and capacitor parameters of the 555 timer chip, the frequency of the fixed carrier signal is set to between 50Hz and 100Hz, and the duty cycle is set to between 10% and 15%.
[0014] Preferably, the three-phase timing generator specifically includes: A ring counter, whose clock input is used as the clock input of a three-phase timing generator to receive a fixed carrier signal, and whose enable is used as the enable of the three-phase timing generator, is configured as a hexadecimal counter to cyclically output high-level pulses on its first to sixth outputs. The first OR gate has its two input terminals connected to the first and fourth output terminals of the ring counter, respectively, and its output terminal is used to output the first phase upper bridge arm drive signal. The second OR gate has its two input terminals connected to the second and fifth output terminals of the ring counter, respectively, and its output terminal is used to output the second phase upper bridge arm drive signal. The third OR gate has its two input terminals connected to the third and sixth output terminals of the ring counter, respectively, and its output terminal is used to output the third phase upper bridge arm drive signal. The circuit consists of a first RC delay circuit, a second RC delay circuit, and a third RC delay circuit. The input terminal of the first RC delay circuit is connected to the output terminal of the first OR gate, the input terminal of the second RC delay circuit is connected to the output terminal of the second OR gate, and the input terminal of the third RC delay circuit is connected to the output terminal of the third OR gate. The first NOT gate, the second NOT gate, and the third NOT gate are connected. The input of the first NOT gate is connected to the output of the first RC delay circuit, the input of the second NOT gate is connected to the output of the second RC delay circuit, and the input of the third NOT gate is connected to the output of the third RC delay circuit. The outputs of the first NOT gate, the second NOT gate, and the third NOT gate are used to output the first phase lower bridge arm drive signal, the second phase lower bridge arm drive signal, and the third phase lower bridge arm drive signal, respectively. Among them, the first phase upper arm drive signal, the second phase upper arm drive signal, the third phase upper arm drive signal, the first phase lower arm drive signal, the second phase lower arm drive signal, and the third phase lower arm drive signal together constitute six redundant drive signals.
[0015] Preferably, the system further includes an overcurrent threshold comparison module. The first input terminal of the overcurrent threshold comparison module is connected to the phase current sensor of the external inverter to obtain the phase current sampling voltage. The second input terminal of the overcurrent threshold comparison module is connected to a preset overcurrent reference voltage source. The output terminal of the overcurrent threshold comparison module is connected to the clock enable terminal of the ring counter. When the phase current sampling voltage exceeds the preset overcurrent reference voltage, the overcurrent threshold comparison module outputs an overcurrent blocking signal to the clock enable terminal to disable the clock input of the ring counter.
[0016] Preferably, the gate driver multiplexer includes six tri-state buffers. The input pins of the six tri-state buffers are respectively connected to one of the six main control drive signals. The output pins of the six tri-state buffers are connected in parallel with one of the six redundant drive signals to serve as the six output terminals of the gate driver multiplexer. The input enable pins of the six tri-state buffers are connected to the limp mode enable signal.
[0017] The present invention proposes a limp-home control method for a redundant drive circuit of a motor controller, applicable to the redundant drive circuit of a motor controller as described in any of the above claims, the method comprising the following steps: S1. The signal monitoring module obtains the dog feed signal output by the main control chip, processes the dog feed signal and determines whether it is in a transition state, and obtains and outputs the fault detection signal when the determination result is no transition or fixed level. S2. Obtain the fault detection signal from the fault latching and logic switching module, process the fault detection signal and latch it, and obtain and output the limp mode enable signal. S3. Obtain the limp mode enable signal from the fixed duty cycle oscillator, start and generate a fixed carrier signal according to the limp mode enable signal, and obtain and output the fixed carrier signal; S4. The limp mode enable signal and fixed carrier signal are obtained by the three-phase timing generator. The fixed carrier signal is subjected to hardware frequency division and logic combination processing to obtain and output six redundant drive signals with a 120-degree phase difference. S5. The gate driver multiplexer obtains the six main control drive signals, six redundant drive signals and limp mode enable signal output by the main control chip. Based on the limp mode enable signal, the six redundant drive signals are selected to replace the six main control drive signals. The switched six redundant drive signals are obtained and output to the subsequent gate driver chip. S6. Drive an external three-phase inverter through six redundant drive signals to enable the motor to run in limp mode with fixed torque and fixed speed. The fixed torque corresponds to the preset duty cycle of the fixed carrier signal, and the fixed speed corresponds to the preset frequency of the fixed carrier signal, thus achieving the function of limping the vehicle home.
[0018] Preferably, step S4 specifically includes: A fixed carrier signal is obtained as a clock input from the ring counter in the three-phase timing generator. The pulses of the fixed carrier signal are cyclically counted to obtain and output six pulse signals that are cyclically set high in sequence. The pulse signals output from the first and fourth output terminals of the ring counter are obtained by the first OR gate and processed by logical OR to obtain the first phase upper bridge arm drive signal; the pulse signals output from the second and fifth output terminals of the ring counter are obtained by the second OR gate and processed by logical OR to obtain the second phase upper bridge arm drive signal; the pulse signals output from the third and sixth output terminals of the ring counter are obtained by the third OR gate and processed by logical OR to obtain the third phase upper bridge arm drive signal. The first phase upper bridge arm drive signal, the second phase upper bridge arm drive signal, and the third phase upper bridge arm drive signal are obtained by the first RC delay circuit, the second RC delay circuit, and the third RC delay circuit, respectively, and are delayed to obtain the delayed three upper bridge arm drive signals. The first NOT gate, the second NOT gate, and the third NOT gate respectively obtain the delayed three-phase lower bridge arm drive signals and perform inversion processing to obtain the first phase lower bridge arm drive signal, the second phase lower bridge arm drive signal, and the third phase lower bridge arm drive signal. The first phase upper arm drive signal, the second phase upper arm drive signal, the third phase upper arm drive signal, the first phase lower arm drive signal, the second phase lower arm drive signal, and the third phase lower arm drive signal are collectively output as six redundant drive signals.
[0019] Preferably, it further includes: During the execution of step S6, the overcurrent threshold comparison module obtains the phase current sampling voltage and the preset overcurrent reference voltage output by the inverter, processes and compares the magnitude of the phase current sampling voltage and the preset overcurrent reference voltage. When the comparison result is that the phase current sampling voltage is greater than the preset overcurrent reference voltage, an overcurrent blocking signal is obtained and output to the clock enable terminal of the three-phase timing generator to block the output of the six redundant drive signals.
[0020] The redundant drive circuit and limp-home control method for motor controllers proposed in this invention construct a pure hardware redundant drive architecture that is completely independent of the main control chip's software logic. With the synergistic effect of the signal monitoring module, fault latching and logic switching module, fixed duty cycle oscillator, three-phase timing generator, gate drive multiplexer, and overcurrent threshold comparison module, it achieves microsecond-level hardware seamless switching and emergency drive control in the event of a main control chip failure. This eliminates the risk of emergency control failure caused by software crashes, system freezes, or power supply anomalies, and improves the functional safety level of the motor controller. The three-phase timing generator utilizes a pure hardware combination of a ring counter and combinational logic circuits to generate six redundant drive signals with a natural 120-degree phase difference and hardware dead-time protection, without requiring any software algorithms or rotor position sensors. This precisely adapts to the stator winding drive characteristics of a three-phase AC motor, achieving true open-loop fixed torque redundant drive. Simultaneously, the integrated RC dead-time delay control and overcurrent threshold comparison blocking mechanism effectively prevent bridge arm shoot-through and motor overcurrent in limp-mode, providing multiple hardware-level safety protections for the inverter, motor, and controller from the drive signal generation source. Furthermore, it is constructed entirely with general-purpose discrete components, eliminating the need for additional commercial main control chips and their accompanying software development, reducing hardware material and system development costs. Its modular circuit design allows for direct integration as a daughter card into existing motor controller main control boards without significant modifications to the original circuitry, offering strong versatility and convenient integration. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of a redundant drive circuit for a motor controller proposed in this invention. Figure 2 This is a circuit diagram of a signal monitoring module for a redundant drive circuit of a motor controller proposed in this invention. Figure 3 This is a circuit diagram of a fault latching and logic switching module for a redundant drive circuit of a motor controller proposed in this invention. Figure 4 This is a circuit diagram of a fixed duty cycle oscillator for a redundant drive circuit of a motor controller, as proposed in this invention. Figure 5 This is a schematic diagram of a three-phase timing generator for a redundant drive circuit of a motor controller proposed in this invention. Figure 6 This is a circuit diagram of a gate drive multiplexer for a redundant drive circuit of a motor controller proposed in this invention. Figure 7 This is a circuit diagram of an overcurrent threshold comparison module for a redundant drive circuit of a motor controller proposed in this invention. Figure 8 This is a flowchart illustrating the limp-home control method for a redundant drive circuit in a motor controller proposed in this invention. Detailed Implementation
[0022] Reference Figures 1-7 The present invention proposes a redundant drive circuit for a motor controller, comprising: The signal monitoring module is used to monitor whether the dog feed signal output by the main control chip is in a transition state, and outputs a fault detection signal when the dog feed signal is not transitioning or is at a fixed level.
[0023] Specifically, such as Figure 2 As shown, the core component of this signal monitoring module is the window watchdog chip U1, specifically the TPS3813. The watchdog signal input pin WDI of the window watchdog chip U1 serves as the input terminal of the signal monitoring module, used to receive the feed signal WDG output by the main control chip. The reset signal output pin RST of the window watchdog chip U1 serves as the output terminal of the signal monitoring module, used to output the fault detection signal WDG_FLT. The power supply pin VDD of the window watchdog chip U1 is connected to the system backup power supply 5V_EM, and the ground pin GND is grounded. A timing capacitor C1 is configured around the window watchdog chip U1 to set the watchdog timeout threshold; for example, the timeout threshold can be set to 100ms by adjusting the capacitor parameters. A filter capacitor C2 is also connected in parallel at the power supply pin to improve power supply stability.
[0024] It should be noted that the signal monitoring module works as follows: When the main control chip is working normally, it continuously outputs a watchdog signal WDG with transition characteristics. This signal continuously triggers the window watchdog chip U1, keeping it in normal monitoring mode. At this time, the RST pin outputs a high-level signal. When the main control chip crashes, experiences software malfunctions, or suffers a power supply failure, the watchdog signal WDG will no longer transition or will present a fixed level. If the window watchdog chip U1 does not detect a valid transition within the set timeout threshold, it triggers its internal logic, causing its RST pin to output a low-level fault detection signal WDG_FLT. This fault detection signal will be transmitted to the subsequent fault latching and logic switching module.
[0025] In this embodiment, the signal monitoring module includes a window watchdog chip. The watchdog signal input pin of the window watchdog chip serves as the input terminal of the signal monitoring module to receive the watchdog feed signal, and the reset signal output pin of the window watchdog chip serves as the output terminal of the signal monitoring module to output a fault detection signal.
[0026] The fault latching and logic switching module is used to receive and latch fault detection signals to generate limp mode enable signals.
[0027] In this embodiment, the fault latching and logic switching module includes an RS flip-flop composed of NAND gates. The set input of the RS flip-flop is connected to the output of the signal monitoring module to receive a fault detection signal. The output of the RS flip-flop serves as the output of the fault latching and logic switching module to output a limp-mode enable signal. The reset input of the RS flip-flop receives a reset signal from the main control chip.
[0028] Specifically, such as Figure 3 As shown, the core component of the fault latching and logic switching module is an RS flip-flop composed of NAND gates, specifically using NAND gate chip U2, which can be of model RS4G00XP. The set input of this RS flip-flop, i.e., the first pin of NAND gate U2, is connected to the output of the signal monitoring module to receive the fault detection signal WDG_FLT. The output of the RS flip-flop, i.e., the third pin of NAND gate U2, serves as the output of the fault latching and logic switching module, used to output the limp mode enable signal Limp_Enable. The reset input of the RS flip-flop, i.e., the tenth pin of NAND gate U2, receives the reset signal DSP_RST from the main control chip through an inverting drive circuit composed of transistor Q1 and resistors R7 and R8. At the third output pin, a current-limiting resistor R6 is also connected to the cathode of the fault indicator LED1. The anode of LED1 is connected to the system backup power supply 5V_EM, used to illuminate the alarm when the limp mode enable signal is valid.
[0029] It should be noted that the fault latching and logic switching module works as follows: When the fault detection signal WDG_FLT output by the signal monitoring module is low, the RS flip-flop is set, and its third output pin outputs and latches a high-level limp mode enable signal Limp_Enable. This limp mode enable signal is the control center of the entire redundant drive circuit, and it performs three functions simultaneously: first, it enables the fixed duty cycle oscillator and three-phase timing generator in the subsequent stage; second, it controls the gate drive multiplexer to cut off the main control drive signal channel; and third, it illuminates the fault indicator LED1 to indicate that it is currently in limp mode. Because the RS flip-flop is used to latch the fault signal, erroneous switching caused by signal jitter can be effectively avoided. When the system needs to return to normal mode, the reset signal DSP_RST output by the main control chip is high, turning on transistor Q1 and pulling the tenth reset pin of the RS flip-flop low, clearing the flip-flop, restoring the limp mode enable signal Limp_Enable to low, and deactivating the limp mode.
[0030] A fixed duty cycle oscillator is used to start and generate a fixed carrier signal with a preset frequency and preset duty cycle when a limp mode enable signal is received.
[0031] In this embodiment, the fixed duty cycle oscillator includes a 555 timer chip configured as an astable multivibrator. The reset terminal of the 555 timer chip serves as the enable terminal of the fixed duty cycle oscillator, and the output terminal of the 555 timer chip serves as the output terminal of the fixed duty cycle oscillator. By configuring the external resistor and capacitor parameters of the 555 timer chip, the frequency of the fixed carrier signal is set between 50Hz and 100Hz, and the duty cycle is set between 10% and 15%.
[0032] Specifically, such as Figure 4 As shown, the core component of the fixed duty cycle oscillator is a 555 timer chip U3 configured as an astable multivibrator, specifically the SE555. The fourth pin of the 555 timer chip U3 serves as the enable pin for the fixed duty cycle oscillator, connected to the output of the fault latch and logic switching module to receive the limp-mode enable signal Limp_Enable. The eighth pin of the 555 timer chip U3's power supply is connected to the system backup power supply 5V_EM, the first pin is grounded, and the third pin serves as the output of the fixed duty cycle oscillator, used to output the fixed carrier signal PWM_FIX. By configuring the parameters of the external resistors R9 and R10 and the timing capacitor C5 of the 555 timer chip U3, the frequency of the fixed carrier signal PWM_FIX can be set between 50Hz and 100Hz, and the duty cycle between 10% and 15%. The fifth pin of the chip is grounded through the filter capacitor C6.
[0033] Specifically, the fixed duty cycle oscillator operates as follows: In normal mode, the limp mode enable signal Limp_Enable is low. This low-level signal is applied to the fourth pin of the reset terminal of the 555 timer chip U3, keeping the internal circuitry of the chip in a reset state. The third output pin has no signal output, and the fixed carrier signal PWM_FIX remains low. When the limp mode enable signal Limp_Enable transitions to a high level, the reset terminal of the 555 timer chip U3 is released, the oscillator starts, and the third output pin outputs a fixed carrier signal PWM_FIX with a preset frequency and preset duty cycle. The low-frequency and low-duty-cycle design aims to strictly limit the average operating current of the motor stator windings, ensuring it does not exceed 20% of the motor's rated current. This effectively avoids overcurrent heating of the motor and power devices while guaranteeing the small torque required for limp mode output.
[0034] The three-phase timing generator has its enable terminal connected to the output terminal of the fault latch and logic switching module, and its clock input terminal connected to the output terminal of the fixed duty cycle oscillator. It is used to generate six redundant drive signals with a 120-degree phase difference through hardware logic when the limp mode enable signal is valid and a fixed carrier signal is received.
[0035] In this embodiment, the three-phase timing generator specifically includes: A ring counter, whose clock input is used as the clock input of a three-phase timing generator to receive a fixed carrier signal, and whose enable is used as the enable of the three-phase timing generator, is configured as a hexadecimal counter to cyclically output high-level pulses on its first to sixth outputs. The first OR gate has its two input terminals connected to the first and fourth output terminals of the ring counter, respectively, and its output terminal is used to output the first phase upper bridge arm drive signal. The second OR gate has its two input terminals connected to the second and fifth output terminals of the ring counter, respectively, and its output terminal is used to output the second phase upper bridge arm drive signal. The third OR gate has its two input terminals connected to the third and sixth output terminals of the ring counter, respectively, and its output terminal is used to output the third phase upper bridge arm drive signal. The circuit consists of a first RC delay circuit, a second RC delay circuit, and a third RC delay circuit. The input terminal of the first RC delay circuit is connected to the output terminal of the first OR gate, the input terminal of the second RC delay circuit is connected to the output terminal of the second OR gate, and the input terminal of the third RC delay circuit is connected to the output terminal of the third OR gate. The first NOT gate, the second NOT gate, and the third NOT gate are connected. The input of the first NOT gate is connected to the output of the first RC delay circuit, the input of the second NOT gate is connected to the output of the second RC delay circuit, and the input of the third NOT gate is connected to the output of the third RC delay circuit. The outputs of the first NOT gate, the second NOT gate, and the third NOT gate are used to output the first phase lower bridge arm drive signal, the second phase lower bridge arm drive signal, and the third phase lower bridge arm drive signal, respectively. Among them, the first phase upper arm drive signal, the second phase upper arm drive signal, the third phase upper arm drive signal, the first phase lower arm drive signal, the second phase lower arm drive signal, and the third phase lower arm drive signal together constitute six redundant drive signals.
[0036] In this embodiment, an overcurrent threshold comparison module is also included. The first input terminal of the overcurrent threshold comparison module is connected to the phase current sensor of the external inverter to obtain the phase current sampling voltage. The second input terminal of the overcurrent threshold comparison module is connected to a preset overcurrent reference voltage source. The output terminal of the overcurrent threshold comparison module is connected to the clock enable terminal of the ring counter. When the phase current sampling voltage exceeds the preset overcurrent reference voltage, the overcurrent threshold comparison module outputs an overcurrent blocking signal to the clock enable terminal to disable the clock input of the ring counter.
[0037] Specifically, such as Figure 5As shown, the three-phase timing generator mainly includes a ring counter U4, a first OR gate U5, a second OR gate U6, a third OR gate U7, a first RC delay circuit, a second RC delay circuit, a third RC delay circuit, a first NOT gate, a second NOT gate, and a third NOT gate. The ring counter U4 can be a CD4017B, and each OR gate can be an RS1G32.
[0038] The fourteenth pin of the clock input terminal of the ring counter U4 serves as the clock input terminal of the three-phase timing generator, connected to the output terminal of the fixed duty cycle oscillator to receive the fixed carrier signal PWM_FIX. The thirteenth pin of the ring counter U4 serves as the enable terminal of the three-phase timing generator, connected to the output terminal of the fault latch and logic switching module to receive the limp mode enable signal Limp_Enable. This enable terminal also receives the overcurrent blocking signal TH_OC from the overcurrent threshold comparison module. The fifteenth pin of the reset terminal of the ring counter U4 is connected to its tenth pin of its fifth output terminal, configuring the ring counter U4 as a hexadecimal counter, causing it to sequentially output high-level pulses on the third pin of the first output terminal, the second pin of the second output terminal, the fourth pin of the third output terminal, the seventh pin of the fourth output terminal, the tenth pin of the fifth output terminal, and the first pin of the sixth output terminal. Each output terminal is equipped with a pull-down resistor.
[0039] The two inputs of the first OR gate U5 are connected to the first and fourth outputs of the ring counter U4, respectively, and its output is used to output the first phase upper bridge arm drive signal PWM_UT. The two inputs of the second OR gate U6 are connected to the second and fifth outputs of the ring counter U4, respectively, and its output is used to output the second phase upper bridge arm drive signal PWM_VT. The two inputs of the third OR gate U7 are connected to the third and sixth outputs of the ring counter U4, respectively, and its output is used to output the third phase upper bridge arm drive signal PWM_WT.
[0040] The input of the first RC delay circuit is connected to the output of the first OR gate U5, the input of the second RC delay circuit is connected to the output of the second OR gate U6, and the input of the third RC delay circuit is connected to the output of the third OR gate U7. Each RC delay circuit consists of resistors and capacitors. The dead time can be set by adjusting the parameters of the resistors and capacitors, for example, to 6µs.
[0041] The input of the first NOT gate is connected to the output of the first RC delay circuit, and its output is used to output the first phase lower bridge arm drive signal PWM_UB. The input of the second NOT gate is connected to the output of the second RC delay circuit, and its output is used to output the second phase lower bridge arm drive signal PWM_VB. The input of the third NOT gate is connected to the output of the third RC delay circuit, and its output is used to output the third phase lower bridge arm drive signal PWM_WB. Figure 5 As shown, each NOT gate is made up of transistors connected together.
[0042] The aforementioned first phase upper bridge arm drive signal PWM_UT, second phase upper bridge arm drive signal PWM_VT, third phase upper bridge arm drive signal PWM_WT, first phase lower bridge arm drive signal PWM_UB, second phase lower bridge arm drive signal PWM_VB, and third phase lower bridge arm drive signal PWM_WB together constitute six redundant drive signals.
[0043] Specifically, the three-phase timing generator works as follows: In limp mode, the limp mode enable signal Limp_Enable is high, and the fixed carrier signal PWM_FIX is input as the clock signal to the clock input of the ring counter U4. For each clock pulse received, the ring counter U4 sequentially outputs a high-level pulse from its first to sixth outputs. The high-level pulses from the first and fourth outputs are logically ORed by the first OR gate U5 to generate the first phase upper bridge arm drive signal PWM_UT. Similarly, the second and third OR gates U6 and U7 generate the second and third phase upper bridge arm drive signals PWM_VT and PWM_WT, respectively. Since the six output signals of the ring counter U4 are evenly distributed in time, after the above combination, the generated three upper bridge arm drive signals naturally have a 120-degree phase difference, perfectly matching the drive phase requirements of the three-phase AC motor stator windings. After the three upper bridge arm drive signals are delayed by their respective RC delay circuits, they are inverted by their respective NOT gates to generate the corresponding three lower bridge arm drive signals. The RC delay circuit introduces a preset dead time during the generation of the lower bridge arm drive signal, preventing shoot-through faults caused by the simultaneous conduction of the upper and lower power transistors of the same bridge arm.
[0044] The gate driver multiplexer has a first signal input terminal, a second signal input terminal, a control terminal, and an output terminal. Its first signal input terminal is used to receive six main control drive signals output by the main control chip. Its second signal input terminal is connected to the output terminal of the three-phase timing generator to receive six redundant drive signals. Its control terminal is connected to the output terminal of the fault latch and logic switching module, and is used to select six main control drive signals or six redundant drive signals to be output to the subsequent gate driver chip under the control of the limp mode enable signal.
[0045] Specifically, such as Figure 6As shown, the gate driver multiplexer includes six tri-state buffers U9 to U14, with the 74LVC1G125GW model being a suitable option. Each tri-state buffer has one input pin, one output pin, and one output enable pin. The input pins of the six tri-state buffers are respectively connected to the six main control drive signals DO_PWM output from one main control chip. The output pins of the six tri-state buffers are connected in parallel with the six redundant drive signals output from the corresponding three-phase timing generator, forming the six outputs of the gate driver multiplexer for connection to the inputs of the subsequent gate driver chip. The output enable pins of the six tri-state buffers are all connected to the limp-mode enable signal Limp_Enable. Pull-down resistors and filter capacitors are configured at the input, output, and power supply pins of each signal to filter out signal interference.
[0046] The gate driver multiplexer operates as follows: In normal mode, the limp-mode enable signal Limp_Enable is low. The input enable pins of the six tri-state buffers receive a low level, and each buffer is enabled. The six main control drive signals DO_PWM output by the main control chip are transmitted to the output via the buffers. At this time, the six redundant drive signals output by the three-phase timing generator remain low, not affecting the normal output of the main control drive signals. In limp-mode, the limp-mode enable signal Limp_Enable transitions to a high level. The input enable pins of the six tri-state buffers receive a high level, and the outputs of each buffer exhibit a high impedance state, thus cutting off the transmission path of the main control drive signals. Simultaneously, the three-phase timing generator is activated and outputs six redundant drive signals, which are directly transmitted to the output of the gate driver multiplexer, thereby driving the subsequent gate driver chip. This switching process is entirely controlled by hardware logic, with a response time down to the microsecond level, achieving seamless switching between the main control drive channel and the redundant drive channel.
[0047] In this embodiment, the gate driver multiplexer includes a six-channel tri-state buffer. The input pins of the six-channel tri-state buffer are respectively connected to one of the six main control drive signals. The output pins of the six-channel tri-state buffer are connected in parallel with the corresponding one of the six redundant drive signals to serve as the six output terminals of the gate driver multiplexer. The input enable pins of the six-channel tri-state buffer are all connected to the limp mode enable signal.
[0048] In this embodiment, as Figure 7As shown, the core component of the overcurrent threshold comparison module is comparator U8, specifically the LM2903. The first input terminal of comparator U8, pin 7 (non-inverting input), is connected to the phase current sensor of the external inverter to obtain the phase current sampling voltage Iw_A. The second input terminal of comparator U8, pin 6 (inverting input), is connected to a preset overcurrent reference voltage source. This preset overcurrent reference voltage is obtained by dividing the system backup power supply 5V_EM using a voltage divider circuit composed of resistors R24 and R25, and its voltage value corresponds to 20% of the motor's rated current. The first output terminal of comparator U8 serves as the output terminal of the overcurrent threshold comparison module and is connected to pin 13 (clock enable) of the ring counter U4 to output the overcurrent blocking signal TH_OC.
[0049] The overcurrent threshold comparison module works as follows: During limp-mode operation, comparator U8 compares the phase current sampling voltage Iw_A with the preset overcurrent reference voltage in real time. When the motor is operating normally and the phase current does not exceed the preset threshold, the phase current sampling voltage Iw_A is lower than the preset overcurrent reference voltage, and the first pin of comparator U8 outputs a low-level signal TH_OC. This signal does not affect the normal operation of the ring counter U4. When the phase current exceeds the preset threshold due to abnormal load or other reasons, the phase current sampling voltage Iw_A will be higher than the preset overcurrent reference voltage, comparator U8 flips, and its first pin outputs a high-level overcurrent blocking signal TH_OC. This high-level signal is applied to the thirteenth pin of the clock enable terminal of the ring counter U4, immediately disabling the clock input of the ring counter U4, causing all its output terminals Q0 to Q5 to remain low, thereby blocking the output of all six redundant drive signals. This overcurrent protection mechanism is entirely implemented in hardware, with a fast response speed, and can cut off the drive signal the instant an abnormal overcurrent occurs in the inverter or motor, effectively protecting the safety of power devices and the motor.
[0050] The overall circuit operation of the redundant drive circuit in this embodiment is as follows: In normal mode, the main control chip operates normally, continuously outputting six main control drive signals DO_PWM and one watchdog signal WDG with jumping characteristics. The window watchdog chip U1 in the signal monitoring module is continuously triggered by the watchdog signal, and its output fault detection signal WDG_FLT remains high. The RS flip-flop in the fault latch and logic switching module remains in a cleared state, and its output limp mode enable signal Limp_Enable is low. The fixed duty cycle oscillator remains off due to the low level of the enable terminal, and there is no fixed carrier signal PWM_FIX output. The ring counter U4 in the three-phase timing generator has no clock input, and the six redundant drive signals remain low. The six tri-state buffers in the gate drive multiplexer are in an enabled state, transmitting the six main control drive signals of the main control chip to the subsequent gate drive chip, and the motor is normally controlled by the main control chip.
[0051] When the main control chip crashes, the software malfunctions, or the power supply fails, the watchdog signal WDG remains unchanged or at a fixed level. The window watchdog chip U1 in the signal monitoring module is triggered after the timeout threshold, and the output fault detection signal WDG_FLT changes to a low level. The RS flip-flop in the fault latch and logic switching module is set by this low-level signal, outputting a high-level limp mode enable signal Limp_Enable, and simultaneously lighting up the fault indicator LED1. The fixed duty cycle oscillator starts after receiving the high-level Limp_Enable signal, and outputs a fixed carrier signal PWM_FIX with a preset frequency and preset duty cycle. The ring counter U4 in the three-phase timing generator uses PWM_FIX as the clock source and generates six redundant drive signals with a 120-degree phase difference and dead-time protection through combinational logic composed of OR gates, RC delay circuits, and NOT gates. The six-channel tri-state buffer in the gate drive multiplexer outputs a high-impedance state when its output enable pin receives a low level, cutting off the main control drive signal. The six redundant drive signals are then transmitted unimpeded to the subsequent gate drive chip, driving the three-phase inverter to put the motor into limp mode.
[0052] During limp mode operation, the overcurrent threshold comparison module monitors the phase current in real time. Once an overcurrent is detected, it immediately outputs an overcurrent blocking signal TH_OC to block the drive signal output, thereby achieving hardware-level safety protection.
[0053] When the reset signal DSP_RST of the main control chip is high, the RS flip-flop in the fault latch and logic switching module is cleared, the limp mode enable signal Limp_Enable returns to low, and the circuit deactivates limp mode. If the main control chip has recovered, the system returns to normal mode; if the main control chip has not recovered, the watchdog circuit will be triggered again, and the circuit will re-enter limp mode.
[0054] Reference Figures 1-8 The present invention proposes a limp-home control method for a redundant drive circuit of a motor controller, applicable to any of the redundant drive circuits for a motor controller as described above, the method comprising the following steps: S1. The signal monitoring module obtains the dog feed signal output by the main control chip, processes the dog feed signal and determines whether it is in a transition state, and obtains and outputs the fault detection signal when the determination result is no transition or fixed level.
[0055] S2. The fault detection signal is obtained by the fault latching and logic switching module, the fault detection signal is processed and latched, and the limp mode enable signal is obtained and output.
[0056] S3. Obtain the limp mode enable signal from the fixed duty cycle oscillator, start and generate a fixed carrier signal according to the limp mode enable signal, and obtain and output the fixed carrier signal.
[0057] S4. The limp mode enable signal and the fixed carrier signal are obtained by the three-phase timing generator. The fixed carrier signal is subjected to hardware frequency division and logic combination processing to obtain and output six redundant drive signals with a 120-degree phase difference.
[0058] In this embodiment, step S4 specifically includes: A fixed carrier signal is obtained as a clock input from the ring counter in the three-phase timing generator. The pulses of the fixed carrier signal are cyclically counted to obtain and output six pulse signals that are cyclically set high in sequence. The pulse signals output from the first and fourth output terminals of the ring counter are obtained by the first OR gate and processed by logical OR to obtain the first phase upper bridge arm drive signal; the pulse signals output from the second and fifth output terminals of the ring counter are obtained by the second OR gate and processed by logical OR to obtain the second phase upper bridge arm drive signal; the pulse signals output from the third and sixth output terminals of the ring counter are obtained by the third OR gate and processed by logical OR to obtain the third phase upper bridge arm drive signal. The first phase upper bridge arm drive signal, the second phase upper bridge arm drive signal, and the third phase upper bridge arm drive signal are obtained by the first RC delay circuit, the second RC delay circuit, and the third RC delay circuit, respectively, and are delayed to obtain the delayed three upper bridge arm drive signals. The first NOT gate, the second NOT gate, and the third NOT gate respectively obtain the delayed three-phase lower bridge arm drive signals and perform inversion processing to obtain the first phase lower bridge arm drive signal, the second phase lower bridge arm drive signal, and the third phase lower bridge arm drive signal. The first phase upper arm drive signal, the second phase upper arm drive signal, the third phase upper arm drive signal, the first phase lower arm drive signal, the second phase lower arm drive signal, and the third phase lower arm drive signal are collectively output as six redundant drive signals.
[0059] S5. The gate driver multiplexer obtains the six main control drive signals, six redundant drive signals, and limp mode enable signal output by the main control chip. Based on the limp mode enable signal, the six redundant drive signals are selected to replace the six main control drive signals, and the switched six redundant drive signals are obtained and output to the subsequent gate driver chip.
[0060] S6. Drive the external three-phase inverter through six redundant drive signals so that the motor runs in limp mode with fixed torque and fixed speed. The fixed torque corresponds to the preset duty cycle of the fixed carrier signal, and the fixed speed corresponds to the preset frequency of the fixed carrier signal, thus obtaining the function result of the vehicle limping home.
[0061] In this embodiment, it also includes: During the execution of step S6, the overcurrent threshold comparison module obtains the phase current sampling voltage and the preset overcurrent reference voltage output by the inverter, processes and compares the magnitude of the phase current sampling voltage and the preset overcurrent reference voltage. When the comparison result is that the phase current sampling voltage is greater than the preset overcurrent reference voltage, an overcurrent blocking signal is obtained and output to the clock enable terminal of the three-phase timing generator to block the output of the six redundant drive signals.
[0062] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.
Claims
1. A redundant drive circuit for a motor controller, characterized in that, include: The signal monitoring module is used to monitor whether the dog feed signal output by the main control chip is in a transition state, and outputs a fault detection signal when the dog feed signal is not transitioning or is at a fixed level; The fault latching and logic switching module is used to receive and latch fault detection signals to generate limp mode enable signals. A fixed duty cycle oscillator is used to start and generate a fixed carrier signal with a preset frequency and a preset duty cycle when a limp mode enable signal is received. The three-phase timing generator has its enable terminal connected to the output terminal of the fault latch and logic switching module, and its clock input terminal connected to the output terminal of the fixed duty cycle oscillator. It is used to generate six redundant drive signals with a 120-degree phase difference through hardware logic when the limp mode enable signal is valid and a fixed carrier signal is received. The gate driver multiplexer has a first signal input terminal, a second signal input terminal, a control terminal, and an output terminal. Its first signal input terminal is used to receive six main control drive signals output by the main control chip. Its second signal input terminal is connected to the output terminal of the three-phase timing generator to receive six redundant drive signals. Its control terminal is connected to the output terminal of the fault latch and logic switching module, and is used to select six main control drive signals or six redundant drive signals to be output to the subsequent gate driver chip under the control of the limp mode enable signal.
2. The redundant drive circuit for a motor controller according to claim 1, characterized in that, The signal monitoring module includes a window watchdog chip. The watchdog signal input pin of the window watchdog chip serves as the input terminal of the signal monitoring module to receive the watchdog signal, and the reset signal output pin of the window watchdog chip serves as the output terminal of the signal monitoring module to output a fault detection signal.
3. The redundant drive circuit for a motor controller according to claim 1, characterized in that, The fault latching and logic switching module includes an RS flip-flop composed of NAND gates. The set input of the RS flip-flop is connected to the output of the signal monitoring module to receive a fault detection signal. The output of the RS flip-flop serves as the output of the fault latching and logic switching module to output a limp-mode enable signal. The reset input of the RS flip-flop receives a reset signal from the main control chip.
4. The redundant drive circuit for a motor controller according to claim 1, characterized in that, The fixed duty cycle oscillator includes a 555 timer chip configured as an astable multivibrator. The reset terminal of the 555 timer chip serves as the enable terminal of the fixed duty cycle oscillator, and the output terminal of the 555 timer chip serves as the output terminal of the fixed duty cycle oscillator. By configuring the external resistor and capacitor parameters of the 555 timer chip, the frequency of the fixed carrier signal is set between 50Hz and 100Hz, and the duty cycle is set between 10% and 15%.
5. The redundant drive circuit for a motor controller according to claim 1, characterized in that, The three-phase timing generator specifically includes: A ring counter, whose clock input is used as the clock input of a three-phase timing generator to receive a fixed carrier signal, and whose enable is used as the enable of the three-phase timing generator, is configured as a hexadecimal counter to cyclically output high-level pulses on its first to sixth outputs. The first OR gate has its two input terminals connected to the first and fourth output terminals of the ring counter, respectively, and its output terminal is used to output the first phase upper bridge arm drive signal. The second OR gate has its two input terminals connected to the second and fifth output terminals of the ring counter, respectively, and its output terminal is used to output the second phase upper bridge arm drive signal. The third OR gate has its two input terminals connected to the third and sixth output terminals of the ring counter, respectively, and its output terminal is used to output the third phase upper bridge arm drive signal. The circuit consists of a first RC delay circuit, a second RC delay circuit, and a third RC delay circuit. The input terminal of the first RC delay circuit is connected to the output terminal of the first OR gate, the input terminal of the second RC delay circuit is connected to the output terminal of the second OR gate, and the input terminal of the third RC delay circuit is connected to the output terminal of the third OR gate. The first NOT gate, the second NOT gate, and the third NOT gate are connected. The input of the first NOT gate is connected to the output of the first RC delay circuit, the input of the second NOT gate is connected to the output of the second RC delay circuit, and the input of the third NOT gate is connected to the output of the third RC delay circuit. The outputs of the first NOT gate, the second NOT gate, and the third NOT gate are used to output the first phase lower bridge arm drive signal, the second phase lower bridge arm drive signal, and the third phase lower bridge arm drive signal, respectively. Among them, the first phase upper arm drive signal, the second phase upper arm drive signal, the third phase upper arm drive signal, the first phase lower arm drive signal, the second phase lower arm drive signal, and the third phase lower arm drive signal together constitute six redundant drive signals.
6. The redundant drive circuit for a motor controller according to claim 5, characterized in that, It also includes an overcurrent threshold comparison module. The first input terminal of the overcurrent threshold comparison module is connected to the phase current sensor of the external inverter to obtain the phase current sampling voltage. The second input terminal of the overcurrent threshold comparison module is connected to a preset overcurrent reference voltage source. The output terminal of the overcurrent threshold comparison module is connected to the clock enable terminal of the ring counter. When the phase current sampling voltage exceeds the preset overcurrent reference voltage, the overcurrent threshold comparison module outputs an overcurrent blocking signal to the clock enable terminal to disable the clock input of the ring counter.
7. The redundant drive circuit for a motor controller according to claim 1, characterized in that, The gate driver multiplexer includes six tri-state buffers. The input pins of the six tri-state buffers are respectively connected to one of the six main control drive signals. The output pins of the six tri-state buffers are connected in parallel with one of the six redundant drive signals to serve as the six output terminals of the gate driver multiplexer. The input enable pins of the six tri-state buffers are all connected to the limp mode enable signal.
8. A limp-home control method for a redundant drive circuit in a motor controller, characterized in that, The method, applied to a redundant drive circuit for a motor controller as described in any one of claims 1-7, comprises the following steps: S1. The signal monitoring module obtains the dog feed signal output by the main control chip, processes the dog feed signal and determines whether it is in a transition state, and obtains and outputs the fault detection signal when the determination result is no transition or fixed level. S2. Obtain the fault detection signal from the fault latching and logic switching module, process the fault detection signal and latch it, and obtain and output the limp mode enable signal. S3. Obtain the limp mode enable signal from the fixed duty cycle oscillator, start and generate a fixed carrier signal according to the limp mode enable signal, and obtain and output the fixed carrier signal; S4. The limp mode enable signal and fixed carrier signal are obtained by the three-phase timing generator. The fixed carrier signal is subjected to hardware frequency division and logic combination processing to obtain and output six redundant drive signals with a 120-degree phase difference. S5. The gate driver multiplexer obtains the six main control drive signals, six redundant drive signals and limp mode enable signal output by the main control chip. Based on the limp mode enable signal, the six redundant drive signals are selected to replace the six main control drive signals. The switched six redundant drive signals are obtained and output to the subsequent gate driver chip. S6. Drive an external three-phase inverter through six redundant drive signals to enable the motor to run in limp mode with fixed torque and fixed speed. The fixed torque corresponds to the preset duty cycle of the fixed carrier signal, and the fixed speed corresponds to the preset frequency of the fixed carrier signal, thus achieving the function of limping the vehicle home.
9. The limp-home control method for a redundant drive circuit of a motor controller according to claim 8, characterized in that, Step S4 specifically includes: A fixed carrier signal is obtained as a clock input from the ring counter in the three-phase timing generator. The pulses of the fixed carrier signal are cyclically counted to obtain and output six pulse signals that are cyclically set high in sequence. The pulse signals output from the first and fourth output terminals of the ring counter are obtained by the first OR gate and processed by logical OR to obtain the first phase upper bridge arm drive signal; the pulse signals output from the second and fifth output terminals of the ring counter are obtained by the second OR gate and processed by logical OR to obtain the second phase upper bridge arm drive signal; the pulse signals output from the third and sixth output terminals of the ring counter are obtained by the third OR gate and processed by logical OR to obtain the third phase upper bridge arm drive signal. The first phase upper bridge arm drive signal, the second phase upper bridge arm drive signal, and the third phase upper bridge arm drive signal are obtained by the first RC delay circuit, the second RC delay circuit, and the third RC delay circuit, respectively, and are delayed to obtain the delayed three upper bridge arm drive signals. The first NOT gate, the second NOT gate, and the third NOT gate respectively obtain the delayed three-phase lower bridge arm drive signals and perform inversion processing to obtain the first phase lower bridge arm drive signal, the second phase lower bridge arm drive signal, and the third phase lower bridge arm drive signal. The first phase upper arm drive signal, the second phase upper arm drive signal, the third phase upper arm drive signal, the first phase lower arm drive signal, the second phase lower arm drive signal, and the third phase lower arm drive signal are collectively output as six redundant drive signals.
10. The limp-home control method for a redundant drive circuit of a motor controller according to claim 8, characterized in that, Also includes: During the execution of step S6, the overcurrent threshold comparison module obtains the phase current sampling voltage and the preset overcurrent reference voltage output by the inverter, processes and compares the magnitude of the phase current sampling voltage and the preset overcurrent reference voltage. When the comparison result is that the phase current sampling voltage is greater than the preset overcurrent reference voltage, an overcurrent blocking signal is obtained and output to the clock enable terminal of the three-phase timing generator to block the output of the six redundant drive signals.