Method and system for back-off efficiency optimization under active load modulation and weight interleaving

Abstract

The application relates to a back-off efficiency optimization method and system under active load modulation and weight interleaving, which comprises the following steps: based on a pre-allocated independent subunit, a digital power amplifier unit is configured; the total number of the independent subunits is redundantly set; according to a target output power corresponding to a target digital bit state, corresponding independent subunits are dynamically selected and combined, while the remaining independent subunits are kept off; according to the topological connection structure between the off independent subunits and the output port of the digital power amplifier unit, the equivalent load impedance of the output port of the digital power amplifier unit is determined, so that in the output power back-off state, the equivalent load impedance matches the preset target load impedance. Through the application, the technical problem that the equivalent load impedance of the conducting transistor cannot be dynamically adjusted to maintain the target efficiency matching in the power back-off state in the related art is solved.

Description

Technical Field

[0001] This application relates to the field of power amplifier technology, and in particular to a method and system for optimizing backoff efficiency under active load modulation and weighted interleaving. Background Technology

[0002] With the increasing demands for multi-mode, multi-frequency, and dynamic power allocation in wireless communication systems, the efficiency characteristics of power amplifiers, as the core power consumption unit of transmitters, at different output power levels have become a key area for improvement in system energy efficiency optimization. Especially in operating scenarios requiring frequent power back-off, maintaining high-efficiency power amplifier conversion has become a research hotspot in this field.

[0003] In related technologies, digital power amplifiers typically employ a fixed-structure output matching network, designed with the optimal load impedance at saturated output power as the matching point. When the system needs to reduce transmit power and enter a fallback state, the equivalent output impedance of the transistor changes with the output power. However, the parameters of the subsequent matching network remain constant, causing the actual load impedance of the conducting transistor to deviate from its high-efficiency operating region, resulting in a significant decrease in DC-to-RF conversion efficiency. This efficiency degradation caused by impedance mismatch in the fixed matching network during power fallback severely restricts the overall energy efficiency performance of the transmitter over a wide dynamic power range.

[0004] There is currently no effective solution to the technical problem that the equivalent load impedance of the conducting transistor cannot be dynamically adjusted to maintain the target efficiency match under power back-off conditions. Summary of the Invention

[0005] This application provides a method and system for optimizing backoff efficiency under active load modulation and weighted interleaving, in order to solve the technical problem in the related art that the equivalent load impedance seen by the conducting transistor cannot be dynamically adjusted in the power backoff state to maintain the target efficiency matching.

[0006] In a first aspect, this application provides a method for optimizing backoff efficiency under active load modulation and weighted interleaving, comprising:

[0007] A digital power amplifier unit is configured based on pre-assigned weights for independent sub-units; the total number of the independent sub-units is greater than the number of the independent sub-units that the digital power amplifier unit needs to activate in the maximum output power state.

[0008] Based on the target output power corresponding to the target digital bit state, dynamically select and combine the corresponding independent sub-units to be turned on, while keeping the other independent sub-units off.

[0009] Based on the topological connection structure between the shut-down independent subunit and the output port of the digital power amplifier unit, the equivalent load impedance of the output port of the digital power amplifier unit is determined so that the equivalent load impedance matches the preset target load impedance in the output power back-off state.

[0010] In some embodiments, the digital power amplifier unit, configured based on pre-assigned weights of independent sub-units, includes:

[0011] A weight is assigned to each of the independent sub-units; the weight is used to determine the contribution ratio of the corresponding independent sub-unit to the output power of the digital power amplifier unit when it is turned on;

[0012] Set a specified maximum output power for the digital power amplifier unit, and ensure that the total output power of all the independent subunits is greater than the specified maximum output power.

[0013] In some further embodiments, determining the weight corresponding to each of the independent sub-units includes:

[0014] Each of the independent sub-units is assigned the same weight, so that the output power of each of the independent sub-units is the same.

[0015] In some further embodiments, determining the weight corresponding to each of the independent sub-units includes:

[0016] The weights of a first number of independent sub-units are set as first weights, and the weights of the remaining independent sub-units are set as second weights; the first weights and the second weights are different.

[0017] In some embodiments, dynamically selecting and combining the activation of the corresponding independent sub-units based on the target output power corresponding to the target digital bit state, while keeping the remaining independent sub-units off, includes:

[0018] The target output power is determined based on the input target digital bit state;

[0019] Select a group of sub-units to be activated from the independent sub-units, and calculate the total output power of the group of sub-units to be activated based on the weights of the sub-units to be activated in the group, so that the total output power matches the target output power;

[0020] A power supply control signal is generated to drive all the independent sub-units corresponding to the sub-unit group to be turned on to conduct.

[0021] In some further embodiments, the method further includes:

[0022] In the first bit state and the second bit state where the same target output power is required, the independent sub-units are dynamically combined, and different groups of sub-units to be turned on are selected respectively, so as to dynamically adjust the equivalent parasitic capacitance value of the output of the digital power amplifier unit in the first bit state and the second bit state.

[0023] In some further embodiments, the step of dynamically combining the independent sub-units under the first bit state and the second bit state where the same target output power is required, and selecting different groups of the sub-units to be activated respectively, includes:

[0024] Based on the weight of each independent sub-unit and the target output power, a first sub-unit group to be activated and a second sub-unit group to be activated are determined.

[0025] The first sub-unit group to be opened is different from the second sub-unit group to be opened;

[0026] The first total output power of the first sub-unit group to be activated is the same as the second total output power of the second sub-unit group to be activated.

[0027] When the first sub-unit group to be activated is turned on, the remaining independent sub-units are all turned off, so that a first equivalent parasitic capacitance value is presented at the output port of the digital power amplifier unit; when the second sub-unit group to be activated is turned on, the remaining independent sub-units are all turned off, so that a second equivalent parasitic capacitance value is presented at the output port of the digital power amplifier unit; the first equivalent parasitic capacitance value is different from the second equivalent parasitic capacitance value.

[0028] In further embodiments, determining the equivalent load impedance of the output port of the digital power amplifier unit based on the topological connection between the switched-off independent subunit and the output port of the digital power amplifier unit includes:

[0029] Based on the topological connection structure between the shut-down independent subunit and the output port of the digital power amplifier unit, the equivalent parasitic capacitance value of the output port of the digital power amplifier unit is obtained.

[0030] The equivalent load impedance is determined based on the equivalent parasitic capacitance value; the equivalent load impedance is matched with the target load impedance.

[0031] In some further embodiments, the method further includes:

[0032] The signal at the output port of the digital power amplifier unit is connected to a balun synthesis network;

[0033] A pre-matching circuit is provided between the digital power amplifier unit and the balun synthesis network;

[0034] Based on the number of independent sub-units turned on and their corresponding weights in the sub-unit groups to be turned on, the turns ratio parameters of the balun synthesis network and the impedance parameters of the pre-matching circuit are configured so that the input impedance of the independent sub-units turned on in different sub-unit groups to be turned on matches the preset target input impedance.

[0035] Secondly, this application provides a backoff efficiency optimization system under active load modulation and weighted interleaving, including a digital power amplifier unit, including independent sub-units with pre-assigned weights; the total number of the independent sub-units is greater than the number of independent sub-units that the digital power amplifier unit needs to activate in the maximum output power state;

[0036] A digital control circuit is used to dynamically select and combine the activation of the corresponding independent sub-units according to the target output power corresponding to the target digital bit state, while keeping the other independent sub-units off.

[0037] A dynamic load modulation structure is used to form an equivalent load impedance at the output port of the digital power amplifier unit based on the parasitic capacitance corresponding to the off independent subunit, so that the equivalent load impedance matches a preset target load impedance in the output power back-off state.

[0038] Compared with existing related technologies, the embodiments of this application have the following beneficial effects:

[0039] This application embodiment configures digital power amplifier units based on pre-weighted independent sub-units, and the total number of these independent sub-units is greater than the number required to be turned on under maximum output power conditions, thus establishing a hardware redundancy foundation. Based on the target output power corresponding to the target digital bit state, the corresponding independent sub-units are dynamically selected and combined for activation, while the remaining independent sub-units remain off, allowing the digital bit state to directly control the activation combination. Based on the parasitic capacitance of the off independent sub-units, and combined with the topological connection structure between the off sub-units and the output port, an equivalent load impedance is formed at the output port, which changes with the activation combination. When entering the output power fallback state, the above mechanism automatically matches the equivalent load impedance with the preset target load impedance. Therefore, this solution can dynamically adjust the equivalent load impedance seen by the conducting transistors during power fallback, avoiding impedance mismatch caused by a fixed matching network, thereby maintaining target efficiency matching and significantly improving overall energy efficiency performance over a wide dynamic power range.

[0040] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0041] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0042] Figure 1 This is a flowchart of a backoff efficiency optimization method under active load modulation and weighted interleaving provided in an embodiment of this application;

[0043] Figure 2 This is a flowchart illustrating the configuration of a digital power amplifier unit according to an embodiment of this application;

[0044] Figure 3 This is a flowchart illustrating the dynamic selection and combination of enabling corresponding independent sub-units according to an embodiment of this application;

[0045] Figure 4 This is a schematic diagram of forming a first equivalent parasitic capacitance in a first bit state according to an embodiment of this application;

[0046] Figure 5 This is a schematic diagram of forming a second equivalent parasitic capacitance in a second bit state according to an embodiment of this application;

[0047] Figure 6 This is a flowchart illustrating the determination of the equivalent load impedance of the output port of a digital power amplifier unit according to an embodiment of this application;

[0048] Figure 7 This is a schematic diagram of the internal redundancy configuration of a digital power amplifier unit and the subsequent balun synthesis network provided in an embodiment of this application;

[0049] Figure 8 This is a schematic diagram of a balun power combining circuit model provided in an embodiment of this application when two digital power amplifier units are turned on simultaneously;

[0050] Figure 9 This is a schematic diagram of a balun power combining circuit model provided in an embodiment of this application when only the first power amplifier unit is turned on;

[0051] Figure 10 This is a schematic diagram of a balun power combining circuit model provided in an embodiment of this application when only the second power amplifier unit is turned on;

[0052] Figure 11 This is a schematic diagram of the impedance Smith chart of a dual-unit balun synthesized digital power amplifier provided in one embodiment of this application;

[0053] Figure 12 This is a schematic diagram of a three-channel parallel digital power amplifier power module unit structure provided in an embodiment of this application;

[0054] Figure 13 This is a graph showing the results of testing the high-efficiency impedance range of a three-way parallel power amplifier provided in an embodiment of this application under different operating modes. Detailed Implementation

[0055] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0056] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order.

[0057] This embodiment provides a method for optimizing backoff efficiency under active load modulation and weighted interleaving. In practical scenarios, this method can be applied to power amplifier modules in base stations, terminal devices, or communication systems. The power amplifier module has the following hardware foundation: a digital power amplifier unit contains multiple parallel independent sub-units, each with a preset weight, and the total number of sub-units is greater than the number required to be turned on under maximum output power conditions, thus forming hardware redundancy; a digital control circuit generates power supply control signals based on the target digital bit state to control the on or off of each independent sub-unit.

[0058] Figure 1 This is a flowchart of the backoff efficiency optimization method under active load modulation and weighted interleaving provided in this embodiment, as follows: Figure 1 As shown, the method includes the following steps:

[0059] Step S110: Configure the digital power amplifier unit based on the pre-assigned weights of the independent sub-units; the total number of independent sub-units is greater than the number of independent sub-units that the digital power amplifier unit needs to activate in the maximum output power state.

[0060] In this step, the weights mentioned refer to the relative capability parameters of each independent sub-unit when participating in power output; the step of configuring the digital power amplifier unit refers to the process of constructing a digital power amplifier unit based on the combination of independent sub-units with preset weights, with the aim of building a hardware redundancy foundation. This step, by assigning weights to independent sub-units and setting the redundancy quantity, enables the digital power amplifier unit to have scalable and configurable power output capabilities, facilitating flexible power allocation in the future.

[0061] Step S120: Based on the target output power corresponding to the target digital bit state, dynamically select and combine the corresponding independent sub-units to be turned on, while keeping the other independent sub-units off.

[0062] In this step, the target digital bit state refers to the externally input digital control signal, which at least directly or indirectly reflects the target output power and its related information. The dynamic selection refers to determining one or more groups of independent sub-units that meet the power requirements based on the target output power and the configuration of each independent sub-unit. This step controls the activation combination of independent sub-units through digital bit states, achieving digital allocation of output power. This establishes a correspondence between the combination of activated independent sub-units and the target output power, avoiding nonlinear distortion and power waste.

[0063] Step S130: Based on the topological connection structure between the shut-off independent subunit and the output port of the digital power amplifier unit, determine the equivalent load impedance of the output port of the digital power amplifier unit so that the equivalent load impedance matches the preset target load impedance in the output power back-off state.

[0064] In this step, the topology connection structure refers to the electrical connection method between the off independent sub-units and the output port. This step utilizes the parasitic characteristics of the off independent sub-units and their connection topology with the output port to dynamically change the equivalent load impedance as the combination of on independent sub-units changes. When the system enters the output power retreat state, different on-state combinations can be selected in step S120 to change the set of off sub-units and their connection topology, thereby automatically adjusting the equivalent load impedance to ensure that the on independent sub-units always operate under the target impedance matching condition.

[0065] In related technologies, digital power amplifiers typically employ a fixed-structure output matching network, designed with the optimal load impedance at saturated output power as the matching point. When the system needs to reduce transmit power and enter a fallback state, the equivalent output impedance of the transistor itself changes with the output power. However, the parameters of the subsequent matching network remain constant, causing the actual load impedance of the conducting transistor to deviate from its target operating region, thus leading to a decrease in conversion efficiency.

[0066] In contrast, this embodiment first constructs a hardware reconfigurable foundation by configuring redundant independent sub-units and assigning weights to them. It then dynamically selects and combines the enabled sub-units based on the target digital bit state to achieve digital control of the output power. Furthermore, by utilizing the parasitic characteristics of the disabled sub-units and their topological connection structure with the output port, the equivalent load impedance dynamically changes with the enabled combination. Through these aforementioned techniques, this embodiment can automatically match the preset target load impedance during power back-off. This mechanism fundamentally solves the impedance mismatch problem of fixed matching networks during power back-off, enabling the enabled sub-units to maintain the target impedance matching condition at different output power levels, thereby significantly improving overall energy efficiency over a wide dynamic power range.

[0067] In some of these embodiments, Figure 2 This is a flowchart of the configuration of the digital power amplifier unit provided in this embodiment. Please refer to it. Figure 2 Step S110, which is the step of configuring the digital power amplifier unit based on the pre-assigned weights of the independent sub-units, specifically includes the following steps:

[0068] Step S111: Assign a weight to each independent subunit; the weight is used to determine the contribution ratio of the corresponding independent subunit to the output power of the digital power amplifier unit when it is turned on.

[0069] Step S112: Set the specified maximum output power of the digital power amplifier unit and make the total output power of all independent sub-units greater than the specified maximum output power.

[0070] Specifically: In step S111, a weight is assigned to each independent subunit, meaning the relative output capability of each subunit during power combining is pre-determined at the hardware or configuration parameter level. In step S112, a specified maximum output power is set for the digital power amplifier unit, and the total output power of all independent subunits is ensured to be greater than this specified maximum output power, thus ensuring that at least one off subunit is available for subsequent impedance modulation. The weighting assigns differentiated power contribution capabilities to different subunits, providing ample power level selection for subsequent dynamic combinations; power redundancy ensures that an off independent subunit always exists in the fallback state, and its parasitic capacitance and topology can be used to adjust the equivalent load impedance, enabling impedance matching in subsequent steps through switching on / off combinations.

[0071] In some further embodiments, in step S111, that is, in the step of determining the weight corresponding to each independent sub-unit, it is possible to set the weight of each independent sub-unit to be the same, so that the output power of each independent sub-unit is the same.

[0072] Specifically: When the weights of each independent subunit are equal, each independent subunit contributes equally to the total output power when in the active state. In this case, the total output power of the digital power amplifier unit is linearly proportional to the number of active independent subunits. The digital control circuit only needs to determine the number of active subunits based on the target output power to achieve power allocation, without the need for weighted calculations. Furthermore, to achieve different parasitic capacitance configurations for the same output power, this can be achieved by switching the active combinations of independent subunits. Specifically, each active combination is configured with the same number of independent subunits, but with different members.

[0073] For example, in two different bit states that require the same power level output, the first group of sub-units and the second group of sub-units are turned on respectively. The two groups of sub-units have the same number of sub-units but different members, which changes the set of turn-off sub-units and the topological connection structure between them and the output port, thus generating different equivalent parasitic capacitance values.

[0074] In some further embodiments, in step S111, that is, in the step of determining the weight corresponding to each independent sub-unit, the weight of a first number of independent sub-units may be set as a first weight, and the weight of the remaining independent sub-units may be set as a second weight; the first weight and the second weight are different.

[0075] Specifically, when independent sub-units are assigned different weights, the contribution of each independent sub-unit to the total output power in the on state is proportional to its weight. To achieve the target output power, the digital control circuit needs to perform a weighted calculation based on the weights of each sub-unit, selecting a set of sub-units so that the total output power after weighting equals the target output power. Due to the differences in weights, the same target output power may correspond to multiple different combinations of sub-units. For example, the same power level can be achieved using a few high-weight independent sub-units or a majority of low-weight independent sub-units. Utilizing this characteristic, under different bit states requiring the same target output power, members can be selected to form different combinations of sub-units, changing the set of off sub-units and thus altering the equivalent parasitic capacitance value of the output port. Unequal weight configuration can provide more combination options while maintaining constant output power, further expanding the adjustable range of the equivalent load impedance.

[0076] In some of these embodiments, Figure 3 This is a flowchart illustrating the dynamic selection and combination of activation of corresponding independent sub-units provided in this embodiment. Please refer to it. Figure 3 Step S120, which involves dynamically selecting and combining the activation of corresponding independent sub-units based on the target output power corresponding to the target digital bit state, while keeping the remaining independent sub-units off, specifically includes the following steps:

[0077] Step S121: Determine the corresponding target output power based on the input target digital bit state;

[0078] Step S122: Select a group of sub-units to be turned on from the independent sub-units, and calculate the total output power of the group of sub-units to be turned on based on the weights of the sub-units to be turned on in the group of sub-units to be turned on, so that the total output power matches the target output power.

[0079] Step S123: Generate a power supply control signal to drive all independent sub-units corresponding to the sub-unit group to be turned on to conduct.

[0080] Specifically: The target digital bit state refers to the externally input digital control signal, which at least directly or indirectly reflects the desired target output power and its related information. In step S121, the target digital bit state is parsed and converted into a specific power value, serving as the basis for subsequent selection of sub-unit combinations. In step S122, based on the weights of each independent sub-unit and the target output power, a group of sub-units is selected such that their weighted total output power equals the target output power. Through the quantization relationship between weights and power, it is ensured that the selected sub-unit group can accurately output the required power level when turned on. The power supply control signal refers to the electrical signal used to control the turn-on or turn-off of independent sub-units, such as gate bias voltage or drain power supply switch signal. In step S123, the digital control circuit sends a power supply control signal to each sub-unit in the sub-unit group to be turned on, enabling it to conduct; simultaneously, it turns off independent sub-units that do not belong to the sub-unit group to be turned on, or maintains their existing off state.

[0081] In some further embodiments, the method further includes the following steps in the process of selecting the sub-unit group to be enabled:

[0082] When the same target output power is required in the first bit state and the second bit state, independent sub-units are dynamically combined and different groups of sub-units to be turned on are selected respectively, so as to dynamically adjust the equivalent parasitic capacitance value of the digital power amplifier unit output in the first bit state and the second bit state.

[0083] Specifically, the first bit state and the second bit state refer to two different digital control signal states, both corresponding to the same target output power. Under this premise, different groups of sub-units to be activated are selected in step S122: a first group of sub-units is selected in the first bit state, and a second group of sub-units is selected in the second bit state. The members of the two groups are not completely identical, therefore the sets of independent sub-units to be turned off corresponding to the two groups are also different. The topological connection structure between the independent sub-units to be turned off and the output port determines the equivalent parasitic capacitance value of the output port. Therefore, when switching from the first bit state to the second bit state, although the output power remains unchanged, the equivalent parasitic capacitance value of the output port changes, thus affecting the equivalent load impedance. Through the above operations, this embodiment can achieve dynamic adjustment of the equivalent load impedance simply by changing the digital bit state under the condition of constant output power, providing an additional control dimension for impedance matching in the power back-off state.

[0084] In some further embodiments, the step of dynamically combining independent sub-units and selecting different groups of sub-units to be activated under the first bit state and the second bit state that require the same target output power specifically includes the following steps:

[0085] Based on the weight of each independent sub-unit and the target output power, determine the first sub-unit group to be activated and the second sub-unit group to be activated;

[0086] The first sub-unit group to be opened is different from the second sub-unit group to be opened;

[0087] The first total output power of the first sub-unit group to be activated is the same as the second total output power of the second sub-unit group to be activated.

[0088] When the first sub-unit group to be activated is turned on, all remaining independent sub-units are turned off, so that the output port of the digital power amplifier unit presents a first equivalent parasitic capacitance value; when the second sub-unit group to be activated is turned on, all remaining independent sub-units are turned off, so that the output port of the digital power amplifier unit presents a second equivalent parasitic capacitance value; the first equivalent parasitic capacitance value is different from the second equivalent parasitic capacitance value.

[0089] In some preferred embodiments, Figure 4 This is a schematic diagram illustrating the formation of the first equivalent parasitic capacitance in the first bit state provided in this embodiment. Figure 5 This is a schematic diagram of forming the second equivalent parasitic capacitance in the second bit state provided in this embodiment.

[0090] The specified maximum output power of the digital power amplifier unit is Internally, it employs four independent sub-units with equal weights, each with an output power of [missing value]. The four independent sub-units are directly connected in parallel to the output port via microstrip lines.

[0091] Please refer to Figure 4 In the first bit state, independent sub-units numbered 1 and 4 are turned on, while independent sub-units numbered 2 and 3 are turned off. At this time, the output power of the digital power amplifier unit is... Because the independent sub-units that are turned off have parasitic capacitance, and their topological connection structure with the output port is specific, they can be equivalent to presenting a first equivalent parasitic capacitance value at the output port. .

[0092] Please refer to Figure 5 In the second bit state, control independent sub-units numbered 2 and 3 to turn on, and control independent sub-units numbered 1 and 4 to turn off. At this time, the output power is still [value missing]. However, due to the different topological connection structure between the shut-off independent subunit and the output port compared to the former, the equivalent parasitic capacitance value of the output port changes to... .

[0093] Through the above operations, this embodiment can obtain different equivalent parasitic capacitance values ​​by simply switching the combination of the activated sub-units while maintaining the same target output power. This changes the equivalent load impedance accordingly, enabling flexible configuration of impedance matching in the power back-off state.

[0094] In some further embodiments, Figure 6 This is a flowchart illustrating the determination of the equivalent load impedance at the output port of the digital power amplifier unit, provided in this embodiment. Please refer to it. Figure 6 Step S130, which is to determine the equivalent load impedance of the output port of the digital power amplifier unit based on the topological connection structure between the shut-down independent subunit and the output port of the digital power amplifier unit, specifically includes the following steps:

[0095] Step S131: Based on the topological connection structure between the shut-off independent subunit and the output port of the digital power amplifier unit, obtain the equivalent parasitic capacitance value of the output port of the digital power amplifier unit.

[0096] Step S132: Determine the equivalent load impedance based on the equivalent parasitic capacitance value; match the equivalent load impedance with the target load impedance.

[0097] Specifically, the topology connection structure refers to the electrical connection method between the independent shutdown sub-units and the output port. In practical scenarios, this can be achieved through direct parallel connection, connection via transmission lines, or connection via other passive components. The physical layout and connection path of different independent shutdown sub-units determine the magnitude of their parasitic capacitance at the output port. In step S131, the equivalent parasitic capacitance value of the output port can be determined based on the set of shutdown sub-units and their specific connection method with the output port. This equivalent parasitic capacitance value reflects the combined effect of the parasitic capacitances of all shutdown sub-units.

[0098] The equivalent load impedance refers to the equivalent impedance obtained from the output port of the digital power amplifier unit towards the load. This impedance is determined by the output matching network or the load, together with the equivalent parasitic capacitance of the output port. In step S132, based on the equivalent parasitic capacitance value obtained in step S131, and combined with the parameters of the output matching network, the equivalent load impedance of the output port can be determined. Through the dynamic switching of the enabled sub-unit combination in the aforementioned steps, the set of disabled sub-units changes accordingly, thereby changing the equivalent parasitic capacitance value, ultimately matching the equivalent load impedance with the preset target load impedance.

[0099] In some further embodiments, the method further includes the following steps:

[0100] Connect the signal at the output port of the digital power amplifier unit to the balun synthesis network;

[0101] A pre-matching circuit is installed between the digital power amplifier unit and the balun synthesis network;

[0102] Based on the number of independent sub-units turned on and their corresponding weights in the sub-unit groups to be turned on, configure the turns ratio parameters of the balun synthesis network and the impedance parameters of the pre-matching circuit so that the input impedance of the independent sub-units turned on in different sub-unit groups to be turned on matches the preset target input impedance.

[0103] Specifically, this embodiment configures the turns ratio parameters of the balun synthesizer network and the impedance parameters of the pre-matching circuit according to the number and weight of the activated sub-unit groups. This ensures that the input impedance of the independently activated sub-units remains consistent with the preset target input impedance under different bit states. This avoids impedance mismatch issues caused by changes in the activation combination, ensuring that the digital power amplifier unit maintains efficient power transmission even in power back-off states. It significantly reduces efficiency loss in non-maximum power states, thereby improving the overall energy efficiency of the entire power amplifier system over a wide dynamic power range.

[0104] In some further embodiments, Figure 7 This is a schematic diagram of the internal redundancy configuration of the digital power amplifier unit and the subsequent balun synthesis network provided in this embodiment. Please refer to it. Figure 7 In this embodiment, a dynamic load compensation design based on redundant switching transistors is employed within each digital power amplifier unit. Specifically, for a given maximum output power of... The digital power amplifier unit is broken down into... Each of the following independent sub-units has the same weight, and the output power of each independent sub-unit is... And satisfy That is, the total achievable power of the independent sub-units is greater than the specified maximum output power. In each bit state that requires the digital power amplifier unit to be turned on, a digital control signal is used to enable one of them. Each independent subunit is enabled ( satisfy ),the remaining Each independent sub-unit is turned off, and these turned-off sub-units are used for load compensation in that bit state. This configuration, by setting redundant sub-units, ensures that the set of turned-off sub-units differs in different bit states, and their parasitic capacitances and topological connections with the output ports also change accordingly, providing a hardware basis for dynamically adjusting the equivalent load impedance. After each digital power amplifier unit circuit, the output signal is connected to a transmission line transformer balun network. Through impedance transformation design, each activated digital power amplifier unit has a good impedance matching state under weighted interleaving, thus ensuring high efficiency even in back-off power mode.

[0105] In some preferred embodiments, Figure 8 This is a schematic diagram of the balun power combining circuit model when the two digital power amplifier units are turned on simultaneously, as provided in this embodiment. Figure 9 This is a schematic diagram of the balun power combining circuit model when only the first power amplifier unit is turned on, as provided in this embodiment. Figure 10 This is a schematic diagram of the balun power combining circuit model when only the second power amplifier unit is turned on, as provided in this embodiment. Figure 11 This is a schematic diagram of the impedance Smith chart of the dual-unit balun synthesized digital power amplifier provided in this embodiment.

[0106] Please refer to Figure 8 Consider the case where two digital power amplifier units combine power through a balun combining network. Let the voltages of the two power amplifier units when they are turned on be respectively... and The voltage turns ratios of the two baluns are respectively and The load resistance is When both power amplifier units are turned on, the voltage is applied to the load by a series balun. At this time:

[0107] The input impedance of the first balun is ;

[0108] The input impedance of the second balun is .

[0109] Please refer to further details. Figure 9 When only the first power amplifier unit is turned on, only the voltage of the first power amplifier unit is applied to the load through the balun, and the input impedance of the first balun changes as follows: .

[0110] Further reference Figure 10 When only the second power amplifier unit is turned on, only the voltage of the second power amplifier unit is applied to the load through the balun, and the input impedance of the second balun changes as follows: .

[0111] Analysis shows that, under the physical premise that all parameters in the formula are greater than zero, and The corresponding value is always less than and The value is as follows. Since digital power amplifiers achieve different states of saturation and back-off by switching each power amplifier unit, the optimal load impedance required for the power amplifier unit turned on in various bit states is the same. Therefore, it is theoretically impossible to achieve perfect matching in all states.

[0112] To address the aforementioned issue, given the known turn-on voltage ratio of the two power amplifier units... Under the premise that the overall impedance matching is not yet fully met, the following steps can be taken to improve the overall impedance matching: Adjust the voltage turns ratio of the two baluns. And select a suitable load resistor. Control and shrink and Deviation on the Smith chart and The degree of combination. Figure 11 Based on the impedance matching rules shown, design a pre-matching circuit to achieve the optimal load impedance of the digital power amplifier unit. Match to and This matching process is visually represented in the Smith chart as the actual input impedance when both paths are simultaneously enabled. Step by step towards optimal matching impedance The adjusted trajectory effectively compensates for the deviation between the input impedance and the optimal matching impedance in the dual-channel synthesis state. Specifically, the actual input impedance... Position relative to the reference impedance when single channel is open The further deviation from the matching point directly confirms the offset characteristics of the input impedance under dual-path synthesis conditions.

[0113] The balun dynamic synthesis network designed through the above operations enables the digital power amplifier unit to have the highest efficiency at the maximum power level, and the efficiency loss is small and controllable at non-maximum power levels, thus ensuring the overall efficiency of the digital power amplifier over a wide power range.

[0114] In some preferred embodiments, Figure 12 This is a schematic diagram of the three-channel parallel digital power amplifier power module unit structure provided in this embodiment. Figure 13 This is a graph showing the results of testing the high-efficiency impedance range of the three-channel parallel power amplifier provided in this embodiment under different operating modes.

[0115] To verify the reliability and feasibility of this invention, and to test the function and effectiveness of the power configuration amplifier, a power module unit from a 25W and two 6W analog systems was used, such as... Figure 12As shown, the system includes three power amplifiers: the main power amplifier has an output power of 25 watts, and the other two auxiliary power amplifiers each have an output power of 6 watts. The outputs of the three power amplifiers are connected in parallel to the load via DC blocking capacitors.

[0116] The circuit parameter design includes: The three RF input ports are each connected to an input matching network, which consists of a 50Ω standard input impedance matching structure and a DC blocking capacitor. The DC blocking capacitor is selected with a capacitance of 100pF, achieving an insertion loss of less than 0.1dB within the 2.9GHz to 4.3GHz operating frequency band, while simultaneously blocking DC signal interference to the preamplifier circuit. The matching circuit adopts an L-type or π-type broadband matching topology, optimized for the input impedance characteristics of the three power amplifiers, achieving an input return loss better than -15dB across the entire operating frequency band, ensuring efficient RF signal transmission. The gate (G pole) of each power amplifier is connected to the first gate bias voltage via a high-impedance RF choke (RFC). Second gate bias voltage and third gate bias voltage The choke inductance is selected as 47nH, and its impedance to RF signals is greater than 1kΩ within the operating frequency band to prevent RF signals from leaking to the bias power supply; the drain (D terminal) is connected to the first drain bias voltage through the RF choke. Second drain bias voltage and third drain bias voltage The choke inductance is selected as 68nH, and a bypass capacitor is used to filter the power supply, providing a stable DC operating point for the power amplifier transistors. The drain bias voltage of the main power amplifier is set to 28V, and the drain bias voltage of the auxiliary power amplifier is set to 12V to match the power supply requirements of the corresponding power levels. The main power amplifier uses a large-size LDMOS / GaN power transistor with a saturated output power of 25W, and the auxiliary power amplifier uses a small-size power transistor of the same process with a saturated output power of 6W. The sources (S) of the three power amplifier transistors are connected to a common ground to ensure that the grounding impedance is less than 0.5Ω to suppress self-oscillation. A DC blocking capacitor (DCBlock) is connected in series at the output, with a value of 47pF. The insertion loss is less than 0.2dB across the entire operating frequency band, and it also blocks the crosstalk between the DC bias voltages of the three power amplifiers. After the DC blocking capacitor, the three outputs are directly connected in parallel and finally connected to a 50Ω load.

[0117] By controlling the on / off state of the two auxiliary power amplifiers and considering the conduction state of the main power amplifier, the output impedance range under different operating modes was measured. Specifically, using load-pull technology, at multiple frequency points, such as 2900 MHz, 3400 MHz, 3900 MHz, and 4300 MHz, the impedance range was measured when only the main power amplifier was on and when all three power amplifiers were on simultaneously. The measured impedance range met the preset efficiency targets, namely, a saturated output power greater than 43 dBm (corresponding to 20W; saturated power not less than 44 dBm / 25W when the main amplifier is on alone, and not less than 46 dBm / 40W when all three are on), and a power-added efficiency greater than 60%. This verified the high-efficiency operating characteristics of the parallel structure under different power back-off states.

[0118] Test results are as follows Figure 13 As shown, Figure 13 The solid lines are all marked with the suffix -3, which represents the high-efficiency impedance profile when all three power amplifiers are turned on at the same time. The dashed lines represent the high-efficiency impedance profile when only the main power amplifier is turned on. The test frequency points cover four key operating frequencies: 2900MHz, 3400MHz, 3900MHz, and 4300MHz. The criteria for judging high-efficiency impedance are: saturated output power not less than 43dBm and power-added efficiency not less than 60%.

[0119] As can be clearly observed from the graph: when only the main power amplifier is on, the dashed outline, representing the high-efficiency impedance range corresponding to each frequency point, exhibits a narrow band and small area distribution, concentrated in a limited region near the center of the Smith chart, with extremely low impedance adjustment margin. The center of the Smith chart corresponds to the 50Ω standard impedance point. However, when all three power amplifiers are on simultaneously, the solid outline, representing the high-efficiency impedance range corresponding to each frequency point, achieves significant lateral and vertical expansion. Not only does the coverage area increase substantially, but the adjustable range of both the real and imaginary parts of the impedance is also significantly widened, forming a wider high-efficiency operating impedance band across the entire test frequency range. Here, j represents the imaginary unit.

[0120] This indicates that by controlling the switching on or off of the auxiliary power amplifier, the set of shutdown sub-units and their topological connection structure with the output port are changed, achieving dynamic modulation of the equivalent load impedance of the output port, thereby expanding the efficient impedance solution space of the power amplifier at different output power levels. The above verification results demonstrate that the dynamic load compensation technology based on redundant switching transistors can effectively achieve dynamic impedance space modulation, proving the feasibility and effectiveness of this scheme in adjusting the equivalent load impedance under power back-off conditions.

[0121] This application also provides a backoff efficiency optimization system under active load modulation and weighted interleaving. The system includes a digital power amplifier unit, which includes independent sub-units with pre-assigned weights. The total number of independent sub-units is greater than the number of independent sub-units that the digital power amplifier unit needs to activate in the maximum output power state.

[0122] The digital control circuit is used to dynamically select and combine the activation of the corresponding independent sub-units according to the target output power corresponding to the target digital bit state, while keeping the other independent sub-units off.

[0123] The dynamic load modulation structure is used to form an equivalent load impedance at the output port of the digital power amplifier unit based on the parasitic capacitance corresponding to the independent sub-units that are turned off, so that the equivalent load impedance matches the preset target load impedance when the output power is back off.

[0124] The backoff efficiency optimization system under active load modulation and weighted interleaving in this embodiment is used to implement the above embodiments and preferred embodiments, and will not be repeated as already described. The terms "module," "unit," "subunit," etc., used above can refer to combinations of software and / or hardware that implement a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0125] It should be noted that the above modules can be functional modules or program modules, and can be implemented through software or hardware. For modules implemented through hardware, the above modules can reside in the same processor; or the above modules can be located in different processors in any combination.

[0126] This embodiment also provides a computer device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0127] Optionally, the computer device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0128] Furthermore, in conjunction with the backoff efficiency optimization method under active load modulation and weighted interleaving provided in the above embodiments, this embodiment can also provide a storage medium for implementation. This storage medium stores a computer program; when executed by a processor, the computer program implements any of the backoff efficiency optimization methods under active load modulation and weighted interleaving in the above embodiments.

[0129] It should be noted that all information and data involved in this application are authorized by the user or fully authorized by all parties and will be used legally.

[0130] It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. All other embodiments derived by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0131] Obviously, the accompanying drawings are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar situations based on these drawings without any creative effort. Furthermore, it is understood that although the work done in this development process may be complex and lengthy, for those skilled in the art, certain design, manufacturing, or production modifications made based on the technical content disclosed in this application are merely conventional technical means and should not be considered as insufficient disclosure of this application.

[0132] The term "embodiment" in this application refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply that it is mutually exclusive with or independent of other embodiments. It will be clearly or implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0133] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of patent protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application.

Claims

1. A method for optimizing backoff efficiency under active load modulation and weighted interleaving, characterized in that, include: Digital power amplifier units are configured based on independent sub-units with pre-assigned weights; The total number of independent sub-units is greater than the number of independent sub-units that the digital power amplifier unit needs to activate in the maximum output power state; Based on the target output power corresponding to the target digital bit state, dynamically select and combine the corresponding independent sub-units to be turned on, while keeping the other independent sub-units off. Based on the topological connection structure between the shut-down independent subunit and the output port of the digital power amplifier unit, the equivalent load impedance of the output port of the digital power amplifier unit is determined so that the equivalent load impedance matches the preset target load impedance in the output power back-off state.

2. The backoff efficiency optimization method under active load modulation and weighted interleaving according to claim 1, characterized in that, The independent sub-units based on pre-assigned weights, configured with digital power amplifier units, include: A weight is assigned to each of the independent sub-units; the weight is used to determine the contribution ratio of the corresponding independent sub-unit to the output power of the digital power amplifier unit when it is turned on; Set a specified maximum output power for the digital power amplifier unit, and ensure that the total output power of all the independent subunits is greater than the specified maximum output power.

3. The method for optimizing backoff efficiency under active load modulation and weighted interleaving according to claim 2, characterized in that, Determining the weight corresponding to each of the independent sub-units includes: Each of the independent sub-units is assigned the same weight, so that the output power of each of the independent sub-units is the same.

4. The method for optimizing backoff efficiency under active load modulation and weighted interleaving according to claim 2, characterized in that, Determining the weight corresponding to each of the independent sub-units includes: The weights of a first number of independent sub-units are set as first weights, and the weights of the remaining independent sub-units are set as second weights; the first weights and the second weights are different.

5. The method for optimizing backoff efficiency under active load modulation and weighted interleaving according to claim 1, characterized in that, The step of dynamically selecting and combining the activation of the corresponding independent sub-units based on the target output power corresponding to the target digital bit state, while keeping the remaining independent sub-units off, includes: The target output power is determined based on the input target digital bit state; Select a group of sub-units to be activated from the independent sub-units, and calculate the total output power of the group of sub-units to be activated based on the weights of the sub-units to be activated in the group, so that the total output power matches the target output power; A power supply control signal is generated to drive all the independent sub-units corresponding to the sub-unit group to be turned on to conduct.

6. The method for optimizing backoff efficiency under active load modulation and weighted interleaving according to claim 5, characterized in that, The method further includes: In the first bit state and the second bit state where the same target output power is required, the independent sub-units are dynamically combined, and different groups of sub-units to be turned on are selected respectively, so as to dynamically adjust the equivalent parasitic capacitance value of the output of the digital power amplifier unit in the first bit state and the second bit state.

7. The method for optimizing backoff efficiency under active load modulation and weighted interleaving according to claim 6, characterized in that, The process of dynamically combining the independent sub-units under the first and second bit states where the same target output power is required, and selecting different groups of the sub-units to be activated, includes: Based on the weight of each independent sub-unit and the target output power, a first sub-unit group to be activated and a second sub-unit group to be activated are determined. The first sub-unit group to be opened is different from the second sub-unit group to be opened; The first total output power of the first sub-unit group to be activated is the same as the second total output power of the second sub-unit group to be activated. When the first sub-unit group to be activated is turned on, the remaining independent sub-units are all turned off, so that a first equivalent parasitic capacitance value is presented at the output port of the digital power amplifier unit; when the second sub-unit group to be activated is turned on, the remaining independent sub-units are all turned off, so that a second equivalent parasitic capacitance value is presented at the output port of the digital power amplifier unit; the first equivalent parasitic capacitance value is different from the second equivalent parasitic capacitance value.

8. The method for optimizing backoff efficiency under active load modulation and weighted interleaving according to claim 7, characterized in that, The step of determining the equivalent load impedance of the output port of the digital power amplifier unit based on the topological connection structure between the shut-down independent subunit and the output port of the digital power amplifier unit includes: Based on the topological connection structure between the shut-down independent subunit and the output port of the digital power amplifier unit, the equivalent parasitic capacitance value of the output port of the digital power amplifier unit is obtained. The equivalent load impedance is determined based on the equivalent parasitic capacitance value; the equivalent load impedance is matched with the target load impedance.

9. The backoff efficiency optimization method under active load modulation and weighted interleaving according to claim 8, characterized in that, The method further includes: The signal at the output port of the digital power amplifier unit is connected to a balun synthesis network; A pre-matching circuit is provided between the digital power amplifier unit and the balun synthesis network; Based on the number of independent sub-units turned on and their corresponding weights in the sub-unit groups to be turned on, the turns ratio parameters of the balun synthesis network and the impedance parameters of the pre-matching circuit are configured so that the input impedance of the independent sub-units turned on in different sub-unit groups to be turned on matches the preset target input impedance.

10. A backoff efficiency optimization system under active load modulation and weighted interleaving, characterized in that, It includes a digital power amplifier unit, which includes independent sub-units with pre-assigned weights; the total number of the independent sub-units is greater than the number of the independent sub-units that the digital power amplifier unit needs to activate in the maximum output power state; A digital control circuit is used to dynamically select and combine the activation of the corresponding independent sub-units according to the target output power corresponding to the target digital bit state, while keeping the other independent sub-units off. A dynamic load modulation structure is used to form an equivalent load impedance at the output port of the digital power amplifier unit based on the parasitic capacitance corresponding to the off independent subunit, so that the equivalent load impedance matches a preset target load impedance in the output power back-off state.

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