Power amplifier circuit, radio frequency front-end module, radio frequency front-end chip and electronic equipment

Abstract

The application discloses a power amplification circuit, a radio frequency front end module, a radio frequency front end chip and electronic equipment, and relates to the technical field of communication.The power amplification circuit comprises: when the power amplification module is in a first power mode, a first number of power transistor units are controlled to be in a conduction state through a plurality of bias circuit units.When the power amplification module is in a second power mode, a second number of power transistor units are controlled to be in a conduction state through the plurality of bias circuit units.Based on the scheme of the application, when the power amplification circuit is in a low power mode, a smaller number of power transistor units are controlled to be in a conduction state, so that the number of power transistor units of the power amplification circuit in the low power mode can be reduced, and the working efficiency is effectively improved.Meanwhile, compensation impedance can be added to the output end of the power amplification module, so that the output impedance of the power amplification module and the power signal in the low power mode are matched with each other, and the working efficiency is further improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a power amplifier circuit, a radio frequency front-end module, a radio frequency front-end chip, and an electronic device. Background Technology

[0002] With the continuous advancement of technology, electronic devices have become increasingly integrated into people's daily lives. Examples include mobile phones, tablets, and laptops. To enable communication, electronic devices typically use power amplifiers (PAs) to amplify radio frequency signals, thereby facilitating communication between the electronic device and a base station. Depending on the transmission power, PAs generally have high-power mode (HPM) and low-power mode (LPM).

[0003] A power amplifier (PA) typically consists of 2-3 stages, including a preamplifier and a power amplifier. The preamplifier, acting as the driver stage, generally has lower power and smaller power transistors. The power amplifier, acting as the power stage, generally has higher power and larger power transistors. Because the primary function of the power amplifier is to output high-power signals, when the power amplifier is in LPM (low power minimization) mode, the output power signal is relatively low, but the larger power transistor area can easily lead to lower efficiency.

[0004] Therefore, a new solution is urgently needed to address the aforementioned problems. Summary of the Invention

[0005] This application provides a power amplifier circuit, an RF front-end module, an RF front-end chip, and an electronic device. By controlling and reducing the number of power transistor units in the power amplifier circuit when it is in low-power mode, the operating efficiency of the power amplifier circuit in low-power mode is effectively improved. Simultaneously, a compensation impedance can be added to the output terminal of the power amplifier circuit, thereby matching the output impedance of the power amplifier module with the power signal in low-power mode, further improving operating efficiency.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] In a first aspect, a power amplifier circuit is provided, including a power amplifier module and a bias circuit module. The power amplifier module includes multiple power transistor units, whose input terminals are interconnected, and whose output terminals are interconnected. The bias circuit module includes multiple bias circuit units, each bias circuit unit being connected to one or more power transistor units. When the power amplifier module is in a first power mode, a first number of power transistor units are controlled to be in a conducting state by the multiple bias circuit units. When the power amplifier module is in a second power mode, a second number of power transistor units are controlled to be in a conducting state by the multiple bias circuit units; the first number is greater than the second number; the power of the first power mode is greater than the power of the second power mode.

[0008] In this embodiment, when the power amplifier circuit is in a high-power first power mode, multiple bias circuit units control a larger number of power transistor units to be in the conducting state to provide a higher-power signal. When the power amplifier circuit is in a low-power second power mode, multiple bias circuit units control a smaller number of power transistor units to be in the conducting state to provide a lower-power signal. Therefore, the power amplifier circuit provided in this application can reduce the number of power transistor units in the low-power mode, effectively improving the operating efficiency of the power amplifier circuit in the low-power mode.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the power amplifier circuit further includes a first output impedance, a first switch, and a second output impedance. A first terminal of the first output impedance is connected to the output terminal of the power amplifier module, a second terminal of the first output impedance is connected to a first terminal of the first switch, and a second terminal of the first switch is connected to a first terminal of the second output impedance. When the power amplifier module is in a first power mode, the first switch is in the off state. When the power amplifier module is in a second power mode, the first switch is in the on state.

[0010] In this implementation, when the power amplifier module is in the first power mode, the first switch is in the off state, so that the output impedance of the power amplifier module is the first output impedance, which matches the higher power of the first power mode. Then, when the power amplifier module is in the second power mode, the first switch is in the on state, so that the output impedance of the power amplifier module is obtained by paralleling the first output impedance with the second output impedance, which matches the lower power of the second power mode.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the power amplifier circuit further includes a second switch. The first terminal of the second switch is connected to the output terminal of the power amplifier module, and the second terminal of the second switch is connected to the second terminal of the second output impedance. When the power amplifier module is in a first power mode, both the first and second switches are in an open state. When the power amplifier module is in a second power mode, both the first and second switches are in a closed state.

[0012] In this implementation, when the power amplifier module is in the first power mode, the first and second switches are in the off state, so the output impedance of the power amplifier module is the first output impedance, which matches the higher power of the first power mode. When the power amplifier module is in the second power mode, the first and second switches are in the on state, so the output impedance of the power amplifier module is the parallel impedance of the first and second output impedances, which matches the lower power of the second power mode.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the first switch includes a single-pole single-throw switch, and the second switch includes a single-pole single-throw switch.

[0014] In this implementation, since the first and second switches only need to achieve the opening and closing of a single path, both the first and second switches can be single-pole single-throw switches, which are smaller in size and lower in cost.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the power amplifier circuit further includes a first band switching module. The input terminal of the first band switching module is connected to the second terminal of the first output impedance, and the output terminal of the first band switching module is used to output signals of multiple power bands.

[0016] In this implementation, the first band switching module is used to select different bands for the output signal of the power amplifier module.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the first band switching module includes a single-pole multiple-throw switch.

[0018] In this implementation, since the first band switching module only needs to select a different band for the output signal of the power output module, the first band switching module can be a single-pole multi-throw switch.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the power amplifier circuit further includes a third switch, a third output impedance, and a fourth output impedance. The input terminal of the third switch is connected to the output terminal of the power amplifier module, the first output terminal of the third switch is connected to the first terminal of the third output impedance, and the second output terminal of the third switch is connected to the first terminal of the fourth output impedance. When the power amplifier module is in a first power mode, the input terminal and the first output terminal of the third switch are in a conducting state. When the power amplifier module is in a second power mode, the input terminal and the second output terminal of the third switch are in a conducting state.

[0020] In this implementation, when the power amplifier module is in the first power mode, the input terminal and the first output terminal of the third switch are in a conducting state, thereby making the output impedance of the power amplifier module the third output impedance, which matches the higher power of the first power mode. When the power amplifier module is in the second power mode, the input terminal and the second output terminal of the third switch are in a conducting state, thereby making the output impedance of the power amplifier module the fourth output impedance, which matches the lower power of the second power mode.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the third switch includes a single-pole double-throw switch.

[0022] In this implementation, since the third switch needs to select whether the output signal of the power amplifier module is turned on to the third output impedance or the fourth output impedance, the third switch can be a single-pole double-throw switch.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the power amplifier circuit further includes a second band switching module; the first input terminal of the second band switching module is connected to the second terminal of the third output impedance, and the second input terminal of the second band switching module is connected to the second terminal of the fourth output impedance; the output terminal of the second band switching module is used to output signals of multiple power bands. When the power amplifier module is in the first power mode, the first input terminal and the output terminal of the second band switching module are in a conducting state. When the power amplifier module is in the second power mode, the second input terminal and the output terminal of the second band switching module are in a conducting state.

[0024] In this implementation, when the power amplifier module is in the first power mode, the first input terminal and the output terminal of the second band switch module are in a conducting state, thereby allowing higher power signals to select different bands for output from the first input terminal of the second band switch. When the power amplifier module is in the second power mode, the second input terminal and the output terminal of the second band switch module are in a conducting state, thereby allowing lower power signals to select different bands for output from the second input terminal of the second band switch module.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, the second band switching module includes a double-pole multi-throw switch.

[0026] In this implementation, since the second band switch module needs to select different bands for the output signals of the third output impedance and the fourth output impedance, the second band switch module can be a double-pole multi-throw switch.

[0027] In conjunction with the first aspect, in some implementations of the first aspect, the power transistor unit includes a MOSFET and / or a triode.

[0028] In this implementation, the power transistor unit can be selected from one or more of MOSFETs and transistors, depending on the actual needs.

[0029] In conjunction with the first aspect, in some implementations of the first aspect, the power amplifier circuit further includes a driver amplifier module, an input impedance, and an interstage impedance. The input terminal of the driver amplifier module is connected to the input impedance, the output terminal of the driver amplifier module is connected to the first terminal of the interstage impedance, and the second terminal of the interstage impedance is connected to the input terminal of the power amplifier module.

[0030] In this implementation, the driver amplifier module acts as the driver stage, used to initially amplify the input signal; its power is generally relatively small. The input impedance is used to match the initial input power signal, and the interstage impedance is used to match the power signal between the driver amplifier module and the power amplifier module.

[0031] Secondly, an RF front-end module is provided, including an antenna switch and a power amplifier circuit. The antenna switch is connected to the power amplifier circuit. The antenna switch is used to select the conducting antenna.

[0032] In this embodiment of the application, different antennas are selected to be turned on by an antenna switch, thereby transmitting the amplified signal output by the power amplifier circuit from different antennas into space.

[0033] Thirdly, a radio frequency (RF) front-end chip is provided, including an RF transceiver chip and an RF front-end module. The RF transceiver chip is connected to the RF front-end module. The RF transceiver chip is used to control RF transmission and reception signals.

[0034] In this embodiment, the radio frequency transceiver chip is used to transmit or receive radio frequency signals, and amplifies the radio frequency signals through the radio frequency front-end module.

[0035] Fourthly, an electronic device is provided, including an antenna subsystem and a radio frequency (RF) front-end chip. The antenna subsystem is connected to the RF front-end chip. The antenna subsystem is used to receive signals from space or transmit signals into space.

[0036] In this embodiment, the radio frequency front-end chip is used to perform front-end processing on radio frequency signals, and the antenna subsystem is used to receive signals from space or transmit signals into space. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a scenario for an electronic device to which an embodiment of this application is applicable;

[0038] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0039] Figure 3 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application;

[0040] Figure 4 A circuit diagram of a conventional power amplifier circuit provided in an embodiment of this application;

[0041] Figure 5 An efficiency diagram of a conventional power amplifier circuit in one of the embodiments of this application, showing its operating mode efficiency.

[0042] Figure 6 This is a static current configuration diagram of a conventional power amplifier circuit provided in an embodiment of this application;

[0043] Figure 7 This is a load traction diagram of the final stage PA in HPM according to an embodiment of this application;

[0044] Figure 8 This is a load traction diagram of the final stage PA in the LPM according to an embodiment of this application;

[0045] Figure 9 A circuit diagram of a conventional power amplifier circuit provided in another embodiment of this application;

[0046] Figure 10 A circuit diagram of a power amplifier circuit provided in an embodiment of this application;

[0047] Figure 11 A circuit diagram of another power amplifier circuit provided in this application embodiment;

[0048] Figure 12 A circuit diagram of another power amplifier circuit provided in this application embodiment;

[0049] Figure 13 A circuit diagram of another power amplifier circuit provided in this application embodiment;

[0050] Figure 14 A circuit diagram of another power amplifier circuit provided in this application embodiment;

[0051] Figure 15 A circuit diagram of another power amplifier circuit provided in this application embodiment;

[0052] Figure 16 A circuit diagram of another power amplifier circuit provided in this application embodiment;

[0053] Figure 17 A circuit diagram of another power amplifier circuit provided in this application embodiment;

[0054] Figure 18 This is a load traction diagram of a power amplifier module in an LPM according to an embodiment of this application;

[0055] Figure 19 This is another embodiment of the power amplifier module provided in this application, showing the load pull diagram of the LPM.

[0056] Figure 20 A simulation diagram of the switching insertion loss of a power amplifier module provided in an embodiment of this application;

[0057] Figure 21 This is a graph showing the operating efficiency of a power amplifier module provided in an embodiment of this application. Detailed Implementation

[0058] The technical solutions in the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; the word "and / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.

[0059] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0060] To facilitate understanding of the embodiments of this application, the relevant concepts involved in the embodiments of this application will be briefly explained first.

[0061] 1. Power amplifier (PA).

[0062] In radio frequency (RF) circuits, a power amplifier is a circuit that amplifies low-power RF signals to high power. The basic principle of a power amplifier is to convert DC power into RF energy. After the input low-power RF signal is amplified, the output high-power RF signal can be used to drive an antenna transmitter or other devices. During the amplification process, it is necessary to ensure the amplifier's linearity, stability, and efficiency to guarantee the quality and stability of the output signal. For example, a power amplifier may include high-power mode (HPM), low-power mode (LPM), and medium-power mode (MPM).

[0063] 2. Radio frequency front end (RFFE).

[0064] In the field of communications, the radio frequency front end refers to a series of components between the radio frequency transceiver and the antenna, mainly including power amplifiers (PA), antenna switches, filters, duplexers and diplexers, and low noise amplifiers (LNA), which directly affect the signal transmission and reception of electronic devices.

[0065] 3. Single-pole double-throw (SPDT) switch.

[0066] In the field of communications, a single-pole double-throw (SPD) switch consists of a moving contact and a fixed contact. The moving contact, also known as the "pole," connects to the incoming power supply line, which is usually the end connected to the switch handle. The other two ends are the power output ends, also known as the fixed contacts, which are connected to the electrical equipment. The function of a SPD switch is twofold: firstly, it can control the power output in two different directions, meaning it can be used to control two devices, or it can control the same device by changing its operating direction.

[0067] 4. Double Pole X Throw (DPXT) switch.

[0068] A double-pole double-throw switch is a type of changeover switch consisting of two moving terminals and multiple stationary terminals, used to control the connection between the power supply at the moving terminals and the electrical equipment at the stationary terminals. For example, a double-pole double-throw (DPDT) switch is a type of changeover switch consisting of two moving terminals and two stationary terminals.

[0069] 5. Metal-oxide-semiconductor field-effect transistor (MOSFET).

[0070] In the field of circuits, a MOSFET refers to a voltage-driven semiconductor device. A MOSFET typically has three electrodes: a gate (G), a source (S), and a drain (D). Based on their semiconductor structure, MOSFETs can be classified into PMOSFETs and NMOSFETs. In general electronic circuits, MOSFETs are commonly used in amplifier circuits or switching circuits. As a voltage-controlled element, a MOSFET allows current to flow through its source and drain when the voltage applied to its gate exceeds a preset value. For example, when the voltage received at the gate of an NMOSFET is greater than a preset value, the source and drain of the NMOSFET conduct; when the voltage received at the gate of an NMOSFET is not greater than the preset value, the source and drain of the NMOSFET are cut off. Similarly, when the voltage received at the gate of a PMOSFET is less than a preset value, the source and drain of the PMOSFET conduct; when the voltage received at the gate of a PMOSFET is not less than the preset value, the source and drain of the PMOSFET are cut off.

[0071] 6. Load pull diagram.

[0072] In the field of communications, load pull diagrams are a graphical representation method used to describe the performance of radio frequency / microwave power devices. Figure 1 Typically, by systematically varying the load impedance applied to the device under test (DUT) and recording performance data under different load values, contour lines reflecting device performance indicators (such as output power, power-added efficiency, etc.) are plotted. These contour lines are usually drawn on a Smith chart to visually demonstrate the performance changes of the device under different load conditions.

[0073] 7. Long Term Evolution (LTE).

[0074] In the field of communications, LTE is a long-term evolution of the Universal Mobile Telecommunications System (UMTS) technical standard developed by the 3rd Generation Partnership Project (3GPP) and is widely used in 4G networks.

[0075] 8. New Radio (NR).

[0076] In the field of communications, NR refers to a global 5G standard based on a new air interface design using orthogonal frequency division multiplexing (OFDM).

[0077] 9. Bias circuit.

[0078] In the field of communications, bias circuits, also known as DC voltage divider networks or offset circuits, are commonly used in electronic devices and integrated circuits to control the operating point of semiconductor devices such as transistors and field-effect transistors (FETs), stabilizing them at a specific operating state. For example, a bias circuit can serve as the base signal circuit for a transistor, providing a bias signal for its operation. The operating point refers to the potential at which the base, emitter, and collector of a transistor are positioned by external circuitry. This potential can be calculated. These external circuits are called bias circuits. They can also be understood as circuits that set the PN junction to forward or reverse bias. Furthermore, the current supplied to the transistor by the bias circuit is called the bias current.

[0079] 10. Power transistors.

[0080] In the field of communications, a power transistor is a semiconductor device used to control large currents and high voltages. It is primarily composed of P-type and N-type semiconductor materials with a PN junction and is typically used as a modulation switch or linear amplifier. They are capable of handling large currents and power while simultaneously providing precise current control, signal amplification, and switching functions. Examples of power transistors include bipolar junction transistors (BJTs), power field-effect transistors (MOSFETs), power electrostatic discharge transistors (ESDs), isolated-gate transistors (IGBTs), and composite transistors.

[0081] The above is a brief introduction to the terms used in the embodiments of this application, and will not be repeated below.

[0082] The following is combined Figures 1 to 3 First, the application scenarios and the structure of the electronic devices used in the embodiments of this application will be introduced.

[0083] Figure 1 This is a schematic diagram of a scenario for an electronic device to which an embodiment of this application applies.

[0084] like Figure 1 As shown, users can communicate with base station 20 using electronic device 10. This application does not specifically limit the type of electronic device 10. In some specific embodiments, electronic device 10 can be a mobile phone, wearable device (e.g., smart bracelet, smartwatch, earphones, etc.), tablet computer, laptop computer, handheld computer, ultra-mobile personal computer (UMPC), cellular phone, personal digital assistant (PDA), augmented reality (AR) / virtual reality (VR) device, or other IoT (Internet of Things) devices, as well as devices such as televisions, large screens, printers, and projectors. For ease of understanding, the following embodiments use a mobile phone as an example for illustrative purposes.

[0085] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0086] like Figure 2 As shown in the embodiments of this application, the electronic device 10 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, a first antenna 1, a second antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an accelerometer sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0087] It should be noted that, Figure 2The structure shown does not constitute a specific limitation on the electronic device 10. In other embodiments of this application, the electronic device 10 may include a larger... Figure 2 The components shown may include more or fewer components, or the electronic device 10 may include... Figure 2 The components shown may be a combination of certain components, or the electronic device 10 may include... Figure 2 Sub-components of some of the components shown. Figure 2 The components shown can be implemented in hardware, software, or a combination of both.

[0088] Processor 110 may include one or more processing units. For example, processor 110 may include at least one of the following processing units: application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and neural network processing unit (NPU). These different processing units may be independent devices or integrated devices. The controller can generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution.

[0089] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0090] In some embodiments, processor 110 may include one or more interfaces. For example, processor 110 may include at least one of the following interfaces: an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a SIM interface, and a USB interface.

[0091] USB interface 130 is used to connect with other devices, thereby enabling electronic device 10 to communicate with the outside world or charge, etc. For example, it supports more than 10 charging protocols, On-the-Go (OTG) USB functionality, analog headset functionality, digital headset functionality, and display port (DP) functionality, etc. For example, USB interface 130 can be a Type-C interface.

[0092] Figure 2 The connection relationships between the modules shown are merely illustrative and do not constitute a limitation on the connection relationships between the modules of the electronic device 10. Optionally, the modules of the electronic device 10 may also adopt a combination of various connection methods described in the above embodiments.

[0093] The charging management module 140 receives power from the charger. While charging the battery 142, the charging management module 140 can also power electronic devices via the power management module 141. The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and powers the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication module 160, etc. The power management module 141 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (e.g., leakage current, impedance). Optionally, the power management module 141 can be located within the processor 110, or the power management module 141 and the charging management module 140 can be located in the same device.

[0094] The wireless communication function of electronic device 10 can be implemented through devices such as a first antenna 1, a second antenna 2, a mobile communication module 150, a wireless communication module 160, a modem processor, and a baseband processor. The first antenna 1 and the second antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 10 can be used to cover one or more communication frequency bands. Different antennas can also be reused to improve antenna utilization.

[0095] The mobile communication module 150 can provide a wireless communication solution for use in electronic devices, such as at least one of the following: a second-generation (2G) mobile communication solution, a third-generation (3G) mobile communication solution, a fourth-generation (5G) mobile communication solution, or a fifth-generation (5G) mobile communication solution.

[0096] The modem processor may include a modulator and a demodulator. The modulator modulates a low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates a received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs sound signals through audio devices (e.g., speaker 170A, receiver 170B) or displays images or videos through the display screen 194. In some embodiments, the modem processor may be a separate device. In other embodiments, the modem processor may be independent of the processor 110 and may be housed in the same device as the mobile communication module 150 or other functional modules.

[0097] Similar to the mobile communication module 150, the wireless communication module 160 can also provide wireless communication solutions for use in electronic devices, such as at least one of the following: wireless local area networks (WLAN), Bluetooth (BT), Bluetooth Low Energy (BLE), ultra-wideband (UWB), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) technology, etc.

[0098] In some embodiments, the first antenna 1 of the electronic device 10 is coupled to the mobile communication module 150, and the second antenna 2 of the electronic device 10 is coupled to the wireless communication module 160, so that the electronic device 10 can communicate with the network and other electronic devices through wireless communication technology.

[0099] Electronic device 10 can implement display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0100] In some embodiments, the first antenna 1 of the electronic device 10 is coupled to the mobile communication module 150, and the second antenna 2 of the electronic device 10 is coupled to the wireless communication module 160, enabling the electronic device to communicate with the network and other electronic devices via wireless communication technology.

[0101] The external storage interface 120 can be used to connect an external memory card, such as a secure digital (SD) card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0102] Internal memory 121 can be used to store executable program code, including instructions. Internal memory 121 may include a program storage area and a data storage area. Internal memory 121 may be volatile memory or non-volatile memory, or both. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0103] The display screen 194 can be used to display images or videos. Optionally, the display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a mini light-emitting diode (Mini LED), a micro light-emitting diode (Micro LED), a micro OLED, or a quantum dot light-emitting diode (QLED). In some embodiments, the electronic device 10 may include one or N displays 194, where N is a positive integer greater than 1.

[0104] Button 190 includes a power button and volume buttons. Button 190 can be a mechanical button or a touch button. The electronic device can receive button input signals and realize functions related to the button input signals.

[0105] Figure 3 This is a schematic diagram of the structure of another electronic device provided in this application embodiment.

[0106] like Figure 3 As shown, the electronic device 10 may include a baseband subsystem 101, a radio frequency subsystem 102 consisting of a radio frequency integrated circuit (RFIC) 1021 and a radio frequency frontend (RFFE) 1022, an antenna (ANT) subsystem 103, a power supply subsystem 104, etc. These devices can be coupled through various interconnect buses or other electrical connection methods.

[0107] The baseband subsystem 101 can extract useful information or data bits from the baseband signal, or convert information or data bits into a baseband signal to be transmitted. These information or data bits can represent user data or control information such as voice, text, or video. For example, the baseband subsystem 101 can implement signal processing operations such as modulation and demodulation, encoding and decoding. Different baseband signal processing operations can be provided for different wireless access technologies, such as 5G New Radio (NR) and 4G Long Term Evolution (LTE). Therefore, to support multiple mobile communication modes, the baseband subsystem 101 can simultaneously include multiple processing cores or multiple hardware accelerators (HACs). The baseband subsystem 101 can be integrated into one or more chips.

[0108] For example, the baseband subsystem 101 can be a standalone chip, which may be referred to as a modem chip. The hardware components of the baseband subsystem 101 can be manufactured and sold as modem chips. The modem chip may also be referred to as a baseband chip or a baseband processor. Furthermore, the baseband subsystem 101 can also be further integrated into a system-on-chip (SOC) chip, manufactured and sold as SOC chips. The software components of the baseband subsystem 101 can be built into the chip's hardware components before the chip leaves the factory, or they can be imported into the chip's hardware components from other non-volatile memory after the chip leaves the factory, or these software components can be downloaded and updated online via a network.

[0109] Furthermore, since radio frequency signals are analog signals, and the baseband subsystem 101 primarily processes digital signals, the electronic device also requires an analog-to-digital converter (ADC). The ADC may include an analog-to-digital converter (ADC) that converts analog signals to digital signals, and a digital-to-analog converter (DAC) that converts digital signals to analog signals. It should be understood that the ADC and DAC can be located in either the baseband subsystem 101 or the radio frequency subsystem 102, and this embodiment does not impose any limitations on this.

[0110] The radio frequency (RF) subsystem 102 can be divided into an RF receive path and an RF transmit path. The RF receive path receives RF signals via an antenna, processes these signals (e.g., amplification, filtering, down-conversion, and analog-to-digital conversion) to obtain a baseband signal, and then transmits it to the baseband subsystem 101. The RF transmit path receives baseband signals from the baseband subsystem 101, processes these signals (e.g., up-conversion, amplification, filtering, and digital-to-analog conversion) to obtain an RF signal, and then radiates this RF signal into space via an antenna. Specifically, the RF subsystem 102 may include electronic components such as RF switches, duplexers, antenna tuners, low-noise amplifiers (LNAs), power amplifiers, mixers, local oscillators (LOs), and filters. These electronic components can be integrated into one or more chips as needed. Antennas can sometimes be considered part of the RF subsystem 102.

[0111] For example, the aforementioned electronic components can be separately disposed in the antenna, the RF front-end module 1022, and the RF transceiver chip 1021 as needed. The RF transceiver chip 1021 can be composed of devices such as a mixer and a local oscillator. The local oscillator is used to provide a local oscillator signal; the mixer is used to mix the RF signal with the local oscillator signal provided by the local oscillator. The RF transceiver chip 1021 can also be referred to as a receiver, transmitter, or transceiver.

[0112] The RF front-end module 1022 can be composed of electronic components such as filters, RF front-end modules, power amplifiers, and RF switches. The RF switches are used to switch between RF signal reception and transmission, and between different frequency bands; the duplexer is used to isolate the RF signal transmission path and the reception path, thereby ensuring normal operation of reception and transmission when sharing the same antenna; the filter is used to retain signals within a specific frequency band while filtering out signals outside the characteristic frequency band. The RF front-end module is used to amplify the RF signal in the receiving channel; the power amplifier is used to amplify the RF signal in the transmitting channel.

[0113] In this embodiment, the radio frequency front-end module 1022 may include a radio frequency switch.

[0114] Here, the RF transceiver chip 1021 can output control signals to components such as the RF switch in the RF front-end module 1022 through the control line, thereby controlling the RF switch to switch between different links.

[0115] It should be understood that the above is only one example. The radio frequency subsystem 102 may also include other devices or adopt other integration methods. For example, some devices belonging to the radio frequency front-end module 1022 may be integrated into the radio frequency transceiver chip 1021. Alternatively, the antenna and the radio frequency front-end module 1022 may both be integrated into the radio frequency transceiver chip 1021. The specific settings and modifications can be made as needed. This application embodiment does not impose any restrictions on this.

[0116] Antenna subsystem 103 includes multiple antennas, where ANT1 represents the first antenna, ANTn represents the nth antenna, and n is a positive integer greater than 1. Antenna subsystem 103 may also include antenna switches for switching to different antennas, thereby enabling different signals to be transmitted using different antennas.

[0117] The power supply subsystem 104 is used to supply power to various devices; for example, the power supply can provide voltage to a power amplifier. The power supply subsystem 104 may include multiple power supplies, which may be the same or different. The power supply subsystem 104 can also supply power to the baseband subsystem 101, the radio frequency subsystem 102, and the antenna subsystem 103, which may use the same power supply or different power supplies.

[0118] In addition, the electronic device 10 may also include an application subsystem, which can serve as the main control system or main computing system of the electronic device 10. This application subsystem runs the main operating system and applications, manages the hardware and software resources of the entire electronic device 10, and provides a user interface. The application subsystem may include one or more processing cores. Furthermore, the application subsystem may also include driver software related to other subsystems (such as the baseband subsystem 101). The baseband subsystem 101 may also include one or more processing cores, as well as hardware accelerators and caches, etc.

[0119] It should be understood that the above is only an example of the structure of electronic device 10. Electronic device 10 may also include other subsystems or devices, which can be set and modified as needed. This application embodiment does not impose any restrictions on this.

[0120] The following is combined Figures 4 to 9 Next, the structure and existing problems of the conventional power amplifier circuit provided in the embodiments of this application will be introduced.

[0121] Figure 4 This is a circuit diagram of a conventional power amplifier circuit provided in an embodiment of this application.

[0122] like Figure 4As shown, the RF front-end module 1022 can use a power amplifier 30 to amplify the RF signal in the communication path, thereby enabling communication with the base station 20 or a WIFI hotspot. Exemplarily, the power amplifier 30 includes a driver stage PA301, a final stage PA302, and a band switch 303. An input matching 304 is connected between the driver stage PA and the input terminal. An inter-stage matching 305 is connected between the driver stage PA301 and the final stage PA302. An output matching 306 is connected between the final stage PA302 and the band switch 303. The driver stage PA301 is mainly used to amplify the input signal, and its power is relatively low, so the number of power transistors in the driver stage PA301 is small, and its area is small. The final stage PA302 is mainly used to further amplify the signal from the driver stage PA301 to a higher power, and its power is relatively high. Therefore, the number of power transistors in the final stage PA302 is large, and its area is large. The band switch 303 is used to select the output to operate on different frequency bands. Exemplarily, the band switch 303 can also be connected to duplexers or filters of different frequency bands. Among them, the input matching 304, the interstage matching 305, and the output matching 306 are all impedance networks.

[0123] Figure 5 This is an efficiency diagram of a conventional power amplifier circuit provided in an embodiment of this application, showing its operating mode.

[0124] As one of the main power-consuming components in a communication system, the power amplifier 30 faces increasingly higher demands for output power and efficiency from smart terminal products due to their demands for communication quality and battery life. In current communication systems, the power amplifier 30 of the terminal product is not always transmitting at maximum power. For example, when the terminal product is in a weak field (e.g., the phone is far from the base station 20), it will transmit at maximum power to ensure communication quality. When the terminal product is in a strong field (e.g., the phone is close to the base station 20), less power is needed for good communication, so it will adjust to a lower power transmission state to save power and improve battery life. In actual applications, high-power and low-power transmission scenarios coexist, and the proportion of low-power transmission scenarios may even be higher. The terminal product adjusts its power output by changing the transceiver's transmit power, thus enabling it to transmit signals at different power levels.

[0125] like Figure 5As shown, currently, when the end product is in different application scenarios, the power amplifier 30 can have three different operating modes: low power mode (LPM), medium power mode (MPM), and high power mode (HPM). The output power of LPM, MPM, and HPM increases in that order, with LPM having the lowest output power. Simultaneously, the operating efficiency of LPM, MPM, and HPM also increases in that order, with LPM having the lowest efficiency. Generally, the power amplifier 30 also incorporates methods to reduce the VCC voltage to improve the operating efficiency of the end product in LPM mode. However, due to the large area of ​​the power transistor in the final stage PA, the operating efficiency of the end product in LPM mode remains relatively low.

[0126] Figure 6 This is a static current configuration diagram of a conventional power amplifier circuit provided in an embodiment of this application.

[0127] like Figure 6 As shown, the end product typically configures the power amplifier 30 to different operating modes simultaneously through output power and static bias current. For example, since the end product can have three output power modes: LPM, MPM, and HPM, correspondingly, the static bias current can also be set to three modes. Generally, LPM, MPM, and HPM will have different static bias currents. When the end product is in LPM mode, the static bias current is lower, and the output power is also lower.

[0128] Figure 7 This is a load traction diagram of the final stage PA in HPM according to an embodiment of this application.

[0129] like Figure 7 The load pull diagram shown illustrates that since the primary function of the final stage PA is to output a high-power signal, the power amplifier 30 will match its output impedance to the high-power region. For example, when the final stage PA is in HPM mode, the optimal power-matched impedance is approximately 9Ω. When the final stage PA outputs a relatively high power of 27dBm, the operating efficiency is 32–36%.

[0130] Figure 8 This is a load traction diagram of the final stage PA in the LPM according to an embodiment of this application.

[0131] like Figure 8The load pull diagram shown illustrates that when the final stage PA is in LPM mode, the power amplifier 30 typically adjusts the static bias current and VCC voltage, resulting in a fixed output matching. Therefore, the output impedance of the final stage PA remains around 9Ω. When the final stage PA outputs a relatively low power of 5dBm, the operating efficiency is 5%, significantly lower than the 32-36% operating efficiency at HPM.

[0132] Currently, to address the issue of low efficiency of the final stage PA in LPM mode, another embodiment can be implemented by adding an HPM switch and an LPM path between the driver stage PA and the final stage PA. When the power amplifier 30 is in LPM mode, the HPM switch is open, and the RF signal reaches the output terminal through the LPM path. Since there is a certain proportional relationship between the area of ​​the driver stage PA and the area of ​​the final stage PA in the power amplifier 30, and the power output capabilities of both the driver stage PA and the final stage PA need to be satisfied simultaneously, the output power of the power amplifier 30 is fixed when it is in LPM mode in this solution. However, when the power amplifier 30 is in HPM mode, more matching components are connected to the output terminal, resulting in more parasitic parameters affecting the output power and operating efficiency of the power amplifier 30.

[0133] Figure 9 This is a circuit diagram of a conventional power amplifier circuit provided in another embodiment of this application.

[0134] like Figure 9 As shown, in another embodiment, an LPM path is added next to the main path of the power amplifier 30 for use when the power amplifier 30 is in LPM mode. The LPM path includes an LPM PA307, an LPM input match 308, and an LPM output match 309. The LPM PA307 is connected to the first terminal of the LPM input match 308 and the first terminal of the LPM output match 309, respectively. The second terminal of the LPM input match 308 is connected to the LPM input signal, and the second terminal of the LPM output match 309 is connected to the band switch 303. The band switch 303 is used to output multiple bands, such as OUT to band x, OUT to band y, OUT to band z, etc.

[0135] It should be understood that in this embodiment, the band switch 303 is a DPNT switch. Although this approach can optimize the design of the LPM path according to the power of the LPM, the separate LPM path and impedance matching not only increase the chip area of ​​the power amplifier 30, but also require the band switch at the output of the power amplifier 30 to be changed from SPnT to DPNT, resulting in a larger size and higher cost.

[0136] In view of this, embodiments of this application provide a power amplifier circuit that effectively improves the operating efficiency of the power amplifier circuit in low-power mode by controlling and reducing the number of power transistor units in the power amplifier circuit in low-power mode.

[0137] The following is combined Figures 10 to 21 The solutions provided in the embodiments of this application will then be described in detail.

[0138] Figure 10 This is a circuit diagram of a power amplifier circuit provided in an embodiment of this application.

[0139] like Figure 10 As shown, in one embodiment of this application, a power amplifier circuit 40 is provided. The power amplifier circuit 40 includes a power amplifier module 401 and a bias circuit module 402. The power amplifier module 401 includes a plurality of power transistor units 4011, the input terminals of which are interconnected, and the output terminals of which are interconnected. The bias circuit module 402 includes a plurality of bias circuit units 4021, each bias circuit unit 4021 being connected to one or more power transistor units 4011. When the power amplifier module 401 is in a first power mode, a first number of power transistor units 4011 are controlled to be in a conducting state by the plurality of bias circuit units 4021. When the power amplifier module 401 is in a second power mode, a second number of power transistor units 4011 are controlled to be in a conducting state by the plurality of bias circuit units 4021. The first number is greater than the second number. The power of the first power mode is greater than the power of the second power mode.

[0140] It should be noted that a power amplifier generally consists of a preamplifier and a final amplifier. The preamplifier, as the driver stage, typically has lower power and fewer internal power transistors. Therefore, whether the power amplifier is in HPM or LPM mode has a relatively small impact on its efficiency. Furthermore, the preamplifier generally uses a bias circuit to control its on / off state. The final amplifier, as the power amplification stage, typically has higher power and more internal power transistors. Therefore, whether the power amplifier is in HPM or LPM mode has a significant impact on its efficiency. Especially when the power amplifier is in LPM mode, the larger number of power transistors can easily lead to lower efficiency. Additionally, the final amplifier generally uses a bias circuit to control its on / off state.

[0141] Therefore, in this embodiment, to facilitate the control of the conduction state of multiple power transistor units 4011, multiple bias circuit units 4021 can be provided, each bias circuit unit 4021 controlling the conduction state of one or more power transistor units 4011. When the power amplifier module 401 is in a higher power first power mode (e.g., HPM), multiple bias circuit units 4021 control a larger number of power transistor units 4011 to be in the conduction state to provide a higher power amplified signal. When the power amplifier module 401 is in a lower power second power mode (e.g., LPM), multiple bias circuit units 4021 control a smaller number of power transistor units 4011 to be in the conduction state to provide a lower power amplified signal. This reduces the number of power transistor units in the power amplifier circuit 40 in the low power mode, effectively improving the operating efficiency of the power amplifier circuit 40 in the low power mode.

[0142] It should be understood that the process of multiple bias circuit units 4021 controlling multiple power transistor units 4011 can be achieved by enabling the bias circuit on the gallium arsenide (GaAs) power amplifier chip through complementary metal-oxide-semiconductor (CMOS) circuitry.

[0143] Optionally, depending on the actual needs, the power transistor unit 4011 can be selected from one or more of MOSFET, transistor or IGBT.

[0144] Figure 11 This is a circuit diagram of another power amplifier circuit provided in this application embodiment.

[0145] like Figure 11As shown, in one embodiment of this application, a power amplifier circuit 40 is provided. The power amplifier circuit 40 includes a power amplifier module 401, a bias circuit module 402, and a first output impedance 403. The power amplifier module 401 includes a plurality of power transistor units 4011, the input terminals of which are interconnected, and the output terminals of which are interconnected. The bias circuit module 402 includes a plurality of bias circuit units 4021, each bias circuit unit 4021 being connected to one or more power transistor units 4011. When the power amplifier module 401 is in a first power mode, a first number of power transistor units 4011 are controlled to be in a conducting state by the plurality of bias circuit units 4021. When the power amplifier module 401 is in a second power mode, a second number of power transistor units 4011 are controlled to be in a conducting state by the plurality of bias circuit units 4021. The first number is greater than the second number. The power of the first power mode is greater than the power of the second power mode. The first end of the first output impedance 403 is connected to the output end of the power amplifier module 401, and the first end of the first output impedance 403 serves as the output end of the power amplifier circuit 40.

[0146] It should be noted that the embodiments of this application are different from those of the previous ones. Figure 10 The difference in the illustrated embodiment is that the output terminal of the power amplifier module 401 is provided with a first output impedance 403. When the power amplifier module 401 is in either the first power mode or the second power mode, the output signal of the power amplifier module 401 passes through the first output impedance 403. Since the impedance value of the first output impedance 403 is fixed, the first output impedance 403 has the same effect on the output signal in both the first power mode and the second power mode.

[0147] The following section provides a detailed introduction to the scheme of adding a single-pole single-throw switch and output impedance in a power amplifier circuit.

[0148] Figure 12 This is a circuit diagram of another power amplifier circuit provided in this application embodiment.

[0149] like Figure 12As shown, in one embodiment of this application, a power amplifier circuit 40 is provided. The power amplifier circuit 40 includes a power amplifier module 401, a bias circuit module 402, a first output impedance 403, a first switch 404, and a second output impedance 405. The power amplifier module 401 includes a plurality of power transistor units 4011, the input terminals of which are interconnected, and the output terminals of which are interconnected. The bias circuit module 402 includes a plurality of bias circuit units 4021, each bias circuit unit 4021 being connected to one or more power transistor units 4011. When the power amplifier module 401 is in a first power mode, a first number of power transistor units 4011 are controlled to be in a conducting state by the plurality of bias circuit units 4021. When the power amplifier module 401 is in a second power mode, a second number of power transistor units 4011 are controlled to be in a conducting state by the plurality of bias circuit units 4021. The first number is greater than the second number. The power of the first power mode is greater than the power of the second power mode. The first terminal of the first output impedance 403 is connected to the output terminal of the power amplifier module 401, and the second terminal of the first output impedance 403 is connected to the first terminal of the first switch 404. The second terminal of the first switch 404 is connected to the first terminal of the second output impedance 405. When the power amplifier module 401 is in the first power mode, the first switch 404 is in the off state. When the power amplifier module 401 is in the second power mode, the first switch 404 is in the on state.

[0150] In this embodiment, when the power amplifier module 401 is in a higher power first power mode (e.g., HPM), a plurality of bias circuit units 4021 control a larger number of power transistor units 4011 to be in the on state to provide a higher power amplified signal. Simultaneously, the first switch 404 is in the off state, thereby making the output impedance of the power amplifier module 401 the first output impedance 403 to match the higher power amplified signal.

[0151] When the power amplifier module 401 is in a lower power second power mode (e.g., LPM), a smaller number of power transistor units 4011 are controlled to be in the conducting state by multiple bias circuit units 4021 to provide a lower power amplified signal. Simultaneously, the first switch 404 is in the conducting state, so that the output impedance of the power amplifier module 401 is obtained by connecting the first output impedance 403 in parallel with the second output impedance 405 to match the lower power amplified signal. This not only reduces the number of power transistor units in the power amplifier circuit 40 in low power mode, but also provides impedance compensation for the power amplifier module 401 in low power mode, adjusting the output impedance of the power amplifier module 401 to adapt to the low power mode, thereby effectively improving the operating efficiency of the power amplifier circuit 40 in low power mode.

[0152] Figure 13 This is a circuit diagram of another power amplifier circuit provided in this application embodiment.

[0153] like Figure 13 As shown, in one embodiment of this application, a power amplifier circuit 40 is provided. The power amplifier circuit 40 includes a power amplifier module 401, a bias circuit module 402, a first output impedance 403, a first switch 404, a second output impedance 405, and a second switch 406. The power amplifier module 401 includes multiple power transistor units 4011, whose input terminals are interconnected, and whose output terminals are interconnected. The bias circuit module 402 includes multiple bias circuit units 4021, each bias circuit unit 4021 being connected to one or more power transistor units 4011. When the power amplifier module 401 is in a first power mode, the multiple bias circuit units 4021 control a first number of power transistor units 4011 to be in a conducting state. When the power amplifier module 401 is in a second power mode, the multiple bias circuit units 4021 control a second number of power transistor units 4011 to be in a conducting state. The first number is greater than the second number. The power of the first power mode is greater than the power of the second power mode. The first terminal of the first output impedance 403 is connected to the output terminal of the power amplifier module 401, and the second terminal of the first output impedance 403 is connected to the first terminal of the first switch 404. The second terminal of the first switch 404 is connected to the first terminal of the second output impedance 405. The first terminal of the second switch 406 is connected to the output terminal of the power amplifier module 401, and the second terminal of the second switch 406 is connected to the second terminal of the second output impedance 405. When the power amplifier module 401 is in the first power mode, the first switch 404 and the second switch 406 are in the off state. When the power amplifier module 401 is in the second power mode, the first switch 404 and the second switch 406 are in the on state.

[0154] In this embodiment, when the power amplifier module 401 is in a higher power first power mode (e.g., HPM), a plurality of bias circuit units 4021 control a larger number of power transistor units 4011 to be in a conducting state to provide a higher power amplified signal. Simultaneously, the first switch 404 and the second switch 406 are in a closed state, thereby making the output impedance of the power amplifier module 401 the first output impedance 403 to match the higher power amplified signal. Furthermore, the quiescent current of each of the larger number of power transistor units 4011 can be the same.

[0155] When the power amplifier module 401 is in a lower power second power mode (e.g., LPM), a smaller number of power transistor units 4011 are controlled to be in the conducting state by multiple bias circuit units 4021 to provide a lower power amplified signal. Simultaneously, the first switch 404 and the second switch 406 are in the conducting state, making the output impedance of the power amplifier module 401 the parallel impedance of the first output impedance 403 and the second output impedance 405, to match the lower power amplified signal. This not only reduces the number of power transistor units in the power amplifier circuit 40 in low power mode, but also provides impedance compensation for the power amplifier module 401 in low power mode, adjusting the output impedance of the power amplifier module 401 to adapt to the low power mode, thereby effectively improving the operating efficiency of the power amplifier circuit 40 in low power mode.

[0156] Optionally, since the first switch 404 and the second switch 406 only need to achieve the opening and closing of a single path, both the first switch 404 and the second switch 406 can be single-pole single-throw switches, which are not only smaller in size and do not occupy too much internal space of the power amplifier module 401, but also have lower cost.

[0157] Figure 14 This is a circuit diagram of another power amplifier circuit provided in this application embodiment.

[0158] like Figure 14As shown, in one embodiment of this application, a power amplifier circuit 40 is provided. The power amplifier circuit 40 includes a power amplifier module 401, a bias circuit module 402, a first output impedance 403, a first switch 404, a second output impedance 405, a second switch 406, and a first band switch module 407. The power amplifier module 401 includes multiple power transistor units 4011, whose input terminals are interconnected, and whose output terminals are interconnected. The bias circuit module 402 includes multiple bias circuit units 4021, each bias circuit unit 4021 being connected to one or more power transistor units 4011. When the power amplifier module 401 is in a first power mode, the multiple bias circuit units 4021 control a first number of power transistor units 4011 to be in a conducting state. When the power amplifier module 401 is in a second power mode, the multiple bias circuit units 4021 control a second number of power transistor units 4011 to be in a conducting state. The first number is greater than the second number. The power of the first power mode is greater than the power of the second power mode. The first terminal of the first output impedance 403 is connected to the output terminal of the power amplifier module 401, the second terminal of the first output impedance 403 is connected to the first terminal of the first switch 404, and the second terminal of the first switch 404 is connected to the first terminal of the second output impedance 405. The first terminal of the second switch 406 is connected to the output terminal of the power amplifier module 401, and the second terminal of the second switch 406 is connected to the second terminal of the second output impedance 405. When the power amplifier module 401 is in the first power mode, the first switch 404 and the second switch 406 are in the off state. When the power amplifier module 401 is in the second power mode, the first switch 404 and the second switch 406 are in the on state. The input terminal of the first band switch module 407 is connected to the second terminal of the first output impedance 403, and the output terminal of the first band switch module 407 is used to output signals of multiple power bands.

[0159] In this embodiment, when the power amplifier module 401 is in a higher power first power mode (e.g., HPM), multiple bias circuit units 4021 control a larger number of power transistor units 4011 to be in a conducting state to provide a higher power amplified signal. Simultaneously, the first switch 404 and the second switch 406 are in a disconnected state, thereby making the output impedance of the power amplifier module 401 the first output impedance 403 to match the higher power amplified signal. Finally, the first band switching module 407 selects the corresponding band for output of the power signal amplified by the power amplifier module 401.

[0160] When the power amplifier module 401 is in a lower power second power mode (e.g., LPM), a smaller number of power transistor units 4011 are controlled to be in the conducting state by multiple bias circuit units 4021 to provide a lower power amplified signal. Simultaneously, the first switch 404 and the second switch 406 are in the conducting state, making the output impedance of the power amplifier module 401 the parallel impedance of the first output impedance 403 and the second output impedance 405, to match the lower power amplified signal. Finally, the first band switching module 407 selects the corresponding band for the output of the power signal amplified by the power amplifier module 401. This not only reduces the number of power transistor units in the low-power mode of the power amplifier circuit 401, but also provides impedance compensation for the power amplifier module 401 in low-power mode, adjusting the output impedance of the power amplifier module 401 to adapt to the low-power mode, thereby effectively improving the operating efficiency of the power amplifier circuit 401 in low-power mode.

[0161] Optionally, since the first band switching module 407 only needs to select a different band output for one output signal of the power amplifier module 401, the first band switching module 407 can be a single-pole multi-throw switch.

[0162] It should be noted that the first switch 404, the second output impedance 405, and the second switch 406 can be disposed either in the first band switch module 407 or on the substrate.

[0163] It should be noted that this solution can also be applied to scenarios where power amplifiers are multiplexed for different signal standards. For example, some standards require high signal power, while others require low signal power. Multiple bias circuit units 4021 can control different numbers of power transistor units 4011 to be in the on state to adapt to standards with different signal power levels. For instance, cellular power amplifiers in certain frequency bands (e.g., high-frequency bands (HB) below 3 GHz) can cover the Bluetooth transmission frequency band, thus allowing cellular power amplifiers to be multiplexed for Bluetooth transmission.

[0164] It should be noted that this solution can also be applied to power amplifiers with different power levels. For example, by grouping the power transistors into different numbers according to the required power level and number of power levels for different application scenarios, and by using an impedance compensation network to compensate for different impedances, the operating efficiency of multiple power levels can be improved.

[0165] The following section provides a detailed explanation of the solution for adding a single-pole double-throw switch and increasing the output impedance in a power amplifier circuit.

[0166] Figure 15This is a circuit diagram of another power amplifier circuit provided in this application embodiment.

[0167] like Figure 15 As shown, in one embodiment of this application, a power amplifier circuit 40 is provided. The power amplifier circuit 40 includes a power amplifier module 401, a bias circuit module 402, a third switch 408, a third output impedance 409, and a fourth output impedance 410. The power amplifier module 401 includes multiple power transistor units 4011, whose input terminals are interconnected, and whose output terminals are interconnected. The bias circuit module 402 includes multiple bias circuit units 4021, each bias circuit unit 4021 being connected to one or more power transistor units 4011. When the power amplifier module 401 is in a first power mode, a first number of power transistor units 4011 are controlled to be in a conducting state by the multiple bias circuit units 4021. When the power amplifier module 401 is in a second power mode, a second number of power transistor units 4011 are controlled to be in a conducting state by the multiple bias circuit units 4021. The first number is greater than the second number. The power of the first power mode is greater than the power of the second power mode. The input terminal of the third switch 408 is connected to the output terminal of the power amplifier module 401. The first output terminal of the third switch 408 is connected to the first terminal of the third output impedance 409, and the second output terminal of the third switch 408 is connected to the first terminal of the fourth output impedance 410. When the power amplifier module 401 is in the first power mode, the input terminal and the first output terminal of the third switch 408 are in a conducting state. When the power amplifier module is in the second power mode, the input terminal and the second output terminal of the third switch 408 are in a conducting state.

[0168] In this embodiment, when the power amplifier module 401 is in a higher power first power mode (e.g., HPM), a plurality of bias circuit units 4021 control a larger number of power transistor units 4011 to be in a conducting state to provide a higher power amplified signal. Simultaneously, the input terminal and the first output terminal of the third switch 408 are controlled to be in a conducting state, making the output impedance of the power amplifier module 401 the third output impedance 409 to match the higher power amplified signal.

[0169] When the power amplifier module 401 is in a lower power second power mode (e.g., LPM), a smaller number of power transistor units 4011 are controlled to be in a conducting state by multiple bias circuit units 4021 to provide a lower power amplified signal. Simultaneously, the input and second output terminals of the third switch 408 are controlled to be in a conducting state, making the output impedance of the power amplifier module 401 a fourth output impedance 410 to match the lower power amplified signal. This not only reduces the number of power transistor units in the power amplifier circuit 40 in low power mode but also provides a suitable impedance for the power amplifier module 401 in low power mode, thereby effectively improving the operating efficiency of the power amplifier circuit 40 in low power mode.

[0170] Optionally, since the third switch 408 needs to select the output signal of the power amplifier module 401 to be turned on to the third output impedance 409 or the fourth output impedance 410, the third switch 408 can be a single-pole double-throw switch.

[0171] Figure 16 This is a circuit diagram of another power amplifier circuit provided in this application embodiment.

[0172] like Figure 16 As shown, in one embodiment of this application, a power amplifier circuit 40 is provided. The power amplifier circuit 40 includes a power amplifier module 401, a bias circuit module 402, a third switch 408, a third output impedance 409, a fourth output impedance 410, and a second band switch module 411. The power amplifier module 401 includes multiple power transistor units 4011, whose input terminals are interconnected, and whose output terminals are interconnected. The bias circuit module 402 includes multiple bias circuit units 4021, each bias circuit unit 4021 being connected to one or more power transistor units 4011. When the power amplifier module 401 is in a first power mode, the multiple bias circuit units 4021 control a first number of power transistor units 4011 to be in a conducting state. When the power amplifier module 401 is in a second power mode, the multiple bias circuit units 4021 control a second number of power transistor units 4011 to be in a conducting state. The first number is greater than the second number. The power of the first power mode is greater than the power of the second power mode. The input terminal of the third switch 408 is connected to the output terminal of the power amplifier module 401. The first output terminal of the third switch 408 is connected to the first terminal of the third output impedance 409, and the second output terminal of the third switch 408 is connected to the first terminal of the fourth output impedance 410. The first input terminal of the second band switch module 411 is connected to the second terminal of the third output impedance 409, and the second input terminal of the second band switch module 411 is connected to the second terminal of the fourth output impedance 410.

[0173] The output of the second band switch module 411 is used to output signals of multiple power bands.

[0174] When the power amplifier module 401 is in the first power mode, the input terminal and the first output terminal of the third switch 408 are in a conducting state, and the first input terminal and the output terminal of the second band switch module 411 are in a conducting state, so as to output a signal of the corresponding band. When the power amplifier module is in the second power mode, the input terminal and the second output terminal of the third switch 408 are in a conducting state, and the second input terminal and the output terminal of the second band switch module 411 are in a conducting state, so as to output a signal of the corresponding band.

[0175] In this embodiment, when the power amplifier module 401 is in a higher power first power mode (e.g., HPM), a plurality of bias circuit units 4021 control a larger number of power transistor units 4011 to be in a conducting state to provide a higher power amplified signal. Simultaneously, the input terminal and the first output terminal of the third switch 408 are controlled to be in a conducting state, making the output impedance of the power amplifier module 401 the third output impedance 409 to match the higher power amplified signal. Simultaneously, the first input terminal and the output terminal of the second band switch module 411 are controlled to be in a conducting state, so that the higher power amplified signal is output as a signal of the corresponding band through the first input and output terminals of the second band switch module 411.

[0176] When the power amplifier module 401 is in a lower power second power mode (e.g., LPM), a smaller number of power transistor units 4011 are controlled to be in a conducting state by multiple bias circuit units 4021 to provide a lower power amplified signal. Simultaneously, the input and second output terminals of the third switch 408 are controlled to be in a conducting state, making the output impedance of the power amplifier module 401 the fourth output impedance 410 to match the lower power amplified signal. At the same time, the second input and output terminals of the second band switch module 411 are controlled to be in a conducting state, allowing the lower power amplified signal to output a signal of the corresponding band through the second input and output terminals of the second band switch module 411. This not only reduces the number of power transistor units in the power amplifier circuit 40 in low power mode, but also provides a suitable impedance for the power amplifier module 401 in low power mode and allows it to output a signal of the corresponding band through the second band switch module 411, thereby effectively improving the operating efficiency of the power amplifier circuit 40 in low power mode.

[0177] Optionally, since the second band switch module 411 needs to select different bands for the output signals of the third output impedance 409 and the fourth output impedance 410, the second band switch module 411 can be a double-pole multi-throw switch.

[0178] The following section provides a detailed introduction to the schemes for setting the drive amplification module, input impedance, and interstage impedance in a power amplifier circuit.

[0179] Figure 17 This is a circuit diagram of another power amplifier circuit provided in this application embodiment.

[0180] like Figure 17 As shown, compared to the above... Figure 14 The power amplifier circuit 40 is formed by adding a drive amplifier module 412, an input impedance 413, and an interstage impedance 414 to create a drive amplifier circuit 40 with a drive stage PA and a final stage PA. Exemplarily, in one embodiment of this application, a power amplifier circuit 40 is provided. The power amplifier circuit 40 includes a power amplifier module 401, a bias circuit module 402, a first output impedance 403, a first switch 404, a second output impedance 405, a second switch 406, a first band switch module 407, a drive amplifier module 412, an input impedance 413, and an interstage impedance 414. The power amplifier module 401 includes a plurality of power transistor units 4011, the input terminals of which are interconnected, and the output terminals of which are interconnected. The bias circuit module 402 includes a plurality of bias circuit units 4021, each bias circuit unit 4021 being connected to one or more power transistor units 4011. When the power amplifier module 401 is in the first power mode, the first number of power transistor units 4011 are controlled to be in the conducting state by multiple bias circuit units 4021.

[0181] When the power amplifier module 401 is in the second power mode, a second number of power transistor units 4011 are controlled to be in the conducting state by multiple bias circuit units 4021. The first number is greater than the second number. The power of the first power mode is greater than the power of the second power mode. The first terminal of the first output impedance 403 is connected to the output terminal of the power amplifier module 401, the second terminal of the first output impedance 403 is connected to the first terminal of the first switch 404, and the second terminal of the first switch 404 is connected to the first terminal of the second output impedance 405. The first terminal of the second switch 406 is connected to the output terminal of the power amplifier module 401, and the second terminal of the second switch 406 is connected to the second terminal of the second output impedance 405. When the power amplifier module 401 is in the first power mode, the first switch 404 and the second switch 406 are in the off state. When the power amplifier module 401 is in the second power mode, the first switch 404 and the second switch 406 are in the conducting state. The input terminal of the first band switch module 407 is connected to the second terminal of the first output impedance 403, and the output terminal of the first band switch module 407 is used to output signals of multiple power bands. The input terminal of the drive amplifier module 412 is connected to the input impedance 413, the output terminal of the drive amplifier module 412 is connected to the first terminal of the interstage impedance 414, and the second terminal of the interstage impedance 414 is connected to the input terminal of the power amplifier module 401.

[0182] In this embodiment, the drive amplifier module 412 serves as a drive stage for preliminary amplification of the input signal, and its power is generally small. The input impedance 413 is used to match the initial input power signal, and the interstage impedance 414 is used to match the power signal between the drive amplifier module 412 and the power amplifier module 401.

[0183] It should be understood that the drive amplifier module 412 may also include multiple power transistor units. Generally, a bias circuit is used to control the on and off states of the drive amplifier module 412. In some special cases, depending on actual needs, multiple bias circuits may be used to control the on and off states of multiple power transistors within the drive amplifier module 412.

[0184] When the power amplifier module 401 is in a higher power first power mode (e.g., HPM), multiple bias circuit units 4021 control a larger number of power transistor units 4011 to be in a conducting state to provide a higher power amplified signal. Simultaneously, the first switch 404 and the second switch 406 are in a closed state, causing the output impedance of the power amplifier module 401 to be the first output impedance 403, matching the higher power amplified signal. Finally, the first band switching module 407 selects the corresponding band for output of the power signal amplified by the power amplifier module 401.

[0185] When the power amplifier module 401 is in a lower power second power mode (e.g., LPM), a smaller number of power transistor units 4011 are controlled to be in the conducting state by multiple bias circuit units 4021 to provide a lower power amplified signal. Simultaneously, the first switch 404 and the second switch 406 are in the conducting state, making the output impedance of the power amplifier module 401 the parallel impedance of the first output impedance 403 and the second output impedance 405, to match the lower power amplified signal. Finally, the first band switching module 407 selects the corresponding band for the output of the power signal amplified by the power amplifier module 401. This not only reduces the number of power transistor units in the low-power mode of the power amplifier circuit 401, but also provides impedance compensation for the power amplifier module 401 in low-power mode, adjusting the output impedance of the power amplifier module 401 to adapt to the low-power mode, thereby effectively improving the operating efficiency of the power amplifier circuit 401 in low-power mode.

[0186] It should be understood that, in order to form a drive amplifier circuit 40 with a driver stage PA and a final stage PA, as described above... Figures 10-16 The input signal can be initially amplified by the drive amplifier module 412, the input impedance 413, and the interstage impedance 414. The drive amplifier module 412 serves as the drive stage, which amplifies the input signal to obtain a smaller power signal. The power amplifier module 401 further amplifies the input signal to obtain a larger power signal.

[0187] The following section provides a detailed explanation of the effects of setting multiple bias circuit units in a power amplifier circuit, using a load traction diagram.

[0188] Figure 18 This is a load traction diagram of a power amplifier module in LPM according to an embodiment of this application.

[0189] like Figure 18 As shown in this embodiment, the power amplifier module 401 includes six power transistor units 4011, and the bias circuit module 402 includes two bias circuit units 4021. The two bias circuit units 4021 control the six power transistor units 4011 separately in a 1:5 ratio. When the power amplifier module 401 is in a second power mode (e.g., LPM), 1 / 6 of the power transistor units 4011 are operational, allowing for... Figure 18 As seen in the diagram, at an impedance of approximately 9Ω, when the power amplifier module 401 outputs a low power of 5dBm, its operating efficiency is 12-18%. This means that, under different power modes, by adjusting the conduction state of multiple power transistor units 4011 through multiple bias circuit units 4021, the operating efficiency of the power amplifier module 401 can be improved.

[0190] The following section provides a detailed explanation of the effects of setting up multiple bias circuit units and compensating impedance in a power amplifier circuit, using a load traction diagram.

[0191] Figure 19 This is another embodiment of the power amplifier module provided in this application, showing the load traction diagram of the LPM.

[0192] like Figure 19 As shown in the embodiment of this application, the power amplification module 401 includes six power transistor units 4011, and the bias circuit module 402 includes two bias circuit units 4021. The two bias circuit units 4021 control the six power transistor units 4011 separately in a 1:5 ratio. Combined with... Figure 18 It can be seen that when the power amplifier module 401 is in the second power mode (e.g., LPM), the impedance of around 9Ω is not in the optimal efficiency range of the 1 / 6 power transistor unit 4011. Therefore, if the output impedance of the power transistor unit 4011 is adjusted to the optimal impedance range, the operating efficiency of the power transistor unit 4011 can be further improved. Figure 18 Based on this, adjust the input power so that the output power at the optimal impedance point is 5dBm. Figure 19 As can be seen, when the output matching of the power amplifier module 401 is adjusted to above 50Ω, the operating efficiency of the power amplifier module 401 can reach 23%. That is to say, under different power modes, the conduction state of multiple power transistor units 4011 in the power amplifier module 401 is first adjusted by multiple bias circuit units 4021, and then the output matching of the power amplifier module 401 is adjusted to adapt to the second power mode, thereby effectively improving the operating efficiency of the power amplifier module 401.

[0193] The following section provides a detailed explanation of the insertion loss effect of setting multiple switches in a power amplifier circuit, using simulation diagrams of switch insertion loss.

[0194] Figure 20 This is a simulation diagram of the switching insertion loss of a power amplifier module provided in an embodiment of this application.

[0195] like Figure 20As shown, in one embodiment of this application, a power amplifier circuit 40 is provided. When the power amplifier circuit 40 outputs four bands, the switching insertion loss of the power amplifier circuit 40 in the HPM path is shown as line a when there is no compensation impedance in the power amplifier circuit 40; the switching insertion loss of the power amplifier circuit 40 in the HPM path is shown as line b when there is a first switch 404 (e.g., SPST) in the power amplifier circuit 40; the switching insertion loss of the power amplifier circuit 40 in the HPM path is shown as line c when there is a first switch 404 (e.g., SPST) and a second switch 406 (e.g., SPST) in the power amplifier circuit 40; and the switching insertion loss of the power amplifier circuit 40 in the HPM path is shown as line d when there is a third switch 408 (e.g., SPDT) in the power amplifier circuit 40. As can be seen from lines a to d, when the first switch 404 and the second switch 406 are added to the power amplifier circuit 40, the switching insertion loss of the HPM path increases slightly. When the third switch 408 is added to the power amplifier circuit 40, the switching insertion loss of the HPM path increases significantly.

[0196] The following section provides a detailed explanation of the effects of adding multiple bias circuits and compensating impedance in power amplifier circuits, using efficiency curves as an example.

[0197] Figure 21 This is a graph showing the operating efficiency of a power amplifier module provided in an embodiment of this application.

[0198] like Figure 21 As shown, in one embodiment of this application, a power amplifier circuit 40 is provided. Exemplarily, in conjunction with... Figure 14The efficiency curves of the power amplifier circuit 40 in HPM mode are shown by line e; the efficiency curve in LPM mode is shown by line f; the efficiency curve when multiple bias circuit units 4021 separately control multiple power transistor units 4011 in LPM mode is shown by line g; and the efficiency curve when multiple bias circuit units 4021 separately control multiple power transistor units 4011 and impedance compensation is applied to the output of the power amplifier circuit 40 in LPM mode is shown by line h. It can be seen from lines e to h that the efficiency of the power amplifier circuit 40 in HPM mode is indeed greater than that in LPM mode. When the power amplifier circuit 40 uses multiple bias circuit units 4021 to separately control the on / off states of multiple power transistor units 4011, the efficiency of the original power amplifier circuit 40 in LPM mode can be improved. When the power amplifier circuit 40 uses multiple bias circuit units 4021 to separately control multiple power transistor units 4011 and performs impedance compensation on the output terminal of the power amplifier circuit 40, the operating efficiency of the power amplifier circuit 40 at LPM can be further improved, and the operating efficiency at 5dBm can be optimized.

[0199] By way of example, this application also provides a radio frequency (RF) front-end module 1022. The RF front-end module 1022 includes an antenna switch and a power amplifier circuit 40. The antenna switch is electrically connected to the power amplifier circuit 40. The antenna switch is used to select the conducting antenna.

[0200] In this embodiment of the application, different antennas can be selected to be turned on by the antenna switch, so that the amplified signal output by the power amplifier circuit 40 can be transmitted to space from different antennas.

[0201] Alternatively, the antenna switch can also be a band switch.

[0202] By way of example, this application also provides a radio frequency (RF) front-end chip. The RF front-end chip includes an RF transceiver chip and an RF front-end module 1022. The RF transceiver chip is electrically connected to the RF front-end module 1022. The RF transceiver chip is used to control RF transmission and reception signals.

[0203] Specifically, in one embodiment, the RF transceiver chip is used to transmit RF signals, and the RF front-end module 1022 amplifies the RF signals before transmitting them into space. In another embodiment, the RF front-end module 1022 is used to amplify signals received from space and send them to the RF transceiver chip for reception.

[0204] For example, this application also provides an electronic device 10, which includes an antenna subsystem and a radio frequency front-end chip. The antenna subsystem is electrically connected to the radio frequency front-end chip. The antenna subsystem is used to receive signals from space or transmit signals into space.

[0205] Specifically, in one embodiment, the radio frequency front-end chip performs front-end processing on the radio frequency signal to be transmitted, and then transmits it into space through the antenna subsystem for communication with other electronic devices 10. In another embodiment, the antenna subsystem receives signals transmitted by other electronic devices 10 from space and sends them to the radio frequency front-end chip for corresponding processing.

[0206] It should be understood that the above is only an example of the structure of electronic device 10. Electronic device 10 may also include other subsystems or devices, which can be set and modified as needed. This application embodiment does not impose any restrictions on this.

[0207] The beneficial effects that the electronic device provided in the above-described embodiments of this application can achieve can be referred to the beneficial effects corresponding to the modules provided above, and will not be repeated here.

[0208] It should be understood that the above description is merely to help those skilled in the art better understand the embodiments of this application, and is not intended to limit the scope of the embodiments of this application. Based on the examples given above, those skilled in the art can obviously make various equivalent modifications or changes. For example, some steps in the various embodiments of the above detection method may be unnecessary, or new steps may be added. Alternatively, any combination of two or more of the above embodiments may be used. Such modifications, changes, or combinations also fall within the scope of the embodiments of this application. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0209] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0210] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0211] It should also be understood that the above description of the embodiments of this application focuses on highlighting the differences between the various embodiments. Any similarities or differences not mentioned can be referred to each other. For the sake of brevity, they will not be repeated here.

[0212] It should also be understood that, in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0213] It should also be understood that in the embodiments of this application, "pre-setting" or "pre-defining" can be achieved by pre-saving the corresponding code, table or other means that can be used to indicate relevant information in the device (e.g., including electronic devices), and this application does not limit the specific implementation method.

[0214] It should also be understood that the methods, situations, categories, and classifications of embodiments in this application are for the convenience of description only and should not constitute a special limitation. Various methods, categories, situations, and features in embodiments can be combined without contradiction.

[0215] It should also be understood that, in the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0216] Finally, it should be noted that the above descriptions are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims. In conclusion, the above descriptions are merely preferred embodiments of the technical solutions of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A power amplifier circuit, characterized in that, It includes a power amplifier module and a bias circuit module; the power amplifier module includes multiple power transistor units, the input terminals of the multiple power transistor units are interconnected, and the output terminals of the multiple power transistor units are interconnected; the bias circuit module includes multiple bias circuit units, each bias circuit unit is connected to one or more of the power transistor units; When the power amplifier module is in the first power mode, the first number of power transistor units are controlled to be in the conducting state by multiple bias circuit units; When the power amplifier module is in the second power mode, a second number of power transistor units are controlled to be in the on state by a plurality of bias circuit units; the first number is greater than the second number; the power of the first power mode is greater than the power of the second power mode.

2. The power amplifier circuit as described in claim 1, characterized in that, The power amplifier circuit also includes a first output impedance, a first switch, and a second output impedance; The first end of the first output impedance is connected to the output end of the power amplifier module, the second end of the first output impedance is connected to the first end of the first switch, and the second end of the first switch is connected to the first end of the second output impedance. When the power amplifier module is in the first power mode, the first switch is in the off state; When the power amplifier module is in the second power mode, the first switch is in the on state.

3. The power amplifier circuit as described in claim 2, characterized in that, The power amplifier circuit further includes a second switch, the first end of which is connected to the output end of the power amplifier module, and the second end of which is connected to the second end of the second output impedance. When the power amplifier module is in the first power mode, the first switch and the second switch are in the off state; When the power amplifier module is in the second power mode, the first switch and the second switch are in the on state.

4. The power amplifier circuit as described in claim 3, characterized in that, The first switch includes a single-pole single-throw switch, and the second switch includes a single-pole single-throw switch.

5. The power amplifier circuit as described in any one of claims 2-4, characterized in that, The power amplifier circuit further includes a first band switching module; the input terminal of the first band switching module is connected to the second terminal of the first output impedance, and the output terminal of the first band switching module is used to output signals of multiple power bands.

6. The power amplifier circuit as described in claim 5, characterized in that, The first band switching module includes a single-pole multi-throw switch.

7. The power amplifier circuit as described in claim 1, characterized in that, The power amplifier circuit also includes a third switch, a third output impedance, and a fourth output impedance; The input terminal of the third switch is connected to the output terminal of the power amplifier module, the first output terminal of the third switch is connected to the first terminal of the third output impedance, and the second output terminal of the third switch is connected to the first terminal of the fourth output impedance. When the power amplifier module is in the first power mode, the input terminal of the third switch and the first output terminal of the third switch are in a conducting state; When the power amplifier module is in the second power mode, the input terminal of the third switch and the second output terminal of the third switch are in a conducting state.

8. The power amplifier circuit as described in claim 7, characterized in that, The third switch includes a single-pole double-throw switch.

9. The power amplifier circuit as described in claim 7 or 8, characterized in that, The power amplifier circuit further includes a second band switching module; the first input terminal of the second band switching module is connected to the second terminal of the third output impedance, and the second input terminal of the second band switching module is connected to the second terminal of the fourth output impedance; the output terminal of the second band switching module is used to output signals of multiple power bands. When the power amplifier module is in the first power mode, the first input terminal of the second band switch module and the output terminal of the second band switch module are in a conducting state; When the power amplifier module is in the second power mode, the second input terminal of the second band switch module and the output terminal of the second band switch module are in a conducting state.

10. The power amplifier circuit as described in claim 9, characterized in that, The second band switching module includes a double-pole multi-throw switch.

11. The power amplifier circuit according to any one of claims 1-10, characterized in that, The power transistor unit includes MOSFETs and / or triodes.

12. The power amplifier circuit according to any one of claims 1-11, characterized in that, The power amplifier circuit also includes a driver amplifier module, an input impedance, and an interstage impedance; The input terminal of the drive amplifier module is connected to the input impedance, the output terminal of the drive amplifier module is connected to the first terminal of the interstage impedance, and the second terminal of the interstage impedance is connected to the input terminal of the power amplifier module.

13. A radio frequency front-end module, characterized in that, Includes an antenna switch and a power amplifier circuit according to any one of claims 1 to 12; The antenna switch is connected to the power amplifier circuit; the antenna switch is used to select the conducting antenna.

14. A radio frequency front-end chip, characterized in that, Includes an RF transceiver chip and the RF front-end module as described in claim 13; The radio frequency transceiver chip is connected to the radio frequency front-end module; the radio frequency transceiver chip is used to control radio frequency transmission and reception signals.

15. An electronic device, characterized in that, Includes an antenna subsystem and the radio frequency front-end chip as described in claim 14; The antenna subsystem is connected to the radio frequency front-end chip; the antenna subsystem is used to receive signals from space or transmit signals into space.

Images