Power amplification system and power amplifier

Abstract

The application relates to a power amplification system and a power amplifier, wherein a common-source amplification circuit of the system comprises a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; a gate of the first NMOS tube is connected with a main-stage bias voltage, and a drain of the first NMOS tube is connected with a drain of the third NMOS tube and a first input end of a common-gate output circuit; a gate of the second NMOS tube is connected with the main-stage bias voltage, and a drain of the second NMOS tube is connected with a drain of the fourth NMOS tube and a second input end of the common-gate output circuit; a gate of the third NMOS tube is used for connecting with an auxiliary-stage bias voltage; the gate of the third NMOS tube is also used for connecting with a first differential input signal in parallel with the gate of the first NMOS tube; a gate of the fourth NMOS tube is used for connecting with the auxiliary-stage bias voltage; the gate of the fourth NMOS tube is also used for connecting with a second differential input signal in parallel with the gate of the second NMOS tube; and the first power amplification circuit further comprises a PMOS compensation tube configured to offset nonlinear changes of gate capacitance of the common-source amplification circuit. The application can improve linearity.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a power amplification system and a power amplifier. Background Technology

[0002] In wireless communication systems, the radio frequency (RF) front-end is typically used to transmit and receive RF signals. Taking Bluetooth and Wi-Fi wireless communication devices as examples, their transmission links generally include functional modules such as RF transceiver chips, filters, matching networks, power amplifiers, and antennas. The power amplifier is usually located in the later or final stage of the transmission link to amplify the low-power RF signals output from the RF transceiver chip, modulation circuit, or driver stage, bringing them to the power level required for antenna transmission and communication distance. Therefore, power amplifiers are widely used in the RF front-ends of Bluetooth modules, Wi-Fi modules, wireless LAN devices, IoT terminals, and other short- or medium-range wireless communication devices.

[0003] With the rapid development of wireless communication technology, the modulation signals of wireless communication technologies such as Bluetooth and Wi-Fi are becoming increasingly complex. Various communication protocols have placed more stringent requirements on the linearity of power amplifiers in order to reduce signal distortion and out-of-band interference.

[0004] Traditional multi-gate biased power amplifiers employ three or more different common-source bias voltages to widen the cancellation region of the third-order transconductance, thereby achieving better linearity. However, the use of multiple bias voltages in traditional multi-gate biased power amplifiers not only increases the complexity of the control circuitry but also reduces the linearity of the power amplifier at low to medium power levels. Summary of the Invention

[0005] Therefore, it is necessary to provide a power amplification system and power amplifier with high linearity.

[0006] In a first aspect, this application provides a power amplification system, the system including a first power amplification circuit; the first power amplification circuit includes a common-source amplification circuit and a common-gate output circuit; the common-source amplification circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;

[0007] The gates of the first NMOS transistor and the second NMOS transistor are respectively used to connect to the main stage bias voltage;

[0008] The gates of the third and fourth NMOS transistors are respectively used to connect the auxiliary bias voltage;

[0009] The drain of the first NMOS transistor is connected to the drain of the third NMOS transistor and together they are connected to the first input terminal of the common gate output circuit.

[0010] The drain of the second NMOS transistor is connected to the drain of the fourth NMOS transistor and together they are connected to the second input terminal of the common gate output circuit;

[0011] The gates of the first NMOS transistor and the third NMOS transistor are connected in parallel to the first differential input signal, and the gates of the second NMOS transistor and the fourth NMOS transistor are connected in parallel to the second differential input signal.

[0012] The first power amplifier circuit also includes a compensation circuit, which includes PMOS compensation transistors coupled to the gates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor, respectively. The PMOS compensation transistors are configured to cancel the nonlinear variation of the gate capacitance of the common-source amplifier circuit.

[0013] In one embodiment, the compensation circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor; wherein,

[0014] The gate of the seventh PMOS transistor is connected to the gate of the first NMOS transistor, and the source and drain of the seventh PMOS transistor are coupled to the second bias voltage.

[0015] The gate of the eighth PMOS transistor is connected to the gate of the second NMOS transistor, and the source and drain of the eighth PMOS transistor are coupled to the second bias voltage.

[0016] The gate of the ninth PMOS transistor is connected to the gate of the third NMOS transistor, and the source and drain of the ninth PMOS transistor are coupled to the second bias voltage.

[0017] The gate of the tenth PMOS transistor is connected to the gate of the fourth NMOS transistor, and the source and drain of the tenth PMOS transistor are coupled to the second bias voltage.

[0018] In one embodiment, the common-source amplifier circuit further includes a first bias resistor, a second bias resistor, a third bias resistor, and a fourth bias resistor; wherein,

[0019] The gate of the first NMOS transistor is connected to the main bias voltage through the first bias resistor;

[0020] The gate of the second NMOS transistor is connected to the main bias voltage through the second bias resistor;

[0021] The gate of the third NMOS transistor is connected to the auxiliary bias voltage through the third bias resistor.

[0022] The gate of the fourth NMOS transistor is connected to the auxiliary bias voltage through the fourth bias resistor.

[0023] In one embodiment, the common-source amplifier circuit further includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; wherein,

[0024] The gate of the first NMOS transistor is connected to the first differential input signal through the first capacitor;

[0025] The gate of the second NMOS transistor is connected to the second differential input signal through the second capacitor;

[0026] The gate of the third NMOS transistor is connected to the first differential input signal through the third capacitor;

[0027] The gate of the fourth NMOS transistor is connected to the second differential input signal through the fourth capacitor.

[0028] In one embodiment, the common-gate output circuit includes a fifth NMOS transistor, a sixth NMOS transistor, and a fifth capacitor; wherein,

[0029] The source of the fifth NMOS transistor is connected to the drain of the first and third NMOS transistors; the source of the sixth NMOS transistor is connected to the drain of the second and fourth NMOS transistors.

[0030] The gates of the fifth and sixth NMOS transistors are both connected to the first bias voltage and are connected to one end of the fifth capacitor, while the other end of the fifth capacitor is grounded.

[0031] In one embodiment, the system further includes a first tuning transformer circuit; the first tuning transformer circuit includes a first adjustable capacitor array, a first transformer, and a first output capacitor; wherein...

[0032] One end of the first adjustable capacitor array is connected to the drain of the fifth NMOS transistor and one end of the primary coil of the first transformer, respectively; the other end of the first adjustable capacitor array is connected to the drain of the sixth NMOS transistor and the other end of the primary coil of the first transformer, respectively; the primary coil of the first transformer is also used to connect to the power supply voltage.

[0033] One end of the first output capacitor is connected to one end of the secondary coil of the first transformer and ground, and the other end of the first output capacitor is connected to the other end of the secondary coil of the first transformer.

[0034] In one embodiment, the first adjustable capacitor array includes a plurality of parallel tuning sub-circuits; the tuning sub-circuit includes a first tuning capacitor, a second tuning capacitor, a first tuning NMOS transistor, and a second tuning NMOS transistor; wherein...

[0035] The source of the first tuned NMOS transistor is connected to ground in parallel with the source of the second tuned NMOS transistor;

[0036] The gate of the first tuned NMOS transistor and the gate of the second tuned NMOS transistor are connected in parallel to the tuning control signal.

[0037] The drain of the first tuned NMOS transistor is connected to the drain of the fifth NMOS transistor and one end of the primary coil of the first transformer through the first tuned capacitor.

[0038] The drain of the second tuned NMOS transistor is connected to the drain of the sixth NMOS transistor and the other end of the primary coil of the first transformer via the second tuned capacitor.

[0039] In one embodiment, the system further includes a second power amplifier circuit and a second tuning transformer circuit;

[0040] The voltage gain of the second power amplifier circuit is adjustable, and it is used to output the first differential input signal and the second differential input signal to the first power amplifier circuit through the second tuning transformer circuit.

[0041] In one embodiment, the second power amplifier circuit includes multiple common-source cascode sub-circuits; each common-source cascode sub-circuit includes a first driving capacitor, a second driving capacitor, a first driving NMOS transistor, a second driving NMOS transistor, a third driving NMOS transistor, and a fourth driving NMOS transistor; wherein,

[0042] The gate of the first driving NMOS transistor is used to connect to the first driving bias voltage and to connect to the third differential input signal through the first driving capacitor; the drain of the first driving NMOS transistor is connected to the source of the third driving NMOS transistor; the source of the first driving NMOS transistor and the source of the second driving NMOS transistor are connected to ground in parallel.

[0043] The gate of the second driving NMOS transistor is used to connect to the first driving bias voltage and to connect to the fourth differential input signal through the second driving capacitor; the drain of the second driving NMOS transistor is connected to the source of the fourth driving NMOS transistor.

[0044] The gates of both the third and fourth driving NMOS transistors are used to connect to the second driving bias voltage.

[0045] The drains of the third driving NMOS transistors of each common-source common-gate sub-circuit are connected in parallel to the first input terminal of the second tuning transformer circuit; the drains of the fourth driving NMOS transistors of each common-source common-gate sub-circuit are connected in parallel to the second input terminal of the second tuning transformer circuit.

[0046] In one embodiment, the second tuning transformer circuit includes a second adjustable capacitor array and a second transformer; wherein...

[0047] One end of the second adjustable capacitor array is connected to the drain of each third driving NMOS transistor and one end of the primary coil of the second transformer, respectively. The other end of the second adjustable capacitor array is connected to the drain of each fourth driving NMOS transistor and the other end of the primary coil of the second transformer, respectively. The primary coil of the second transformer is also used to connect to the power supply voltage.

[0048] The two ends of the secondary coil of the second transformer are used to output the first differential input signal and the second differential input signal to the first power amplifier circuit, respectively.

[0049] In one embodiment, the second power amplifier circuit includes five common-source cascode sub-circuits, and the MOS transistor size ratio among the various common-source cascode sub-circuits is set to 1:1:2:4:8.

[0050] In one embodiment, the system further includes a filter module connected to the second power amplifier circuit;

[0051] The filter module is used to filter the fifth and sixth differential input signals and then output the third and fourth differential input signals to the second power amplifier circuit; the filtering process includes filtering out the mixing spurious signals at the third harmonic.

[0052] In a second aspect, this application provides a power amplifier, including the power amplification system as described in any of the first aspects.

[0053] The aforementioned power amplification system and power amplifier, wherein the first power amplification circuit of the power amplification system includes a common-source amplifier circuit and a common-gate output circuit, and the common-source amplifier circuit and the common-gate output circuit can construct a third-order transconductance near-zero region using only two stages of multi-gate bias, thereby significantly improving the linearity performance of the power amplifier under high power conditions compared to traditional multi-gate bias power amplifiers. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a schematic diagram of the power amplifier system in one embodiment;

[0056] Figure 2 This is a schematic diagram of the circuit structure of the first power amplifier circuit in one embodiment;

[0057] Figure 3 This is a schematic diagram of the circuit structure of the first adjustable capacitor array in one embodiment;

[0058] Figure 4 This is a schematic diagram of the power amplifier system in another embodiment;

[0059] Figure 5This is a schematic diagram of the circuit structure of the second power amplifier circuit in one embodiment;

[0060] Figure 6 This is a schematic diagram of the third-order intermodulation distortion curve of a power amplifier in one embodiment;

[0061] Figure 7 This is a schematic diagram showing the power-added efficiency curve of a power amplifier in one embodiment. Detailed Implementation

[0062] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0064] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0065] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0066] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0067] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0068] In one exemplary embodiment, such as Figure 1 and Figure 2 As shown, this application provides a power amplification system 100, which includes a first power amplification circuit 200; the first power amplification circuit 200 includes a common-source amplifier circuit 202 and a common-gate output circuit 204; the common-source amplifier circuit 202 includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3 and a fourth NMOS transistor M4;

[0069] The gates of the first NMOS transistor M1 and the second NMOS transistor M2 are respectively used to connect to the main stage bias voltage. ;

[0070] The gates of the third NMOS transistor M3 and the fourth NMOS transistor M4 are respectively used to connect the auxiliary bias voltage. ;

[0071] The drain of the first NMOS transistor M1 is connected to the drain of the third NMOS transistor M3 and together they are connected to the first input terminal of the common gate output circuit 204.

[0072] The drain of the second NMOS transistor M2 is connected to the drain of the fourth NMOS transistor M4 and together they are connected to the second input terminal of the common gate output circuit 204;

[0073] The gates of the first NMOS transistor M1 and the third NMOS transistor M3 are connected in parallel to the first differential input signal, and the gates of the second NMOS transistor M2 and the fourth NMOS transistor M4 are connected in parallel to the second differential input signal.

[0074] The first power amplifier circuit 200 further includes a compensation circuit 206, which includes PMOS compensation transistors coupled to the gates of the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4, respectively. The PMOS compensation transistors are configured to cancel the nonlinear changes in the gate capacitance of the common-source amplifier circuit 202.

[0075] Among them, the main stage bias voltage and auxiliary bias voltage Both can be DC bias voltages, and the main stage bias voltage can be increased. With auxiliary bias voltage The bias voltage difference between them can be used to construct a third-order transconductance near-zero region.

[0076] For example, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 can all be thin-gate NMOS transistors to form the common-source stage of the first power amplifier circuit 200 to realize signal amplification.

[0077] In some examples, the common-gate output circuit 204 can be used as the common-gate stage of the first power amplifier circuit 200 for input-output isolation while providing good linearity and gain.

[0078] Understandably, traditional multi-gate biased power amplifiers typically employ three or more different common-source bias voltages to widen the cancellation region of the third-order transconductance, thereby reducing third-order intermodulation and achieving better linearity. However, this method of setting multiple bias voltages in traditional multi-gate biased power amplifiers not only makes the control circuit more complex, but in practical applications, it can also reduce the linearity of the power amplifier in low-to-medium power scenarios.

[0079] Specifically, the first power amplifier circuit 200 of the power amplifier system 100 in this application embodiment adopts a pseudo-differential cascode structure, thereby using the differential structure to suppress even-order harmonics and reduce substrate losses. In practical applications, by increasing the bias voltage difference between the main stage bias voltage and the auxiliary stage bias voltage (for example, the main stage biased in class AB and the auxiliary stage biased in class C), it is possible to construct a third-order transconductance near-zero region using only two stages of multi-gate bias. This improves the linearity performance of the power amplifier system 100 under high power conditions and also facilitates further overcoming performance degradation under medium and low power conditions through PMOS capacitor compensation.

[0080] In one embodiment, the compensation circuit includes a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth PMOS transistor M9, and a tenth PMOS transistor M10; wherein,

[0081] The gate of the seventh PMOS transistor M7 is connected to the gate of the first NMOS transistor, and the source and drain of the seventh PMOS transistor M7 are coupled to the second bias voltage. ;

[0082] The gate of the eighth PMOS transistor M8 is connected to the gate of the second NMOS transistor, and the source and drain of the eighth PMOS transistor M8 are coupled to the second bias voltage. ;

[0083] The gate of the ninth PMOS transistor M9 is connected to the gate of the third NMOS transistor, and the source and drain of the ninth PMOS transistor M9 are coupled to the second bias voltage. ;

[0084] The gate of the tenth PMOS transistor M10 is connected to the gate of the fourth NMOS transistor, and the source and drain of the tenth PMOS transistor M10 are coupled to the second bias voltage. .

[0085] For example, the seventh PMOS transistor M7, the eighth PMOS transistor M8, the ninth PMOS transistor M9, and the tenth PMOS transistor M10 can all be thin-gate PMOS transistors, and are connected to the gate of the common source transistor in the common source amplifier circuit 202 in a diode configuration. This allows for the adjustment of the transistor size and drain-source voltage to offset the changes in the gate capacitance Cgg of the NMOS common source transistor, thereby providing a stable gate capacitance over a wider input voltage range and effectively reducing AM-PM distortion.

[0086] It should be noted that traditional multi-gate biased power amplifiers employ three or more bias stages, which are difficult to control and sacrifice some performance at low to medium output power. Furthermore, traditional PMOS capacitor compensation technology, when used alone under large signal conditions, exhibits reduced effectiveness. However, this application combines these two technologies, resulting in a mutually optimized technical effect. The following sections will explain the basic working principles of these two technologies and their synergistic optimization effect:

[0087] It is known that the current of a MOSFET is mainly determined by its transconductance and gate-source voltage. Therefore, as shown in Equation 1 below, the current can be expressed using Taylor expansion as follows:

[0088] (Formula 1)

[0089] in, This represents the change in current of the MOSFET. The i-th order transconductance of the MOSFET. This represents the change in gate-source voltage of the MOSFET.

[0090] In the two-tone test, when the input signal is At that time, the third-order intermodulation component can be expressed as the following formula 2:

[0091] (Formula 2)

[0092] IM3 is a third-order intermodulation component. Here, A represents the third transconductance of the MOSFET, and A is the amplitude of the test signal. The angular frequency of the first test signal in the two-tone test. The angular frequency of the second test signal in the dual-tone test.

[0093] It is understandable that by making the above third-order transconductance Superimposing these biases to approximate zero can suppress third-order nonlinearity to a large extent. However, power amplifiers often operate under large-signal conditions, and traditional multi-gate biasing requires multiple biases to construct a sufficiently large bias. Near-zero regions lead to high transistor consumption and difficulty in control adjustment, rendering them impractical in real-world applications. Furthermore, The curve typically increases to a maximum positive value as the gate input voltage increases, and then decreases to a minimum negative value. Therefore, in the multi-stage cancellation process, at lower input voltages... There will be regions where the positive values ​​overlap, meaning that linearity will deteriorate at low to medium output power.

[0094] For example, the embodiments of this application employ a two-stage multi-gate bias, which can bias the main stage of the common-source amplifier circuit 202 in class AB and the auxiliary stage in class C. By increasing the bias voltage difference, a structure can be constructed. The near-zero region ensures its cancellation effect under large signal conditions and reduces the degradation of the low-to-medium output power region. Furthermore, in this embodiment, based on a two-stage multi-gate bias, PMOS capacitor compensation is achieved through a compensation circuit, thereby increasing the overall gate capacitance of the first power amplifier circuit 200 while providing a stable gate capacitance. It can be understood that for AC signals, the capacitance impedance can be expressed as follows: Formula 3:

[0095] (Formula 3)

[0096] Therefore, for high-frequency components, the smaller the capacitor impedance, the more signal leakage there will be. This, to some extent, reduces the higher-order components of the input signal, allowing the PMOS capacitor compensation technology corresponding to the compensation circuit to not only compensate for phase distortion but also indirectly offset some of the IM3 degradation caused by the multi-gate bias technology corresponding to the common-source amplifier circuit 202 at low to medium output power. That is, in this embodiment, the multi-gate bias technology and the MOS capacitor compensation technology achieve complementary technical effects. In practical applications, by biasing the common-source transistor of the first power amplifier circuit 200 into deep AB and C classes respectively, the power amplifier structure can achieve both high linearity and good efficiency.

[0097] In one embodiment, such as Figure 2 As shown, the common-source amplifier circuit 202 also includes a first bias resistor R1, a second bias resistor R2, a third bias resistor R3, and a fourth bias resistor R4; wherein,

[0098] The gate of the first NMOS transistor M1 is connected to the main bias voltage through the first bias resistor R1. ;

[0099] The gate of the second NMOS transistor M2 is connected to the main bias voltage through the second bias resistor R2. ;

[0100] The gate of the third NMOS transistor M3 is connected to the auxiliary bias voltage through the third bias resistor R3. ;

[0101] The gate of the fourth NMOS transistor M4 is connected to the auxiliary bias voltage through the fourth bias resistor R4. .

[0102] Specifically, DC main stage bias voltage and DC auxiliary bias voltage The common-source transistor gate of the common-source amplifier circuit 202 can be supplied through a resistor, thereby increasing the main stage bias voltage. With auxiliary bias voltage The difference in bias voltage between the two stages allows for the construction of a third-order transconductance near-zero region using only two-stage multi-gate bias, thereby effectively improving the linearity of the power amplifier system 100 under high power conditions.

[0103] In one embodiment, such as Figure 2 As shown, the common-source amplifier circuit 202 also includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; wherein,

[0104] The gate of the first NMOS transistor M1 is connected to the first differential input signal through the first capacitor C1;

[0105] The gate of the second NMOS transistor M2 is connected to the second differential input signal through the second capacitor C2;

[0106] The gate of the third NMOS transistor M3 is connected to the first differential input signal through the third capacitor C3;

[0107] The gate of the fourth NMOS transistor M4 is connected to the second differential input signal through the fourth capacitor C4.

[0108] Specifically, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can block DC from the input signal. After the first differential input signal and the second differential input signal are blocked by the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, they enter the common source amplifier circuit 202 of the first power amplifier circuit 200.

[0109] In one embodiment, the common-gate output circuit includes a fifth NMOS transistor M5, a sixth NMOS transistor M6, and a fifth capacitor C5; wherein,

[0110] The source of the fifth NMOS transistor M5 is connected to the drain of the first NMOS transistor M1 and the third NMOS transistor M3; the source of the sixth NMOS transistor M6 is connected to the drain of the second NMOS transistor M2 and the fourth NMOS transistor M4.

[0111] The gates of both the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are used to connect to the first bias voltage. They are interconnected, with one end of the fifth capacitor C5 connected and the other end of the fifth capacitor C5 grounded.

[0112] For example, both the fifth NMOS transistor M5 and the sixth NMOS transistor M6 can be thick-gate NMOS transistors. In practical applications, the fifth capacitor C5 can be used as a bootstrap capacitor at the gate of the common-gate transistor to improve circuit stability and AC signal gain.

[0113] Specifically, the common-gate output circuit 204, as the common-gate stage of the first power amplifier circuit 200, receives the amplified signal output from the common-source amplifier circuit 202 to perform input-output isolation and increase the output impedance, thereby providing good linearity and AC signal gain.

[0114] In one embodiment, such as Figure 1 and Figure 2 As shown, the system also includes a first tuning transformer circuit 300; the first tuning transformer circuit 300 includes a first adjustable capacitor array. First transformer TR1 and first output capacitor ;in,

[0115] One end of the first adjustable capacitor array is connected to the drain of the fifth NMOS transistor M5 and one end of the primary coil of the first transformer TR1, respectively. The other end is connected to the drain of the sixth NMOS transistor M6 and the other end of the primary coil of the first transformer TR1, respectively; the primary coil of the first transformer TR1 is also used to connect to the power supply voltage. ;

[0116] First output capacitor One end is connected to one end of the secondary coil of the first transformer TR1 and ground, respectively, and the first output capacitor The other end is connected to the other end of the secondary coil of the first transformer TR1.

[0117] Specifically, the output signal of the common-gate output circuit 204 is transmitted through the first transformer TR1 and the first output capacitor. The differential single balun and tuning capacitor array are matched to achieve good tuning performance and reduce the impact of Q value on the linearity of the power amplifier.

[0118] In one embodiment, such as Figure 3 As shown, the first adjustable capacitor array includes multiple parallel tuning sub-circuits 302; each tuning sub-circuit 302 includes a first tuning capacitor. Second tuning capacitor First tuned NMOS transistor and the second tuned NMOS transistor ;in,

[0119] First tuning NMOS transistor The source and the second tuned NMOS transistor The source pole is connected to the ground in parallel;

[0120] First tuning NMOS transistor The gate of the second tuned NMOS transistor The gate is connected in parallel to the tuning control signal. (For example Figure 3 In to );

[0121] First tuning NMOS transistor The drain is connected to the first tuning capacitor. Connect the drain of the fifth NMOS transistor M5 to one end of the primary coil of the first transformer TR1, respectively;

[0122] Second tuning NMOS transistor The drain is connected to the second tuning capacitor. Connect the drain of the sixth NMOS transistor M6 to the other end of the primary coil of the first transformer TR1, respectively.

[0123] Based on the preceding analysis, the first power amplifier circuit 200 contains two matching networks: inter-stage matching and output matching. Traditional matching methods use a transformer with parallel capacitors to achieve fixed-frequency matching. However, to address potential manufacturing deviations and adapt to a wider range of practical applications, the circuit needs to further possess a certain range of tuning capabilities. Therefore, this embodiment proposes to employ... Figure 3 The diagram shows a capacitor array connected in parallel to ground to achieve tuning operation.

[0124] It should be noted that traditional capacitor arrays, compared to using fixed-value capacitors, introduce some NMOS transistors, leading to an increase in the real part of the impedance, a decrease in the Q value, and a deterioration in linearity. However, the parallel ground connection method used in this application provides a high-frequency path to ground, thereby suppressing common-mode noise without affecting the differential-mode component, which to some extent offsets the performance degradation caused by the capacitor array. On the other hand, in practical applications, the number of capacitors in the array should be minimized to keep the Q value degradation within a reasonable range and reduce insertion loss. It can be understood that the use of capacitor arrays in this application not only provides good tuning performance but also further improves the linearity of the power amplifier through the ground path.

[0125] In one embodiment, such as Figure 4 As shown, the system also includes a second power amplifier circuit 400 and a second tuning transformer circuit 500;

[0126] The voltage gain of the second power amplifier circuit 400 is adjustable, and it is used to output the first differential input signal and the second differential input signal to the first power amplifier circuit 200 through the second tuning transformer circuit 500.

[0127] It is understandable that the first power amplifier circuit 200 (also known as the output stage power amplifier circuit) plays a decisive role in the power amplifier system 100. In practical applications, other modules in the power amplifier system 100 can still be used to help achieve optimal performance.

[0128] Specifically, the second power amplifier circuit 400 (also known as the driver stage power amplifier circuit) can be used to provide good linearity and a sufficiently large gain to drive the first power amplifier circuit 200, and the driver stage power amplifier circuit and the output stage power amplifier circuit achieve interstage matching through the second tuning transformer circuit 500.

[0129] In one embodiment, such as Figure 5 As shown, the second power amplifier circuit 400 includes multiple common-source cascode sub-circuits 402; each common-source cascode sub-circuit 402 includes a first driving capacitor C11, a second driving capacitor C12, a first driving NMOS transistor M11, a second driving NMOS transistor M12, a third driving NMOS transistor M13, and a fourth driving NMOS transistor M14; wherein,

[0130] The gate of the first driving NMOS transistor M11 is used to connect to the first driving bias voltage. The third differential input signal is connected through the first driving capacitor C11; the drain of the first driving NMOS transistor M11 is connected to the source of the third driving NMOS transistor M13; the source of the first driving NMOS transistor M11 and the source of the second driving NMOS transistor M12 are connected to ground in parallel.

[0131] The gate of the second driving NMOS transistor M12 is used to connect to the first driving bias voltage. The fourth differential input signal is connected through the second driving capacitor C12; the drain of the second driving NMOS transistor M12 is connected to the source of the fourth driving NMOS transistor M14.

[0132] The gates of both the third driving NMOS transistor M13 and the fourth driving NMOS transistor M14 are used to connect to the second driving bias voltage. ;

[0133] The drains of the third driving NMOS transistors M13 of each common-source common-gate circuit 402 are connected in parallel to the first input terminal of the second tuning transformer circuit 500; the drains of the fourth driving NMOS transistors M14 of each common-source common-gate circuit 402 are connected in parallel to the second input terminal of the second tuning transformer circuit 500.

[0134] For example, the driver stage power amplifier circuit structure can be as follows: Figure 5 As shown, it also employs a common source, common gate structure to provide good linearity and sufficiently large gain to drive the output stage power amplifier circuit.

[0135] Specifically, the gain variation range of the second power amplifier circuit 400 is adjusted by setting the number of common source cascode sub-circuits 402 and the size of the NMOS transistors in the common source cascode sub-circuits 402.

[0136] In one embodiment, such as Figure 4 As shown, the second tuning transformer circuit 500 includes a second adjustable capacitor array. The second transformer TR2; where,

[0137] Second adjustable capacitor array One end is connected to the drain of each of the third driving NMOS transistors M13 and one end of the primary coil of the second transformer TR2, respectively, and the second adjustable capacitor array The other end is connected to the drain of each of the fourth driving NMOS transistors M14 and the other end of the primary coil of the second transformer TR2; the primary coil of the second transformer TR2 is also used to connect the power supply voltage. ;

[0138] The two ends of the secondary coil of the second transformer TR2 are used to output the first differential input signal and the second differential input signal to the first power amplifier circuit 200, respectively.

[0139] For example, the second adjustable capacitor array can also be adopted as follows: Figure 3 The adjustable capacitor array structure shown can also include multiple parallel tuning sub-circuits 302 to provide good tuning performance. For example, one end of each tuning sub-circuit of the second adjustable capacitor array can be connected between the drain of each third driving NMOS transistor M13 and one end of the primary coil of the second transformer TR2, and the other end of each tuning sub-circuit of the second adjustable capacitor array can be connected between the drain of each fourth driving NMOS transistor M14 and the other end of the primary coil of the second transformer TR2.

[0140] In one embodiment, such as Figure 5 As shown, the second power amplifier circuit 400 includes five common-source common-gate sub-circuits 402, and the MOS transistor size ratio among the various common-source common-gate sub-circuits 402 is set to 1:1:2:4:8.

[0141] Specifically, the MOSFET size ratio among the five common-source common-gate sub-circuits 402 of the second power amplifier circuit 400 is set to 1:1:2:4:8 (that is, L in the width-to-length ratio W / L of the MOSFET remains unchanged, while W increases in a ratio of 1:1:2:4:8), thereby enabling the second power amplifier circuit 400 to achieve a gain step of 6dB. Furthermore, the gain variation of the second power amplifier circuit 400 in the range of 6-30dB can be achieved through switching control.

[0142] In one embodiment, such as Figure 4 As shown, the system also includes a filter module 600 connected to the second power amplifier circuit 400;

[0143] The filter module 600 is used to filter the fifth and sixth differential input signals and then output the third and fourth differential input signals to the second power amplifier circuit 400; the filtering process includes filtering out the mixing spurious signals at the third harmonic.

[0144] It should be noted that in the TX link, a passive mixer is often connected to the input of the power amplifier system 100 to ensure linearity. Passive mixers offer advantages such as high bandwidth, high dynamic range, and high port isolation, effectively reducing the nonlinear distortion easily introduced by active devices. However, passive mixers have limitations in local oscillator signal... and intermediate frequency signal Spurious signals are inevitably generated during the mixing process. - Referring to Formula 2 above, it is related to the desired signal. This will generate a frequency of The third-order intermodulation component falls into the in-band, thus degrading the linearity of the power amplifier system 100.

[0145] Specifically, in this embodiment, the filter module 600 can first filter out 3 The nonlinear components at the third harmonic (i.e., mixing spurious signals at the third harmonic) are preprocessed on the input signal of the power amplifier system 100, thereby further improving the linearity of the power amplifier system 100 at the system level, and in 3 The passive components used for passive filtering at high frequencies have relatively small inductors and capacitors, which will not cause excessive area loss in practical applications.

[0146] In one exemplary embodiment, this application provides a power amplifier including the power amplification system 100 described in any of the above embodiments.

[0147] It is understood that the solutions provided in this application are similar to the solutions from the perspective of the power amplifier system 100 described above. Therefore, the specific limitations of this application can be found in the limitations of the power amplifier system 100 embodiments described above, and will not be repeated here.

[0148] To further explain the technical solution of this invention, the application of this solution will be described in detail below through an exemplary signal amplification process in a practical application. Please refer to... Figures 1 to 5 An exemplary signal amplification process based on the power amplification system 100 described in this application is as follows:

[0149] First, the differential mixing signal RFIN output from the passive mixer is input to the filter module 600 of the power amplifier system 100 to filter out mixing spurious signals at the third harmonic. Then, the filtered differential signal is input to the second power amplifier circuit 400 (i.e., the driver stage power amplifier circuit) of the power amplifier system 100.

[0150] The driver-stage power amplifier circuit can control the voltage gain of the second power amplifier circuit 400 according to the actual application requirements by controlling the switch. Then, the amplified differential signal is input to the first power amplifier circuit 200 (i.e., the output stage power amplifier circuit) through the adjustable capacitor array of the second tuning transformer circuit 500 and the matching network composed of the second transformer TR2.

[0151] The differential signal input to the first power amplifier circuit 200 first enters the common-source stages M1, M2, M3, and M4 through DC blocking capacitors C1, C2, C3, and C4. The common-source stages are connected to the bias circuit through a large resistor to obtain a multi-gate bias voltage (i.e., and In the first power amplifier circuit 200, the main differential pair transistors M1 and M2 are biased in deep AB class, while the auxiliary differential pair transistors M3 and M4 are biased in class C. In practical applications, the auxiliary common-source stage can be controlled by the bias circuit according to the actual application requirements, so as to enable the auxiliary stage in large-signal application scenarios, thereby achieving higher efficiency and linearity.

[0152] In the first power amplifier circuit 200, diode-connected PMOS transistors M7, M8, M9, and M10 are added to the gate of the common-source transistor for capacitance compensation. These transistors not only compensate for the gate capacitance variation of the common-source NMOS transistor with the input signal, reducing AM-PM distortion, but also indirectly increase the differential-mode signal's capacitance to ground, filtering out some higher-order harmonics. Furthermore, the direct parallel connection of the common-source stages in the first power amplifier circuit 200 facilitates third-order transconductance. This offsets the difference, resulting in a relatively wide width. The near-zero region reduces the influence of the third-order intermodulation component, thus improving linearity. Furthermore, the third-order transconductance... After cancellation, the signal is passed through common-gate transistors M5 and M6, resulting in greater signal gain and better output isolation. Furthermore, M5 and M6, using thick-gate transistors, can withstand higher supply voltages. The first power amplifier circuit 200, however, has a fixed-bias gate in its common-gate configuration. By connecting the bootstrap capacitor C5, the voltage and gain can be further stabilized, thereby forming a ground capacitance path, filtering out high-order harmonics, and thus reducing the impact of non-ideal bias.

[0153] Finally, the output signal of the first power amplifier circuit 200 passes through the adjustable capacitor array. The output matching network, consisting of a sum-to-difference single-output balun, outputs to the antenna port.

[0154] Through the above-described exemplary signal amplification process, the embodiments of this application can effectively suppress the linearity degradation caused by the third-order intermodulation component under large signal conditions without sacrificing performance at low and medium output power, while reducing AM-PM and AM-AM distortion. In addition, the present application can also provide good tuning performance for the power amplification system through the structural optimization of the adjustable capacitor array.

[0155] It is understood that, compared to traditional power amplifiers, the power amplification system and power amplifier described in the various embodiments of this application above have at least the following beneficial technical effects:

[0156] ① High linearity: such as Figure 6 As shown, Figure 6 To improve the linearity of power amplifiers in practical applications, compared to traditional linear power amplifiers, the third-order intermodulation distortion (IMD3) of the power amplifier system in this application is significantly improved under high-power output conditions. For example, it can be optimized by about 5.8 dB under 20 dBm output conditions, while the power amplifier system in this application also has good IMD3 performance under medium and low output power conditions.

[0157] ② High efficiency: such as Figure 7 As shown, since the first power amplifier circuit of the power amplifier system of this application can adopt a combination of deep AB class and C class two-gate bias, compared with the traditional linear power amplifier, the power added efficiency (PAE) of the power amplifier system of this application can achieve an optimization effect of more than 3% under the power back-off conditions of 6dB and 9dB.

[0158] ③ Excellent tuning performance: The power amplifier system of this application, by adopting an adjustable capacitor array, can achieve tuning function while ensuring performance such as linearity and efficiency, so as to provide excellent tuning performance in various application scenarios.

[0159] Furthermore, to facilitate the application of the power amplification system and power amplifier described in this application in practical scenarios, this application embodiment provides an exemplary power amplifier design flow. Please refer to... Figures 1 to 5 The structure shown illustrates the exemplary power amplifier design process as follows:

[0160] First, the current consumption can be initially determined based on specifications such as the saturated output power requirement, thereby determining the dimensions of the MOSFETs corresponding to the common-source transistors M1, M2, M3, and M4 in the first power amplifier circuit. Next, the dimensions of the common-gate transistors M5 and M6 in the first power amplifier circuit are roughly determined based on the aforementioned common-source transistor dimensions. Then, based on the common-source transistors... Determine the appropriate bias voltage difference between the main power amplifier and the auxiliary power amplifier in the first power amplifier circuit as the bias voltage changes (i.e., and (Bias voltage difference). Furthermore, a suitable output impedance is determined by load pull and the saturated output power is checked to see if it meets the requirements. The size of each power transistor is adjusted based on the simulation results. The bias voltage can be scanned to meet the output power requirements of specific application scenarios under the lowest possible bias voltage conditions, thereby minimizing system power consumption and improving efficiency.

[0161] After determining the main structure of the output stage power amplifier circuit, PMOS capacitor compensation transistors are added. In practical applications, the appropriate drain-source voltage and size of the PMOS in the compensation circuit can be determined by simulating the sum of the gate capacitances of the NMOS and PMOS transistors as a function of the input voltage, thereby achieving a stable gate capacitance and reducing AM_PM distortion. Next, the output matching network is designed based on the output impedance determined by load pull. By connecting an adjustable capacitor array and a differential single balun in parallel, the values ​​of the capacitors and inductors are calculated and simulated for adjustment. Based on the capacitor values, the adjustment range of the adjustable capacitor array is further determined. It is important to note that the array structure should be simplified as much as possible during the design to ensure the Q value and thus reduce the impact on the performance of the power amplifier system.

[0162] After finalizing the output stage power amplifier circuit design, the dimensions of the driver stage amplifier can be refined based on the gain requirements, and a parallel structure can be designed to achieve adjustable gain. It's also important to note that the driver stage power amplifier circuit needs to saturate only after the output stage power amplifier circuit has saturated; therefore, the 1dB input gain compression point of both circuits must be carefully considered during the design. Specifically, the driver stage power amplifier circuit should have a higher 1dB input gain compression point, and a 2-3dB margin should be retained in the design. The matching process between the output stage power amplifier circuit and the driver stage power amplifier circuit is similar to output matching and will not be elaborated further. Adding an adjustable capacitor array can further widen the tuning range.

[0163] Regarding the design of passive components, the passive inductors in this application mainly include filters, interstage matching networks, and output matching networks. The capacitor array design employs the aforementioned adjustable structure to provide tuning range and ground coupling path. The matching inductors can utilize symmetrical octagonal structures and horizontal structures, which offer better magnetic coupling coefficients compared to stacked structures. The primary and secondary coils of the horizontal structure can be constructed by stacking the highest and second-highest layer of metal, with a bottom layer of metal underneath to improve the quality factor of the corresponding frequency band, reduce insertion loss, and save area. For the filter module design, the inductor value can be minimized. Specifically, a notch filter structure can be used to achieve filtering at specific power levels, reducing intermodulation distortion in the power amplifier and its system, minimizing area consumption, and reducing the impact on signal gain. In summary, during the overall design of passive components, it is necessary to ensure a high Q value to avoid power loss and performance degradation caused by an excessively low Q value.

[0164] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0165] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0166] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A power amplification system, characterized in that, The system includes a first power amplifier circuit; the first power amplifier circuit includes a common-source amplifier circuit and a common-gate output circuit; the common-source amplifier circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The gates of the first NMOS transistor and the second NMOS transistor are respectively used to connect to the main stage bias voltage; The gates of the third and fourth NMOS transistors are respectively used to connect to the auxiliary bias voltage; The drain of the first NMOS transistor is connected to the drain of the third NMOS transistor and together they are connected to the first input terminal of the common gate output circuit; The drain of the second NMOS transistor is connected to the drain of the fourth NMOS transistor and together they are connected to the second input terminal of the common gate output circuit; The gates of the first NMOS transistor and the third NMOS transistor are connected in parallel to the first differential input signal, and the gates of the second NMOS transistor and the fourth NMOS transistor are connected in parallel to the second differential input signal. The first power amplifier circuit further includes a compensation circuit, which includes a PMOS compensation transistor coupled to the gates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor, respectively. The PMOS compensation transistor is configured to cancel the nonlinear variation of the gate capacitance of the common-source amplifier circuit.

2. The system according to claim 1, characterized in that, The PMOS compensation transistors include a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor; wherein, The gate of the seventh PMOS transistor is connected to the gate of the first NMOS transistor, and the source and drain of the seventh PMOS transistor are coupled to the second bias voltage. The gate of the eighth PMOS transistor is connected to the gate of the second NMOS transistor, and the source and drain of the eighth PMOS transistor are coupled to the second bias voltage. The gate of the ninth PMOS transistor is connected to the gate of the third NMOS transistor, and the source and drain of the ninth PMOS transistor are coupled to the second bias voltage. The gate of the tenth PMOS transistor is connected to the gate of the fourth NMOS transistor, and the source and drain of the tenth PMOS transistor are coupled to the second bias voltage.

3. The system according to claim 1, characterized in that, The common-source amplifier circuit further includes a first bias resistor, a second bias resistor, a third bias resistor, and a fourth bias resistor; wherein, The gate of the first NMOS transistor is connected to the main stage bias voltage through the first bias resistor; The gate of the second NMOS transistor is connected to the main stage bias voltage through the second bias resistor; The gate of the third NMOS transistor is connected to the auxiliary bias voltage through the third bias resistor. The gate of the fourth NMOS transistor is connected to the auxiliary bias voltage through the fourth bias resistor.

4. The system according to claim 1, characterized in that, The common-source amplifier circuit further includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; wherein, The gate of the first NMOS transistor is connected to the first differential input signal through the first capacitor; The gate of the second NMOS transistor is connected to the second differential input signal through the second capacitor; The gate of the third NMOS transistor is connected to the first differential input signal through the third capacitor; The gate of the fourth NMOS transistor is connected to the second differential input signal through the fourth capacitor.

5. The system according to claim 1, characterized in that, The common-gate output circuit includes a fifth NMOS transistor, a sixth NMOS transistor, and a fifth capacitor; wherein... The source of the fifth NMOS transistor is connected to the drain of the first NMOS transistor and the third NMOS transistor; the source of the sixth NMOS transistor is connected to the drain of the second NMOS transistor and the fourth NMOS transistor. The gates of the fifth NMOS transistor and the sixth NMOS transistor are both connected to the first bias voltage and are connected to one end of the fifth capacitor, while the other end of the fifth capacitor is grounded.

6. The system according to claim 5, characterized in that, The system further includes a first tuning transformer circuit; the first tuning transformer circuit includes a first adjustable capacitor array, a first transformer, and a first output capacitor; wherein... One end of the first adjustable capacitor array is connected to the drain of the fifth NMOS transistor and one end of the primary coil of the first transformer, respectively; the other end of the first adjustable capacitor array is connected to the drain of the sixth NMOS transistor and the other end of the primary coil of the first transformer, respectively; the primary coil of the first transformer is also used to connect to the power supply voltage. One end of the first output capacitor is connected to one end of the secondary coil of the first transformer and ground, respectively, and the other end of the first output capacitor is connected to the other end of the secondary coil of the first transformer.

7. The system according to claim 6, characterized in that, The first adjustable capacitor array includes multiple parallel tuning sub-circuits; each tuning sub-circuit includes a first tuning capacitor, a second tuning capacitor, a first tuning NMOS transistor, and a second tuning NMOS transistor; wherein, The source of the first tuned NMOS transistor is connected to ground in parallel with the source of the second tuned NMOS transistor; The gate of the first tuning NMOS transistor and the gate of the second tuning NMOS transistor are connected in parallel to the tuning control signal. The drain of the first tuned NMOS transistor is connected to the drain of the fifth NMOS transistor and one end of the primary coil of the first transformer through the first tuned capacitor. The drain of the second tuned NMOS transistor is connected to the drain of the sixth NMOS transistor and the other end of the primary coil of the first transformer through the second tuned capacitor.

8. The system according to any one of claims 1 to 7, characterized in that, The system also includes a second power amplifier circuit and a second tuning transformer circuit. The voltage gain of the second power amplifier circuit is adjustable, and it is used to output the first differential input signal and the second differential input signal to the first power amplifier circuit through the second tuning transformer circuit.

9. The system according to claim 8, characterized in that, The second power amplifier circuit includes multiple common-source cascode sub-circuits; each common-source cascode sub-circuit includes a first driving capacitor, a second driving capacitor, a first driving NMOS transistor, a second driving NMOS transistor, a third driving NMOS transistor, and a fourth driving NMOS transistor; wherein, The gate of the first driving NMOS transistor is used to connect to the first driving bias voltage and to connect to the third differential input signal through the first driving capacitor; the drain of the first driving NMOS transistor is connected to the source of the third driving NMOS transistor; the source of the first driving NMOS transistor and the source of the second driving NMOS transistor are connected to ground in parallel. The gate of the second driving NMOS transistor is used to connect to the first driving bias voltage and to connect to the fourth differential input signal through the second driving capacitor; the drain of the second driving NMOS transistor is connected to the source of the fourth driving NMOS transistor. The gates of the third driving NMOS transistor and the fourth driving NMOS transistor are both used to connect to the second driving bias voltage. The drains of the third driving NMOS transistors of each of the common-source common-gate sub-circuits are connected in parallel to the first input terminal of the second tuning transformer circuit; the drains of the fourth driving NMOS transistors of each of the common-source common-gate sub-circuits are connected in parallel to the second input terminal of the second tuning transformer circuit.

10. The system according to claim 9, characterized in that, The second tuning transformer circuit includes a second adjustable capacitor array and a second transformer; wherein, One end of the second adjustable capacitor array is connected to the drain of each of the third driving NMOS transistors and one end of the primary coil of the second transformer, and the other end of the second adjustable capacitor array is connected to the drain of each of the fourth driving NMOS transistors and the other end of the primary coil of the second transformer; the primary coil of the second transformer is also used to connect to the power supply voltage. The two ends of the secondary coil of the second transformer are respectively used to output the first differential input signal and the second differential input signal to the first power amplifier circuit.

11. The system according to claim 9, characterized in that, The second power amplifier circuit includes five common-source common-gate sub-circuits, and the MOS transistor size ratio among the various common-source common-gate sub-circuits is set to 1:1:2:4:

8.

12. The system according to claim 9, characterized in that, The system also includes a filter module connected to the second power amplifier circuit; The filter module is used to filter the fifth and sixth differential input signals and then output the third and fourth differential input signals to the second power amplifier circuit; the filtering process includes filtering out mixing spurious signals at the third harmonic.

13. A power amplifier, characterized in that, Includes the power amplifier system as described in any one of claims 1 to 12.

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