Hybrid continuous-time and discrete-time signal folding circuit architecture and physiological signal acquisition device

Abstract

A hybrid continuous-time and discrete-time signal folding circuit architecture, comprising a continuous-time resistive signal folding amplifier, an analog-to-digital converter, a folding error adaptive compensation digital reconstructor; the continuous-time resistive signal folding amplifier is used for asynchronous folding and amplifying the input signal, and updating the control code D 1. to fold and amplify the input signal V IN into a predefined threshold window to obtain a folded and amplified signal V FA ; the V FA into the analog-to-digital converter is quantized as D 2; thereby achieving the folded and amplified input signal, thereby avoiding signal chain saturation. The present application has wide input range and large artifact recovery speed performance under embedded signal chain gain conditions, and can realize adaptive compensation of folding error in the digital reconstruction process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a signal folding circuit architecture that combines continuous-time and discrete-time signals, and a physiological signal acquisition device. Background Technology

[0002] With the development of integrated circuits, physiological signal monitoring devices are becoming miniaturized and intelligent. Accurate monitoring and feedback of physiological information relies on precise acquisition of physiological electrical signals. The signal acquisition quality of the analog front-end directly affects the quality of the entire signal acquisition link, which in turn affects the quality of the back-end digital signal processing, thus limiting the performance of the entire physiological electrical signal monitoring system. In wearable sensors, firstly, even small movements can cause significant changes in electrode impedance, resulting in common-mode artifacts and common-mode to differential-mode artifacts due to impedance mismatch between electrodes and skin. Secondly, skin compression and deformation can easily generate low-frequency differential-mode signal interference of up to hundreds of millivolts. These motion artifacts, far exceeding the bioelectrical signal itself, strongly disrupt the ExG signal baseline, often causing analog front-end output signal saturation, leading to acquisition failure and severely limiting the application scenarios of wearable devices. Neural implantation devices often encounter stimulation artifacts, which are particularly significant in closed-loop systems that implement adaptive stimulation based on pathological feature analysis feedback. Because the acquisition and stimulation electrodes are often integrated on the same microelectrode array, the stimulation voltage fluctuations generated by the stimulation current in the tissue fluid can easily be conducted to adjacent acquisition electrodes, manifesting as step-like stimulation artifacts of up to hundreds of mV.

[0003] Since low-frequency interference is mixed with the effective signal and cannot be effectively removed in the analog domain, the dynamic range can be increased to accommodate differential mode artifacts and prevent signal saturation or distortion. Then, analysis can be performed in the digital domain using advanced signal processing techniques. Regarding the impact of stimulus artifacts, such as the fact that stimulus-evoked neural responses may appear within 1 ms after stimulation, the analog front-end must recover rapidly after stimulation to minimize information loss in neural response signal acquisition. In summary, the key issue is how to achieve a wide input range with high energy efficiency to accommodate low-frequency artifacts while simultaneously recovering rapidly from sudden stimulus artifact interference.

[0004] While traditional low-noise amplifier-cascaded analog-to-digital converter (ADC) architectures achieve high energy efficiency and low noise, they are prone to saturation under significant artifact interference. Existing signal folding techniques can effectively extend the input range to accommodate low-frequency interference signals. However, since the clock control of the folding process is synchronized with the ADC sampling clock, it can be understood as a discrete signal folder. Its fastest recovery time under sudden stimulus artifact interference is limited by the feedback clock frequency, leading to signal chain saturation and information loss. Increasing the synchronization clock frequency can reduce the recovery time, but higher sampling rates result in significant increases in ADC power consumption. Introducing a digital domain artifact detector to activate a fast artifact recovery loop when the ADC output is saturated increases the recovery time due to the logic delay of the digital domain artifact detector and the ADC quantization delay. Furthermore, considering the dynamic changes in folding errors, the fixed threshold reconstruction process in digital reconstruction leads to poor linearity in the output. Lookup tables or first-order dynamic error compensation offer some optimization, but consume hardware resources and increase power consumption. Currently, there is no systematic solution that can simultaneously solve the problems of motion artifact compatibility, fast recovery under stimulus artifacts, and efficient dynamic compensation of folding errors in a single chip design. Summary of the Invention

[0005] This invention addresses the technical problem that existing technologies cannot simultaneously achieve a wide input range and a high artifact recovery speed. It improves the circuit architecture used for physiological signal acquisition and provides a physiological signal acquisition circuit architecture that combines a wide input range and a high artifact recovery speed.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A hybrid continuous-time and discrete-time signal folding circuit architecture includes a continuous-time resistive signal folding amplifier, an analog-to-digital converter, and a folding error adaptive compensation digital reconstructor. The continuous-time resistive signal folding amplifier is used to process the folded and amplified signal. V FA Perform continuous tracking and update the control code. D 1, to input signal V IN Continuous time folding magnification to a predefined threshold window ( Vth down , Vth up (within) the; the said V FA The input to the analog-to-digital converter is quantized. D 2; This achieves the folding and amplification of the input signal, thereby avoiding signal chain saturation. The output of the analog-to-digital converter... D 2. The quantization result of the original signal is obtained after passing through the folding error adaptive compensation digital reconstructor. D OUTBecause the folding process is triggered asynchronously in a continuous time frame rather than controlled by an external fixed clock frequency, it can quickly stabilize under fast artifact signal interference. The beneficial effects are that it combines a wide input range with high artifact recovery speed while also enabling dynamic compensation for folding errors, all within the embedded signal chain gain condition.

[0007] Preferably, the continuous-time resistive signal folding amplifier includes an upper threshold continuous-time comparator COMP. UP Lower threshold comparator COMP DOWN The system includes an upper and lower threshold counter, a digital-to-analog converter (DAC), and a resistive amplifier; the upper threshold continuous-time comparator COMP... UP Input negative terminal and threshold voltage Vth UP Connect the positive input terminal to the folded signal. V FOLD Connected, the lower threshold continuous-time comparator COMP DOWN Input positive terminal and threshold voltage Vth DOWN Connect the negative input terminal to the folded signal. V FA The UP input port of the upper and lower counters is connected to the output of the upper threshold comparator, and the DOWN input port is connected to the output of the lower threshold comparator. The output counting results of the upper and lower counters are... M -bit signal D 1. Connected to a digital-to-analog converter and a digital reconfigurator, the positive and negative current outputs of the DAC are connected to the internal nodes of a resistive amplifier. I OP and I ON Thus achieving input V IN Subtraction yields the folded and amplified signal. V FA .

[0008] Preferably, the analog-to-digital converter will V FA Quantified as N -bit signal D 2. And output connected to the digital reconfiguration processor.

[0009] Preferably, the folding error adaptive compensation digital reconstructor... D 2. Perform dynamic offset compensation and reconstruction to obtain the final output. D OUT .

[0010] Preferably, the up / down counter is asynchronously controlled by the output of the threshold detection comparator and is not synchronized with the clock of the analog-to-digital converter.

[0011] Preferably, the threshold voltage of the upper / lower threshold comparator is determined by an input embedded DC shifter.

[0012] The present invention also provides a physiological signal acquisition device, characterized in that it includes the above-mentioned signal folding circuit architecture that combines continuous time and discrete time, for acquiring and processing physiological electrical signals, and is compatible with large-amplitude motion artifacts and can achieve rapid recovery under rapid stimulation artifacts, and can achieve adaptive compensation of folding errors in the digital reconstruction process.

[0013] The beneficial effects of the hybrid continuous-time and discrete-time signal folding circuit architecture of the present invention are as follows: (1) The continuous time signal folding improves the input range, while its asynchronous control folding feature enables the system to recover in time under rapid stimulation and interference.

[0014] (2) The hybrid continuous-time and discrete-time signal folding circuit architecture enables the system to have the high energy efficiency of traditional amplifier cascade quantizers.

[0015] (3) The integration of signal folding and amplification helps to reduce hardware resource consumption.

[0016] (4) The digital reconstructor reduces hardware resources and optimizes output linearity by adaptively compensating for folding errors. Attached Figure Description

[0017] Figure 1 shows the circuit implementation structure (I) and specific embodiment (II) of a sensor interface circuit for physiological signal acquisition based on a hybrid continuous-time and discrete-time signal folding architecture.

[0018] Figure 2 This is a threshold detection comparator circuit implementation structure (I) and a specific example diagram (II).

[0019] Figure 3 This is a schematic diagram of the adaptive error compensation process of the digital reconfigurator.

[0020] Figure 4 This is a simulation image of electrocardiogram signals superimposed with motion artifacts acquired using the technology of this invention. Detailed Implementation

[0021] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. The invention is by no means limited to any specific configurations and algorithms presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the inventive concept. In the accompanying drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the invention.

[0022] Example This embodiment implements a sensor interface circuit for physiological signal acquisition based on a signal folding architecture that combines continuous and discrete time.

[0023] Figure 1 This is a system architecture diagram of the signal folding circuit that combines continuous-time and discrete-time signals in this embodiment. Figure 1 As shown in (I), since this embodiment is a sensor interface circuit for physiological signal acquisition, an additional buffer is added to the input stage to perform signal conditioning, and it is set to unity gain to avoid loss of input range. The subsequent stage is the core circuit architecture of this invention, including a continuous-time resistive signal folding amplifier, an analog-to-digital converter, and a folding error adaptive compensation digital reconstructor. The circuit input in this embodiment is an analog signal. V IN The output is a digital signal. D OUT A unity-gain buffer completely replicates the input signal to the output and connects to the input of a continuous-time resistive signal folding amplifier. The output of the continuous-time resistive signal folding amplifier... V FA Connect the positive terminal of the threshold detection comparator, and connect its negative terminal to the threshold. Vth UP Therefore, only V FA Only a sufficiently large value will trigger the upper threshold detection comparator. Similarly, V FA Connect the negative terminal of the lower threshold detection comparator, and connect its positive terminal to... Vth DOWN Therefore, only V FA The threshold value must be small enough to trigger the lower threshold detection comparator. The outputs of the upper / lower threshold comparators are connected to the UP and DOWN ports of the upper / lower counters, respectively. The outputs of the upper / lower counters... N position D1. Connect to the digital-to-analog converter and subtract it from the input signal, so that... V FA The changes in value are offset, thus limiting the value to the threshold window. Vth UP , Vth DOWN This completes the continuous-time portion of the invention. Next is the discrete-time portion. V FA Connected to an analog-to-digital converter, it is quantized to M position D 2. The aforementioned D 2 and D 1. All are connected to the digital reconstruction processor and undergo adaptive reconstruction to obtain D OUT .

[0024] like Figure 1 (II) shows a differential circuit implementation diagram of a signal folding circuit architecture that combines continuous-time and discrete-time methods. Analog input differential signal. V IP and V IN First, the signal passes through a unity-gain buffer. This buffer can be AC-coupled or DC-coupled. The differential output of the buffer is connected to a differential continuous-time resistive signal folding amplifier. This amplifier is cascaded in sequence with an input crossbar, a resistive amplifier, a resistive digital-to-analog converter, an output crossbar, a threshold detection comparator, and an up / down counter. The input resistance of the resistive amplifier is... R IN The feedback resistor is R F The output of the up / down counter contains 6 bits of the absolute count value. Sum and sign bit Dir ,in Dir The connection between the buffer output signal and the resistive amplifier is changed by controlling the input cross switch. The output current terminal of the resistive analog-to-digital converter is connected to the resistive amplifier. I ON The current-absorbing terminal is connected to the resistive amplifier. I OP After passing through the resistive amplifier, the output cross switch changes again, making... V IP_BUF and V IN_BUF The corresponding folded and amplified signal V FAP and V FANThese are connected to the positive and negative input terminals of the threshold detection comparator, respectively. The output of the threshold detection comparator is then connected to the DOWN and UP terminals of the up / down counter, respectively. V FAP and V FAN It is also connected to a 12-bit analog-to-digital converter. The 12-bit analog-to-digital converter outputs a 12-bit code. D 2 and data stability signal DR Connected to the digital reconstruction processor. The up / down counter simultaneously outputs a folding event indication signal. FLAG The digital reconstruction processor utilizes the aforementioned... D 1 and D 2 Adaptive Reconstruction Output D out .

[0025] Threshold detection comparator circuit (with) Figure 2 For example, not limited to Figure 2 This implementation method) Figure 2 (I) shows the basic structure of the differential threshold detection comparator. It contains two identical fixed threshold comparators, with the upper threshold comparator being COMP. UP positive input terminal connected V ip Negative input terminal connected V in COMP of the lower threshold comparator DOWN positive input terminal connected V in negative input terminal connected V ip . Figure 2 (II) is a detailed circuit diagram of the threshold detection comparator, including a DC shifter and a tail current source I. ss Gate control signals for NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, and M5. DPulseB Gate control signal of NMOS transistor M8 DPulse Inverter INV1, buffer BUF1. Comparator positive input signal. V ip Output after DC shifter V ip ’ Connect the gate and negative terminal of NMOS transistor M2 to input signals. V in The gate of NMOS transistor M1 and the sources of NMOS transistors M1 and M2 are both connected to the tail current source I. ssThe drain of NMOS transistor M1 is connected to the gate of PMOS transistors M3 and M4; the sources of PMOS transistors M3-M6 are connected to the power supply AVDD; the drains of PMOS transistors M4 and M2 are connected to the drain of PMOS transistor M5; the gates of PMOS transistors M6 and M7 are connected to the drain of PMOS transistor M5; the drain of NMOS transistor M8 is connected to the drain of NMOS transistor M7; and the sources of NMOS transistors M7 and M8 are connected to ground AGND. DPulse Connect the input of the inverter, DPulseB Connect the input to the inverter.

[0026] The input resistance at the positive and negative terminals of the resistive amplifier is R IN The feedback resistors at both the positive and negative ends are R F The positive end R F A negative feedback is formed by bridging the positive input terminal and the negative output terminal, wherein the negative terminal... R F A negative feedback loop is formed between the negative input terminal and the positive output terminal. The set gain is... .

[0027] The resistive digital-to-analog converter includes a binary resistor array at both ends of the differential circuit. The resistance values ​​of the resistor array are respectively the input resistances of the resistive amplifier. R F 1 times, 2 times, ... A times. A This corresponds to the gain setting of the resistive amplifier.

[0028] The algorithm structure of the adaptive compensation digital reconstructor for folding error is as follows: Figure 3 As shown, the output of the initial state digital reconstructor D out Set to 0, folding error Rec It is also set to 0. Each cycle outputs a digital code by judging whether the counter is up or down. D The change in 1 determines whether a folding event has occurred. If a folding event occurs, the folding error is updated synchronously, and the updated value is the sum of the output of the analog-to-digital converter. D The change value of 2. Finally, through the current period's... D 2. Add the folding error of the current period to obtain the reconstructed output of the current period. D out .

[0029] The following describes the working process of the sensor interface circuit for physiological signal acquisition based on a hybrid continuous-time and discrete-time signal folding architecture provided in this embodiment.

[0030] like Figure 1 (II) shows a sensor interface circuit implementation diagram for physiological signal acquisition based on a hybrid continuous-time and discrete-time signal folding architecture. It employs a differential structure to suppress common-mode interference. The input differential signal passes through a unity-gain buffer. V IP > V IN For example, the control signal of the cross switch at this time Dir The initial value is 0, and the output of the unity-gain buffer is directly connected to the subsequent continuous-time resistive signal folding circuit. At this time, the initial control code of the resistive digital-to-analog converter is also 0, thus enabling normal amplification. When V FAP - V FAN > Vth up At this time, it will trigger the upper threshold comparator in the threshold detection comparator, and then trigger the UP port of the upper / lower counter. The output result of the upper / lower counter Sum Increase by 1. Control the resistive digital-to-analog converter to enable the corresponding number of cells. The result is obtained from... I OP Extracting current, for I ON Injected current will cause the output of the resistive amplifier to... V FAP Shift down, and at the same time V FAN Shift up. This makes V FAP - V FAN Return to the defined threshold window. Then the... V FAP - V FAN After passing through a 12-bit ADC quantizer, a 12-bit digital code is output. D 2 and quantization completion signal DR . Dir and Sum Combine to obtain a 7-bit digital code D 1 represents the DAC control code of the continuous-time signal folder. In DR Triggered by the folding error adaptive compensation digital reconstruction processor, the recombination operation is performed to obtain the final digital code. D OUT .

[0031] The circuit-level simulation in this embodiment uses a CMOS 180nm process and is obtained using Cadence's Spectre in the ADE (Analog Integrated Circuit Design Automation) environment. The power supply voltage for the circuit operation is 1.8V. Figure 4 This refers to the superposition of 100mV on the ECG signal using the technology of this invention. pp Simulation results of sinusoidal interference signals show that the signal after passing through the continuous-time signal folder... V FOLD It is limited to a preset threshold window. And the processor output is reconstructed through digital signal reconstruction. D DOUT The input signal can be fully recovered and the electrocardiogram signal can be extracted from it through a digital filter.

[0032] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM).

[0033] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and additions without departing from the principle of the present invention, and these improvements and additions should also be considered within the scope of protection of the present invention.

Claims

1. A signal folding circuit architecture that combines continuous-time and discrete-time methods, characterized in that, include: Continuous-time resistive signal folding amplifier, used for input signal... V IN Perform continuous tracking and update the control code. D 1, and the input signal V IN Dynamically fold and enlarge, and limit to a predefined threshold window ( Vth down , Vth up Within ) output the folded and amplified signal V FA ; An analog-to-digital converter, whose input is connected to the output of the continuous-time resistive signal folding amplifier, is used to process the folded and amplified signal under the control of a synchronous clock. V FA Perform periodic sampling and quantization to output digital codes. D 2; fold An error-adaptive compensation digital reconstructor, the first input of which is connected to the control code of the continuous-time resistive signal folding amplifier. D 1. Its second input terminal is connected to the output terminal of the analog-to-digital converter to receive the digital code, used to adaptively reconstruct the control code to output a representative of the input signal. V IN The final quantification result D OUT .

2. The signal folding circuit architecture combining continuous-time and discrete-time signals according to claim 1, characterized in that: The continuous-time resistive signal folding amplifier includes a resistive signal amplifier and an upper threshold continuous-time comparator COMP. UP Lower threshold continuous-time comparator COMP DOWN Up and down counters and digital-to-analog converters (DACs); The positive input terminal of the resistive signal amplifier is V IP The negative input is V IN The input resistance is R IN The feedback resistor is R F The positive output terminal is V FAP The negative output terminal is V FAN The difference signal between the two is V FA . The upper threshold continuous-time comparator COMP UP Connect the threshold voltage to the negative input terminal Vth UP The positive input terminal is connected to the folded and amplified signal. V FA The lower threshold continuous-time comparator COMP DOWN The lower threshold voltage is connected to the positive input terminal. Vth DOWN The negative input terminal is connected to the folded and amplified signal. V FA The UP control terminal of the upper and lower counters is connected to the output terminal of the upper threshold continuous-time comparator, and the DOWN control terminal of the upper and lower counters is connected to the output terminal of the lower threshold continuous-time comparator. This is used to perform counting operations based on the comparison result. The output terminal of the upper and lower counters outputs the control code. D 1; The input terminal of the digital-to-analog converter is connected to the output terminal of the upper and lower counters, and is used to convert the control code... D 1 is converted to output current; its positive output terminal is I OP The negative output terminal is I ON They are respectively connected to the resistive signal amplifier. I OP and I ON The terminal achieves the effect of subtracting from the input.

3. The signal folding circuit architecture combining continuous-time and discrete-time signals according to claim 1, characterized in that: The analog-to-digital converter is N A bit-level analog-to-digital converter, whose input is connected to the output of the resistive signal folding amplifier, is used to convert the amplified signal... V AMP Quantified as N -bit of the digital output code D 2. And output the digital reconstructor with adaptive compensation for folding error.

4. The signal folding circuit architecture combining continuous-time and discrete-time signals according to claim 1, characterized in that: The reconstruction process of the folding error adaptive digital reconstructor includes: combining the digital output code... D 1 and D 2. Perform adaptive reconstruction to obtain the final quantization result. D OUT。 5. The resistive signal folding amplifier according to claim 2, characterized in that: The triggering of the up / down counter is controlled by the continuous time threshold comparator, which is an asynchronous triggering control and is not synchronized with the clock of the analog-to-digital converter.

6. The continuous-time threshold comparator according to claim 2, characterized in that: The threshold voltage of the upper / lower threshold comparator is determined by the input embedded DC shifter.

7. A physiological signal acquisition device, characterized in that, The system includes a signal folding circuit architecture that combines continuous-time and discrete-time signals as described in any one of claims 1-7. This architecture is used to acquire and process physiological electrical signals and is compatible with large-amplitude motion artifacts. It can also achieve rapid recovery under rapid stimulation artifacts and adaptively compensate for folding errors during the digital reconstruction process.

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