High-gain double-layer active bootstrap amplifier circuit without low-frequency cutoff effect and design method
By using a transistor to implement a double-layer self-driven bootstrap amplifier circuit, the problems of large area occupation and low-frequency cutoff of capacitor bootstrap in transistor circuits are solved, realizing the effective acquisition of high-gain and low-frequency signals, which is suitable for high-density integration and large-scale production.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTH CHINA UNIV OF TECH
- Filing Date
- 2026-03-24
- Publication Date
- 2026-07-21
AI Technical Summary
In the prior art, capacitive bootstrap in dual-type transistor circuits has the problems of large area occupation and low-frequency cutoff frequency, which limits the high-density integration of the circuit and the passage of low-frequency signals.
A high-gain amplifier circuit is achieved by employing a double-layer self-bootstrapping structure implemented entirely by transistors. Through a transconductance amplifier and a double-layer self-bootstrapping load, the gain bootstrapping is performed on the common-source transistor and the common-gate transistor of the common-source and common-gate loads, respectively, avoiding the use of capacitor components.
It significantly improves the gain of the amplifier circuit, saves layout area, ensures the smooth acquisition of sub-hertz low-frequency electrical signals, avoids the introduction of low-frequency cutoff frequency, and has good process compatibility and application flexibility.
Smart Images
Figure CN122437507A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of analog integrated circuits, and more particularly to a high-gain, low-frequency cutoff-free, two-layer source-driven amplifier circuit and its design method. Background Technology
[0002] Bootstrapping is a technique that uses a local feedback network to make the potential or impedance of one node in a circuit change synchronously with that of another node, thereby removing the constraints of the static operating point and improving key performance aspects such as circuit gain. This technique has wide and crucial applications in various electronic information systems and analog integrated circuits.
[0003] Currently, capacitive bootstrap, due to its simple structure, has become the most common form of bootstrap, especially widely used in single-type transistor circuits such as TFTs. Due to the lack of complementary transistors, gain is limited, making capacitive bootstrap one of the most common methods to improve the gain of single-type transistor amplifiers. For dual-type transistors, represented by CMOS, capacitive bootstrap also has unique value in certain specific scenarios, such as high-precision sample-and-hold circuits. However, the presence of the bootstrap capacitor requires a large physical area for circuit implementation, which is detrimental to high-density integration and mass production of related circuits. Furthermore, the presence of the bootstrap capacitor inevitably introduces a low-frequency cutoff frequency, hindering the passage of low-frequency electrical signals, especially those below sub-Hertz frequencies. Summary of the Invention
[0004] The main objective of this application is to propose a high-gain, low-frequency cutoff-free, double-layer self-driven amplifier circuit and its design method. This circuit adopts a double-layer self-driven structure implemented entirely by transistors, which significantly improves the gain of the amplifier circuit without introducing a low-frequency cutoff frequency or adding additional capacitors.
[0005] To achieve the above objectives, one aspect of this application proposes a high-gain, low-frequency cutoff-free, two-layer self-propelled amplifier circuit, comprising: A transconductance amplifier, the input terminal of which serves as the input terminal of the amplifier circuit; A dual-layer self-lifted load is connected to the output of the transconductance amplifier; The dual-layer self-generated load includes: A common-source, common-gate load, wherein the source of the common-gate transistor serves as the output terminal of the amplifier circuit; The common-source stage has a self-push amplifier, whose input terminal is connected to the source of the common-gate transistor of the common-source common-gate load, and whose output terminal is connected to the gate of the common-source common-gate load. The common-source stage has a self-pumping amplifier, the input of which is connected to the output of the common-source stage has a self-pumping amplifier, and the output of which is connected to the gate of the common-source common-gate load common-gate transistor.
[0006] In some embodiments, the transconductance amplifier can be of various transconductance amplifier types, such as single-ended amplifier, differential amplifier, common-source amplifier, common-source cascode amplifier, etc. Taking a fully differential cascode transconductance amplifier as an example, the transconductance amplifier includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, and a first tail current source; The gate of the first MOS transistor serves as the non-inverting input terminal of the transconductance amplifier and also as the non-inverting input terminal of the amplifier circuit. Its drain is connected to the source of the third MOS transistor, and its source is connected to the first tail current source. The gate of the second MOS transistor serves as the inverting input terminal of the transconductance amplifier and also as the inverting input terminal of the amplifier circuit. Its drain is connected to the source of the fourth MOS transistor, and its source is connected to the first tail current source. The gate of the third MOS transistor is connected to the bias voltage Vb1, and the drain serves as the inverting output terminal of the transconductance amplifier. The gate of the fourth MOS transistor is connected to the bias voltage Vb1, and the drain serves as the non-inverting output terminal of the transconductance amplifier.
[0007] In some embodiments, the dual-layer source load can be either a single-ended structure or a differential structure; Taking a differential structured double-layer self-lifted load as an example, the common-source common-gate load includes a first common-source common-gate load and a second common-source common-gate load. The first common-source common-gate load includes a fifth MOSFET and a seventh MOSFET, and the second common-source common-gate load includes a sixth MOSFET and an eighth MOSFET. The drain of the fifth MOS transistor is connected to the source of the seventh MOS transistor, and the source serves as the inverting output terminal of the amplifier circuit and is also connected to the drain of the third MOS transistor. The drain of the sixth MOS transistor is connected to the source of the eighth MOS transistor, and the source serves as the non-inverting output terminal of the amplifier circuit and is also connected to the drain of the fourth MOS transistor. The drain of the seventh MOS transistor is connected to the power supply; The drain of the eighth MOS transistor is connected to the power supply.
[0008] In some embodiments, the common-source stage self-lifting amplifier can be any voltage amplifier with a gain less than 1, and the closer the gain is to 1, the better the gain performance of the double-layer self-lifting amplifier circuit; for the differential double-layer self-lifting load, the common-source stage self-lifting amplifier can be either two completely identical single-ended amplifiers or a fully differential amplifier. Taking a fully differential common-source self-pumping amplifier as an example, the common-source self-pumping amplifier includes: a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, and a second tail current source; The gate of the ninth MOS transistor serves as the non-inverting input terminal of the common-source stage self-lifting amplifier, and the drain serves as the inverting output terminal of the common-source stage self-lifting amplifier. It is connected to the gate of the eighth MOS transistor and the source of the eleventh MOS transistor, with the source connected to the second tail current source. The gate of the tenth MOS transistor serves as the inverting input terminal of the common-source stage self-lift amplifier, and the drain serves as the non-inverting output terminal of the common-source stage self-lift amplifier. It is connected to the gate of the seventh MOS transistor and the source of the twelfth MOS transistor, with the source connected to the second tail current source. The gate and drain of the eleventh MOS transistor are both connected to the power supply; The gate and drain of the twelfth MOS transistor are both connected to the power supply.
[0009] In some embodiments, the common-gate self-lifted amplifier can be any voltage amplifier with a gain less than 1, and the closer the gain is to 1, the better the gain performance of the dual-layer self-lifted amplifier circuit; for the differential dual-layer self-lifted load, the common-gate self-lifted amplifier can be either two identical single-ended amplifiers or a fully differential amplifier. Taking two identical single-ended common-gate self-lifting amplifiers as an example, the common-gate self-lifting amplifier includes a first common-gate self-lifting amplifier and a second common-gate self-lifting amplifier. The first common-gate self-lifting amplifier includes a thirteenth MOS transistor and a fifteenth MOS transistor, and the second common-gate self-lifting amplifier includes a fourteenth MOS transistor and a sixteenth MOS transistor. The gate of the thirteenth MOS transistor serves as the input terminal of the first common-gate self-propelled amplifier, the drain is connected to the power supply, and the source serves as the output terminal of the first common-gate self-propelled amplifier, connected to the gate of the fifth MOS transistor and the drain of the fifteenth MOS transistor. The gate of the fourteenth MOS transistor serves as the input terminal of the second common-gate power source booster amplifier, the drain is connected to the power supply, and the source serves as the output terminal of the second common-gate power source booster amplifier, connected to the gate of the sixth MOS transistor and the drain of the sixteenth MOS transistor. The gate of the fifteenth MOS transistor is connected to the bias voltage Vb2, and the source is grounded; The gate of the sixteenth MOS transistor is connected to the bias voltage Vb2, and the source is grounded.
[0010] In some embodiments, all MOS transistors are either N-type transistors or all P-type transistors.
[0011] In some embodiments, the amplifier circuit is implemented based on silicon-based processes, N-type metal-oxide thin-film transistor processes, amorphous silicon thin-film transistor processes, polycrystalline silicon thin-film transistor processes, or P-type organic thin-film transistor processes.
[0012] To achieve the above objectives, another aspect of this application provides a method for designing the double-layer self-propagating amplifier circuit described above, comprising the following steps: S1: The voltage at the output terminal of the common-source cascode load is amplified by a common-source stage self-bootstrapping amplifier with a gain less than 1 and close to 1, and the amplified voltage is coupled to the control terminal of the common-source transistor in the common-source cascode load to realize the first stage gain bootstrapping of the common-source transistor. S2: The voltage amplified by the common-source self-pumping amplifier is amplified a second time with a gain less than 1 and close to 1. The amplified voltage is then coupled to the control terminal of the common-source common-gate transistor in the common-source common-gate load to achieve the second stage gain bootstrapping of the common-gate transistor, thereby improving the overall gain of the amplifier circuit without introducing a low-frequency cutoff frequency.
[0013] Compared with the prior art, this application has the following beneficial effects: (1) This application adopts a self-boosting structure that is fully implemented by transistors, without the need for capacitor components, thereby greatly saving the layout area and facilitating high-density integration and large-scale production of circuits.
[0014] (2) Since no capacitor element is introduced, the amplifier circuit of this application does not have zeros or poles at low frequencies and does not introduce a low-frequency cutoff frequency, which can ensure the smooth acquisition of sub-hertz low-frequency electrical signals.
[0015] (3) By using a double-layer self-bootstrapping structure, gain bootstrapping is performed on the common-source transistor and the common-gate transistor of the common-source and common-gate loads respectively, so that the load impedance is approximately increased to Compared to traditional single-layer bootstrap structures, this represents a quadratic increase in impedance, significantly improving the overall gain of the amplifier circuit.
[0016] (4) The circuit structure of this application can be implemented using either a differential structure or a single-ended structure; it can be implemented using either CMOS technology or various thin-film transistor technologies, and has good process compatibility and application flexibility. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A schematic diagram of a high-gain, low-frequency cutoff-free, dual-layer source-driven amplifier circuit is provided as an embodiment of this application. Figure 2 For this application Figure 1 A schematic diagram of the circuit structure of one embodiment of a source-level boost amplifier; Figure 3 For this application Figure 1 A schematic diagram of the circuit structure of an embodiment of a common-gate stage derived from a lift amplifier; Figure 4 A schematic diagram of a two-layer half-circuit structure with a source-driven load provided in one embodiment of this application; Figure 5 A schematic diagram of the overall implementation circuit structure of a high-gain, low-frequency cutoff-free, dual-layer source-driven amplifier circuit provided in one embodiment of this application; Figure 6 This is a schematic diagram illustrating the amplification effect of a high-gain, low-frequency cutoff-free, dual-layer source-driven amplifier circuit according to an embodiment of this application. Detailed Implementation
[0019] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.
[0020] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0021] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.
[0022] Furthermore, in the description of this invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0023] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.
[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of a high-gain, low-frequency cutoff-free, dual-layer self-lifting amplifier circuit according to one embodiment of this application. In one embodiment, the high-gain, low-frequency cutoff-free, dual-layer self-lifting amplifier circuit includes a transconductance amplifier 1 and a dual-layer self-lifting load 2. The dual-layer self-lifting load 2 includes a first common-source cascode load 3, a second common-source cascode load 4, a common-source stage self-lifting amplifier 5, a first common-gate stage self-lifting amplifier 6, and a second common-gate stage self-lifting amplifier 7. The non-inverting input of transconductance amplifier 1 serves as the non-inverting input of the entire amplifier circuit, and the inverting input serves as the inverting input of the entire amplifier circuit. The non-inverting output is connected to the second cascode load 4, and the inverting output is connected to the first cascode load 3. The source of the common-gate transistor of the first cascode load 3 serves as the inverting output of the entire amplifier circuit, and the source of the common-gate transistor of the second cascode load 4 serves as the non-inverting output of the entire amplifier circuit.
[0025] The common-source stage has a non-inverting input terminal of the boost amplifier 5 connected to the source of the common-gate transistor of the first common-source common-gate load 3, an inverting input terminal connected to the source of the common-gate transistor of the second common-source common-gate load 4, a non-inverting output terminal connected to the gate of the common-source transistor of the first common-source common-gate load 3, and an inverting output terminal connected to the gate of the common-source transistor of the second common-source common-gate load 4.
[0026] The input terminal of the first common-source stage source-lift amplifier 6 is connected to the non-inverting output terminal of the common-source stage source-lift amplifier 5, and the output terminal is connected to the gate of the common-source common-gate load 3; the input terminal of the second common-source stage source-lift amplifier 7 is connected to the inverting output terminal of the common-source stage source-lift amplifier 5, and the output terminal is connected to the gate of the common-source common-gate load 4.
[0027] The transconductance amplifier 1 includes a first MOSFET (M1), a second MOSFET (M2), a third MOSFET (M3), a fourth MOSFET (M4), and a first tail current source (ISS1). The gate of MOSFET M1 serves as the non-inverting input of the transconductance amplifier 1, and its drain is connected to the source of MOSFET M3, whose source is connected to the tail current source of ISS1. The gate of MOSFET M2 serves as the inverting input of the transconductance amplifier 1, and its drain is connected to the source of MOSFET M4, whose source is connected to the tail current source of ISS1. The gate of MOSFET M3 is connected to a bias voltage Vb1, and its drain serves as the inverting output of the transconductance amplifier 1. The gate of MOSFET M4 is connected to a bias voltage Vb1, and its drain serves as the non-inverting output of the transconductance amplifier 1.
[0028] The first common-source common-gate load 3 includes the fifth MOSFET (M5) and the seventh MOSFET (M7), and the second common-source common-gate load 4 includes the sixth MOSFET (M6) and the eighth MOSFET (M8). The gate of MOSFET M5 is connected to the output terminal of the first common-source stage source booster amplifier 6, and its drain is connected to the source of MOSFET M7, whose source is connected to the drain of MOSFET M3. The gate of MOSFET M6 is connected to the output terminal of the second common-source stage source booster amplifier 7, and its drain is connected to the source of MOSFET M8, whose source is connected to the drain of MOSFET M4. The gate of MOSFET M7 is connected to the non-inverting output terminal of the common-source stage source booster amplifier 5, and its drain is connected to the power supply. The gate of MOSFET M8 is connected to the inverting output terminal of the common-source stage source booster amplifier 5, and its drain is connected to the power supply.
[0029] Please see Figure 2 , Figure 2For this application Figure 1 A schematic diagram of the circuit structure of one embodiment of the common-source stage self-lifting amplifier 5. In one embodiment, the common-source stage self-lifting amplifier includes a ninth MOS transistor (M9), a tenth MOS transistor (M10), an eleventh MOS transistor (M11), a twelfth MOS transistor (M12), and a second tail current source (ISS2). The gate of transistor M9 serves as the non-inverting input terminal of the common-source stage self-lifting amplifier 5, and its drain serves as the inverting output terminal of the common-source stage self-lifting amplifier 5, and is connected to the source of transistor M11, whose source is connected to the tail current source of ISS2; the gate of transistor M10 serves as the inverting input terminal of the common-source stage self-lifting amplifier 5, and its drain serves as the non-inverting output terminal of the common-source stage self-lifting amplifier 5, and is connected to the source of transistor M12, whose source is connected to the tail current source of ISS2; the gate and drain of transistor M11 are both connected to the power supply; the gate and drain of transistor M12 are both connected to the power supply.
[0030] Please see Figure 3 , Figure 3 For this application Figure 1 A schematic diagram of the circuit structure of one embodiment of the first (second) common-gate source-driven amplifier 6 (7). In one embodiment, the first common-gate source-driven amplifier 6 includes a thirteenth MOS transistor (M13) and a fifteenth MOS transistor (M15), and the second common-gate source-driven amplifier 7 includes a fourteenth MOS transistor (M14) and a sixteenth MOS transistor (M16). The gate of transistor M13 (M14) serves as the input terminal of the first (second) common-gate source-driven amplifier 6 (7), the drain is connected to the power supply, and the source serves as the output terminal of the first (second) common-gate source-driven amplifier 6 (7) and is connected to the drain of transistor M15 (M16); the gate of transistor M15 (M16) is connected to the bias voltage Vb2, and the source is grounded.
[0031] Please see Figure 4 , Figure 4 This is a schematic diagram of a half-circuit structure for a dual-layer self-lifted load provided in one embodiment of this application. In one embodiment, the method for increasing the load impedance of a single-type common-source cascode dual-transistor circuit consists of two steps. The first step is to construct an amplifier, i.e., a common-source self-lifted amplifier, between the source and gate of the common-gate transistor. The gain of this amplifier is used... The second step involves constructing an amplifier between the output of the common-source booster amplifier and the gate of the common-gate transistor; this is called a common-gate booster amplifier. The gain of this amplifier is... The equivalent load impedance can be expressed as:
[0032] As can be seen from the formula, this load has no zeros or poles at low frequencies, and no low-frequency cutoff frequency is introduced. When and Approaching unity gain, the load of this amplifier circuit is as follows:
[0033] Please see Figure 5 , Figure 5 This document provides a schematic diagram of the overall implementation circuit structure of a high-gain, low-frequency cutoff-free, dual-layer self-propelled amplifier circuit according to one embodiment of this application. In one embodiment, the voltage gain of the amplifier circuit is calculated as follows:
[0034] in, This is the resistance value viewed from the output of the amplifier circuit downwards. Within the effective frequency range of low-to-mid-frequency signals, this value can be considered a frequency-independent constant. The resistance of the load is also independent of frequency at low frequencies, resulting in the following gain of the amplifier circuit:
[0035] The formula shows that the gain of this amplifier circuit is a frequency-independent constant at low frequencies, which is beneficial for the acquisition of sub-Hertz low-frequency electrical signals. At the same time, this amplifier circuit also achieves a high gain.
[0036] Please see Figure 6 , Figure 6 This diagram illustrates the amplification effect of a high-gain, low-frequency cutoff-free, dual-layer source-driven amplifier circuit according to one embodiment of this application. As can be seen from the diagram, the entire amplitude-frequency curve exhibits low-pass characteristics, with no low-frequency cutoff frequency. The gain reaches 34 dB, and the bandwidth is 2 kHz, demonstrating excellent overall performance.
[0037] Based on the above-described integrated notch filter amplifier circuit, this embodiment also provides a design method for a high-gain dual-layer self-source boosting cascode amplifier circuit, which includes the following steps: S1: The voltage at the output terminal of the common-source cascode load is amplified by a common-source stage self-bootstrapping amplifier with a gain less than 1 and close to 1, and the amplified voltage is coupled to the control terminal of the common-source transistor in the common-source cascode load to realize the first stage gain bootstrapping of the common-source transistor. S2: The voltage amplified by the common-source self-pumping amplifier is amplified a second time with a gain less than 1 and close to 1. The amplified voltage is then coupled to the control terminal of the common-source common-gate transistor in the common-source common-gate load to achieve the second stage gain bootstrapping of the common-gate transistor, thereby improving the overall gain of the amplifier circuit without introducing a low-frequency cutoff frequency.
[0038] In this embodiment, the high-gain dual-layer self-bootstrapping amplifier circuit includes a transconductance amplifier and a dual-layer self-bootstrapping load. By adding two layers of self-bootstrapping structures to the amplifier load, gain bootstrapping is performed on the common-gate transistor and common-source transistor of the common-source load, so that the amplifier gain is further improved without introducing a low-frequency cutoff frequency.
[0039] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0040] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
[0041] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.
Claims
1. A high-gain, low-frequency cutoff-free, two-layer intrinsically powered amplifier circuit, characterized in that, include: A transconductance amplifier, the input terminal of which serves as the input terminal of the amplifier circuit; A dual-layer self-lifted load is connected to the output of the transconductance amplifier; The dual-layer self-generated load includes: A common-source, common-gate load, wherein the source of the common-gate transistor serves as the output terminal of the amplifier circuit; The common-source stage has a self-push amplifier, whose input terminal is connected to the source of the common-gate transistor of the common-source common-gate load, and whose output terminal is connected to the gate of the common-source common-gate load. The common-source stage has a self-pumping amplifier, the input of which is connected to the output of the common-source stage has a self-pumping amplifier, and the output of which is connected to the gate of the common-source common-gate load common-gate transistor.
2. The dual-layer self-propelled amplifier circuit according to claim 1, characterized in that, Both the common-source stage self-lifting amplifier and the common-gate stage self-lifting amplifier are voltage amplifiers with a gain of less than 1, and the closer the gain is to 1, the better the gain performance of the dual-layer self-lifting amplifier circuit.
3. The dual-layer self-propelled amplifier circuit according to claim 1, characterized in that, The transconductance amplifier is a fully differential cascode transconductance amplifier, which includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, and a first tail current source; The gate of the first MOS transistor serves as the non-inverting input terminal of the transconductance amplifier and also as the non-inverting input terminal of the amplifier circuit. Its drain is connected to the source of the third MOS transistor, and its source is connected to the first tail current source. The gate of the second MOS transistor serves as the inverting input terminal of the transconductance amplifier and also as the inverting input terminal of the amplifier circuit. Its drain is connected to the source of the fourth MOS transistor, and its source is connected to the first tail current source. The gate of the third MOS transistor is connected to the bias voltage Vb1, and the drain serves as the inverting output terminal of the transconductance amplifier. The gate of the fourth MOS transistor is connected to the bias voltage Vb1, and the drain serves as the non-inverting output terminal of the transconductance amplifier.
4. The dual-layer self-propelled amplifier circuit according to claim 1, characterized in that, The dual-layer self-lifting load is a differential structure; The common-source common-gate load includes a first common-source common-gate load and a second common-source common-gate load. The first common-source common-gate load includes a fifth MOSFET and a seventh MOSFET, wherein the fifth MOSFET is a common-gate transistor and the seventh MOSFET is a common-source transistor. The second common-source common-gate load includes a sixth MOSFET and an eighth MOSFET, wherein the sixth MOSFET is a common-gate transistor and the eighth MOSFET is a common-source transistor. The drain of the fifth MOS transistor is connected to the source of the seventh MOS transistor, and the source serves as the inverting output terminal of the amplifier circuit. The drain of the sixth MOS transistor is connected to the source of the eighth MOS transistor, and the source serves as the non-inverting output terminal of the amplifier circuit. The drain of the seventh MOS transistor is connected to the power supply; The drain of the eighth MOS transistor is connected to the power supply.
5. The dual-layer self-propelled amplifier circuit according to claim 1, characterized in that, The common-source self-lift amplifier includes: a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, and a second tail current source; The gate of the ninth MOS transistor serves as the non-inverting input terminal of the common-source stage self-lifting amplifier, and the drain serves as the inverting output terminal of the common-source stage self-lifting amplifier. It is also connected to the source of the eleventh MOS transistor, and the source is connected to the second tail current source. The gate of the tenth MOS transistor serves as the inverting input terminal of the common-source stage self-lift amplifier, and the drain serves as the non-inverting output terminal of the common-source stage self-lift amplifier. It is also connected to the source of the twelfth MOS transistor, and the source is connected to the second tail current source. The gate and drain of the eleventh MOS transistor are both connected to the power supply; The gate and drain of the twelfth MOS transistor are both connected to the power supply.
6. The dual-layer self-propelled amplifier circuit according to claim 1, characterized in that, The common-gate self-lifting amplifier includes a first common-gate self-lifting amplifier and a second common-gate self-lifting amplifier. The first common-gate self-lifting amplifier includes a thirteenth MOS transistor and a fifteenth MOS transistor, and the second common-gate self-lifting amplifier includes a fourteenth MOS transistor and a sixteenth MOS transistor. The gate of the thirteenth MOS transistor serves as the input terminal of the first common-gate source-driven amplifier, the drain is connected to the power supply, and the source serves as the output terminal of the first common-gate source-driven amplifier and is connected to the drain of the fifteenth MOS transistor. The gate of the fourteenth MOS transistor serves as the input terminal of the second common-gate source-driven amplifier, the drain is connected to the power supply, and the source serves as the output terminal of the second common-gate source-driven amplifier and is connected to the drain of the sixteenth MOS transistor. The gate of the fifteenth MOS transistor is connected to the bias voltage Vb2, and the source is grounded; The gate of the sixteenth MOS transistor is connected to the bias voltage Vb2, and the source is grounded.
7. The dual-layer self-propelled amplifier circuit according to any one of claims 1 to 7, characterized in that, All MOS transistors constituting the amplifier circuit are either N-type transistors or P-type transistors.
8. The dual-layer self-propelled amplifier circuit according to any one of claims 1 to 7, characterized in that, The amplifier circuit is implemented based on silicon-based technology, N-type metal oxide thin-film transistor technology, amorphous silicon thin-film transistor technology, polycrystalline silicon thin-film transistor technology, or P-type organic thin-film transistor technology.
9. A method for designing a double-layer self-propagating amplifier circuit as described in any one of claims 1 to 8, characterized in that, Includes the following steps: S1: The voltage at the output terminal of the common-source cascode load is amplified by a common-source stage self-bootstrapping amplifier with a gain less than 1 and close to 1, and the amplified voltage is coupled to the control terminal of the common-source transistor in the common-source cascode load to realize the first stage gain bootstrapping of the common-source transistor. S2: The voltage amplified by the common-source self-pumping amplifier is amplified a second time with a gain less than 1 and close to 1. The amplified voltage is then coupled to the control terminal of the common-source common-gate transistor in the common-source common-gate load to achieve the second stage gain bootstrapping of the common-gate transistor, thereby improving the overall gain of the amplifier circuit without introducing a low-frequency cutoff frequency.