Multi-lane lvds synchronization circuit and method

Abstract

The application discloses a multi-channel LVDS synchronization circuit and a synchronization method. The multi-channel LVDS synchronization circuit comprises N LVDS signal processing channels and a logic unit, the signal processing channels have the same circuit structure, and the logic unit is connected with each LVDS signal processing channel. The synchronization method inputs corresponding LVDS input data into each signal processing channel, quantizes the delay information of the LVDS data of each channel to obtain delay quantization results of the channels, compares the delay information of the LVDS of the multiple channels to generate delay adjustment control signals of the channels, adjusts the delay amount of the corresponding channel according to the delay adjustment control signals, and repeats the operation until the multi-channel LVDS data output is completely aligned, and the multi-channel synchronization is completed. The application can detect the delay difference of each channel in real time, adjust the delay amount of each channel through closed-loop feedback, and finally realize the completely synchronized output of the multi-channel LVDS data.

Description

Technical Field

[0001] This invention belongs to the field of interface circuit simulation technology, specifically relating to multi-channel LVDS synchronization circuits and synchronization methods. Background Technology

[0002] Low-voltage differential signaling (LVDS) interface circuits are widely used in high-speed data transmission systems due to their advantages such as low power consumption, low electromagnetic interference, and high-speed transmission. In multi-channel LVDS transmission applications, such as high-resolution image sensors, multi-channel data acquisition systems, and radar signal processing, multiple LVDS channels often need to transmit data simultaneously, and the data from each channel must be strictly aligned at the receiving end to ensure correct parallel data readout.

[0003] However, due to factors such as chip manufacturing process variations, temperature changes, and power supply fluctuations, different LVDS signal transmission paths introduce varying delays, causing inconsistent arrival times of data from each channel at the receiver, resulting in channel skew. Traditional solutions typically employ manual calibration or external delay lines, but these are difficult to implement with adaptive, high-precision synchronization, and the calibration process is complex and costly. Therefore, how to automatically and accurately align multi-channel LVDS data is a pressing technical challenge that needs to be addressed. Summary of the Invention

[0004] The purpose of this invention is to provide a multi-channel LVDS synchronization circuit that can detect the delay difference of each channel in real time and adjust the delay of each channel through closed-loop feedback, so as to achieve complete synchronous output of multi-channel LVDS data.

[0005] A second objective of this invention is to provide a synchronization method for a multi-channel LVDS synchronization circuit.

[0006] The first technical solution adopted in this invention is a multi-channel LVDS synchronization circuit, including N LVDS signal processing channels and logic units. Each LVDS signal processing channel includes an adjustable delay unit, a pre-emphasis logic unit, a driving circuit and an M-bit time-to-digital converter circuit connected in sequence. The input data is respectively connected to the input terminals of the adjustable delay unit and the M-bit time-to-digital converter circuit. The input terminals of the logic unit are connected to the output terminals of the M-bit time-to-digital converter circuit of each LVDS signal processing channel; The LVDS signal processing channel also includes an adjustment unit. The output of the logic unit is connected to the input of the adjustment unit of each LVDS signal processing channel. The adjustment unit is used to receive the adjustment command issued by the logic unit and output the control signal to the control terminal of the adjustable delay unit to adjust the delay of the corresponding channel.

[0007] The first technical solution of the present invention is further characterized in that, The adjustable delay unit includes PMOS transistors M13, M14, M15, M16, M17, and M18 and NMOS transistors M19, M20, M21, and M22; The source of PMOS transistor M13 is connected to VDD, the gate is connected to control signal S0, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M15 is connected to VDD, the gate is connected to control signal S2, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M16 is connected to VDD, the gate is connected to GND, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M17 is connected to VDD, the gate is connected to GND, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M17 is connected to VDD, the gate is connected to control signal S2, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S2 ... The source of NMOS transistor M18 is connected to VDD, the gate is connected to the data signal, and the drain is connected to the drain of NMOS transistor M19, the gate of PMOS transistor M18, and the gate of NMOS transistor M20. The source of PMOS transistor M18 is connected to VDD, and the drain is connected to the output terminal and the drain of NMOS transistor M20. The source of NMOS transistor M19 is connected to the drain of NMOS transistor M22, and the gate is connected to the data signal. The sources of NMOS transistors M20, M21, and M22 are connected to GND. The gate of NMOS transistor M22 is connected to the drain and gate of NMOS transistor M21.

[0008] The pre-emphasis logic unit is a pulse generator composed of an XOR gate and a short delay chain.

[0009] The driving circuit is an NMOS full-bridge driver with an H-bridge structure.

[0010] The M-bit time-to-digital converter is a delay chain type time-to-digital converter, which includes a delay chain consisting of M basic delay units connected in series and M D flip-flops or latches.

[0011] The adjustment unit contains a counting circuit, which is a Gray code counter or a binary counter; The adjustment unit receives the adjustment command issued by the logic unit, generates a step-type digital code through the counting circuit, and outputs it to the control terminal of the adjustable delay unit.

[0012] The logic unit is a digital logic controller, which integrates a subtraction algorithm module to detect the difference between the output code values ​​of each channel's M-bit time-to-digital converter circuit and quantize the difference into an adjustment command.

[0013] The adjustment instructions include increasing the delay and maintaining the current state; when the difference is not 0, the adjustment unit controls the delay time of the adjustable delay unit to increase; when the difference is 0, the adjustment unit stops stepping and locks the current state.

[0014] The second technical solution adopted in this invention is a synchronization method for a multi-channel LVDS synchronization circuit, comprising the following steps: S1, input the corresponding LVDS input data_i for each signal processing channel; S2, the delay information of the LVDS data of each channel is quantized by the M-bit time-to-digital converter circuit to obtain the delay quantization result dou_i of each channel; S3, input the N-channel dou_i into the logic unit, compare the delay information of multiple channel LVDS, and generate delay adjustment control signals for each channel; S4, the logic unit outputs the delay adjustment control signal to the adjustment unit of the corresponding channel, and the adjustment unit controls the adjustable delay unit to adjust the delay amount of the corresponding channel; S5. Repeat steps S2-S4 until the multi-channel LVDS data outputs are fully aligned, completing multi-channel synchronization.

[0015] The beneficial effects of this invention are: This invention quantizes channel delay in real time through a built-in M-bit time-to-digital converter, and achieves closed-loop automatic calibration by combining comparison and feedback control of the logic unit. Simultaneously, the use of an adjustable delay unit enables fine-grained delay adjustment and measurement. Without significantly increasing power consumption and area, it accurately aligns the output data of multi-channel LVDS circuits, eliminating delay deviations between channels. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the multi-channel LVDS synchronization circuit of the present invention; Figure 2 This is a structural diagram of the adjustable delay unit in an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] Example 1 The multi-channel LVDS synchronization circuit of this invention, such as Figure 1 As shown, it includes N identical LVDS signal processing channels and one logic unit. Each LVDS signal processing channel includes an adjustable delay unit, a pre-emphasis logic unit, a driver circuit, an M-bit time-to-digital converter circuit, and an adjustment unit.

[0019] The input data `data_i` is connected to the input terminal of the adjustable delay unit and the first input terminal of the M-bit time-to-digital converter circuit, respectively. The output terminal of the adjustable delay unit is connected sequentially to the pre-emphasis logic unit and the driver circuit. The output terminal `dataout_i` of the driver circuit is connected to the second input terminal of the M-bit time-to-digital converter circuit, enabling the M-bit time-to-digital converter circuit to directly quantize the path delay from input to output. The input terminals of the logic units are connected to the output terminals of each channel's M-bit time-to-digital converter circuit to receive the delay quantization results; the output terminals of the logic units are connected to the input terminals of each channel's adjustment unit. The adjustment unit receives the adjustment commands issued by the logic units and outputs control signals to the control terminal of the adjustable delay unit to adjust the delay amount of the corresponding channel.

[0020] This circuit uses an M-bit time-to-digital converter to quantize the delay of each channel in real time. The logic unit compares the delay differences of each channel and generates adjustment commands. Through the adjustment unit and the adjustable delay unit, a closed-loop feedback is formed to automatically eliminate the offset between channels and realize the synchronous output of multi-channel data.

[0021] Example 2 The multi-channel LVDS synchronization circuit of this invention, such as Figure 1 As shown, the analog front end includes N LVDS signal processing channels and logic units; each LVDS signal processing channel has the same circuit structure, that is, each LVDS signal processing channel includes an adjustable delay unit, a pre-emphasis logic unit, a driving circuit and an M-bit time-to-digital converter circuit connected in sequence, and the input data is respectively connected to the input terminals of the adjustable delay unit and the M-bit time-to-digital converter circuit; like Figure 2 As shown, the adjustable delay unit includes PMOS transistors M13, M14, M15, M16, M17, and M18 and NMOS transistors M19, M20, M21, and M22. The source of PMOS transistor M13 is connected to VDD, the gate is connected to control signal S0, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M15 is connected to VDD, the gate is connected to control signal S2, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M16 is connected to VDD, the gate is connected to GND, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M17 is connected to VDD, the gate is connected to GND, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M17 is connected to VDD, the gate is connected to control signal S2, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S2 ... The source of NMOS transistor M18 is connected to VDD, the gate is connected to the data signal, and the drain is connected to the drain of NMOS transistor M19, the gate of PMOS transistor M18, and the gate of NMOS transistor M20. The source of PMOS transistor M18 is connected to VDD, and the drain is connected to the output terminal and the drain of NMOS transistor M20. The source of NMOS transistor M19 is connected to the drain of NMOS transistor M22, and the gate is connected to the data signal. The sources of NMOS transistors M20, M21, and M22 are connected to GND. The gate of NMOS transistor M22 is connected to the drain and gate of NMOS transistor M21.

[0022] Under the control of the adjustment unit, the adjustable delay unit selects the corresponding PMOS load transistor through different combinations of three control signals S0, S1, and S2, changing the output current of the mirror current source and thus adjusting the node charging and discharging rate of the inverter core path, achieving continuous adjustment of the transmission delay. PMOS transistor M16 is a normally-on load transistor, providing a fixed base delay to ensure no dead zone across the entire adjustment range. The delay adjustment range of this unit is designed to cover the maximum inter-channel delay offset introduced by chip process deviations, temperature changes, and power supply fluctuations. The delayed signal is then sent from the output terminal OUT to the subsequent pre-emphasis logic unit. The pre-emphasis logic unit detects the transition edge of the input signal and generates a corresponding pre-emphasis pulse signal, completing the pre-emphasis processing of the signal.

[0023] The input terminals of the logic unit are connected to the output terminals of the M-bit time-to-digital converter circuit of each LVDS signal processing channel; The LVDS signal processing channel also includes an adjustment unit. The output of the logic unit is connected to the input of the adjustment unit of each LVDS signal processing channel. The adjustment unit is used to receive the adjustment command issued by the logic unit and output the control signal to the control terminal of the adjustable delay unit to adjust the delay of the corresponding channel.

[0024] Example 3 The multi-channel LVDS synchronization circuit of this invention, such as Figure 1As shown, the analog front end includes N LVDS signal processing channels and logic units; each LVDS signal processing channel has the same circuit structure, that is, each LVDS signal processing channel includes an adjustable delay unit, a pre-emphasis logic unit, a driver circuit and an M-bit time-to-digital converter circuit connected in sequence, and the input data is respectively connected to the input terminals of the adjustable delay unit and the M-bit time-to-digital converter circuit; the input terminal of the logic unit is respectively connected to the output terminal of the M-bit time-to-digital converter circuit of each LVDS signal processing channel.

[0025] The pre-emphasis logic unit uses an edge detection pulse generator composed of an XOR gate and a short delay chain. When the input data undergoes a level transition, it can generate a pre-emphasis pulse signal with adjustable width. The pulse width can be flexibly configured by adjusting the number of stages of the short delay chain to compensate for high-frequency attenuation during high-speed LVDS signal transmission and improve signal integrity.

[0026] The driving circuit adopts a standard H-bridge structure, with an NMOS full-bridge driver as the switching network. The constant current source is connected to the source of the switching transistor, and the constant current is switched to both ends of the load resistor through the differential pair transistors to generate an LVDS differential output signal that conforms to the ANSI / TIA / EIA-644 standard. It has the characteristics of strong driving capability, low static power consumption and low electromagnetic interference.

[0027] The M-bit time-to-digital converter adopts a delay-chain time-to-digital conversion structure, which consists of M basic delay units (buffers or inverter pairs) with identical electrical characteristics connected in series to form a delay sampling chain, and M parallel D flip-flops or latches to form a sampling array. The channel input data data_i is used as the sampling start signal, and the single-ended signal dataout_i converted from the differential output of the drive circuit is used as the sampling stop signal. It can accurately quantize the entire path transmission delay of this channel from input to output and output the corresponding M-bit binary quantization result. The quantization resolution is determined by the single-stage delay of the basic delay unit.

[0028] The LVDS signal processing channel also includes an adjustment unit, which is a digital logic controller generated based on Verilog code synthesis. The output of the logic unit is connected to the input of the adjustment unit of each LVDS signal processing channel. The adjustment unit is used to receive the adjustment instructions issued by the logic unit and output control signals to the control terminal of the adjustable delay unit to adjust the delay of the corresponding channel.

[0029] For the i-th signal processing channel (i=1,2,…,N), its signal connection relationship is as follows: the input data data_i is connected in parallel to the signal input terminal of the adjustable delay unit of this channel and the start signal input terminal of the M-bit time-to-digital converter circuit; the control terminal of the adjustable delay unit is connected to the output terminal of the adjustment unit of this channel; the signal output terminal of the adjustable delay unit is connected to the input terminal of the pre-emphasis logic unit and the driving circuit; the output terminal of the pre-emphasis logic unit is connected to the input terminal of the driving circuit; the output dataout_i of the driving circuit is simultaneously connected to the signal input terminal of the M-bit time-to-digital converter circuit.

[0030] Example 4 Based on Embodiment 3 above, the logic unit of this invention is a synchronous digital logic controller synthesized using Verilog hardware description language. It adopts a global synchronous timing design, and its multiple signal input terminals are respectively connected to the quantization result output terminals dou_i (i=1,2,…,N) of the M-bit time-to-digital conversion circuits of N signal processing channels. The multiple control output terminals c_i (i=1,2,…,N) of the logic unit are respectively connected to the instruction input terminals of the adjustment units of N signal processing channels.

[0031] The adjustment unit is a step control logic circuit synthesized using Verilog hardware description language. It integrates a counting circuit, AND gates, and latches. The counting circuit can use a Gray code counter or a binary counter, with a Gray code counter preferred to avoid metastability risks caused by multi-bit synchronous transitions. The adjustment unit receives the difference adjustment command from the logic unit, generates a step-type digital control code through its internal counting circuit, and outputs it to the control terminal of the adjustable delay unit in this channel, achieving precise step adjustment of the delay. The logic unit integrates a subtraction module, a difference comparison and decision module, and an adjustment instruction generation module. All modules are implemented through combinational logic and sequential logic. Its core working logic is as follows: The difference in code value between dout_1 and dout_1…dout_N is detected by a subtraction circuit, and the difference is quantized into an adjustment instruction c_i (i=1,2,…,N) (including: increasing the delay, maintaining the current state). The adjustment instruction controls the working state of the adjustment unit. When the difference is not 0, the adjustment unit generates a continuously stepping digital code through a counting circuit to control the delay time of the adjustable delay unit to increase continuously. When the difference is 0, the stepping stops and the current state is locked.

[0032] Example 5 The synchronization method of the multi-channel LVDS synchronization circuit of the present invention includes the following steps: S1, power on to complete initialization configuration, input corresponding synchronous single-ended input data data_i (i=1,2,…,N) to N parallel LVDS signal processing channels respectively, and provide a unified time reference for full-channel synchronous calibration; S2, the M-bit time-to-digital converter circuit of each channel uses the input data data_i of this channel as the sampling start signal and the output data dataout_i of this channel's driving circuit as the sampling stop signal to quantize the actual delay information of the entire data transmission path of this channel in real time, and outputs the delay quantization result dou_i in the corresponding M-bit binary format; S3, synchronously input the delay quantization results dou_1~dout_N of N channels into the logic unit. The logic unit uses the delay quantization result dou_1 of channel 1 as the global synchronization reference, performs differential comparison on the delay quantization results of all channels, calculates the delay code value difference between each channel and the reference channel, and generates the delay adjustment control signal of the corresponding channel based on the difference decision result. S4, the logic unit synchronously sends the delay adjustment control signals of each channel to the corresponding channel adjustment unit. The adjustment unit generates a digital control code with corresponding steps according to the received control command and outputs it to the adjustable delay unit of this channel. The signal transmission delay of the adjustable delay unit is adjusted by the digital control code to realize the closed-loop adjustment of the channel delay. S5. Repeat steps S2 to S4 for delay quantization, differential comparison, and delay adjustment until the code value difference between the delay quantization result dou_i of all channels and the reference channel dou_1 is 0. At this time, the LVDS output data of all channels are fully aligned in time, completing the synchronization calibration of the multi-channel LVDS signal and locking the current synchronization state.

[0033] Example 6 This embodiment provides a multi-channel LVDS synchronization circuit, such as Figure 1 As shown, it includes N LVDS signal processing channels (channel 1 to channel N) and one logic unit. All LVDS signal processing channels have the exact same circuit structure.

[0034] Each LVDS signal processing channel includes: an adjustable delay unit, a pre-emphasis logic unit, a drive circuit, an M-bit time-to-digital converter, and an adjustment unit.

[0035] The input data, data_i, first includes an adjustable delay unit. The specific structure of the adjustable delay unit is as follows: Figure 2As shown. The adjustable delay unit includes PMOS transistors M13, M14, M15, M16, M17, and M18, and NMOS transistors M19, M20, M21, and M22; wherein, the source of PMOS transistor M13 is connected to VDD, the gate is connected to the control signal S0, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to the control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M15 is connected to VDD, the gate is connected to the control signal S2, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M16 is connected to VDD, and the gate is connected to... GND, drain connected to the drain of NMOS transistor M21; source of PMOS transistor M17 connected to VDD, gate connected to data signal data_i, drain connected to the drain of NMOS transistor M19, gate of PMOS transistor M18, and gate of NMOS transistor M20; source of PMOS transistor M18 connected to VDD, drain connected to output terminal out and drain of M20; source of NMOS transistor M19 connected to drain of NMOS transistor M22, gate connected to data signal data_i; sources of NMOS transistors M20, M21, and M22 connected to GND; gate of NMOS transistor M22 connected to drain and gate of M21.

[0036] Under the control of the adjustment unit, the adjustable delay unit achieves continuous adjustment of the transmission delay through different combinations of control signals S0, S1, and S2. The delay adjustment range is designed to cover the expected maximum inter-channel delay offset. The signal after delay adjustment is sent from the output to the pre-emphasis logic unit. The pre-emphasis logic unit detects the changing edge of the input signal and generates a pre-emphasis pulse signal Pre_en to complete the pre-emphasis processing of the signal. The pre-emphasis signal is sent to the driver circuit, which converts it into a differential signal conforming to the LVDS protocol standard and outputs dataout_i.

[0037] The M-bit time-to-digital converter uses the input data data_i of this channel as the start signal and the output dataout_i of the driver circuit as the stop signal to quantize the actual transmission delay of the entire path from data_i to dataout_i of this channel, and outputs the M-bit binary quantization result dou_i.

[0038] The logic unit employs a synchronous digital logic controller synthesized using the Verilog hardware description language. Internally, it integrates a subtraction algorithm module (implemented through combinational or sequential logic), a difference comparison and decision module, and an instruction generation module. The logic unit acquires in real-time the quantized code values ​​dou_1, dou_2, ..., dou_N output from the M-bit time-to-digital converters of N signal processing channels. Using the quantized code value dou_1 of channel 1 as the global synchronization reference, the subtraction module detects the code value difference between dou_i of the remaining channels and the reference dou_1. This difference is then quantized into corresponding adjustment instructions c_i (i=1,2,...,N) through internal comparison and decision logic. These adjustment instructions include two types: "increase delay" and "maintain current state." The logic unit controls the operating state of the corresponding channel adjustment unit through these instructions.

[0039] The adjustment unit is a step control logic synthesized based on the Verilog hardware description language. It contains a counting circuit, AND logic gates, and latches. The counting circuit can be a Gray code counter or a binary counter, with a Gray code counter preferred. The adjustment unit generates a step-type digital control code through the internal counting circuit according to the adjustment command issued by the logic unit, and outputs it to the control terminal of the adjustable delay unit.

[0040] The specific working logic of the adjustment unit is as follows: when the received difference adjustment command is non-zero, the counting circuit monotonically increases the digital control code by a fixed step size, thereby controlling the transmission delay time of the adjustable delay unit to increase linearly; when the received difference is zero, the counting circuit immediately stops counting and locks the current digital control code output through a latch to maintain the current delay amount. The above-mentioned delay quantization, comparison, adjustment, and locking processes constitute a complete closed-loop feedback synchronous control system.

[0041] During circuit operation, the above closed-loop calibration process is repeated until the output dataout_i waveforms of all channels are perfectly aligned in time, completing the full-channel synchronous calibration. In this embodiment, the quantization resolution of the M-bit time-to-digital converter determines the synchronization accuracy of the circuit. The value of M can be flexibly selected according to the system's synchronization accuracy requirements, with a preferred value of 6 to 10 bits, corresponding to a quantization resolution of tens of picoseconds, which can meet the synchronization requirements of high-speed LVDS transmission above 1Gbps.

[0042] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0043] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-channel LVDS synchronization circuit, characterized in that, It includes N LVDS signal processing channels and logic units. Each LVDS signal processing channel includes an adjustable delay unit, a pre-emphasis logic unit, a driving circuit, and an M-bit time-to-digital converter circuit connected in sequence. The input data is respectively connected to the input terminals of the adjustable delay unit and the M-bit time-to-digital converter circuit. The input terminals of the logic unit are connected to the output terminals of the M-bit time-to-digital converter circuit of each LVDS signal processing channel; The LVDS signal processing channel also includes an adjustment unit. The output of the logic unit is connected to the input of the adjustment unit of each LVDS signal processing channel. The adjustment unit is used to receive the adjustment command issued by the logic unit and output the control signal to the control terminal of the adjustable delay unit to adjust the delay of the corresponding channel.

2. The multi-channel LVDS synchronization circuit according to claim 1, characterized in that, The adjustable delay unit includes PMOS transistors M13, M14, M15, M16, M17, and M18 and NMOS transistors M19, M20, M21, and M22; The source of PMOS transistor M13 is connected to VDD, the gate is connected to control signal S0, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M15 is connected to VDD, the gate is connected to control signal S2, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M16 is connected to VDD, the gate is connected to GND, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M17 is connected to VDD, the gate is connected to GND, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M17 is connected to VDD, the gate is connected to control signal S2, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S1, and the drain is connected to the drain of NMOS transistor M21; the source of PMOS transistor M14 is connected to VDD, the gate is connected to control signal S2 ... The source of NMOS transistor M18 is connected to VDD, the gate is connected to the data signal, and the drain is connected to the drain of NMOS transistor M19, the gate of PMOS transistor M18, and the gate of NMOS transistor M20. The source of PMOS transistor M18 is connected to VDD, and the drain is connected to the output terminal and the drain of NMOS transistor M20. The source of NMOS transistor M19 is connected to the drain of NMOS transistor M22, and the gate is connected to the data signal. The sources of NMOS transistors M20, M21, and M22 are connected to GND. The gate of NMOS transistor M22 is connected to the drain and gate of NMOS transistor M21.

3. The multi-channel LVDS synchronization circuit according to claim 1, characterized in that, The pre-emphasis logic unit is a pulse generator composed of an XOR gate and a short delay chain.

4. The multi-channel LVDS synchronization circuit according to claim 1, characterized in that, The driving circuit is an NMOS full-bridge driver with an H-bridge structure.

5. The multi-channel LVDS synchronization circuit according to claim 1, characterized in that, The M-bit time-to-digital converter circuit is a delay chain type time-to-digital converter circuit, which includes a delay chain consisting of M basic delay units connected in series and M D flip-flops or latches.

6. The multi-channel LVDS synchronization circuit according to claim 1, characterized in that, The adjustment unit contains a counting circuit, which is a Gray code counter or a binary counter. The adjustment unit receives the adjustment command issued by the logic unit, generates a step-type digital code through the counting circuit, and outputs it to the control terminal of the adjustable delay unit.

7. The multi-channel LVDS synchronization circuit according to claim 1, characterized in that, The logic unit is a digital logic controller, which integrates a subtraction algorithm module to detect the difference between the output code values ​​of each channel's M-bit time-to-digital converter circuit and quantize the difference into an adjustment command.

8. The multi-channel LVDS synchronization circuit according to claim 7, characterized in that, The adjustment instructions include increasing the delay and maintaining the current state; when the difference is not 0, the adjustment unit controls the delay time of the adjustable delay unit to increase; when the difference is 0, the adjustment unit stops stepping and locks the current state.

9. A multi-channel LVDS synchronization method, characterized in that, The multi-channel LVDS synchronization circuit described in any one of claims 1 to 8 includes the following steps: S1, input the corresponding LVDS input data_i for each signal processing channel; S2, the delay information of the LVDS data of each channel is quantized by the M-bit time-to-digital converter circuit to obtain the delay quantization result dou_i of each channel; S3, input the N-channel dou_i into the logic unit, compare the delay information of multiple channel LVDS, and generate delay adjustment control signals for each channel; S4, the logic unit outputs the delay adjustment control signal to the adjustment unit of the corresponding channel, and the adjustment unit controls the adjustable delay unit to adjust the delay amount of the corresponding channel; S5. Repeat steps S2-S4 until the multi-channel LVDS data outputs are fully aligned, completing multi-channel synchronization.

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