A novel touch screen power-on reset circuit and control method for preventing ESD false triggering
By introducing an ESD interference shielding circuit and a low-pass filter circuit into the power-on reset circuit of a large chip, combined with a selection circuit control method, the problem of false triggering caused by ESD is solved, ensuring that the circuit works normally during ESD events.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NEW VISION MICROELECTRONICS INC
- Filing Date
- 2025-01-21
- Publication Date
- 2026-07-21
AI Technical Summary
Existing power-on reset circuits are prone to false triggering due to ESD in large chips, especially when the internal power and ground lines are long. The parasitic resistance and capacitance of the power and ground lines are large, resulting in inconsistent potentials and causing false triggering that affects the normal operation of the circuit.
The power-on reset circuit incorporates an ESD interference shielding circuit, a low-pass filter circuit, and a selection circuit. The output of the ESD interference shielding circuit controls the input of the selection circuit, ensuring that the output is a high level above ground potential when an ESD event occurs, thus preventing false triggering.
It effectively prevents false triggering caused by power supply or ground potential rise due to ESD, ensures that the power-on reset circuit works normally during ESD events, and avoids false triggering affecting circuit function.
Smart Images
Figure CN122437529A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chips, specifically to large chips, especially power-on reset circuits in large chips, and more specifically to power-on reset circuits with high internal power supply ground impedance and high ESD level requirements, as well as corresponding control methods for controlling these power-on reset circuits. Background Technology
[0002] A power-on reset circuit is a circuit that generates an automatic reset signal when the chip is powered on. It can prevent the circuit from being in an uncertain or erroneous state during the power rise process, and enable the circuit to start working from a definite state.
[0003] The principle of power-on reset circuit can be used Figure 1 For example, see the waveforms of each signal. Figure 2 As shown. The voltage of power supply VDD when it is working normally is VCC, and the voltage of ground when it is working normally is 0.
[0004] When power supply VDD is applied, V1 initially rises following VDD due to the effect of capacitor C1. When V1 rises above the turn-on threshold of NM0, NM0 begins to conduct, discharging capacitor C1, and V1 begins to fall. When V1 falls to the turn-on threshold of PM0, PM0 begins to conduct, slowly charging capacitor C2 through resistor R1. The voltage V2 across capacitor C2 then slowly rises until it reaches the high threshold VT of Schmitt trigger X1. X1 At this point, the output V4 of Schmitt trigger X1 flips from high to low. The low V4 then turns on PM1, directly pulling V3 high, causing V2 to be pulled directly up to the power supply voltage VDD. After Schmitt trigger X1 flips, the output POR of inverter X2 also flips from low to high during the initial power-on phase, thus ending the power-on reset process. The period during which POR remains low is the required power-on reset signal. After the power-on phase is complete, voltage V2 remains high, the output V4 of Schmitt trigger X1 remains low, and the output POR of inverter X2 remains high, without affecting the normal operation of the circuit.
[0005] The defects of power-on reset circuits in the prior art can be listed as follows:
[0006] Existing power-on reset circuits are prone to false triggering during electrostatic discharge (ESD), causing the chip to enter a reset state and affecting product functionality.
[0007] Currently, the above problems are often addressed by adding filter circuits to weaken ESD signals and adding Schmitt triggers to improve noise margin. These methods usually focus on dealing with ESD incidents on the power supply.
[0008] However, when the power and ground lines inside large chips are relatively long, and the parasitic resistance and capacitance of the power and ground lines are large, when ESD occurs, the ESD effect on the power and ground lines is out of phase. The ground potential is often raised in a short time, or even the power and ground potentials are reversed. This causes the existing POR circuit to be falsely triggered, causing the circuit to return to the reset state and affecting the normal operation of the circuit.
[0009] In another aspect, existing power-on reset circuits can also be used as follows: Figure 3 As shown, the waveforms of each signal are shown below. Figure 4 As shown. When a positive ESD signal appears on the ground line VSS, VSS is instantly raised to VESD. Due to the principle of charge conservation, the upper plate V2 of capacitor C2 is also raised to VESD along with the ground line. At this time, VSS = VESD, V2 = VCC + VESD, V2 - VSS = VCC, and V2 remains unchanged relative to VSS. Similarly, V3 is also raised to VESD. The drain voltage of PM0, V3 = VCC + VESD, and the substrate voltage of PM0 is VCC. Therefore, the parasitic diode D0 from the drain of PM0 to the substrate is easily turned on, causing V3 to discharge to the power supply VDD through D0. Similarly, capacitor C2 begins to discharge rapidly to the power supply VDD through resistor R1, and the voltage of V2 begins to drop rapidly to a value higher than the power supply VDD by the threshold voltage VT of the parasitic diode D0. D0 At this point, V2 = VCC + VT D0 V2-VSS=VCC+VT D0 -VESD. Due to the parasitic diode D0 threshold VT D0 It is much smaller than VESD. Therefore, V2 becomes lower relative to VSS. The ground VSS is raised, and the high threshold VT of the Schmitt trigger X1 is increased. X1 While VSS remains constant, V2 becomes lower than VSS, causing the output V4 of Schmitt trigger X1 to become higher than VSS. V4 = VCC + VESD, V4 - VSS = VCC. Consequently, the output POR of inverter X2 becomes lower than VSS. POR = VESD, POR - VSS = 0, resulting in a false trigger.
[0010] Because of the aforementioned false triggering problem in the existing technology, and because there is no good circuit structure to solve the similar problem in the power-on reset circuit, there is a need to provide a technical solution that can solve the false triggering problem in the existing power-on reset circuit. Summary of the Invention
[0011] To address the technical deficiencies of existing technologies, the present invention aims to provide a power-on reset circuit for preventing ESD false triggering. This circuit controls the normal operation of a power-on reset circuit 9 when an ESD false trigger occurs. The power-on reset circuit 9 is connected to the power supply VDD and the ground VSS. The invention is characterized by further including at least an ESD interference shielding circuit 1, a low-pass filter circuit 2, and a selection circuit 3. The output terminal POR1 of the power-on reset circuit 9 and the output terminal POR2 of the ESD interference shielding circuit 1 serve as input terminals of the selection circuit 3. The output of the selection circuit 3 serves as the output of the power-on reset circuit for preventing ESD false triggering. When an ESD false trigger occurs, the output terminal POR2 of the ESD interference shielding circuit 1 outputs a high level, causing the output of the selection circuit 3 to be higher than the high level of VSS.
[0012] Preferably, when an ESD event causes the ground potential VSS to be raised for a short time, the output terminal POR1 of the power-on reset circuit 9 is at a low level, and correspondingly, the output terminal POR2 of the shielding ESD interference circuit 1 outputs a high level, so that the output of the selection circuit 3 is a high level higher than VSS.
[0013] Preferably, when an ESD event causes the power supply VDD potential to rise in a short time, the output terminal POR1 of the power-on reset circuit 9 is at a low level, and correspondingly, the output terminal POR2 of the shielding ESD interference circuit 1 outputs a high level, so that the output of the selection circuit 3 is higher than the high level of VSS.
[0014] Preferably, the selection circuit is an OR gate circuit X4, which includes at least two input terminals. One of the two input terminals is connected to the output terminal POR1 of the power-on reset circuit 9, and the other is connected to the output terminal POR2 of the shielded ESD interference circuit 1.
[0015] Preferably, the low-pass filter circuit 2 is connected to the power supply VDD and the ground line VSS, and is used to filter the power supply VDD and the ground line VSS.
[0016] Preferably, the ESD interference shielding circuit 1 includes at least a weak pull-down circuit 11, a third PMOS transistor PM3, and a first inverter X3. The output terminal V5 of the weak pull-down circuit 11 is connected to the gate terminal of the third PMOS transistor PM3, the input terminal of the first inverter X3 is connected to the drain terminal V6 of the third PMOS transistor PM3, and the output terminal of the first inverter X3 is the output terminal POR2 of the ESD interference shielding circuit 1.
[0017] Preferably, the shielding ESD interference circuit 1 further includes a first capacitor C3, the upper stage of the first capacitor C3 is connected to the drain terminal V6 of the third PMOS transistor PM3, and the lower stage of the first capacitor C3 is grounded.
[0018] Preferably, the weak pull-down circuit 11 includes at least a second PMOS transistor PM2 and a first NMOS transistor NM1. The gate terminal of the second PMOS transistor PM2 is connected to the drain terminal, and the drain terminal of the second PMOS transistor PM2 is connected to the gate terminal of the first NMOS transistor NM1. The drain terminal of the first NMOS transistor NM1 is the output terminal V5 of the weak pull-down circuit 11.
[0019] Preferably, the weak pull-down circuit 11 includes at least a fifth resistor R5, one end of which is connected to the drain of the first NMOS transistor NM1 and the other end is connected to the ground line VSS.
[0020] According to another aspect of the present invention, a power-on reset circuit control method for preventing ESD false triggering is also provided, for controlling the power-on reset circuit 9 to operate normally when an ESD false triggering occurs, characterized by comprising the following steps:
[0021] Step a. Use the output terminal POR1 of the power-on reset circuit 9 as the first input terminal of the selection circuit 3;
[0022] Step b. When an ESD event occurs, control the second input terminal POR2 of the selection circuit 3 to output a high level, so that the output of the selection circuit 3 is a high level higher than the ground potential VSS connected to the power-on reset circuit 9.
[0023] Preferably, the ground potential VSS is raised for a short time or the power supply potential VDD connected to the power-on reset circuit 9 is raised for a short time during an ESD event.
[0024] Preferably, the selection circuit is an OR gate circuit X4 according to any one of claims 4 to 9, and its second input terminal is connected to the output terminal POR2 of the ESD interference shielding circuit 1 according to any one of claims 4 to 9.
[0025] The power-on reset circuit and corresponding control method for preventing ESD false triggering provided by this invention can prevent both power-on reset false triggering caused by ESD-induced power supply rise and power-on reset false triggering caused by ESD-induced ground rise. Furthermore, it can ensure the normal operation of the power-on reset function during the normal power-on phase. Attached Figure Description
[0026] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0027] Figure 1 A schematic diagram of the circuit structure of a power-on reset circuit in the prior art is shown;
[0028] Figure 2 It shows the relationship with Figure 1 The corresponding signal waveform diagrams for the power-on reset circuit in the existing technology are shown below;
[0029] Figure 3 A schematic diagram of the circuit structure of a power-on reset circuit in the prior art is shown;
[0030] Figure 4 It shows the relationship with Figure 1 The corresponding signal waveforms of the power-on reset circuit in the existing technology are shown in the diagram.
[0031] Figure 5 A schematic diagram of a circuit structure for preventing false triggering of a power-on reset circuit due to ESD is shown according to a first embodiment of the present invention.
[0032] Figure 6 The diagram shows the corresponding signal waveforms of the power-on reset circuit when an ESD event causes the ground potential to be raised in a short time, according to a first embodiment of the present invention.
[0033] Figure 7 The diagram shows the corresponding signal waveforms of the power-on reset circuit when an ESD event causes the power supply VDD potential to be raised in a short time, according to a first embodiment of the present invention.
[0034] Figure 8 A schematic diagram of a circuit structure for a shielded ESD interference circuit in a power-on reset circuit to prevent false triggering due to ESD, according to another preferred embodiment of the present invention, is shown; and
[0035] Figure 9 A flowchart illustrating a control method for preventing false triggering of a power-on reset circuit due to ESD, according to a preferred embodiment of the present invention, is shown. Detailed Implementation
[0036] To better illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings.
[0037] Figures 1 to 4The circuit structure of existing power-on reset circuits and the waveforms in such circuits when a false trigger occurs are summarized. According to an embodiment of the present invention, a power-on reset circuit for preventing false triggering due to ESD is provided, comprising an ESD interference shielding circuit 1, a low-pass filter circuit 2, and a selection circuit 3, thereby enabling a power-on reset circuit to prevent false triggering due to ESD. Specifically, those skilled in the art will understand that the low-pass filter circuit 2 is used to filter the power supply VDD and the ground VSS, and is preferably connected between the power supply VDD and the ground VSS. Further, those skilled in the art will understand that, depending on different implementation needs, the low-pass filter circuit 2 can be implemented with different circuit components, for example in… Figure 5 In the preferred embodiment shown, the low-pass filter circuit 2 is implemented by connecting two resistors and one capacitor C4. These variations are all within the protection scope of this invention.
[0038] Further, preferably, the selection circuit 3 is an OR gate circuit X4, which includes at least two input terminals. One of these input terminals is connected to the output terminal POR1 of the power-on reset circuit 9, and the other is connected to the output terminal POR2 of the ESD interference shielding circuit 1. By configuring the selection circuit 3, the output terminal POR2 of the ESD interference shielding circuit 1 can change according to the false triggering situation, thereby ensuring that the final output POR of the selection circuit 3 is always correct, avoiding errors caused to the power-on reset circuit by ESD false triggering. Furthermore, those skilled in the art will understand that, depending on different implementation needs, the selection circuit 3 can be implemented with different circuit components, and these variations are all within the scope of protection of this invention.
[0039] Furthermore, the ESD interference shielding circuit 1 includes at least a weak pull-down circuit 11, a third PMOS transistor PM3, and a first inverter X3. The output terminal V5 of the weak pull-down circuit 11 is connected to the gate terminal of the third PMOS transistor PM3, the input terminal of the first inverter X3 is connected to the drain terminal V6 of the third PMOS transistor PM3, and the output terminal of the first inverter X3 is the output terminal POR2 of the ESD interference shielding circuit 1. Wherein, in Figure 5 In the preferred embodiment shown, one end of the weak pull-down circuit 11 is connected to the power supply VDD, and the other end is connected to the ground line VSS. Further, in Figure 5In the illustrated embodiment, the weak pull-down circuit 11 includes at least a second PMOS transistor PM2 and a first NMOS transistor NM1. The gate terminal of the second PMOS transistor PM2 is connected to its drain terminal, and the drain terminal of the second PMOS transistor PM2 is connected to the gate terminal of the first NMOS transistor NM1. The drain terminal of the first NMOS transistor NM1 is the output terminal V5 of the weak pull-down circuit 11, and the source terminal of the first NMOS transistor NM1 is grounded to the ground line VSS.
[0040] And in Figure 8 In one variation shown, the weak pull-down circuit 11 includes at least a fifth resistor R5, one end of which is connected to the drain of the first NMOS transistor NM1 and the other end is connected to ground VSS.
[0041] Furthermore, those skilled in the art will understand that, Figure 5 The low-pass filter circuit 2 shown is not drawn in the same circuit structure as the ESD interference shielding circuit 1, but in practical applications, it is included in a larger circuit structure. Figure 5 The low-pass filter circuit 2 and the ESD interference shielding circuit 1 are shown separately for ease of description only, and this does not affect the essence of the invention. Furthermore, those skilled in the art will understand that the voltage filtered by the low-pass filter circuit 2 serves as the power supply VDD4 for the power-on reset circuit, and these variations are all within the scope of protection of this invention.
[0042] Taking it a step further, combining Figures 5 to 8 Those skilled in the art will understand that this involves adding a low-pass filter circuit, an ESD shielding circuit, and a two-input OR gate to the original power-on reset circuit. A low-pass filter circuit consisting of resistors and capacitors is added between the power supply and ground. The outputs VDD4 and VSS4 of the low-pass filter circuit are connected to the power supply and ground of the original power-on reset circuit, respectively. The original power-on reset circuit outputs signal POR1, and the ESD shielding circuit outputs signal POR2. POR1 and POR2 are connected to the two input terminals of the two-input OR gate X4, respectively. The output POR of the two-input OR gate X4 is the output of the entire ESD-resistant power-on reset circuit. The circuit is as follows: Figure 5 As shown.
[0043] The low-pass filter circuit filters the power supply line VDD and the ground line VSS, reducing ESD interference on these lines. Adding a low-pass filter circuit reduces the voltage difference between power supply VDD4 and ground line VSS4 in the original power-on reset circuit caused by ESD, slows down the discharge rate of capacitor C2 in the original power-on reset circuit, and improves the original power-on reset circuit's immunity to ESD interference. Considering the chip area and ESD pulse width, appropriate resistor R4 and capacitor C4 are selected to ensure that the RC time constant of the low-pass filter circuit is >10ns.
[0044] The power and ground wires of the ESD interference shielding circuit are connected to VDD and VSS. The circuit consists of PMOS transistors PM2 and PM3, NMOS transistor NM1, capacitor C3, and inverter X3. PM2 and NM1 form a typical weak pull-down circuit. The gate of PM2 is connected to its drain, forming a diode-like connection, and the drain of PM2 outputs a high level. The drain output of PM2 is connected to the gate of NM1, turning on NM1, and the drain V5 of NM1 outputs a low level. The output V5 of the weak pull-down circuit is connected to the gate of PM3, and the drain V6 of PM3 is connected to the upper plate of capacitor C3. The input of inverter X3 is connected to V6, and its output is connected to POR2.
[0045] When the circuit is operating normally, the gate voltage V5 of PM3 is pulled low, causing PM3 to conduct and pull the upper plate V6 of capacitor C3 high. After passing through inverter X3, the output POR2 is low. Since POR2 is connected to the input of an OR gate, POR2 being low during normal operation does not affect the function of the entire POR circuit.
[0046] During the power-on process, V5 remains at a low level, V6 remains at a high level as the power supply rises, and the output POR2 remains at a low level, which does not affect the normal operation of the entire circuit.
[0047] When an ESD event occurs, causing the ground potential to rise in a short period of time, or even causing the power supply and ground potential to reverse, the output POR1 of the original power-on reset circuit will show a low level relative to VSS, and POR1 will be falsely triggered.
[0048] Each signal waveform is as follows: Figure 6 As shown. The phenomenon occurring in the ESD interference shielding circuit is the same as in the original power-on reset circuit. When a positive ESD signal appears on the ground line VSS, VSS is instantly raised to VESD. Due to the principle of charge conservation, the upper plate V6 of capacitor C3 is also raised to VESD along with VSS. At this time, V6 = VCC + VESD, V6 - VSS = VCC, and V6 remains unchanged relative to VSS. The drain voltage of PM3, V6 = VCC + VESD, and the substrate voltage of PM3 is VCC. Therefore, the parasitic diode D1 from the drain to the substrate of PM3 easily conducts, causing V6 to discharge to the power supply VDD through D1. The V6 voltage begins to drop rapidly to a level higher than the power supply VDD by one parasitic diode D1 threshold voltage VT. D1 At this point, V6 = VCC + VT D1 V6-VSS = VCC+VT D1 -VESD. Due to the parasitic diode D1 threshold VT D1 It is much smaller than VESD. Therefore, V6 is lower relative to VSS. The ground line VSS is raised, and the threshold VT of inverter X3 is lower. X3While the voltage relative to VSS remains unchanged, the voltage of V6 becomes lower relative to VSS, causing the output POR2 of inverter X3 to become higher relative to VSS and maintain this high level during ESD events. Since POR2 is connected to one input of an OR gate, during an ESD event, the output POR1 of the original power-on reset circuit becomes low relative to VSS, while the output POR2 of the ESD shielding circuit becomes high relative to VSS, and the output POR of OR gate X4 becomes high relative to VSS. This shields against the false triggering of the original power-on reset circuit relative to VSS during ESD events, ensuring the entire circuit can function normally during ESD events. ESD events typically last only 100–200 ns; therefore, designing an ESD shielding circuit that generates at least 1 µs of high-level shielding time relative to VSS during an ESD event is sufficient to ensure the circuit effectively shields against ESD interference.
[0049] When an ESD event causes the power supply VDD potential to rise for a short period of time, the waveforms of each signal are as follows: Figure 7 As shown, in the ESD-shielded circuit, a rise in power supply VDD causes the threshold voltage of inverter X3 to increase. The threshold voltage VT of inverter X3... X3 Typically, it is half of the power supply voltage VDD, VT. X3 =VCC / 2, the power supply VDD is raised to become VT X3 = (VCC+VESD) / 2, while the upper plate V6 of capacitor C3 remains unchanged due to the effect of the capacitor, V6=VCC. The ESD voltage is definitely higher than the power supply voltage, VESD>VCC, therefore VCC<(VCC+VESD) / 2. The output POR2 of inverter X3 is high, and the output POR of OR gate X4 is also high, which shields the false triggering caused by the original power-on reset during the ESD occurrence, ensuring that the entire circuit can work normally during the ESD occurrence.
[0050] Refer to the above Figures 5 to 8 Those skilled in the art will understand that the circuit structure provided by the present invention can avoid ESD false triggering to a great extent. For example, the above embodiments have been analyzed in detail. When an ESD event causes the ground potential VSS to be raised in a short time or when an ESD event causes the power supply potential VDD to be raised in a short time, the ESD false triggering event can be effectively avoided, thereby effectively providing a power-on reset circuit to prevent false triggering caused by ESD.
[0051] Figure 9A flowchart illustrating a preferred embodiment of the present invention is shown, illustrating a control method for preventing false triggering of a power-on reset circuit due to ESD. This method controls the false triggering caused by ESD, preventing the power-on reset circuit from being falsely triggered by ESD. Specifically, in step S101, the output terminal (POR1) of the power-on reset circuit (9) is used as the first input terminal of a selection circuit (3). Correspondingly, in step S102, when an ESD event occurs, the second input terminal (POR2) of the selection circuit (3) is controlled to output a high level, making the output of the selection circuit (3) higher than the ground potential VSS connected to the power-on reset circuit (9). Those skilled in the art will understand that, through the above control method, when the ground potential VSS is raised for a short time or the power supply potential VDD connected to the power-on reset circuit (9) is raised for a short time after an ESD event, the above steps can prevent false triggering of ESD.
[0052] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.
Claims
1. A power-on reset circuit for preventing ESD false triggering, used to control the normal operation of a power-on reset circuit (9) when an ESD false triggering occurs, wherein the power-on reset circuit (9) is connected to power supply VDD and ground VSS, and wherein, characterized in that, It also includes at least an ESD interference shielding circuit (1), a low-pass filter circuit (2), and a selection circuit (3), wherein: The output terminal (POR1) of the power-on reset circuit (9) and the output terminal (POR2) of the shielding ESD interference circuit (1) serve as the input terminal of the selection circuit (3), and the output of the selection circuit (3) serves as the output of the power-on reset circuit for preventing ESD false triggering. When an ESD false trigger occurs, the output terminal (POR2) of the shielding ESD interference circuit (1) outputs a high level, so that the output of the selection circuit (3) is higher than the high level of the VSS.
2. The power-on reset circuit for preventing ESD false triggering according to claim 1, characterized in that, When an ESD event occurs, causing the ground potential VSS to be raised for a short period of time, the output terminal (POR1) of the power-on reset circuit (9) is at a low level. Correspondingly, the output terminal (POR2) of the shielding ESD interference circuit (1) outputs a high level, making the output of the selection circuit (3) higher than the high level of VSS.
3. The power-on reset circuit for preventing ESD false triggering according to claim 1, characterized in that, When an ESD event occurs and the power supply VDD potential is raised in a short time, the output terminal (POR1) of the power-on reset circuit (9) is at a low level, and correspondingly, the output terminal (POR2) of the shielding ESD interference circuit (1) outputs a high level, so that the output of the selection circuit (3) is higher than the high level of VSS.
4. The power-on reset circuit for preventing ESD false triggering according to any one of claims 1 to 3, characterized in that, The selection circuit is an OR gate (X4), which includes at least two input terminals. One of the two input terminals is connected to the output terminal (POR1) of the power-on reset circuit (9), and the other is connected to the output terminal (POR2) of the shielded ESD interference circuit (1).
5. The power-on reset circuit for preventing ESD false triggering according to any one of claims 1 to 4, characterized in that, The low-pass filter circuit (2) is connected to the power supply VDD and the ground line VSS, and is used to filter the power supply VDD and the ground line VSS.
6. The power-on reset circuit for preventing ESD false triggering according to any one of claims 1 to 5, characterized in that, The shielded ESD interference circuit (1) comprises at least a weak pull-down circuit (11), a third PMOS transistor (PM3), and a first inverter (X3). The output terminal (V5) of the weak pull-down circuit (11) is connected to the gate terminal of the third PMOS transistor (PM3), the input terminal of the first inverter (X3) is connected to the drain terminal (V6) of the third PMOS transistor (PM3), and the output terminal of the first inverter (X3) is the output terminal (POR2) of the shielded ESD interference circuit (1).
7. The power-on reset circuit for preventing ESD false triggering according to claim 6, characterized in that, The shielding ESD interference circuit (1) further includes a first capacitor (C3), the upper stage of the first capacitor (C3) is connected to the drain terminal (V6) of the third PMOS transistor (PM3), and the lower stage of the first capacitor (C3) is grounded.
8. The power-on reset circuit for preventing ESD false triggering according to any one of claims 1 to 5, characterized in that, The weak pull-down circuit (11) includes at least a second PMOS transistor (PM2) and a first NMOS transistor (NM1). The gate terminal of the second PMOS transistor (PM2) is connected to the drain terminal, and the drain terminal of the second PMOS transistor (PM2) is connected to the gate terminal of the first NMOS transistor (NM1). The drain terminal of the first NMOS transistor (NM1) is the output terminal (V5) of the weak pull-down circuit (11).
9. The power-on reset circuit for preventing ESD false triggering according to any one of claims 1 to 5, characterized in that, The weak pull-down circuit (11) includes at least a fifth resistor (R5), one end of which is connected to the drain of the first NMOS transistor (NM1) and the other end is connected to the ground line VSS.
10. A power-on reset circuit control method for preventing ESD false triggering, used to control the power-on reset circuit (9) to operate normally when ESD false triggering occurs, characterized in that, Includes the following steps: a. Use the output terminal (POR1) of the power-on reset circuit (9) as the first input terminal of a selection circuit (3); b. When an ESD event occurs, control the second input terminal (POR2) of the selection circuit (3) to output a high level, so that the output of the selection circuit (3) is a high level higher than the ground potential VSS connected to the power-on reset circuit (9).
11. The control method according to claim 10, characterized in that, In the event of an ESD event, the ground potential VSS is raised for a short period of time or the power supply potential VDD connected to the power-on reset circuit (9) is raised for a short period of time.
12. The control method according to claim 10 or 11, characterized in that, The selection circuit is an OR gate circuit (X4) according to any one of claims 4 to 9, and its second input terminal is connected to the output terminal (POR2) of the shielded ESD interference circuit (1) according to any one of claims 4 to 9.