A monitoring circuit for resetting the circuit state in the production process of an electric heating table

Abstract

The application discloses a monitoring circuit for resetting the circuit state in the production process of an electric heating table, characterized in that the monitoring circuit comprises a time length monitoring circuit and a response monitoring circuit, the time length monitoring circuit and the response monitoring circuit are connected, the time length monitoring circuit is used for monitoring the reset time length of the reset signal of the product when the product is initially powered on and after power-on interference, the response monitoring circuit is used for feeding back the reset signal and the starting monitoring signal to the time length monitoring circuit, the response monitoring circuit is used for monitoring the response time length of the reset signal of the product when the product is interfered, the circuit can monitor whether the reset signal fed back by the internal reset circuit of the product to the MCU conforms to the specified time length when the product is powered on and after power-on interference, and feed back corresponding warning signals according to the monitoring result, and whether the response time length of the reset signal conforms to the specified response time length when the product is interfered can be monitored.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically a monitoring circuit for the status of a reset circuit during the production process of an electric heating table. Background Technology

[0002] In the existing production process of electric heating tables, monitoring the status of the internal reset circuit is one of the important factors to ensure product safety. To ensure that the product can work normally, functional continuity tests are usually performed on the product, that is, after powering on, button or touch tests are performed on each function. This method can meet the testing needs of most electrical appliances. However, electric heating tables often have special characteristics such as high power, wooden structure, and need to be used by people close to them. Therefore, if the MCU program runs away due to the failure of the reset circuit, the temperature control logic may be interrupted, and the heating element may continue to heat at full power, which may lead to safety accidents such as runaway overheating and fire. Summary of the Invention

[0003] To address the above problems, this invention provides a monitoring circuit for the status of the reset circuit during the production process of an electric heating table. This circuit can monitor whether the reset signal fed back to the MCU by the internal reset circuit meets the specified duration when the product is powered on and after power-on interference, and feed back corresponding alarm signals based on the monitoring results. It can monitor whether the response time of the reset signal meets the specified response time when power-on interference occurs.

[0004] To achieve the above objectives, this invention proposes a monitoring circuit for the reset circuit status during the production process of an electric heating table. The monitoring circuit includes a duration monitoring circuit and a response monitoring circuit, which are connected together. The duration monitoring circuit is used to monitor the reset duration of the reset signal when the product is initially powered on and after power-on interference. The response monitoring circuit is used to feed back the reset signal and the initial monitoring signal to the duration monitoring circuit. The response monitoring circuit is used to monitor the response duration of the reset signal when the product is subjected to interference.

[0005] Furthermore, the duration monitoring circuit includes two duration monitoring units. Each duration monitoring unit includes resistors R1, R2, R3, and R4, transistors Q1, Q2, Q3, and Q4, capacitor C1, AND gate U1, inverter U2, AND gate U3, and port IO1. Port IO1 is connected to one end of resistor R1, the first input terminal of AND gate U1, the collector of transistor Q3, the base of transistor Q1, and one end of resistor R2. The other end of resistor R1 is connected to one end of capacitor C1, the collector of transistor Q2, the emitter of transistor Q1, and the second input terminal of AND gate U1. The base of transistor Q2 is connected to the emitter of transistor Q4 and one end of resistor R3. The output of AND gate U1 is connected to the input of inverter U2 and one end of resistor R4; the other end of resistor R4 is connected to the base of transistor Q4; the first input of AND gate U3 is connected to the output of inverter U2, the second input is connected to the other end of resistor R3 and the emitter of transistor Q3, and the output is connected to the base of transistor Q3; the emitters of transistor Q4, Q2, and Q1, the other end of capacitor C1, and the other end of resistor R2 are grounded; port IO1 is used to acquire the start monitoring signal; the start monitoring signal input to port IO1 of any one duration monitoring unit is fed back by the upper-level module, and the start monitoring signal input to port IO1 of the other duration monitoring unit is fed back by the response monitoring module.

[0006] Furthermore, the response monitoring circuit includes diodes D1, D2, D3, D4, D5, and D6; resistors R5, R6, R7, R8, R9, and R10; capacitors C2 and C3; transistor Q5; AND gate U4; XOR gate U5; operational amplifiers U6, U8, and U9; and port IO2. The anodes of diodes D2 and D3, the cathode of diode D1, the base of transistor Q7, one end of resistor R8, the second input of AND gate U7, one end of resistor R10, and the output of XOR gate U5 are connected to the duration monitoring module. The anode of diode D1 is connected to one end of resistor R9, one end of resistor R7, port IO2, and the first input of AND gate U7. The output of AND gate U7 is connected to the other end of resistor R8. The first input of AND gate U4 is connected to the cathode of diode D2 and the cathode of diode D6. 3. The cathode and second input terminal are connected to the other end of resistor R9 and the collector of transistor Q6. The output terminal is connected to one end of resistor R5, the base of transistor Q5, one end of resistor R6, the anode of diode D5, and the second input terminal of XOR gate U5. The non-inverting input of operational amplifier U6 is connected to the other end of resistor R5, one end of capacitor C2, and the emitter of transistor Q5. The inverting input is connected to the cathode of diode D4, the emitter of transistor Q7, one end of capacitor C3, the non-inverting input of operational amplifier U8, the non-inverting input of operational amplifier U9, and the output terminal is connected to the anode of diode D4. The base of transistor Q6 is connected to the other end of resistor R10. The first input terminal of XOR gate U5 is connected to the cathodes of diode D6 and D5. The output terminal of operational amplifier U8 is connected to the anode of diode D6. The emitter of transistor Q6, the other end of capacitor C2, the collector of transistor Q5, the collector of transistor Q7, the other end of capacitor C3, the other end of resistor R6, and the other end of resistor R7 are grounded.

[0007] Furthermore, the resistor R1 is an adjustable resistor; the capacitor C1 is an adjustable capacitor.

[0008] Furthermore, the resistor R5 is an adjustable resistor; the capacitor C2 is an adjustable capacitor.

[0009] Furthermore, the capacitor C3 is an adjustable capacitor. Attached Figure Description

[0010] Figure 1 A schematic diagram of the overall structure of the monitoring circuit for the reset circuit status is provided for this application.

[0011] Figure 2 A schematic diagram of the circuit connection of the duration monitoring unit provided in this application.

[0012] Figure 3 A schematic diagram of the response monitoring circuit structure provided in this application. Detailed Implementation

[0013] To enable those skilled in the art to better understand the technical solution, the present invention will be described in detail below with reference to embodiments. The description in this part is only exemplary and explanatory, and should not be used to limit the scope of protection of the present invention in any way.

[0014] See Figure 2 , Figure 3 The duration monitoring circuit includes two duration monitoring units, used to monitor the reset duration of the product's reset signal during initial power-on and after power-on interference. The initial monitoring signal input to port IO1 of one duration monitoring unit is fed back from the upper-level module, while the initial monitoring signal input to port IO1 of the other duration monitoring unit is fed back from the response monitoring module. The upper-level module powers the product on and off and, based on the feedback from the response monitoring circuit, applies interference to the product after power-on and reset. When the product powers on, the upper-level module continuously inputs an initial monitoring signal (high level) to port IO1 of either duration monitoring unit. When port IO1 receives a high-level signal, the signal rises through resistor R1, causing the voltage at capacitor C1 to increase. The signal at capacitor C1 is then fed back to the second input of AND gate U1. The input terminal is connected to the collector of transistor Q2 and the emitter of transistor Q1. Resistor R1 is the current-limiting resistor for capacitor C1. The signal from port IO1 is fed back to the first input terminal of AND gate U1, the base of transistor Q1, and the collector of transistor Q3. Referring to the driving voltage of AND gate U1 and the specified duration of the reset signal of the internal MCU of the product during initial power-up, the time it takes for the voltage at the end of capacitor C1 to rise from zero to the driving voltage of AND gate U1 can be set by adjusting the resistance value of resistor R1 and the capacitance value of capacitor C1. The specified duration of the reset signal during power-up can be set. The port IO2 in the response monitoring circuit synchronously obtains the reset signal fed back to the MCU by the internal reset circuit of the product. When the reset signal is low, the MCU is in the reset state; when the signal is high, the MCU is in the reset completed state.

[0015] See Figure 2When the current duration monitoring unit port IO1 receives a high-level signal and the internal reset circuit of the product responds to the MCU reset signal for the specified duration (i.e., the low-level duration of the reset signal exceeds the specified duration), AND gate U1 outputs a high-level signal before port IO2 receives a high-level signal. The signal output from AND gate U1 passes through resistor R4, the base of transistor Q4, and the emitter of transistor Q4 to ground, turning on transistor Q4. When the MCU is in the reset complete state, the signal at port IO2 passes through diode D1, resistor R3, the collector of transistor Q4, and the emitter of transistor Q4. With the emitter grounded, AND gate U1 maintains its output. The potential at the capacitor C1 terminal will rise and remain at the potential at port IO1. The high-level signal at the output of AND gate U1 is an alarm signal indicating that the product's reset signal meets the specified duration when it is powered on. When port IO1 of the duration monitoring unit receives a high-level signal and the reset signal fed back by the MCU from the product's internal reset circuit does not meet the specified duration (i.e., the low-level duration of the reset signal is less than the specified duration), port IO2 receives a high-level signal before AND gate U1 outputs a high-level signal. The signal at port IO2 passes through diode D1 and... Resistor R3, the base of transistor Q2, and the emitter of transistor Q2 are grounded, turning on transistor Q2. The signal at the terminal of capacitor C1 passes through the emitter and collector of transistor Q2 to ground, pulling the potential at the terminal of capacitor C1 to ground. Simultaneously, the signal at port IO2 is input to the second input terminal of AND gate U3 through diode D1. Inverter U2 inverts the output signal of AND gate U1, and the high-level output of inverter U2 is input to the first input terminal of AND gate U3, causing AND gate U3 to output a high level. The signal at the output terminal of AND gate U3 passes through the base and emitter of transistor Q3, turning on transistor Q3. Port IO2... The signal from O1 passes through the collector and emitter of transistor Q3, resistor R3, base and emitter of transistor Q2, and then to ground. When the MCU is in a reset state, port IO2 is at a low level, AND gate U3 maintains its output, and the potential of capacitor C1 remains at ground. The high-level signal at the output of AND gate U3 is an alarm signal indicating that the reset signal has not met the specified duration when the product is powered on. This allows the system to monitor whether the reset signal fed back by the MCU from the internal reset circuit meets the specified duration when the product is powered on, and to feed back the corresponding alarm signal based on the monitoring results.

[0016] See Figure 3The current duration monitoring unit's AND gate U1 output signal is fed back to the first input of AND gate U4 via diode D2, and the AND gate U3 output signal is fed back to the first input of AND gate U4 via diode D3. When the product is powered on and reset is complete, the signal at port IO2 is fed back to the second input of AND gate U4 via resistor R9, and AND gate U4 outputs a high level. The AND gate U4 output signal, after passing through resistor R5, causes the potential at capacitor C2 to rise. The upper-level module synchronously obtains the AND gate U4 output signal. When the upper-level module obtains the high-level signal at the AND gate U4 output, it applies interference to the product. The AND gate U4 output signal is fed back to the base of transistor Q5, causing transistor Q5 to always be in the cutoff state when the AND gate U4 output is high. The signal at capacitor C2... The signal is fed back to the non-inverting input of op-amp U6. The output signal of op-amp U6 is fed back to the inverting input of op-amp U6 and the emitter of transistor Q7 via diode D4. The signal at port IO1 is fed back to the base of transistor Q7, ensuring that transistor Q7 remains in the off state when the start monitoring signal is input to port IO1. The offset signal is input to the inverting input of op-amp U8, and the offset signal is fed back from the adjustable power supply. The amplitude of the offset signal is slightly higher than ground potential. The signal at capacitor C3 is fed back to the non-inverting input of op-amp U8. The signal at capacitor C3 is the response time signal. When the upper-level module applies interference to the product, the high-level signal output of AND gate U4 is fed back to the first input of XOR gate U5 via diode D5, and the other path is fed back to the second input of XOR gate U5. The two inputs of XOR gate U5... When the input is high, XOR gate U5 is cut off, and the potential at capacitor C2 rises simultaneously. The potential at capacitor C3 also rises synchronously. When the potential at capacitor C3 is higher than the offset signal, operational amplifier U8 outputs. The output signal of operational amplifier U8 is fed back to the first input of XOR gate U5 via diode D6. When the internal reset circuit puts the MCU in a reset hold state, AND gate U4 is cut off, and XOR gate U5 outputs a high level. The output signal of XOR gate U5 passes through resistor R10, the base of transistor Q6, and the emitter of transistor Q6 to ground, turning on transistor Q6. The signal at port IO2 passes through resistor R9, the collector of transistor Q6, and the emitter of transistor Q6 to ground. AND gate U4 remains cut off, and XOR gate U5 maintains its output. The signal at capacitor C2 passes through transistor Q... 5. The emitter, base of transistor Q5, and resistor R6 are grounded. The potential of capacitor C2 is pulled low to ground. Simultaneously, diode D4 is used for reverse protection. The potential of capacitor C2 is maintained at the terminal of capacitor C3 before AND gate U4 is turned off. The signal at the terminal of capacitor C3 is fed back to the non-inverting input of op-amp U9. The inverting input of op-amp U9 receives a reference signal with a specified response time. The reference signal with the specified response time is fed back by an adjustable power supply. When the product is disturbed and its internal reset circuit fails to feed back a reset signal to the MCU within the specified response time, op-amp U9 outputs; otherwise, it is turned off. In this way, after monitoring the specified duration of the reset signal during the product's power-on process, the upper-level module applies interference to the product and monitors whether its reset circuit feeds back a reset signal to the MCU within the specified response time.

[0017] See Figure 1 , Figure 3 When the XOR gate U5 of the response monitoring circuit outputs, it feeds back the start monitoring signal to port IO1 of another duration monitoring unit. The second input of AND gate U7 synchronously receives the signal from the output of XOR gate U5, and the first input of AND gate U7 synchronously receives the signal from port IO2. When the second input of AND gate U7 is high, its output level follows the level of port IO2. The output signal of AND gate U7 is fed back to the second input of AND gate U3 of this duration monitoring unit via resistor R8. After the response duration monitoring is completed, the potential at the capacitor C1 of this monitoring unit begins to rise. By adjusting the resistance value of resistor R1 and the capacitance value of capacitor C1 in the duration monitoring unit, the time it takes for the voltage at the capacitor C1 terminal to rise from zero to the driving voltage of AND gate U1 can be set. This allows setting the specified duration of the reset signal after power-on interference. The high-level signals at the output terminals of AND gate U1 and AND gate U3 of the duration monitoring unit are alarm signals indicating whether the reset signal meets or does not meet the specified duration after the product is subjected to power-on interference. After monitoring is completed, the upper-level module will power off the product. After power-off, disconnecting the feedback of the initial monitoring signal of the duration monitoring unit will reset the circuit.

[0018] It should be noted that, in this document, the terms "comprising," "including," and any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Specific examples have been used in this document to illustrate the principles and implementation methods of the present invention. These examples are merely for the purpose of helping to understand the method and core ideas of the present invention. The above descriptions are only preferred embodiments of the present invention. It should be pointed out that, due to the limitations of written expression and the objective existence of infinite specific structures, those skilled in the art can make several improvements, modifications, or variations without departing from the principles of the present invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, variations, or combinations, or the direct application of the concept and technical solution of the present invention to other situations without modification, should all be considered within the scope of protection of the present invention.

Claims

1. A monitoring circuit for the reset circuit status during the production process of an electric heating table, characterized in that, The monitoring circuit includes a duration monitoring circuit and a response monitoring circuit, which are connected together. The duration monitoring circuit is used to monitor the reset duration of the reset signal when the product is initially powered on and after power-on interference. The response monitoring circuit is used to feed back the reset signal and the start monitoring signal to the duration monitoring circuit. The response monitoring circuit is used to monitor the response duration of the reset signal when the product is interfered with.

2. The monitoring circuit for the reset circuit status during the production process of an electric heating table according to claim 1, characterized in that, The duration monitoring circuit includes two duration monitoring units. Each duration monitoring unit includes resistors R1, R2, R3, and R4; transistors Q1, Q2, Q3, and Q4; capacitor C1; AND gate U1; inverter U2; AND gate U3; and port IO1. Port IO1 is connected to one end of resistor R1, the first input of AND gate U1, the collector of transistor Q3, the base of transistor Q1, and one end of resistor R2. The other end of resistor R1 is connected to one end of capacitor C1, the collector of transistor Q2, the emitter of transistor Q1, and the second input of AND gate U1. The base of transistor Q2 is connected to the emitter of transistor Q4 and one end of resistor R3. The AND gate... The output of U1 is connected to the input of inverter U2 and one end of resistor R4; the other end of resistor R4 is connected to the base of transistor Q4; the first input of AND gate U3 is connected to the output of inverter U2, the second input is connected to the other end of resistor R3 and the emitter of transistor Q3, and the output is connected to the base of transistor Q3; the emitters of transistor Q4, Q2, and Q1, the other end of capacitor C1, and the other end of resistor R2 are grounded; port IO1 is used to acquire the start monitoring signal; the start monitoring signal input to port IO1 of any one duration monitoring unit is fed back by the upper-level module, and the start monitoring signal input to port IO1 of the other duration monitoring unit is fed back by the response monitoring module.

3. The monitoring circuit for the reset circuit status during the production process of an electric heating table according to claim 1, characterized in that, The response monitoring circuit includes diodes D1, D2, D3, D4, D5, and D6; resistors R5, R6, R7, R8, R9, and R10; capacitors C2 and C3; transistor Q5; AND gate U4; XOR gate U5; operational amplifiers U6, U8, and U9; and port IO2. The anodes of diodes D2 and D3, the cathode of diode D1, the base of transistor Q7, one end of resistor R8, the second input of AND gate U7, one end of resistor R10, and the output of XOR gate U5 are connected to the duration monitoring module. The anode of diode D1 is connected to one end of resistor R9, one end of resistor R7, port IO2, and the first input of AND gate U7. The output of AND gate U7 is connected to the other end of resistor R8. The first input of AND gate U4 is connected to the cathodes of diodes D2 and D3. The second input terminal is connected to the other end of resistor R9 and the collector of transistor Q6. The output terminal is connected to one end of resistor R5, the base of transistor Q5, one end of resistor R6, the anode of diode D5, and the second input terminal of XOR gate U5. The non-inverting input of operational amplifier U6 is connected to the other end of resistor R5, one end of capacitor C2, and the emitter of transistor Q5. The inverting input is connected to the cathode of diode D4, the emitter of transistor Q7, one end of capacitor C3, the non-inverting input of operational amplifier U8, the non-inverting input of operational amplifier U9, and the output terminal is connected to the anode of diode D4. The base of transistor Q6 is connected to the other end of resistor R10. The first input terminal of XOR gate U5 is connected to the cathodes of diode D6 and D5. The output terminal of operational amplifier U8 is connected to the anode of diode D6. The emitter of transistor Q6, the other end of capacitor C2, the collector of transistor Q5, the collector of transistor Q7, the other end of capacitor C3, the other end of resistor R6, and the other end of resistor R7 are grounded.

4. The monitoring circuit for the reset circuit status during the production process of an electric heating table according to claim 2, characterized in that, The resistor R1 is an adjustable resistor; the capacitor C1 is an adjustable capacitor.

5. The monitoring circuit for the reset circuit status during the production process of an electric heating table according to claim 3, characterized in that, The resistor R5 is an adjustable resistor; the capacitor C2 is an adjustable capacitor.

6. The monitoring circuit for the reset circuit status during the production process of an electric heating table according to claim 3, characterized in that, The capacitor C3 is an adjustable capacitor.

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