Multi-channel ttl signal synchronous output system and method

Abstract

The application provides a multi-channel TTL signal synchronous output system and method, and relates to the technical field of signal processing.In the application, a field programmable logic gate array is configured to generate an original synchronous signal when receiving a synchronous signal generation command, to perform synchronous processing on the original synchronous signal based on a reference clock signal to generate a plurality of target synchronous signals, and to perform synchronous output on the plurality of target synchronous signals; and each TTL level conversion chip is configured to receive a target synchronous signal synchronously output by a connected synchronous signal output port, and to output a target TTL signal through a corresponding synchronous signal conversion output port after performing level conversion on the target synchronous signal.Based on the above, the problem of relatively low synchronization accuracy of the multi-channel TTL signal in the prior art can be solved.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and more specifically, to a multi-channel TTL signal synchronous output system and method. Background Technology

[0002] In modern electronic systems, it is often necessary to synchronize multiple signals to ensure coordinated operation between components. However, due to factors such as physical circuit delays and differences in device response times, traditional TTL signal synchronization schemes often fail to meet the required accuracy. Therefore, developing a control system and method capable of achieving high-precision synchronization of multiple TTL signals is particularly important. Specifically, in traditional TTL signal high-precision synchronization control systems, the phase difference between the clock signals of different channels makes it difficult to meet high-precision synchronization requirements when multiple channels are outputting. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a multi-channel TTL signal synchronous output system and method to improve the problem of relatively low synchronization accuracy of multi-channel TTL signals in the prior art.

[0004] To achieve the above objectives, this application adopts the following technical solution: A multi-channel TTL signal synchronous output system, comprising: A field-programmable gate array (FPGA) includes a host control command input port, a clock signal input port, and multiple synchronization signal output ports. The FPGA is configured to generate an initial synchronization signal when a synchronization signal generation command is received through the host control command input port, and to perform synchronization processing on the initial synchronization signal based on a reference clock signal received through the clock signal input port to generate multiple target synchronization signals. The FPGA is also configured to synchronously output the multiple target synchronization signals through the multiple synchronization signal output ports. At least one TTL level conversion chip, wherein each TTL level conversion chip includes at least one synchronization signal input port and at least one synchronization signal conversion output port, and the at least one TTL level conversion chip includes multiple synchronization signal input ports and multiple synchronization signal conversion output ports, wherein the synchronization signal input ports are connected to the synchronization signal output ports, and each TTL level conversion chip is configured to receive a target synchronization signal synchronously output by the connected synchronization signal output port, and after level conversion of the target synchronization signal, output a target TTL signal through a corresponding synchronization signal conversion output port.

[0005] In a preferred embodiment of this application, in the aforementioned multi-channel TTL signal synchronous output system, there are multiple TTL level conversion chips, and each pair of TTL level conversion chips has the same circuit configuration.

[0006] In a preferred embodiment of this application, in the aforementioned multi-channel TTL signal synchronous output system, the length difference of the input line of the target synchronization signal between any two TTL level conversion chips is less than a predetermined first length threshold, and the length difference of the output line of the target TTL signal between any two TTL level conversion chips is less than a predetermined second length threshold.

[0007] In a preferred embodiment of this application, the multi-channel TTL signal synchronous output system further includes: A clock signal generation circuit, wherein the clock signal output port of the clock signal generation circuit is connected to the clock signal input port, and the clock signal generation circuit is configured to generate the reference clock signal and output the reference clock signal to the field programmable gate array through the clock signal output port and the clock signal input port.

[0008] In a preferred embodiment of this application, in the aforementioned multi-channel TTL signal synchronous output system, the clock signal generation circuit includes: A crystal oscillator device, wherein the crystal oscillator device includes a crystal signal output port, and the crystal oscillator device is configured to generate a crystal signal by performing a temperature-controlled crystal oscillation, and output the crystal signal through the crystal signal output port; A signal processing component, wherein the signal processing component includes a crystal oscillator signal input port and a clock signal output port, and the signal processing component is configured to perform signal processing on the crystal oscillator signal received through the crystal oscillator signal input port to generate a reference clock signal.

[0009] In a preferred embodiment of this application, in the aforementioned multi-channel TTL signal synchronous output system, the signal processing component includes: A frequency multiplier device, wherein the frequency multiplier device includes a crystal oscillator signal input port and a frequency multiplier signal output port, and the frequency multiplier device is configured to perform frequency multiplication processing on the crystal oscillator signal received through the crystal oscillator signal input port, and output the formed frequency multiplier signal through the frequency multiplier signal output port, the frequency multiplier signal serving as the basis for generating the reference clock signal.

[0010] In a preferred embodiment of this application, in the aforementioned multi-channel TTL signal synchronous output system, the signal processing component further includes: A filtering device, comprising a filtering input port and a filtering output port, wherein the filtering input port is connected to the frequency multiplication signal output port, and the filtering device is configured to, after receiving the frequency multiplication signal output from the frequency multiplication signal output port through the filtering input port, perform filtering processing to suppress high-frequency harmonic components in the frequency multiplication signal, forming a filtered signal, and outputting it through the filtering output port, wherein the filtered signal serves as the basis for generating the reference clock signal.

[0011] In a preferred embodiment of this application, in the aforementioned multi-channel TTL signal synchronous output system, the signal processing component further includes: An amplifying device, wherein the amplifying device includes an amplification input port and a clock signal output port, the amplification input port is connected to the filter output port, and the amplifying device is configured to, after receiving the filtered signal output from the filter output port through the amplification input port, amplify and shape the filtered signal to obtain a square wave signal whose amplitude meets a set condition, and output it as the reference clock signal.

[0012] Based on the above, this application also provides a method for synchronous output of multiple TTL signals, applied to the aforementioned system for synchronous output of multiple TTL signals. The system includes a field-programmable gate array (FPGA) and at least one TTL level conversion chip. The method for synchronous output of multiple TTL signals includes: When the field-programmable gate array receives a synchronization signal generation command through the upper-level control command input port, it generates an original synchronization signal. The field-programmable gate array (FPGA) performs synchronization processing on the original synchronization signal based on the reference clock signal received through the clock signal input port, generates multiple target synchronization signals, and outputs the multiple target synchronization signals synchronously through multiple synchronization signal output ports. After receiving a target synchronization signal synchronously output from the connected synchronization signal output port, each TTL level conversion chip performs level conversion on the target synchronization signal and outputs the formed target TTL signal through a corresponding synchronization signal conversion output port.

[0013] In a preferred embodiment of this application, the multi-channel TTL signal synchronous output method further includes a crystal oscillator, a frequency multiplier, and an amplifying device. The multi-channel TTL signal synchronous output method also includes: The crystal oscillator device performs isothermal crystal oscillation to generate a crystal oscillator signal, and outputs the crystal oscillator signal through the crystal oscillator signal output port; After receiving the crystal oscillator signal output from the crystal oscillator signal output port through the crystal oscillator signal input port, the frequency multiplier device performs frequency multiplication processing to form a frequency multiplier signal, and outputs it through the frequency multiplier signal output port; After receiving the frequency multiplier signal output from the frequency multiplier signal output port through the filter input port, the filter device performs filtering processing to suppress the high-frequency harmonic components in the frequency multiplier signal, forming a filtered signal, and outputs it through the filter output port. After receiving the filtered signal from the filtered output port through the amplification input port, the amplification device amplifies and shapes the filtered signal to form a square wave signal with an amplitude that meets the set conditions, and outputs it to the field programmable gate array as a reference clock signal.

[0014] In the multi-channel TTL signal synchronous output system and method provided in this application, a field-programmable gate array (FPGA) is configured to generate an original synchronization signal upon receiving a synchronization signal generation command, perform synchronization processing on the original synchronization signal based on a reference clock signal to generate multiple target synchronization signals, and synchronously output the multiple target synchronization signals. Each TTL level conversion chip is configured to receive a target synchronization signal synchronously output from a connected synchronization signal output port, and after level conversion of the target synchronization signal, output the target TTL signal through the corresponding synchronization signal conversion output port. Based on the above, since the generation of multiple target synchronization signals is based on a reference clock signal and an original synchronization signal, it can, to a certain extent, improve the problem that traditional high-precision synchronization control systems for TTL signals suffer from insufficient synchronization accuracy due to phase differences between clock signals of different channels when outputting multiple channels. Attached Figure Description

[0015] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings.

[0016] Figure 1 This is a schematic diagram of the architecture of a multi-channel TTL signal synchronous output system provided in an embodiment of this application.

[0017] Figure 2 This is a functional schematic diagram of a multi-channel TTL signal synchronous output system provided in an embodiment of this application.

[0018] Figure 3 This is a schematic diagram of the function of the D flip-flop provided in the embodiments of this application.

[0019] Figure 4 This is a schematic diagram illustrating the timing synchronization principle provided in an embodiment of this application.

[0020] Figure 5 The timing diagram for generating the 6-channel synchronization signal provided in the embodiments of this application is shown.

[0021] Figure 6 This is a schematic diagram of a method for synchronous output of multiple TTL signals provided in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] like Figure 1 As shown in the figure, this application provides a multi-channel TTL signal synchronous output system. The multi-channel TTL signal synchronous output system may include a field-programmable gate array (FPGA) and at least one TTL level conversion chip.

[0025] In detail, the field-programmable gate array includes a host control command input port, a clock signal input port, and multiple synchronization signal output ports. Each TTL level converter chip includes at least one synchronization signal input port and at least one synchronization signal conversion output port. The at least one TTL level converter chip includes multiple synchronization signal input ports and multiple synchronization signal conversion output ports, and the synchronization signal input ports are connected to the synchronization signal output ports. For example, the multiple synchronization signal output ports and the multiple synchronization signal input ports are connected in a one-to-one correspondence, and the multiple synchronization signal input ports and the multiple synchronization signal conversion output ports also have a one-to-one correspondence, thus forming multiple signal channels.

[0026] Furthermore, the field-programmable gate array is configured to generate an initial synchronization signal upon receiving a synchronization signal generation command (issued by the host computer) through the host control command input port, and to perform synchronization processing on the initial synchronization signal based on a reference clock signal received through the clock signal input port to generate multiple target synchronization signals, and to synchronously output the multiple target synchronization signals through the multiple synchronization signal output ports. Additionally, each TTL level conversion chip is configured to receive a target synchronization signal synchronously output from the connected synchronization signal output port, and after level conversion of the target synchronization signal, output a target TTL signal through a corresponding synchronization signal conversion output port.

[0027] Based on the above, since the generation of multiple target synchronization signals is based on a reference clock signal and an original synchronization signal, it can improve to some extent the problem that the synchronization accuracy of traditional TTL signal high-precision synchronization control systems is difficult to meet the high-precision requirements when there is a phase difference between the clock signals of each channel when there is multi-channel output.

[0028] It is understood that the specific number of TTL level conversion chips is not limited and can be selected and configured according to actual needs, as long as multiple synchronization signal input ports and multiple synchronization signal conversion output ports are provided, enabling level conversion of multiple target synchronization signals to form multiple target TTL signals. For example... Figure 1 As shown, there can be two TTL level conversion chips (such as the AiPTS0103 level conversion chip). Each TTL level conversion chip has three synchronization signal input ports and three synchronization signal conversion output ports, thus enabling the synchronous output of six target TTL signals. Furthermore, it should be noted that while a field-programmable gate array (FPGA) can generate six target synchronization signals from one original synchronization signal (exemplarily, this can be implemented using Verilog programming), since the high level output of the FPGA is 1.8V or 3.3V, two TTL level conversion chips are needed to achieve a 5V high-level output.

[0029] Furthermore, it should be noted that, in order to further improve the accuracy of signal synchronization, in an alternative implementation, every two TTL level conversion chips among the plurality of TTL level conversion chips have the same circuit configuration, thereby further reducing the synchronization error caused by circuit differences between TTL level conversion chips.

[0030] Furthermore, it should be further explained that, in order to further improve the accuracy of signal synchronization, in an alternative implementation, the length difference of the input line of the target synchronization signal between any two TTL level conversion chips in the plurality of TTL level conversion chips is less than a predetermined first length threshold, and the length difference of the output line of the target TTL signal between any two TTL level conversion chips in the plurality of TTL level conversion chips is less than a predetermined second length threshold. It is understood that the specific values ​​of the first and second length thresholds are not limited; for example, in an alternative implementation, both the first and second length thresholds can be 5 mm. Alternatively, the total length difference between the input and output lines can be less than 5 mm. Thus, during the input and output process, the delay error can be: Δt = 0.005 / (0.3×0.85) = 0.0196ns ≈ 0.02ns, where the speed of light = 0.3 m / nanosecond and the propagation efficiency is 0.85.

[0031] Understandably, in order to provide a reliable reference clock signal to the field-programmable gate array, in an alternative implementation, the multi-channel TTL signal synchronization output system may further include a clock signal generation circuit.

[0032] Specifically, the clock signal generation circuit may include a clock signal output port, and the clock signal output port is connected to the clock signal input port. The clock signal generation circuit is configured to generate the reference clock signal and output the reference clock signal to the field-programmable gate array (FPGA) through the clock signal output port and the clock signal input port, enabling the FPGA to acquire the reference clock signal.

[0033] It is understood that the specific configuration of the clock signal generation circuit is not limited and can be configured according to actual needs. For example, in an alternative implementation, it can be combined with... Figure 2 The clock signal generation circuit may further include a crystal oscillator and a signal processing component.

[0034] Specifically, the crystal oscillator includes a crystal signal output port, and is configured to generate a crystal signal by performing a temperature-controlled crystal oscillation (e.g., 100MHz), and output the crystal signal through the crystal signal output port. The signal processing component includes a crystal signal input port and a clock signal output port, and is configured to process the crystal signal received through the crystal signal input port to generate a reference clock signal, and output the reference clock signal through the clock signal output port. The specific signal processing method can be configured according to actual needs, as long as it meets the requirements of the field-programmable gate array for the reference clock signal.

[0035] It is understood that the specific configuration of the signal processing component is not limited and can be configured according to actual needs; that is, the configuration of the signal processing component can differ depending on the signal processing requirements. For example, in an alternative embodiment, the signal processing component may further include a frequency multiplier.

[0036] In detail, the frequency multiplier includes a crystal oscillator signal input port and a frequency multiplier signal output port. The frequency multiplier is configured to multiply the crystal oscillator signal received through the crystal oscillator signal input port and output the resulting multiplied signal through the frequency multiplier signal output port. This multiplied signal serves as the basis for generating the reference clock signal. For example, the crystal oscillator signal output by the crystal oscillator can be 100MHz, which, after being multiplied by two by the frequency multiplier, becomes a 200MHz sine wave signal, which is then used as the multiplied signal.

[0037] It is understood that, in an alternative implementation, the signal processing component may further include filtering devices.

[0038] In detail, the filtering device includes a filtering input port and a filtering output port. The filtering input port is connected to the frequency multiplication signal output port. The filtering device is configured to perform filtering processing on the frequency multiplication signal after receiving it through the filtering input port to suppress high-frequency harmonic components in the frequency multiplication signal (which can improve the spectral purity of the clock signal), forming a filtered signal, which is then output through the filtering output port. This filtered signal serves as the basis for generating the reference clock signal.

[0039] It is understood that, in an alternative implementation, the signal processing component may further include an amplification device.

[0040] Specifically, the amplifying device includes an amplification input port and a clock signal output port. The amplification input port is connected to the filtering output port, and the amplifying device is configured to, after receiving the filtered signal output from the filtering output port through the amplification input port, amplify and shape the filtered signal to obtain a square wave signal with an amplitude that meets a set condition (i.e., obtain a square wave signal with a high amplitude), and output it as the reference clock signal. Based on this, in an alternative embodiment, when the field-programmable gate array receives a synchronization signal generation command from the host computer, under the timing constraint of a 200MHz reference clock signal, it synchronously outputs six high-precision target synchronization signals, thereby forming six high-precision TTL synchronization signals.

[0041] Furthermore, it needs to be clarified that in the design of the aforementioned high-precision synchronous control system with 6 TTL synchronous signals, the 200MHz signal serves as the reference clock signal for the entire system, provided to the FPGA as a single timing input source, and has no synchronization timing requirements. The key to generating the 6 synchronous signals lies in the logic design within the FPGA (Field-Programmable Gate Array). After receiving the synchronization signal generation command from the host computer, the FPGA first generates the required synchronization signal, using the 200MHz input signal as the internal clock reference signal of the FPGA, and as a trigger signal similar to a D flip-flop. When the trigger edge arrives, it directly generates 6 synchronous output signals based on one synchronous input signal. The functional block diagram of the D flip-flop is shown below. Figure 3 As shown. It should be further explained that using a 200MHz clock signal as the trigger synchronization clock signal ensures that the timing of the six synchronous output signals is simultaneous. The timing synchronization principle is as follows: Figure 4 As shown, the input synchronization signal refers to the original synchronization signal mentioned above, and the output synchronization signal refers to the target synchronization signal mentioned above.

[0042] In addition, a 200MHz clock signal is used as the "switch" control for the six synchronization signal outputs to ensure that the output timing of the six synchronization signals is completely consistent. Simulation results obtained using Vivado simulation software are as follows: Figure 5As shown. Analyzing the simulation results, the timing of the six synchronous output signals, using the rising edge as the standard, is compared. Theoretically, the timing difference of the six synchronous signals is close to 0 ns. Considering the 10%–90% uncertainty of the rising edge, the estimated timing error is approximately 5 ns × 10% × 2 = 1 ns. The six synchronous signals output from the FPGA enter two TTL voltage conversion chips, generating six synchronous TTL signals, which are provided to various units of the system. Since 200MHz is used as the clock source, there is also a 1 ns delay error. As mentioned earlier, in the circuit design, it is necessary to ensure that the circuit design of the two TTL voltage conversion chips is completely consistent, ensuring that the circuit design of the two TTL voltage conversion chips is completely symmetrical, and the theoretical requirement for the trace length of each input signal and output signal is equal. Considering that actual circuit designs cannot achieve exactly the same length, the expected length error between actual signal traces is about 5mm. Therefore, the calculated delay error is Δt = 0.005 / (0.3×0.85)=0.0196ns≈0.02ns.

[0043] In addition, the time delay error between the three paths of the TTL voltage conversion chip also needs to be considered. According to the component specifications, the time delay error between the three paths of the voltage conversion chip is 1ns.

[0044] Based on this, six synchronous signals are generated simultaneously, and the design and implementation are shown in the table below.

[0045]

[0046] Therefore, the time delay error between the 6 synchronization signals is: 1 + 1 + 0.02 + 1 = 3.02 ns < 5 ns.

[0047] Combination Figure 6 This application also provides a method for synchronously outputting multiple TTL signals, applicable to the aforementioned multi-channel TTL signal synchronous output system. The method steps defined in the relevant process of the multi-channel TTL signal synchronous output method can be implemented by the multi-channel TTL signal synchronous output system. The following will describe... Figure 6 The specific process shown will be explained in detail.

[0048] In step S110, when the field-programmable gate array receives a synchronization signal generation command through the upper-level control command input port, it generates an original synchronization signal.

[0049] In this embodiment, the field-programmable gate array (FPGA) generates an initial synchronization signal upon receiving a synchronization signal generation command through the host computer's control command input port. In other words, after receiving the synchronization signal generation command from the host computer, an initial synchronization signal can be generated first.

[0050] In step S120, the field-programmable gate array performs synchronization processing on the original synchronization signal based on the reference clock signal received through the clock signal input port to generate multiple target synchronization signals, and outputs the multiple target synchronization signals synchronously through multiple synchronization signal output ports.

[0051] In this embodiment, after the original synchronization signal is generated, the field-programmable gate array (FPGA) can perform synchronization processing on the original synchronization signal based on a reference clock signal received through the clock signal input port to generate multiple target synchronization signals, and output the multiple target synchronization signals synchronously through multiple synchronization signal output ports. For example, six target synchronization signals can be generated based on one original synchronization signal.

[0052] In step S130, after each TTL level conversion chip receives a target synchronization signal synchronously output from the connected synchronization signal output port, it performs level conversion on the target synchronization signal and outputs the formed target TTL signal through a corresponding synchronization signal conversion output port.

[0053] In this embodiment of the application, after the plurality of target synchronization signals are formed, each of the TTL level conversion chips can perform level conversion on the target synchronization signal after receiving a target synchronization signal synchronously output by the connected synchronization signal output port, and output the formed target TTL signal through a corresponding synchronization signal conversion output port.

[0054] It should be noted that the specific execution process of each of the above steps can be referred to the relevant explanations and descriptions of the multi-channel TTL signal synchronous output system in the preceding text.

[0055] It is understood that, in an alternative implementation, the method for synchronous output of multiple TTL signals may further include steps S140, S150 and S160, the details of which are as follows.

[0056] In step S140, the crystal oscillator device performs isothermal crystal oscillation to generate a crystal oscillator signal, and outputs the crystal oscillator signal through the crystal oscillator signal output port. For details, please refer to the relevant explanation of the crystal oscillator device above.

[0057] In step S150, after receiving the crystal oscillator signal output from the crystal oscillator signal output port through the crystal oscillator signal input port, the frequency multiplier device performs frequency multiplication processing to form a frequency multiplier signal, and outputs it through the frequency multiplier signal output port. For details, please refer to the relevant explanation of the frequency multiplier device above.

[0058] In step S160, after receiving the frequency harmonic signal output from the frequency harmonic signal output port through the filter input port, the filter device performs filtering processing to suppress the high-frequency harmonic components in the frequency harmonic signal, forming a filtered signal, and outputting it through the filter output port. For details, please refer to the relevant explanation of the filter device above.

[0059] In step S170, after receiving the filtered signal output from the filtered output port through the amplification input port, the amplifying device amplifies and shapes the filtered signal to form a square wave signal whose amplitude meets the set conditions, and outputs it to the field programmable gate array as a reference clock signal. For details, please refer to the relevant explanation of the amplifying device above.

[0060] In summary, in the multi-channel TTL signal synchronous output system and method provided in this application, the field-programmable gate array (FPGA) is configured to generate an original synchronization signal upon receiving a synchronization signal generation command, perform synchronization processing on the original synchronization signal based on a reference clock signal to generate multiple target synchronization signals, and synchronously output the multiple target synchronization signals. Each TTL level conversion chip is configured to receive a target synchronization signal synchronously output from a connected synchronization signal output port, and after level conversion of the target synchronization signal, output the target TTL signal through the corresponding synchronization signal conversion output port. Based on the above, since the generation of multiple target synchronization signals is based on a reference clock signal and an original synchronization signal, it can, to a certain extent, improve the problem that traditional high-precision synchronization control systems for TTL signals suffer from insufficient synchronization accuracy due to phase differences between clock signals of different channels when outputting multiple channels.

[0061] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A multi-channel TTL signal synchronous output system, characterized in that, include: A field-programmable gate array (FPGA) includes a host control command input port, a clock signal input port, and multiple synchronization signal output ports. The FPGA is configured to generate an initial synchronization signal when a synchronization signal generation command is received through the host control command input port, and to perform synchronization processing on the initial synchronization signal based on a reference clock signal received through the clock signal input port to generate multiple target synchronization signals. The FPGA is also configured to synchronously output the multiple target synchronization signals through the multiple synchronization signal output ports. At least one TTL level conversion chip, wherein each TTL level conversion chip includes at least one synchronization signal input port and at least one synchronization signal conversion output port, and the at least one TTL level conversion chip includes multiple synchronization signal input ports and multiple synchronization signal conversion output ports, wherein the synchronization signal input ports are connected to the synchronization signal output ports, and each TTL level conversion chip is configured to receive a target synchronization signal synchronously output by the connected synchronization signal output port, and after level conversion of the target synchronization signal, output a target TTL signal through a corresponding synchronization signal conversion output port.

2. The multi-channel TTL signal synchronous output system according to claim 1, characterized in that, There are multiple TTL level conversion chips, and every two TTL level conversion chips have the same circuit configuration.

3. The multi-channel TTL signal synchronous output system according to claim 2, characterized in that, The length difference of the input line of the target synchronization signal between any two TTL level conversion chips in the plurality of TTL level conversion chips is less than a predetermined first length threshold, and the length difference of the output line of the target TTL signal between any two TTL level conversion chips in the plurality of TTL level conversion chips is less than a predetermined second length threshold.

4. The multi-channel TTL signal synchronous output system according to any one of claims 1-3, characterized in that, The multi-channel TTL signal synchronous output system also includes: A clock signal generation circuit, wherein the clock signal output port of the clock signal generation circuit is connected to the clock signal input port, and the clock signal generation circuit is configured to generate the reference clock signal and output the reference clock signal to the field programmable gate array through the clock signal output port and the clock signal input port.

5. The multi-channel TTL signal synchronous output system according to claim 4, characterized in that, The clock signal generation circuit includes: A crystal oscillator device, wherein the crystal oscillator device includes a crystal signal output port, and the crystal oscillator device is configured to generate a crystal signal by performing a temperature-controlled crystal oscillation, and output the crystal signal through the crystal signal output port; A signal processing component, wherein the signal processing component includes a crystal oscillator signal input port and a clock signal output port, and the signal processing component is configured to perform signal processing on the crystal oscillator signal received through the crystal oscillator signal input port to generate a reference clock signal.

6. The multi-channel TTL signal synchronous output system according to claim 5, characterized in that, The signal processing component includes: A frequency multiplier device, wherein the frequency multiplier device includes a crystal oscillator signal input port and a frequency multiplier signal output port, and the frequency multiplier device is configured to perform frequency multiplication processing on the crystal oscillator signal received through the crystal oscillator signal input port, and output the formed frequency multiplier signal through the frequency multiplier signal output port, the frequency multiplier signal serving as the basis for generating the reference clock signal.

7. The multi-channel TTL signal synchronous output system according to claim 6, characterized in that, The signal processing component further includes: A filtering device, comprising a filtering input port and a filtering output port, wherein the filtering input port is connected to the frequency multiplication signal output port, and the filtering device is configured to, after receiving the frequency multiplication signal output from the frequency multiplication signal output port through the filtering input port, perform filtering processing to suppress high-frequency harmonic components in the frequency multiplication signal, forming a filtered signal, and outputting it through the filtering output port, wherein the filtered signal serves as the basis for generating the reference clock signal.

8. The multi-channel TTL signal synchronous output system according to claim 7, characterized in that, The signal processing component further includes: An amplifying device, wherein the amplifying device includes an amplification input port and a clock signal output port, the amplification input port is connected to the filter output port, and the amplifying device is configured to, after receiving the filtered signal output from the filter output port through the amplification input port, amplify and shape the filtered signal to obtain a square wave signal whose amplitude meets a set condition, and output it as the reference clock signal.

9. A method for synchronous output of multiple TTL signals, characterized in that, The method for synchronously outputting multiple TTL signals, applicable to any one of claims 1-8, comprises a field-programmable gate array (FPGA) and at least one TTL level conversion chip, wherein the method for synchronously outputting multiple TTL signals includes: When the field-programmable gate array receives a synchronization signal generation command through the upper-level control command input port, it generates an original synchronization signal. The field-programmable gate array (FPGA) performs synchronization processing on the original synchronization signal based on the reference clock signal received through the clock signal input port, generates multiple target synchronization signals, and outputs the multiple target synchronization signals synchronously through multiple synchronization signal output ports. After receiving a target synchronization signal synchronously output from the connected synchronization signal output port, each TTL level conversion chip performs level conversion on the target synchronization signal and outputs the formed target TTL signal through a corresponding synchronization signal conversion output port.

10. The method for synchronous output of multiple TTL signals according to claim 9, characterized in that, The multi-channel TTL signal synchronous output system further includes a crystal oscillator, a frequency multiplier, and an amplifier; the multi-channel TTL signal synchronous output method further includes: The crystal oscillator device performs isothermal crystal oscillation to generate a crystal oscillator signal, and outputs the crystal oscillator signal through the crystal oscillator signal output port; After receiving the crystal oscillator signal output from the crystal oscillator signal output port through the crystal oscillator signal input port, the frequency multiplier device performs frequency multiplication processing to form a frequency multiplier signal, and outputs it through the frequency multiplier signal output port; After receiving the frequency multiplier signal output from the frequency multiplier signal output port through the filter input port, the filter device performs filtering processing to suppress the high-frequency harmonic components in the frequency multiplier signal, forming a filtered signal, and outputs it through the filter output port. After receiving the filtered signal from the filtered output port through the amplification input port, the amplification device amplifies and shapes the filtered signal to form a square wave signal with an amplitude that meets the set conditions, and outputs it to the field programmable gate array as a reference clock signal.

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