A clock buffer control circuit under dynamic voltage frequency scaling

Abstract

The application discloses a clock buffer control circuit under dynamic voltage frequency adjustment, comprising a clock buffer driving circuit, a clock skew calibration circuit, a DVFS kernel voltage sampling circuit and a power-on anti-spur and soft start control circuit; the clock skew calibration circuit is composed of an independent hardware module and realizes clock phase calibration and waveform trimming by relying on an on-chip closed loop; the DVFS kernel voltage sampling circuit is an independent single-ended sampling hardware loop, only completes FPGA kernel voltage collection, amplification and output, and does not form electrical signal interaction with the rest of the circuit, the clock skew calibration circuit adopts closed-loop independent regulation and control design, the direct current control voltage required for phase adjustment is a loop exclusive self-generated voltage, is completely electrically isolated from the DVFS kernel voltage sampling circuit, and interference of dynamic fluctuation of the kernel voltage on the clock phase calibration loop is reduced.

Description

Technical Field

[0001] This invention relates to the field of FPGA dynamic voltage and frequency regulation technology, and in particular to a clock buffer control circuit under dynamic voltage and frequency regulation. Background Technology

[0002] With the large-scale integration of field-programmable gate arrays, dynamic voltage-frequency regulation (DVFS) technology has become a core means for chips to achieve low power consumption and dynamic operating condition adaptation. In the dynamic voltage and frequency regulation operation scenario of DVFS, the clock buffer circuit, as the core hardware for digital logic timing transmission, suffers from several problems. Traditional clock skew calibration circuit modules exhibit chaotic integration, the control voltage for phase adjustment is susceptible to interference from fluctuations in the chip core power supply, the matching architecture of the feedback clock and reference clock is poorly designed, and there is a lack of an independent external waveform repair structure. This leads to phase shifts, pulse distortion, and insufficient timing calibration accuracy in the clock signal. Furthermore, the conventional DVFS core voltage acquisition circuit has a crude design, with chaotic series arrangement of voltage divider resistors, misaligned connection nodes of RC components at the operational amplifier feedback end, and an unreasonable selection of the amplification sampling architecture. This easily causes voltage sampling signal distortion and poor filtering, making it impossible to accurately capture the dynamic changes in the core voltage under DVFS conditions and failing to meet basic hardware monitoring requirements. Simultaneously, the clock hardware circuit lacks a dedicated protection structure during power-on startup and has no standardized reference level matching branch, commonly exhibiting problems such as transient voltage glitches, reverse current backflow, and potential drift. These issues can easily cause false triggering of the clock drive module, signal disturbances, and shorten the circuit's lifespan. Summary of the Invention

[0003] The purpose of this invention is to address the shortcomings of existing technologies, such as "chaotic integration of traditional clock skew calibration circuit modules, susceptibility of phase adjustment control voltage to power supply fluctuations in the chip core, unreasonable matching architecture design of feedback clock and reference clock, lack of independent external waveform repair structure, easy phase shift and pulse distortion of clock signals, and insufficient timing calibration accuracy; in addition, the conventional DVFS core voltage acquisition circuit has a rough design, chaotic series arrangement of voltage divider resistors, misaligned connection nodes of RC components at the operational amplifier feedback end, and unreasonable selection of amplification sampling architecture, which easily leads to voltage sampling signal distortion, poor filtering effect, inability to accurately capture dynamic changes in core voltage under DVFS conditions, and difficulty in meeting basic hardware monitoring requirements; at the same time, the clock hardware circuit lacks a dedicated protection structure during power-on startup, has no standardized reference level matching branch, and generally suffers from transient voltage glitches, reverse current backflow, and potential drift, which can easily cause clock drive module mis-triggering, signal disorder, and shorten circuit lifespan." Therefore, this invention proposes a clock buffer control circuit under dynamic voltage frequency adjustment.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A clock buffer control circuit under dynamic voltage and frequency adjustment includes: a clock buffer drive circuit, a clock skew calibration circuit, a DVFS core voltage sampling circuit, and a power-on anti-glitch and soft-start control circuit.

[0006] The clock skew calibration circuit is composed of an independent hardware module, which relies on the on-chip closed loop to achieve clock phase calibration and waveform trimming.

[0007] The DVFS core voltage sampling circuit is an independent single-ended sampling hardware loop that only completes the FPGA core voltage acquisition, amplification, and output, and does not interact with other circuits.

[0008] The power-on anti-glitch and soft-start control circuit suppresses power-on voltage glitches and transient interference through an RC network, diode clamping, and operational amplifier shaping.

[0009] The clock buffer drive circuit is an independent clock drive hardware loop that receives the clock signal output by the clock skew calibration circuit independently.

[0010] As a preferred embodiment of the clock buffer control circuit under dynamic voltage frequency adjustment described in this invention, the DVFS core voltage sampling circuit includes resistors R1, R11, R12, R13, R14, R15, R16, R17, and R18, capacitors C1, C11, and C12, and operational amplifier U1.

[0011] This circuit is a single-ended amplification and sampling structure. The core power supply positive voltage BAT+ is connected in series with R17, R13, R14, and R15, with R15 not grounded. The core power supply negative voltage BAT- is connected in series with R18, R1, R11, and R12, with the end of R12 grounded. The non-inverting input of the operational amplifier U1 is connected to the junction of R14 and R15, and the inverting input of the operational amplifier U1 is connected to the junction of R11 and R12. R16 is connected between the inverting input and output of the operational amplifier U1. C11 is connected in parallel with R16 and is connected between the inverting input and output of the operational amplifier U1. C1 is connected between the non-inverting input of the operational amplifier U1 and ground, and C12 is connected between the output of the operational amplifier U1 and ground.

[0012] As a preferred embodiment of the clock buffer control circuit under dynamic voltage and frequency regulation described in this invention, the clock skew calibration circuit includes a voltage-controlled delay line, an independent external pulse width recovery unit, a phase detector, a charge pump, and a loop filter unit.

[0013] The pulse width recovery unit is an independent external hardware module. The input clock signal is connected to the input terminal of the voltage-controlled delay line (VCD). The VCD outputs eight working clocks (DCK0~DCK7) and leads out an independent feedback clock (DCK8). One phase detector is connected to an external reference clock, and the other is connected to the feedback clock (DCK8). The phase detector outputs a phase error signal to a charge pump, which is connected to a loop filter unit. The loop filter unit outputs a dedicated DC control voltage to the VCD. This voltage is isolated from the DVFS core voltage sampling circuit. The DCK0~DCK7 outputs of the VCD are respectively connected to the corresponding pulse width recovery units.

[0014] As a preferred embodiment of the clock buffer control circuit under dynamic voltage frequency adjustment described in this invention, the power-on anti-glitch and soft-start control circuit includes resistors R21, R22, R23, R24, R25, and R26, capacitor C2, diodes D2 and D21, and operational amplifier U2.

[0015] The anode of diode D2 is connected to the power supply sampling node, the cathode of D2 is connected to R23, R23 is connected to both R21 and C2, the other end of C2 is grounded, R21 is connected to the fixed internal reference level terminal of the system after being connected in series with R22, R24 is connected across the non-inverting input terminal of operational amplifier U2 and the front-end voltage divider node, the output terminal of operational amplifier U2 is connected in series with R25, R25 is connected to the anode of D21 and R26 respectively, R26 is connected to the working power supply, and D21 is used for level clamping and preventing current reverse flow.

[0016] As a preferred embodiment of the clock buffer control circuit under dynamic voltage and frequency regulation described in this invention, the clock buffer drive circuit includes a grouped P-terminal inverter chain, a grouped N-terminal inverter chain, a PMOS transistor array, and an NMOS transistor array.

[0017] The P-terminal inverter chain and the N-terminal inverter chain are independent of each other. Each group of inverter chains is connected to a multi-channel calibration clock signal output by the clock skew calibration circuit. Each group of P-terminal inverter chains drives a PMOS transistor array, and each group of N-terminal inverter chains drives an NMOS transistor array. The source of the PMOS transistor array is connected to the system power supply voltage, and the source of the NMOS transistor array is grounded. The drains of each group of MOS transistor arrays are connected in parallel to form a clock signal output terminal.

[0018] As a preferred embodiment of the clock buffer control circuit under dynamic voltage and frequency adjustment described in this invention, the DVFS core voltage sampling circuit is an independent sampling loop. The DVFS core voltage sampling circuit only performs core voltage division, amplification and filtering acquisition. The circuit output terminal is floating and does not establish physical connections or signal interactions with other circuits.

[0019] As a preferred embodiment of the clock buffer control circuit under dynamic voltage and frequency adjustment described in this invention, the DC control voltage output by the loop filter unit is a dedicated control voltage inside the clock skew calibration circuit, and the power-on anti-glitch and soft-start control circuits output independent level signals.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] The clock skew calibration circuit adopts a closed-loop independent control design. The DC control voltage required for phase adjustment is a self-generated voltage dedicated to the circuit, which is completely electrically isolated from the DVFS core voltage sampling circuit. This reduces the interference of core voltage dynamic fluctuations on the clock phase calibration circuit. At the same time, it distinguishes the hardware definitions of multiple working clocks and independent feedback clocks. With an independent external pulse width recovery unit, it solves the problems of severe clock skew, waveform distortion and low calibration accuracy in traditional circuits, and greatly improves the stability of timing transmission under DVFS conditions.

[0022] The hardware topology of the DVFS core voltage sampling circuit has been optimized, limiting the series sequence of voltage divider resistors, the sampling node at the op-amp input, and the RC connection relationship of the feedback branch. A single-ended amplification sampling architecture adapted to the chip's operating conditions has been adopted. The component layout is reasonable, and the filtering and negative feedback structure are accurately matched, avoiding defects such as voltage sampling signal distortion and filtering failure. It can acquire the FPGA core power supply voltage for a long time and accurately, providing reliable hardware sampling data support for the dynamic strategy control of DVFS.

[0023] The addition of power-on protection hardware structure relies on the RC filter network to filter out power supply noise, and the matching system fixes the internal reference level terminal to complete the voltage division ratio. Combined with diode level clamping and anti-reverse flow design, it effectively suppresses voltage spikes, potential drift and reverse current impact at the moment of power-on, avoids the problem of clock circuit false start-up and signal glitches, and enhances the overall circuit's fault tolerance and operational safety. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the adaptive adjustment circuit for the driving capability of a clock buffer control circuit under dynamic voltage and frequency regulation proposed in this invention.

[0025] Figure 2 This is a diagram of the DVFS core voltage sampling circuit of a clock buffer control circuit under dynamic voltage frequency adjustment proposed in this invention.

[0026] Figure 3 This is a clock skew calibration circuit diagram for a clock buffer control circuit under dynamic voltage frequency adjustment proposed in this invention.

[0027] Figure 4This invention presents a power-on anti-glitch and soft-start control circuit diagram for a clock buffer control circuit under dynamic voltage and frequency regulation. Detailed Implementation

[0028] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0029] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] Reference Figures 1-4 A clock buffer control circuit for dynamic voltage and frequency regulation is proposed. Considering that under dynamic voltage and frequency regulation conditions, the integrated layout of multiple circuits such as clock calibration, voltage sampling, power-on control, and clock drive is prone to signal coupling and crosstalk, and the disordered linkage of various functional loops can reduce overall operational stability, this circuit includes a clock buffer drive circuit, a clock skew calibration circuit, a DVFS core voltage sampling circuit, and a power-on anti-ghosting and soft-start control circuit. The clock skew calibration circuit consists of an independent hardware module, relying on an on-chip closed-loop circuit to achieve clock phase calibration and waveform trimming. The DVFS core voltage sampling circuit is an independent single-ended sampling hardware loop, only completing the acquisition, amplification, and output of the FPGA core voltage, without interacting with other circuits. The power-on anti-ghosting and soft-start control circuit suppresses power-on voltage glitches and transient interference through an RC network, diode clamping, and operational amplifier shaping. The clock buffer drive circuit is an independent clock drive hardware loop, receiving the clock signal output from the clock skew calibration circuit independently. Each circuit module is independent and there is no cross-loop signal binding, making it suitable for dynamic voltage and frequency regulation applications.

[0031] Considering that conventional DVFS voltage acquisition circuits suffer from disordered voltage divider resistor arrangements, misaligned operational amplifier feedback components, and unreasonable sampling topology, which can easily lead to core voltage acquisition distortion, feedback compensation failure, and insufficient filtering capability, thus failing to accurately adapt to dynamic voltage monitoring requirements, the DVFS core voltage sampling circuit includes resistors R1, R11, R12, R13, R14, R15, R16, R17, and R18, capacitors C1, C11, and C12, and operational amplifier U1.

[0032] This circuit is a single-ended amplification and sampling structure. The core power supply positive voltage BAT+ is connected in series with R17, R13, R14, and R15, with R15 not grounded. The core power supply negative voltage BAT- is connected in series with R18, R1, R11, and R12, with the end of R12 grounded. The non-inverting input of operational amplifier U1 is connected to the junction of R14 and R15, and the inverting input of operational amplifier U1 is connected to the junction of R11 and R12. R16 is connected between the inverting input and output of operational amplifier U1. C11 is connected in parallel with R16 and is connected between the inverting input and output of operational amplifier U1. C1 is connected between the non-inverting input of operational amplifier U1 and ground, and C12 is connected between the output of operational amplifier U1 and ground.

[0033] Furthermore, considering that traditional clock skew calibration structures often integrate waveform repair modules, the boundary between the working clock and the feedback clock is vaguely defined, and the phase adjustment control voltage is easily affected by core power supply fluctuations, resulting in poor clock calibration accuracy and waveform distortion that cannot be eradicated, the clock skew calibration circuit includes a voltage-controlled delay line, an independent external pulse width recovery unit, a phase detector, a charge pump, and a loop filter unit.

[0034] The pulse width recovery unit is an independent external hardware module. The input clock signal is connected to the input terminal of the voltage-controlled delay line (VCD). The VCD outputs eight working clocks (DCK0~DCK7) and leads out an independent feedback clock (DCK8). One phase detector is connected to an external reference clock, and the other is connected to the feedback clock (DCK8). The phase detector outputs a phase error signal to the charge pump, which is connected to the loop filter unit. The loop filter unit outputs a dedicated DC control voltage to the VCD. This voltage is isolated from the DVFS core voltage sampling circuit. The DCK0~DCK7 outputs of the VCD are connected to the corresponding pulse width recovery units.

[0035] Furthermore, considering that transient voltage spikes and high-frequency noise interference are common during the power-on startup phase of hardware circuits, the lack of standard reference level support, and the susceptibility to reverse current backflow and potential drift, which can easily cause clock circuit malfunctions and signal glitches, the power-on anti-glitch and soft-start control circuit includes resistors R21, R22, R23, R24, R25, and R26, capacitor C2, diodes D2 and D21, and operational amplifier U2.

[0036] The anode of diode D2 is connected to the power supply sampling node, and the cathode of D2 is connected to R23. R23 is also connected to R21 and C2. The other end of C2 is grounded. R21 is connected to the fixed internal reference level terminal of the system after being connected in series with R22. R24 is connected across the non-inverting input terminal of operational amplifier U2 and the front-end voltage divider node. The output terminal of operational amplifier U2 is connected in series with R25. R25 is connected to the anode of D21 and R26 respectively. R26 is connected to the working power supply. D21 is used for level clamping and preventing current reverse flow.

[0037] Furthermore, considering that traditional clock buffer drives mostly adopt a single-link drive design without distinguishing complementary drive architectures, they cannot adapt to load fluctuations caused by dynamic voltage and frequency changes in DVFS, and the clock load capacity and timing drive stability are limited. Therefore, the clock buffer drive circuit includes a grouped P-terminal inverter chain, a grouped N-terminal inverter chain, a PMOS transistor array, and an NMOS transistor array.

[0038] The P-terminal inverter chain and the N-terminal inverter chain are independent of each other. Each group of inverters is connected to the multi-channel calibration clock signal output by the clock skew calibration circuit. Each group of P-terminal inverters drives a PMOS transistor array, and each group of N-terminal inverters drives an NMOS transistor array. The source of the PMOS transistor array is connected to the system power supply voltage, and the source of the NMOS transistor array is grounded. The drains of each group of MOS transistor arrays are connected in parallel to form the clock signal output terminal.

[0039] Considering that redundant physical connections and signal interactions between multi-module circuits can generate spurious crosstalk, compromising the independence and accuracy of voltage sampling, the DVFS core voltage sampling circuit is an independent sampling loop. The DVFS core voltage sampling circuit only performs core voltage division, amplification, and filtering acquisition; its output is left floating and does not establish physical connections or signal interactions with other circuits. The DC control voltage output by the loop filter unit is a dedicated control voltage within the clock skew calibration circuit. The power-on anti-ghosting and soft-start control circuits independently output level signals.

[0040] It is worth noting that the entire device is controlled by a controller. Since the controller is a common device and belongs to existing mature technology, its electrical connection relationship and specific circuit structure will not be described in detail here.

[0041] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the technical scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," or "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

Claims

1. A clock buffer control circuit under dynamic voltage frequency adjustment, characterized in that, include: Clock buffer drive circuit, clock skew calibration circuit, DVFS core voltage sampling circuit, and power-on anti-glitch and soft-start control circuit; The clock skew calibration circuit is composed of an independent hardware module, which relies on the on-chip closed loop to achieve clock phase calibration and waveform trimming. The DVFS core voltage sampling circuit is an independent single-ended sampling hardware loop that only completes the FPGA core voltage acquisition, amplification, and output, and does not interact with other circuits. The power-on anti-glitch and soft-start control circuit suppresses power-on voltage glitches and transient interference through an RC network, diode clamping, and operational amplifier shaping. The clock buffer drive circuit is an independent clock drive hardware loop that receives the clock signal output by the clock skew calibration circuit independently.

2. The clock buffer control circuit under dynamic voltage and frequency regulation according to claim 1, characterized in that: The DVFS core voltage sampling circuit includes resistors R1, R11, R12, R13, R14, R15, R16, R17, and R18, capacitors C1, C11, and C12, and operational amplifier U1. This circuit is a single-ended amplification and sampling structure. The core power supply positive voltage BAT+ is connected in series with R17, R13, R14, and R15, with R15 not grounded. The core power supply negative voltage BAT- is connected in series with R18, R1, R11, and R12, with the end of R12 grounded. The non-inverting input of the operational amplifier U1 is connected to the junction of R14 and R15, and the inverting input of the operational amplifier U1 is connected to the junction of R11 and R12. R16 is connected between the inverting input and output of the operational amplifier U1. C11 is connected in parallel with R16 and is connected between the inverting input and output of the operational amplifier U1. C1 is connected between the non-inverting input of the operational amplifier U1 and ground, and C12 is connected between the output of the operational amplifier U1 and ground.

3. The clock buffer control circuit under dynamic voltage and frequency regulation according to claim 1, characterized in that: The clock skew calibration circuit includes a voltage-controlled delay line, an independent external pulse width recovery unit, a phase detector, a charge pump, and a loop filter unit. The pulse width recovery unit is an independent external hardware module. The input clock signal is connected to the input terminal of the voltage-controlled delay line. The voltage-controlled delay line outputs eight working clocks DCK0~DCK7 and leads out one independent feedback clock DCK8. One of the phase detectors is connected to an external reference clock, and the other is connected to the feedback clock DCK8. The phase detector outputs a phase error signal to the charge pump, which is connected to the loop filter unit. The loop filter unit outputs a dedicated DC control voltage to supply the voltage-controlled delay line separately. This voltage is isolated from the DVFS core voltage sampling circuit. The DCK0~DCK7 outputs of the voltage-controlled delay line are respectively connected to the corresponding pulse width recovery units.

4. The clock buffer control circuit under dynamic voltage and frequency adjustment according to claim 1, characterized in that: The power-on anti-burr and soft-start control circuit includes resistors R21, R22, R23, R24, R25, and R26, capacitor C2, diodes D2 and D21, and operational amplifier U2. The anode of diode D2 is connected to the power supply sampling node, the cathode of D2 is connected to R23, R23 is connected to both R21 and C2, the other end of C2 is grounded, R21 is connected to the fixed internal reference level terminal of the system after being connected in series with R22, R24 is connected across the non-inverting input terminal of operational amplifier U2 and the front-end voltage divider node, the output terminal of operational amplifier U2 is connected in series with R25, R25 is connected to the anode of D21 and R26 respectively, R26 is connected to the working power supply, and D21 is used for level clamping and preventing current reverse flow.

5. The clock buffer control circuit under dynamic voltage and frequency regulation according to claim 1, characterized in that: The clock buffer drive circuit includes a grouped P-terminal inverter chain, a grouped N-terminal inverter chain, a PMOS transistor array, and an NMOS transistor array. The P-terminal inverter chain and the N-terminal inverter chain are independent of each other. Each group of inverter chains is connected to a multi-channel calibration clock signal output by the clock skew calibration circuit. Each group of P-terminal inverter chains drives a PMOS transistor array, and each group of N-terminal inverter chains drives an NMOS transistor array. The source of the PMOS transistor array is connected to the system power supply voltage, and the source of the NMOS transistor array is grounded. The drains of each group of MOS transistor arrays are connected in parallel to form a clock signal output terminal.

6. The clock buffer control circuit under dynamic voltage and frequency regulation according to claim 1, characterized in that: The DVFS core voltage sampling circuit is an independent sampling loop. The DVFS core voltage sampling circuit only performs core voltage division, amplification and filtering acquisition.

7. The clock buffer control circuit under dynamic voltage and frequency adjustment according to claim 3, characterized in that: The DC control voltage output by the loop filter unit is a dedicated control voltage inside the clock skew calibration circuit, and the power-on anti-glitch and soft-start control circuits output independent level signals.

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