Bidirectional level conversion circuit and integrated circuit chip

Abstract

The application discloses a bidirectional level conversion circuit and an integrated circuit chip. The bidirectional level conversion circuit comprises a first transmission path and a second transmission path connected between a core logic power supply network and an input / output power supply network, a first monostable edge detection circuit and a second monostable edge detection circuit arranged on an input side, and a first feedback loop and a second feedback loop arranged on an output side and comprising a series dynamic maintenance inhibition transistor and a weak pull-up transistor; the first monostable edge detection circuit and the second monostable edge detection circuit generate inhibition pulses in response to input jump to actively close the dynamic maintenance inhibition transistor on the opposite side, and the transmission path comprises a transient charge injection network composed of a bootstrap capacitor, a driving transistor and a pre-charge bias transistor. The application can eliminate short-circuit competitive current when crossing a large voltage domain flip without increasing the size of a driving tube and static power consumption, and effectively supports high-speed bidirectional signal communication with low parasitic capacitance.

Description

Technical Field

[0001] This application relates to the field of integrated circuit level conversion technology, specifically a bidirectional level conversion circuit and integrated circuit chip, which is applied to transient charge pump bootstrap and dynamic feedback control in heterogeneous voltage interface environments such as automotive domain controller chips. Background Technology

[0002] Currently, in the application scenarios of domain controller system-on-a-chip (SoC) in automotive advanced driver assistance systems (ADAS), the internal hardware architecture of the chip faces complex power network planning. The system needs to simultaneously handle core logic signals in the low-voltage domain and peripheral communication signals in the high-voltage domain, with a large voltage difference between the two. For example, the nominal value of the core logic voltage under advanced process technology is typically around 0.8 volts, while the peripheral communication voltage of the input / output interface is as high as 3.3 volts. This heterogeneous voltage interface environment presents a technical challenge to high-speed, low-power signal transmission across power domains.

[0003] Conventional cross-coupled level converters across voltage domains typically employ static transistor feedback networks to maintain stable high and low level states. However, when a signal from the low-voltage domain attempts to flip the output node that is in a high-level state, the low-voltage signal is often below the inherent threshold voltage of the thick-gate oxide MOSFET on the high-voltage side, or it can only barely operate in the weak subthreshold region, resulting in weak pull-down current discharge capability of the low-voltage side transistor. Simultaneously, the cross-coupled pull-up transistor on the high-voltage side remains fully on, continuously providing a strong pull-up current. At this point, a short-circuit current competition occurs between the pull-down low-voltage transistor and the pull-up high-voltage transistor.

[0004] This static feedback pull-up short-circuit current contention not only increases the signal state transition delay, limiting data throughput, but also generates punch-through current during the transient state transition, increasing the dynamic power consumption of the system-on-a-chip. To alleviate this contention, existing conventional technologies typically increase the physical size of the low-voltage side driver transistor to forcibly enhance its pull-down drive capability. However, this physical size enlargement increases the parasitic capacitance of the input node, slowing down the operation speed of the interconnect bus within the low-voltage domain. Furthermore, excessively large input parasitic capacitance cannot meet the timing setup and power consumption limitations of high-speed bidirectional serial peripheral interfaces or secure digital input / output interfaces.

[0005] Existing level converters are difficult to effectively eliminate short-circuit competing currents without increasing parasitic capacitance, resulting in technical defects such as large switching delay, high dynamic power consumption, and inability to accommodate high-speed communication. Summary of the Invention

[0006] This application provides a bidirectional level conversion circuit and integrated circuit chip, which solves the technical problems of short-circuit current competition, large switching delay, and inability to balance high speed and low parasitic capacitance when level conversion is performed across a large voltage domain in the prior art.

[0007] This application provides a bidirectional level shifting circuit, bridging a core logic power network with a first supply voltage and an input / output power network with a second supply voltage. The bidirectional level shifting circuit includes a first transmission path and a second transmission path that are cross-connected. It includes a first monostable edge detection circuit and a second monostable edge detection circuit, disposed on the input port side. It also includes a first feedback loop and a second feedback loop, disposed on the output side. Both the first and second feedback loops include a dynamically sustaining suppressor transistor and a weak pull-up transistor connected in series. The output of the first monostable edge detection circuit is connected to the gate of the dynamically sustaining suppressor transistor in the second feedback loop. The output of the second monostable edge detection circuit is connected to the gate of the dynamically sustaining suppressor transistor in the first feedback loop. Both the first and second transmission paths are configured to generate a suppression pulse in response to an input transition edge, turning off the opposing dynamically sustaining suppressor transistor. Both the first and second transmission paths include a transient charge injection network, which includes a bootstrap capacitor, a driving transistor, and a pre-charge bias transistor. In steady state, the pre-charge bias transistor pre-charges the top plate of the bootstrap capacitor to the bias voltage. In response to a rising input transition, the bootstrap capacitor is configured to transiently pump up its top plate voltage and control the drive transistor to conduct deeply.

[0008] In a preferred embodiment, the first monostable edge detection circuit and the second monostable edge detection circuit employ a consistent symmetrical structure. The first monostable edge detection circuit includes a delayed inverter chain and an AND gate. The input of the delayed inverter chain and the first input of the AND gate are connected to the input port side. The output of the delayed inverter chain is connected to the second input of the AND gate. The delayed inverter chain comprises multiple complementary metal-oxide-semiconductor inverters connected in series. The delayed inverter chain is configured to time-delay and phase-flip the input signal. The AND gate is configured to generate a suppression pulse based on the original input signal and the delayed-flipped signal.

[0009] In a preferred embodiment, the microphysical structure of multiple interconnected complementary metal-oxide-semiconductor (CMOS) inverters in the delay inverter chain is configured as a non-uniform array. Along the signal propagation direction, the channel lengths of the metal-oxide-semiconductor (MOSFETs) in each CMOS inverter are arranged in a progressively increasing order. The channel length of the first CMOS inverter in the delay inverter chain is defined as a base length value, and the channel lengths of subsequent CMOS inverters are configured based on an incremental step size factor. The base length value corresponds to the standard process minimum channel length under a first supply voltage domain. The charge / discharge current drive capability of each inverter varies progressively along the signal propagation path, configured to progressively smooth the slope of the internal signal flip edges.

[0010] In a preferred embodiment, the source of the precharge bias transistor is connected to the core logic power network to receive a first supply voltage, and the drain of the precharge bias transistor is connected to the top plate of the bootstrap capacitor and the gate of the drive transistor. The bottom plate of the bootstrap capacitor is connected to the signal input terminal on the input port side. The source of the drive transistor is connected to the core logic power network, and the drain of the drive transistor is connected to the corresponding node on the output port side.

[0011] In a preferred embodiment, the bootstrap capacitor employs a metal-insulator-metal capacitor structure, comprising a first plate parasitic capacitance and a second plate parasitic capacitance. The physical layout area and internal dielectric layer thickness of the bootstrap capacitor are configured based on the gate parasitic capacitance value of the driving transistor. Specifically, the inherent capacitance value of the bootstrap capacitor is greater than or equal to a preset capacitance threshold, which is determined by the gate parasitic capacitance value of the driving transistor, the first plate parasitic capacitance value, and the ratio of the first supply voltage to the second supply voltage. At the instant of the bottom plate input rise transition, the charge redistribution network composed of the inherent capacitance value, the gate parasitic capacitance value, and the first plate parasitic capacitance value transiently boosts the voltage of the top plate, configured to raise the gate-source voltage difference of the driving transistor to greater than or equal to twice its nominal threshold voltage.

[0012] In a preferred embodiment, the first and second transmission paths are arranged in a symmetrical differential cross-coupled topology. The transistor arrays in the first and second transmission paths are configured to maintain a consistent ratio in terms of physical size and spacing. The bidirectional level shifting circuit does not include a direction enable control pin and is configured to adaptively identify the bidirectional signal transmission direction based on the drive strength of the physical level at the pin.

[0013] In a preferred embodiment, both the first and second feedback loops employ positive-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). The ratio of the effective channel width to the effective channel length of the weak pull-up transistor is configured to be less than one. The effective channel width is configured to be 120 nanometers, and the effective channel length is configured to be 800 nanometers. The gate of the weak pull-up transistor is cross-connected to the output node of the opposite transmission path, the source of the weak pull-up transistor is connected to the input / output power supply network to receive a second supply voltage, and the drain of the weak pull-up transistor is connected in series to the source of the dynamic sustaining suppression transistor. The static leakage current of the bidirectional level shifting circuit during the steady-state sustaining phase is limited to a preset current threshold.

[0014] In a preferred embodiment, the first supply voltage and the second supply voltage belong to different voltage domains. The first supply voltage of the core logic power network is nominally 0.8 volts. The second supply voltage of the input / output power network is nominally 3.3 volts.

[0015] In a preferred embodiment, the drain of the dynamically sustaining suppressor transistor is directly connected to the drain of the driving transistor to form a common output node. The duration of the suppressor pulse is configured to cover the time period during which the transient charge injection network will turn on the driving transistor.

[0016] This application also provides an integrated circuit chip, including a logic gate array, input / output pins, and the aforementioned bidirectional level shifting circuit. The bidirectional level shifting circuit is configured on the signal communication path between the logic gate array and the input / output pins.

[0017] This application utilizes a monostable edge detection circuit bypassed on the input port side and a dynamically sustaining suppression transistor connected in series in the output feedback loop. This proactively cuts off the original static feedback pull at the initial stage of signal transition, creating a contention-free physical time window for the transition operation. By combining a bootstrap capacitor and a transient charge injection network, the charge redistribution at the moment of input edge transition is used to transiently pump the low-voltage side signal to a high-voltage level, thus deeply activating the drive transistor. This solution eliminates the short-circuit contention current during state transitions across large voltage domains without increasing the steady-state static power consumption, effectively supporting high-speed bidirectional signal communication with low parasitic capacitance. Attached Figure Description

[0018] Figure 1 This is an overall structural block diagram of the bidirectional level conversion circuit provided in the embodiments of this application.

[0019] Figure 2 This is a detailed diagram of the logic and circuit structure of the bidirectional level conversion circuit provided in the embodiments of this application.

[0020] Figure 3This is a schematic diagram of the application architecture of the integrated circuit chip provided in the embodiments of this application.

[0021] Explanation of reference numerals in the attached figures

[0022] In the diagram: 100 - Bidirectional level shifting circuit, 101 - Core logic power network, 102 - Input / output power network, 110 - Low-voltage side interface network, 120 - High-voltage side interface network, 130 - Adaptive edge acceleration and control core, 131 - First transmission path, 131a - Input port, 132 - Second transmission path, 141 - First monostable edge detection circuit, 142 - Second monostable edge detection circuit, 143 - Delayed inverter chain, 151 - First feedback loop, 152 - Second feedback loop, 153 - Dynamic sustaining suppression transistor, 154 - Weak pull-up transistor, 161 - First transient charge injection network, 163 - Bootstrap capacitor, 164 - Driver transistor, 165 - Precharge bias transistor, 300 - Integrated circuit chip, 310 - Logic gate array, 320 - Input / output pin, 330 - Clamping diode. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. The various embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0024] Example 1: Main Architecture and Control Mechanism of Bidirectional Level Conversion Circuit

[0025] Combination Figure 1 and Figure 2 As shown, this application embodiment provides a bidirectional level conversion circuit 100. This bidirectional level conversion circuit 100 is specifically deployed within the peripheral input / output communication loop of a system-on-a-chip at the physical level architecture. Its core physical function is to enable bidirectional communication across heterogeneous power domains, bridging voltage gradients.

[0026] Specifically, a bidirectional level shifting circuit 100 is connected between the core logic power network 101 (first supply voltage) and the input / output power network 102 (second supply voltage). The core logic power network 101 provides the first supply voltage representing low internal chip logic domain signals; in this embodiment, its nominal value is precisely set to 0.8 volts. The input / output power network 102 provides the second supply voltage representing high-voltage peripheral communication signals; its nominal value is set to 3.3 volts. This voltage domain division satisfies the isolation and bridging requirements between internal advanced process miniaturized transistors and external traditional anti-interference communication protocols.

[0027] The overall hardware structure of the bidirectional level shifting circuit 100 includes a low-voltage side interface network 110, a high-voltage side interface network 120, and an adaptive edge acceleration and control core 130 located between them. The low-voltage side interface network 110 is directly connected to the core logic power network 101 and establishes a hard-wired conductive connection with one end of the core power domain and the input port side. The high-voltage side interface network 120 is connected to the input / output power network 102 and to the peripheral output side. The bidirectional level shifting circuit 100 does not contain a dedicated direction enable control pin in its physical structure; each port pin of its low-voltage side interface network 110 and high-voltage side interface network 120 has dual physical attributes of input signal sampling and output level driving. The bidirectional level shifting circuit 100 is configured to adaptively identify the bidirectional signal transmission direction based on the drive strength of the pin's physical level. This fully adaptive communication architecture, which eliminates the need for explicit direction enable signal lines, significantly reduces silicon wiring channel resources at the chip level and lowers the complexity of the system control logic.

[0028] like Figure 2 Further demonstrating the internal structure, the adaptive edge acceleration and control core 130 houses a first transmission path 131 and a second transmission path 132, which are cross-connected and responsible for signal flow in different directions. The first transmission path 131 and the second transmission path 132 are physically symmetrically arranged in a differential cross-coupled topology. Specifically, the transistor arrays in the first transmission path 131 and the second transmission path 132 maintain a consistent proportional configuration in terms of physical size, channel doping concentration, and spacing distribution. Based on this perfectly symmetrical differential topology, the parasitic resistance-capacitance network parameters on the bidirectional signal paths can be effectively balanced, and the differential geometry can be used to offset delay mismatches and common-mode noise caused by variations in semiconductor manufacturing processes.

[0029] To proactively overcome short-circuit competition in traditional structures, the bidirectional level shifting circuit 100 includes a first monostable edge detection circuit 141 and a second monostable edge detection circuit 142. The first monostable edge detection circuit 141 is located at the input port 131a of the first transmission path 131, bypassing the sensing of the input state of the first transmission path 131. Similarly, the second monostable edge detection circuit 142 is located at the corresponding input port of the second transmission path 132. Both the first and second monostable edge detection circuits 141 and 142 adopt a consistent symmetrical structure and are configured to monitor the voltage crossing behavior at the corresponding input port in real time. When the voltage state at the input port crosses a preset edge detection threshold, the edge detection circuit is triggered instantaneously. In the 0.8-volt core logic domain of this embodiment, the edge detection threshold is preferably configured as 0.4 volts.

[0030] On the output side, the bidirectional level conversion circuit 100 includes a first feedback loop 151 and a second feedback loop 152. The first feedback loop 151 is connected to the output of the first transmission path 131, and the second feedback loop 152 is connected to the output of the second transmission path 132. Both the first feedback loop 151 and the second feedback loop 152 include a dynamically sustaining suppression transistor 153 and a weak pull-up transistor 154 connected in series. The output of the first monostable edge detection circuit 141 is physically connected to the gate of the dynamically sustaining suppression transistor 153 in the second feedback loop 152 via a cross trace. Similarly, the output of the second monostable edge detection circuit 142 is connected to the gate of the dynamically sustaining suppression transistor 153 in the first feedback loop 151.

[0031] In the above connection architecture, the first monostable edge detection circuit 141 and the second monostable edge detection circuit 142 are configured to generate a suppression pulse in response to the input transition edge at the input port, and inject the suppression pulse into the gate of the dynamic sustaining suppression transistor 153 on the opposite side, forcibly turning it off. By using a short pulse to cut off the original static feedback pull at the initial stage of signal transition, a physical time window can be forcibly cleared for subsequent level transitions, eliminating dynamic punch-through current.

[0032] In this embodiment, to minimize steady-state power consumption, the dynamic sustaining suppression transistor 153 in both the first feedback loop 151 and the second feedback loop 152 is a positive-channel metal-oxide-semiconductor field-effect transistor (MOSFET). The weak pull-up transistor 154 also employs a high-threshold, low-drive-capability positive-channel MOSFET. The ratio of the effective channel width to the effective channel length of the weak pull-up transistor 154 is precisely configured to be less than one. Specifically, its effective channel width W is configured to be 120 nm, and its effective channel length L is configured to be a long 800 nm. The gate of the weak pull-up transistor 154 is cross-connected to the output node of the opposite transmission path, its source is connected to the input / output power network 102 to receive a second supply voltage of 3.3 volts, and its drain is connected in series to the source of the dynamic sustaining suppression transistor 153. By employing an extreme width-to-length ratio of 120 nm / 800 nm, this structure can limit the static leakage current of the bidirectional level shifting circuit 100 during the steady-state sustaining phase to an extremely low preset current threshold, improving the overall energy efficiency of the system.

[0033] Example 2: Dynamic Suppression of Pulse Generation and Non-Uniform Process Architecture

[0034] This embodiment further discloses the internal microstructure of the first monostable edge detection circuit 141 and the second monostable edge detection circuit 142. For example... Figure 2As shown, the edge detection circuit not only needs to generate pulses, but also needs to precisely control the pulse's duration. The first monostable edge detection circuit 141 internally includes a delay inverter chain 143 and logic gates.

[0035] The input terminals of the delay inverter chain 143 and the first input terminal of the AND gate are physically connected in parallel to each other, both connected to input port 131a to obtain the original input signal. The output terminal of the delay inverter chain 143 is fed into the second input terminal of the AND gate. The delay inverter chain 143 consists of multiple complementary metal-oxide-semiconductor inverters connected in series. Due to the odd-number cascaded characteristic of the inverters, the delay inverter chain 143 is configured to not only perform intrinsic time delay on the original input signal, but also achieve absolute phase reversal of its polarity. The AND gate is configured such that when a rising edge from low to high occurs at input port 131a, the original input terminal immediately goes high, but due to the blocking effect of the delay inverter chain 143, its output terminal has not yet flipped and remains at the original high level. The AND gate generates a high-level suppression pulse based on these two transient high levels. Once the delay inverter chain 143 completes its delay time and flips to output a low level, the suppression pulse immediately terminates.

[0036] In integrated circuit manufacturing processes, even slight fluctuations in process parameters can easily cause short pulses to be swallowed up or mutated by subsequent parasitic capacitances. To address this issue, in this embodiment, the microstructure of multiple interconnected complementary metal-oxide-semiconductor (CMOS) inverters in the delay inverter chain 143 is configured as a non-uniform array. Specifically, along the signal transmission direction, the physical channel lengths of the metal-oxide-semiconductor (MOSFET) transistors in each CMOS inverter exhibit a progressively increasing arrangement.

[0037] In a preferred embodiment, the arrangement logic of the above-mentioned non-uniform microchannel length is implemented by the following mathematical formula:

[0038]

[0039] Where L0 represents the base channel length of the first complementary metal-oxide-semiconductor inverter in the delay inverter chain 143, which corresponds to the standard process minimum channel length under the first supply voltage domain of 0.8 volts; n is a positive integer variable representing the stage number of subsequent inverters along the signal propagation direction; k represents the increment step size coefficient of the process configuration; L n This represents the calculated channel length of the subsequent nth complementary metal-oxide-semiconductor inverter.

[0040] By employing the aforementioned physical structure arrangement, the charging and discharging current driving capability and the gate parasitic capacitance of each inverter stage gradually change along the signal transmission path. This structure is configured to progressively smooth the slope of the internal signal flipping edges. Through this progressively increasing arrangement, it can effectively resist the process width fluctuations in chip manufacturing, ensuring the waveform integrity of the finally extracted suppression pulse. Under this architecture, the duration of the suppression pulse output by the first monostable edge detection circuit 141 is precisely configured to cover the entire critical cycle of subsequent charge pump conduction. In this embodiment, the total intrinsic propagation delay of the delayed inverter chain 143 is designed to be extracted and locked to 800 picoseconds. Therefore, the final output suppression pulse width of the system is controlled at 800 picoseconds, which is exactly equivalent to the minimum safe window time required to break the high-voltage side lock-up. It should be noted that, depending on different application scenarios and foundry nodes, the above-mentioned k value and 800 picosecond parameter are only examples, and those skilled in the art can perform proportional adaptive scaling to achieve the pulse width protection purpose of this application. To enhance the driving capability for long-distance traces, a pulse shaping buffer is further connected in series at the output of the AND gate. The final output of the pulse shaping buffer is connected to the dynamic sustain suppression transistor 153 as the external output of the detection circuit.

[0041] Example 3: Transient Charge Injection Network and Bootstrap Pumping Mechanism

[0042] To enable the pull-down of high-voltage nodes even under low input voltage, both the first transmission path 131 and the second transmission path 132 include transient charge injection networks. Taking the first transient charge injection network 161 as an example, its core topology includes a bootstrap capacitor 163, a driving transistor 164, and a pre-charge bias transistor 165. In this embodiment, both the driving transistor 164 and the pre-charge bias transistor 165 are high-voltage thick-gate negative-channel metal-oxide-semiconductor field-effect transistors capable of withstanding 3.3-volt high-voltage surges.

[0043] The source of the precharge bias transistor 165 is physically connected to the core logic power network 101 to continuously receive a first supply voltage of 0.8 volts. The drain of the precharge bias transistor 165 is connected to the top plate of the bootstrap capacitor 163 and shares a gate control node with the drive transistor 164. The bottom plate of the bootstrap capacitor 163 is connected to the input port 131a to receive low-voltage signal transitions. The source of the drive transistor 164 is connected to the internal chip ground, and its drain is directly connected to the corresponding node on the output side. This drain node is also directly connected to the drain of the dynamic sustain suppression transistor 153 in the feedback loop to form a common output node.

[0044] In semiconductor manufacturing processes, to achieve extremely high capacitance density per unit area and control leakage current, the bootstrap capacitor 163 preferably employs a metal-insulator-metal capacitor structure, or uses the gate oxide layer of a thick oxide-metal-oxide-semiconductor field-effect transistor as the dielectric layer. Due to limitations imposed by the surrounding wiring environment, this structure inevitably possesses parasitic capacitances at both the first and second plates. The physical layout area of ​​the bootstrap capacitor 163 and the thickness of its internal high-dielectric-constant dielectric layer must be matched and configured based on the gate parasitic capacitance value of the driving transistor 164.

[0045] The specific working mechanism is manifested in a strict time-locking process.

[0046] In the first stage of pre-charge steady state, when input port 131a is in a low voltage steady state of 0 volts, the pre-charge bias transistor 165 is in the on state, and it uses the core logic power supply connected to the source to pre-charge the top plate node of the bootstrap capacitor 163. The top plate voltage is pre-charged to be equal to the bias voltage.

[0047] The second stage is a competition-free pump-up. When the input port 131a experiences a rising transition from 0 volts to 0.8 volts, as mentioned earlier, the first monostable edge detection circuit 141 has already preemptively cut off the feedback pull from the high-voltage side. The input transition edge is coupled through the bottom plate of the bootstrap capacitor 163. Since the charge cannot dissipate instantaneously, the charge redistribution network formed by the bootstrap capacitor 163 and its surrounding parasitic capacitances instantaneously pumps up the voltage of its top plate and controls the drive transistor 164 to conduct deeply.

[0048] Specifically, the system executes voltage boost calculation logic based on the physical laws of energy conservation and charge distribution, that is, it determines the boost peak value based on a network of ratios between the inherent capacitance of the bootstrap capacitor and the total parasitic capacitance of the node. In a preferred embodiment, the above-mentioned transient charge injection logic of the top plate is accurately characterized by the following formula:

[0049]

[0050] Among them, V boost The variable represents the transient overshoot peak voltage that the top plate of the bootstrap capacitor 163 can reach under transient conditions; V ddL The variable represents the nominal value of the first supply voltage provided and pre-charged by the core logic power network 101, which is 0.8 volts in this example; C boot The variable represents the equivalent intrinsic capacitance of the bootstrap capacitor 163 entity, whose actual value is configured as 150 femtofarads; C parasitic The variable represents the parasitic capacitance of the top plate node, which is actually measured to be approximately 20 femtofarads. The variable represents the input voltage increment that triggers the pump; this increment is 0.8 volts when the core logic level flips.

[0051] Substituting the selected process parameters into the formula, the transient overshoot peak voltage V of the top plate of bootstrap capacitor 163 is calculated. boost It can be instantaneously pumped up to approximately 1.5 volts. This 1.5-volt high voltage is configured to pull the gate-source voltage difference of the drive transistor 164 to more than twice its nominal threshold voltage. Under the transient gate bias stimulus of up to 1.5 volts, the drive transistor 164 enters a deep linear conduction region, instantaneously discharging up to 3.3 volts of output node charge to ground, completing a high-speed level transition.

[0052] By constructing a bootstrap capacitor and transient charge injection network, the energy generated during low-voltage input transitions can be used to self-boost the drive gate voltage to a high-voltage level. This structure utilizes a time window, eliminating the need for bulky, large-size negative-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and avoiding the drawback of increased parasitic capacitance in the input stage. It achieves zero short-circuit static power consumption while ensuring high-passband characteristics for bidirectional transmission.

[0053] Example 4: System-on-a-Chip and Application Architecture

[0054] Based on the basic modules described in all the foregoing embodiments, such as Figure 3 As shown, this application further provides a macroscopic integrated circuit chip 300. This integrated circuit chip 300 serves as the core control hub in an automotive electronic system. Its physical architecture includes a logic gate array 310 responsible for core operations, input / output pins 320 responsible for communication with external devices, and a bidirectional level shifting circuit 100 physically deployed on the boundary loop.

[0055] The gate array 310 represents the core computing brain of the chip. To achieve high logic density and low dynamic power consumption, the gate array 310 is forced to operate in a 0.8-volt voltage range and is directly hardwired to the low-voltage side interface network of the bidirectional level shifter circuit 100. The input / output pins 320 are located on the edge of the chip's physical casing, directly exposed to withstand the harsh automotive electromagnetic and surge environment, and are responsible for interfacing with an external 3.3-volt high-voltage bus. The bidirectional level shifter circuit 100 is physically serially configured on the single signal communication path between the gate array 310 and the input / output pins 320.

[0056] Furthermore, to protect the internal precision structure from damage caused by external electrostatic discharge pulses of several kilovolts, an electrostatic discharge (ESD) protection network and a clamping diode 330 are connected in parallel on the side of the signal communication path near the input / output pin 320. Since the bidirectional level shifting circuit 100 provided in this application completely abandons the approach of increasing the size of the driving transistor 164 to gain a short-circuit competitive advantage from the outset, it saves silicon area in its layout and strictly controls the intrinsic capacitance of internal nodes. Therefore, this lightweight switching circuit architecture provides ample process placement space and node parasitic capacitance budget for the externally loaded clamping diode 330.

[0057] In the actual signal communication workflow, when the logic gate array 310 generates low-voltage control message data and outputs it through the communication path, this signal is injected into the input side of the bidirectional level conversion circuit 100, activating the internal first monostable edge detection circuit 141. The generated 800 picosecond short suppression pulse clears the pull-up obstacle caused by the preceding feedback loop in advance. Immediately afterwards, the charge stored in the first transient charge injection network 161 completes the redistribution operation, the top plate pumps up to 1.5 volts, driving the thick-gate negative channel metal-oxide-semiconductor field-effect transistor to completely penetrate the residual charge of the output node, and finally generating a high-speed, high-voltage, steep 3.3-volt command waveform at the input / output pin 320 and sending it to the controller area network. During the silent period, the 120nm / 800nm ​​size weak pull-up transistor maintains a nanoampere-level leakage current latch-up state like a trickle.

[0058] In summary, the integrated circuit chip and bidirectional level conversion circuit provided in this application, by bridging voltage domains and configuring a time-interlocked collaborative mechanism of dynamic sustain suppression pulse and transient charge distribution pump, not only eliminates the power consumption problem caused by shoot-through short-circuit contention during state transitions across voltage domains at its physical root, but also successfully suppresses the parasitic capacitance of the input node to a low level. This solution supports high-speed bidirectional bus data transmission protocols with bandwidths exceeding 100MHz, improving the communication throughput and overall system energy efficiency of the onboard core processor in a heterogeneous bus environment.

Claims

1. A bidirectional level conversion circuit, characterized in that, A bidirectional level shifting circuit is connected between a core logic power network with a first supply voltage and an input / output power network with a second supply voltage. The circuit includes a first transmission path and a second transmission path that are cross-connected. A first monostable edge detection circuit and a second monostable edge detection circuit are located on the input port side. A first feedback loop and a second feedback loop are located on the output side. Both the first and second feedback loops include a dynamically sustaining suppression transistor and a weak pull-up transistor connected in series. The output of the first monostable edge detection circuit is connected to the gate of the dynamically sustaining suppression transistor in the second feedback loop. The output of the second monostable edge detection circuit is connected to the gate of the dynamic sustaining suppression transistor in the first feedback loop; the first and second monostable edge detection circuits are configured to generate a suppression pulse in response to an input transition edge to turn off the opposite dynamic sustaining suppression transistor; both the first and second transmission paths include a transient charge injection network, which includes a bootstrap capacitor, a driving transistor, and a precharge bias transistor; in steady state, the precharge bias transistor precharges the top plate of the bootstrap capacitor to a bias voltage; in response to an input rising transition, the bootstrap capacitor is configured to transiently pump up its top plate voltage and control the driving transistor to be deeply turned on.

2. The bidirectional level conversion circuit according to claim 1, characterized in that, The first monostable edge detection circuit and the second monostable edge detection circuit adopt the same symmetrical structure; the first monostable edge detection circuit includes a delayed inverter chain and a logic AND gate; the input terminal of the delayed inverter chain and the first input terminal of the logic AND gate are connected to the input port side; the output terminal of the delayed inverter chain is connected to the second input terminal of the logic AND gate; the delayed inverter chain includes multiple complementary metal-oxide-semiconductor inverters connected in series; the delayed inverter chain is configured to perform time delay and phase flipping on the input signal; the logic AND gate is configured to generate the suppression pulse based on the original input signal and the delayed and flipped signal.

3. The bidirectional level conversion circuit according to claim 2, characterized in that, The microstructure of the multiple interconnected complementary metal-oxide-semiconductor (CMOS) inverters in the delay inverter chain is configured as a non-uniform array; along the signal transmission direction, the channel lengths of the metal-oxide-semiconductor (MOSFETs) in each CMOS inverter are arranged in a progressively increasing order; the channel length of the first CMOS inverter in the delay inverter chain is defined as the base length value L0; the channel length of the subsequent nth CMOS inverter is configured as... , where n is a positive integer and parameter k is an increment step size coefficient; the basic length value L0 corresponds to the standard process minimum channel length under the first power supply voltage domain; the charging and discharging current driving capability of each inverter changes step by step along the signal transmission path, configured to smooth the slope of the internal signal flipping edge step by step.

4. The bidirectional level conversion circuit according to claim 1, characterized in that, The source of the precharge bias transistor is connected to the core logic power network to receive the first supply voltage, and the drain of the precharge bias transistor is connected to the top plate of the bootstrap capacitor and the gate of the drive transistor. The bottom plate of the bootstrap capacitor is connected to the signal input terminal on the input port side; the source of the driving transistor is connected to the core logic power network, and the drain of the driving transistor is connected to the corresponding node on the output terminal side.

5. The bidirectional level conversion circuit according to claim 4, characterized in that, The bootstrap capacitor adopts a metal-insulator-metal capacitor structure, having a first plate parasitic capacitance and a second plate parasitic capacitance; the physical layout area and internal dielectric layer thickness of the bootstrap capacitor are configured based on the gate parasitic capacitance value of the driving transistor; specifically, the inherent capacitance value C of the bootstrap capacitor is configured as follows: b The capacitance value is greater than or equal to a preset capacitance threshold, which is determined by the gate parasitic capacitance value C of the driving transistor. g The parasitic capacitance value C of the first electrode plate p1 and the first power supply voltage V ddL Second supply voltage V ddH The ratio is jointly determined; at the instant of the input jump at the bottom plate, it is determined by the inherent capacitance value C. b Gate parasitic capacitance C g and the parasitic capacitance value C of the first plate p1 The charge redistribution network constitutes a transient boost to the voltage of the top plate, configured to raise the gate-source voltage difference of the driving transistor to more than twice its nominal threshold voltage.

6. The bidirectional level conversion circuit according to claim 1, characterized in that, The first transmission path and the second transmission path are arranged in a symmetrical differential cross-coupled topology in the layout; the transistor arrays in the first transmission path and the transistor arrays in the second transmission path are configured in a consistent ratio in terms of physical size and spacing; the bidirectional level conversion circuit does not include a direction enable control pin and is configured to adaptively identify the bidirectional signal transmission direction based on the drive strength of the physical level at the pin.

7. The bidirectional level conversion circuit according to claim 6, characterized in that, Both the weak pull-up transistors in the first and second feedback loops are positive-channel metal-oxide-semiconductor field-effect transistors; the ratio of the effective channel width to the effective channel length of the weak pull-up transistor is configured to be less than one; the effective channel width is configured to be 120 nanometers, and the effective channel length is configured to be 800 nanometers; the gate of the weak pull-up transistor is cross-connected to the output node of the opposite transmission path, the source of the weak pull-up transistor is connected to the input / output power network to receive the second supply voltage, and the drain of the weak pull-up transistor is connected in series to the source of the dynamic sustain suppression transistor; The static leakage current of the bidirectional level conversion circuit during the steady-state maintenance phase is limited to a preset current threshold.

8. The bidirectional level conversion circuit according to claim 1, characterized in that, The first supply voltage and the second supply voltage belong to different voltage domain configurations; the nominal value of the first supply voltage configured in the core logic power network is 0.8 volts; the nominal value of the second supply voltage configured in the input / output power network is 3.3 volts.

9. The bidirectional level conversion circuit according to claim 1, characterized in that, The drain of the dynamically sustaining suppression transistor is directly connected to the drain of the driving transistor to form a common output node; the duration of the suppression pulse is configured to cover the time period during which the transient charge injection network turns on the driving transistor.

10. An integrated circuit chip, characterized in that, Includes a bidirectional level conversion circuit as described in any one of claims 1 to 9.

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