Level shifting circuit and related apparatus

Abstract

A level conversion circuit and related device, the level conversion circuit comprises: a transition signal generation module, for generating a transition signal based on an input signal, wherein the high level voltage of the transition signal is greater than the high level voltage of the input signal; an output signal generation module connected to the transition signal generation module, for generating a first output signal and a second output signal based on the transition signal; the output signal generation module comprises a control signal generation unit, and a pull-up unit and a pull-down unit connected to the control signal generation unit; wherein the control signal generation unit is used for generating a first control signal based on the transition signal, and the pull-up unit and the pull-down unit respectively execute a signal processing flow based on the first control signal to generate a first output signal and a second output signal. The level conversion circuit can ensure the output quality of high frequency signals.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a level conversion circuit and related equipment. Background Technology

[0002] A level shifter circuit is an interface circuit used to convert signal levels between circuits with different power supply voltage levels, ensuring signal transmission between different voltage domains. For example, in integrated circuit systems, core logic units typically operate at lower voltages, while input / output units typically operate at higher voltages. In this case, a level shifter circuit is needed to convert a logic signal with a higher voltage level (input signal) into a logic signal with a higher voltage level (output signal).

[0003] However, for high-frequency signal transmission, the signal output quality of the corresponding level conversion circuit needs to be improved. Summary of the Invention

[0004] This disclosure provides a level conversion circuit and related equipment that can guarantee the output quality of high-frequency signals.

[0005] To address the above problems, this disclosure provides a level conversion circuit, comprising:

[0006] A transition signal generation module is used to generate a transition signal based on an input signal, wherein the high-level voltage of the transition signal is greater than the high-level voltage of the input signal;

[0007] The output signal generation module connected to the transition signal generation module is used to generate a first output signal and a second output signal based on the transition signal, wherein the high-level voltage of the first output signal is greater than the high-level voltage of the transition signal;

[0008] The output signal generation module includes a control signal generation unit, and a pull-up unit and a pull-down unit connected to the control signal generation unit; wherein, the control signal generation unit is used to generate a first control signal based on the transition signal, and the pull-up unit and the pull-down unit respectively execute a signal processing flow based on the first control signal to generate a first output signal and a second output signal.

[0009] Optionally, it further includes: a clamping module connected to the transition signal generation module, used to clamp the first voltage output by the first voltage source to a second voltage, the second voltage being less than the first voltage; the first voltage source is used to provide the first voltage to the level conversion circuit, and the clamping module is used to provide the second voltage to the transition signal generation module.

[0010] Optionally, the clamping module includes a clamping transistor, the drain of which receives the first voltage, the source of which is connected to the transition signal generation module, and the gate of which receives a first voltage divider. The first voltage divider is used to control the clamping transistor to turn on and to cause the drain to output a second voltage with a preset potential.

[0011] Optionally, the transition signal generation module includes a first signal generation unit and a power consumption control unit; wherein, the first signal generation unit is used to generate a transition signal based on the input signal; and the power consumption control unit is used to control the first signal generation unit to input or disable the input of the second voltage based on the transition signal.

[0012] Optionally, the first signal generation unit includes a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, and a first inverter;

[0013] The source terminal of the first pull-up transistor is used to input a second voltage, and its drain terminal is connected to the drain terminal of the first pull-down transistor via a first node; the gate terminal of the first pull-down transistor is used to input the input signal, and its source terminal is grounded; the source terminal of the second pull-up transistor is used to input a second voltage, and its drain terminal and gate terminal are connected and connected to the drain terminal of the second pull-down transistor via a second node; the gate terminal of the second pull-down transistor is used to input a second control signal, and its source terminal is grounded; the input terminal of the first inverter is connected to the first node;

[0014] The second control signal is used to turn on the second pull-down transistor during the signal pull-up phase and turn off the second pull-down transistor during the signal pull-down phase.

[0015] Optionally, the power consumption control unit includes: a NOR cell and a second inverter;

[0016] The input terminal of the second inverter is used to input a transition signal, and the output terminal is connected to one input terminal of the NOR unit; the other input terminal of the NOR unit is used to input the input signal, and the output terminal is used to output a second control signal.

[0017] Optionally, the transition signal generation module further includes a first signal compensation unit, which is used to perform signal compensation on the first signal generation unit;

[0018] The first signal compensation unit includes a first signal compensation transistor, the source terminal of which is used to input a second voltage, the drain terminal is connected to a first node, and the gate terminal is used to input a transition signal.

[0019] Optionally, the control signal generation unit includes a third inverter, a third pull-up transistor, a fourth pull-up transistor, a first voltage divider transistor, a second voltage divider transistor, a third voltage divider transistor, and a fourth voltage divider transistor.

[0020] The input terminal of the third inverter is used to input the transition signal and output the first control signal;

[0021] The source terminal of the third pull-up transistor is used to input the first voltage, and the drain terminal is connected to the source terminal of the first voltage divider transistor via the third node; the drain terminal of the first voltage divider transistor is connected to the drain terminal of the second voltage divider transistor; the source terminal of the second voltage divider transistor is connected to the output terminal of the third inverter via the fifth node.

[0022] The source terminal of the fourth pull-up transistor is used to input a first voltage, and its drain terminal is connected to the source terminal of the third voltage divider transistor via a fourth node; the drain terminal of the third voltage divider transistor is connected to the drain terminal of the fourth voltage divider transistor; the source terminal of the fourth voltage divider transistor is used to input a third control signal.

[0023] The gate terminals of the third and fourth pull-up transistors are connected to the fourth node, and the fifth and third nodes are used to output a first control signal; the gate terminals of the first and third voltage divider transistors are used to input a second voltage divider, and the gate terminals of the second and fourth voltage divider transistors are used to input a first voltage divider; the third control signal is used to pull the fourth node down to a low level during the signal pull-up phase to turn on the third and fourth pull-up transistors, and to pull the fourth node up to a high level during the signal pull-down phase to turn off the third and fourth pull-up transistors.

[0024] Optionally, the output signal generation module further includes a signal adjustment unit, which generates a third control signal with a preset signal length to control the signal lengths of the first output signal and the second output signal.

[0025] Optionally, the signal adjustment unit includes a signal buffer and a NAND unit, wherein the signal buffer is used to delay the input signal to the output terminal by a preset time length;

[0026] The input terminal of the signal buffer is used to input the first output signal, and the output terminal is connected to one input terminal of the NAND unit; the other input terminal of the NAND unit is used to connect to the fifth node, and the output terminal is used to output the third control signal.

[0027] Optionally, the output signal generation module further includes a second signal compensation unit, which is used to perform signal compensation on the control signal generation unit;

[0028] The second signal compensation unit includes a second signal compensation transistor. The source terminal of the second signal compensation transistor is used to input a first voltage, the drain terminal is connected to a third node, and the gate terminal is used to input a first output signal.

[0029] Optionally, the output signal generation module further includes a voltage divider unit located between the pull-up unit and the pull-down unit, the voltage divider unit being used to divide the voltage for the first output signal and the second output signal.

[0030] Optionally, the pull-up unit includes a fifth pull-up transistor, and the pull-down unit includes a fifth pull-down transistor; the voltage divider unit includes a fifth voltage divider transistor and a sixth voltage divider transistor connected in series.

[0031] The source of the fifth pull-up transistor receives the first voltage, its drain is connected to the fifth voltage divider transistor via the sixth node, and its gate is used to input the first control signal of the third node; the drain of the fifth voltage divider transistor is connected to the drain of the sixth voltage divider transistor, and its gate is used to input the second voltage divider; the source of the sixth voltage divider transistor is connected to the drain of the fifth pull-down transistor via the seventh node, and its gate is used to input the first voltage divider; the source of the fifth pull-down transistor is grounded, and its gate is used to input the first control signal of the fifth node.

[0032] The sixth node is connected to the first output terminal and is used to output the first output signal; the seventh node is connected to the second output terminal and is used to output the second output signal.

[0033] Optionally, it also includes: a voltage divider generation module, which is used to generate a first voltage divider and a second voltage divider;

[0034] The voltage divider generation module includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor, as well as a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and a fourth voltage divider resistor.

[0035] The source of the first control transistor is input with a first voltage, and its drain is connected to one end of the first voltage divider resistor; the other end of the first voltage divider resistor is connected to one end of the second voltage divider resistor; the other end of the second voltage divider resistor is grounded; the node between the first voltage divider resistor and the second voltage divider resistor is designated as the eighth node, and this eighth node is used to output the second voltage divider voltage; the drain of the third control transistor is connected to the eighth node, and its source is grounded.

[0036] One end of the third voltage divider resistor is input with the first voltage, and the other end is connected to one end of the fourth voltage divider resistor; the other end of the fourth voltage divider resistor is connected to the drain of the second control transistor; the source of the second control transistor is grounded, and the node between the third and fourth voltage divider resistors is the ninth node, which is used to output the first voltage divider voltage; the source of the fourth control transistor is connected to the first voltage, and the drain is connected to the ninth node.

[0037] This disclosure also provides a chip configured with the level conversion circuit described in this disclosure.

[0038] This disclosure also provides an electronic device, including the chip described in this disclosure.

[0039] Compared with the prior art, the technical solution of the present disclosure has the following advantages:

[0040] This disclosure provides a level conversion circuit and related devices. The level conversion circuit includes a transition signal generation module for generating a transition signal based on an input signal, wherein the high-level voltage of the transition signal is greater than the high-level voltage of the input signal; an output signal generation module connected to the transition signal generation module for generating a first output signal and a second output signal based on the transition signal, wherein the high-level voltage of the first output signal is greater than the high-level voltage of the transition signal; the output signal generation module includes a control signal generation unit, and a pull-up unit and a pull-down unit connected to the control signal generation unit; wherein the control signal generation unit is used to generate a first control signal based on the transition signal, and the pull-up unit and the pull-down unit respectively execute a signal processing flow based on the first control signal to generate the first output signal and the second output signal.

[0041] As can be seen, in the level conversion circuit of this embodiment, during the generation of the output signal, the signal pull-up / pull-down processing flow is executed respectively by the first control signal obtained based on the transition signal to generate the first output signal and the second output signal. Thus, the pull-up and pull-down processes can be independently controlled based on the first control signal, avoiding the influence of the output signal on the control signal, thereby avoiding defects such as steps in the output signal and ensuring the output quality of the high-frequency signal. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the circuit structure of a level conversion circuit;

[0043] Figure 2 This is a schematic diagram of an optional frame structure of the level conversion circuit provided in this disclosure.

[0044] Figure 3This is a schematic diagram of another optional framework structure of the level conversion circuit provided in this disclosure.

[0045] Figure 4 This is a schematic diagram of the circuit structure of the level conversion circuit provided in this technical solution. Detailed Implementation

[0046] As described in the background section, a level shifter circuit is an interface circuit used to convert signal levels between circuits with different power supply voltage levels, ensuring that signals are transmitted between different voltage domains.

[0047] by Figure 1 Taking a level conversion circuit as an example, this circuit is used to generate two sets of output signals with different output ranges based on the input signal IN: a low-voltage output signal OUTL and a high-voltage output signal OTH. The low-voltage output signal OUTL can be, for example, an output signal with a low voltage level of 0 volts and a high voltage level of 1.8 volts, while the high-voltage output signal can be, for example, an output signal with a low voltage level of 1.5 volts and a high voltage level of 3.3 volts.

[0048] In the above scheme, the voltage divider unit composed of voltage divider transistors PM3, PM4, NM1, and NM2 (where PM represents a PMOS transistor and NM represents an NMOS transistor) is used to control the voltage range of the output signal. The pull-up unit composed of pull-up transistors PM1 and PM2 and the pull-down unit composed of pull-down transistors NM3 and NM4 are used to control the pull-up and pull-down of the signal. However, the inventors believe that the signal processing flow of the pull-up and pull-down units in this level conversion circuit makes it difficult to guarantee the waveform quality of the output signal. After further analysis, the inventors believe that in this level conversion circuit, the control signal corresponding to the pull-up unit needs to be generated based on the output signal IN, which causes the control signal and the output signal to interfere with each other, making it difficult to guarantee the output signal quality in high-frequency signal transmission scenarios.

[0049] Still with Figure 1For example, when the input signal IN is at a high level, the pull-up transistor PM2 in the pull-up unit is turned on, and the pull-down transistor NM4 in the pull-down unit is turned off, so that both the high-voltage output signal and the low-voltage output signal are at a high level. However, when the input signal IN changes from a high level to a low level, the input signal needs to be flipped to a low level by the inverter INV, thereby controlling the pull-down transistor NM4 to turn on, causing the low-voltage output signal OUTL to be pulled down to a low level. Then, the second node net2 is pulled down accordingly, and the high-voltage output signal OUTH is also pulled down accordingly. However, since the pull-up transistor PM2 is still turned on, the high-voltage output signal OUTH will only be pulled down partially to form an intermediate potential. At this time, the intermediate potential of the high-voltage output signal OUTH further serves as the first pull-up control signal to turn on the pull-up transistor PM1, and causes the potential of the first node net1 to be pulled up to a high level, which in turn serves as the second pull-up control signal to turn off the pull-up transistor PM2, thereby causing the high-voltage output signal OUTH to be pulled down to a preset low level voltage based on the turned-on pull-down transistor NM4.

[0050] Obviously, in the above signal processing flow, when the high-voltage output signal OTH changes from a high-level potential to a low-level potential, it will form a brief intermediate potential as a control signal. This intermediate potential is represented as a step in the signal waveform. The appearance of this step defect can be understood as the signal output quality being low.

[0051] To address the aforementioned problems, this disclosure provides a level conversion circuit and related equipment. The level conversion circuit includes a transition signal generation module for generating a transition signal based on an input signal, wherein the high-level voltage of the transition signal is greater than the high-level voltage of the input signal; an output signal generation module connected to the transition signal generation module for generating a first output signal and a second output signal based on the transition signal, wherein the high-level voltage of the first output signal is greater than the high-level voltage of the transition signal; the output signal generation module includes a control signal generation unit, and a pull-up unit and a pull-down unit connected to the control signal generation unit; wherein the control signal generation unit generates a first control signal based on the transition signal, and the pull-up unit and the pull-down unit respectively execute signal processing procedures based on the first control signal to generate the first output signal and the second output signal.

[0052] As can be seen, in the level conversion circuit of this embodiment, during the generation of the output signal, the signal pull-up / pull-down processing flow is executed respectively by the first control signal obtained based on the transition signal to generate the first output signal and the second output signal. Thus, the pull-up and pull-down processes can be independently controlled based on the first control signal, avoiding the influence of the output signal on the control signal, thereby avoiding defects such as steps in the output signal and ensuring the output quality of the high-frequency signal.

[0053] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0054] First, it should be noted that in this embodiment, the voltage value is a signless voltage value, that is, the absolute value of the voltage. The specific signal typically includes a high-level voltage with a larger value and a low-level voltage with a smaller value. The signal content is characterized by the change between the high-level and low-level voltages. A low-level potential signal can be understood as the digital signal "0", and a high-level potential signal can be understood as the digital signal "1".

[0055] Figure 2 This is a schematic diagram of an optional frame structure of the level conversion circuit provided in this disclosure. Figure 3 This is a schematic diagram of another optional framework structure of the level conversion circuit provided in this disclosure. Figure 4 This is a schematic diagram of the circuit structure of the level conversion circuit provided in this technical solution.

[0056] refer to Figure 2 This disclosure provides a level conversion circuit, which includes a transition signal generation module for generating a transition signal based on an input signal, wherein the high-level voltage of the transition signal is greater than the high-level voltage of the input signal; an output signal generation module connected to the transition signal generation module for generating a first output signal and a second output signal based on the transition signal, wherein the high-level voltage of the first output signal is greater than the high-level voltage of the transition signal; the output signal generation module includes a control signal generation unit, and a pull-up unit and a pull-down unit connected to the control signal generation unit; wherein the control signal generation unit is used to generate a first control signal based on the transition signal, and the pull-up unit and the pull-down unit respectively execute a signal processing flow based on the first control signal to generate the first output signal and the second output signal.

[0057] In conjunction with the foregoing, the level conversion circuit in this embodiment of the present disclosure, during the generation of the output signal, executes the signal pull-up / pull-down processing flow respectively through the first control signal obtained based on the transition signal to generate the first output signal and the second output signal. This enables independent control of the pull-up and pull-down processes based on the first control signal, avoiding the influence of the output signal on the control signal, thereby avoiding defects such as steps in the output signal and ensuring the output quality of the high-frequency signal.

[0058] In the optional example, refer to Figure 3 The level conversion circuit of this embodiment further includes a clamping module connected to the transition signal generation module, used to clamp the first voltage output by the first voltage source to a second voltage, the second voltage being less than the first voltage; the first voltage source is used to provide the first voltage to the level conversion circuit, and the clamping module is used to provide the second voltage to the transition signal generation module.

[0059] It is understood that the clamping module is used to provide intermediate power to the level conversion circuit. Specifically, it clamps the first voltage output from the first voltage source to a second voltage, thereby outputting an intermediate power supply with the second voltage. In an optional example, the rated voltage of the first voltage can be, for example, 3.3 volts, and the rated voltage of the second voltage can be, for example, 1.8 volts. It should be noted that the rated voltage can be understood as the voltage value under ideal conditions. In actual circuits, the corresponding actual voltage may fluctuate within a preset range. The voltage within this fluctuation range can be understood as the corresponding first and second voltages. This preset range fluctuation is, for example, less than or equal to 30%, 50%, 70%, etc., of the rated voltage. That is, taking a preset range less than or equal to 30% of the rated voltage as an example, the corresponding preset range fluctuates around the rated voltage by 30%.

[0060] It should be noted that the output signal generation module of this embodiment performs corresponding signal processing control based on the transition signal to generate the corresponding first output signal and second output signal, without placing excessive demands on the driving capability of the power supply. This allows the clamping module in this embodiment to clamp the first voltage to obtain the second voltage as an intermediate power supply, thereby eliminating the need for complex external power supply circuits or independent power conversion circuits to provide a power supply with strong driving capability, and reducing the complexity of the circuit.

[0061] In specific examples, refer to Figure 4 The clamping module 210 may include a clamping transistor NM3, the drain of which receives the first voltage VDDIO, the source of which is connected to the transition signal generation module 220, and the gate of which is used to input the first voltage divider voltage V. REFNThe first voltage divider V REFN The second voltage VDDL, used to control the clamping transistor NM3 to turn on and to output a preset potential at the drain, is used in a specific example. The first voltage divider voltage V... REFN Based on the first voltage VDDIO output from the first voltage source, a corresponding first voltage divider voltage V is generated when the first voltage source is turned on. REFN Therefore, based on the first voltage divider V REFN The clamping transistor NM3 is controlled to be normally open. In this specific example, the clamping transistor is an NMOS transistor.

[0062] The transition signal generation module 220 is used to boost the high-level voltage of the input signal IN, thereby using the second voltage VDDL as a voltage source to generate a transition signal INN_L with a high-level voltage greater than that of the input signal. Then, in the subsequent signal processing flow of the circuit, the output signal generation process is further executed based on the transition signal INN_L.

[0063] In an optional example, the rated voltage of the high-level voltage of the input signal IN can be, for example, 1.8 volts, and the rated voltage of the high-level voltage of the transition signal INN_L can be, for example, 2.5 volts. Similarly, the rated voltage can be understood as the voltage value under ideal conditions. In actual circuits, the corresponding actual voltage may fluctuate within a preset range. Voltages within this fluctuation range can be understood as the high-level voltage of the corresponding input signal and the high-level voltage of the transition signal. This preset range fluctuation is, for example, less than or equal to 30%, 50%, 70%, etc., of the rated voltage. That is, taking a preset range less than or equal to 30% of the rated voltage as an example, the corresponding preset range fluctuates around the rated voltage by 30%.

[0064] In the optional implementation, continue to refer to Figure 4 The transition signal generation module 220 may include a first signal generation unit (not shown in the figure) and a power consumption control unit 221. The first signal generation unit generates a transition signal INN_L based on the input signal IN; the power consumption control unit controls the first signal generation unit to input or disable the input of the second voltage VDDL based on the transition signal INN_L.

[0065] The first signal generation unit may include a first pull-up transistor PM3, a second pull-up transistor PM4, a first pull-down transistor NM4, a second pull-down transistor NM5, and a first inverter INV1;

[0066] The first pull-up transistor PM3 and the first pull-down transistor NM4 are connected in series, the second pull-up transistor PM4 and the second pull-down transistor NM5 are connected in series, the gate terminals of the first pull-up transistor PM3 and the second pull-up transistor PM4 are connected, the node between the first pull-up transistor PM3 and the first pull-down transistor NM4 is designated as the first node N1, the node between the second pull-up transistor PM4 and the second pull-down transistor NM5 is designated as the second node N2, and the input terminal of the first inverter INV1 is connected to the first node N1;

[0067] Specifically, the source of the first pull-up transistor PM3 is used to input the second voltage VDDL, and its drain is connected to the drain of the first pull-down transistor NM4 via the first node N1; the gate of the first pull-down transistor NM4 is used to input the input signal IN, and its source is grounded (grounded means connected to the GND signal); the source of the second pull-up transistor PM4 is used to input the second voltage VDDL, and its drain and gate are connected and connected to the drain of the second pull-down transistor NM5 via the second node N2; the gate of the second pull-down transistor NM5 is used to input the second control signal C2, and its source is grounded. The second control signal C2 is used to turn on the second pull-down transistor NM5 during the signal pull-up phase and turn it off during the signal pull-down phase.

[0068] In the specific signal transmission process, when the input signal IN is a low-level voltage, the first signal generation unit is in the signal pull-up stage. Correspondingly, the second pull-down transistor NM5 is turned on under the control of the second control signal C2, making the second node N2 low-level, thereby controlling the second pull-up transistor PM4 and the first pull-up transistor PM3 to turn on. At this time, the first pull-down transistor NM4 is turned off under the control of the input signal IN, making the first node N1 high-level, and outputting a low-level transition signal INN_L after being inverted by the first inverter INV1.

[0069] In the specific signal transmission process, when the input signal IN is a high-level voltage, the first signal generation unit is in the signal pull-down stage. Correspondingly, the second pull-down transistor NM5 is turned off under the control of the second control signal C2, making the second node N2 high-level, thereby controlling the second pull-up transistor PM4 and the first pull-up transistor PM3 to turn off. At this time, the first pull-down transistor NM4 is turned on under the control of the input signal, making the first node N1 low-level, and outputting a high-level transition signal INN_L after being inverted by the first inverter INV1.

[0070] In an optional example, the first pull-up transistor PM3 and the second pull-up transistor PM4 are of the same conductivity type, namely PMOS transistors, and the first pull-down transistor NM4 and the second pull-down transistor NM5 are of the same conductivity type, namely NMOS transistors. The second control signal C2 can be the inverted signal of the input signal (i.e., the signal obtained after the original signal is inverted). For example, a control signal inverter is set to input the input signal, and the output terminal of the control signal inverter is connected to the gate terminal of the second pull-down transistor NM5.

[0071] For further optional examples, please refer to [link / reference]. Figure 4 The second control signal C2 can also be generated based on the power consumption control unit 221, thereby controlling the power consumption of the first signal generation unit based on the power consumption control unit 221.

[0072] In a specific example, the power consumption control unit 221 may include: a NOR cell D1 and a second inverter INV2 connected to an input terminal of the NOR cell D1.

[0073] Specifically, the input terminal of the second inverter INV2 is used to input the transition signal INN_L, and the output terminal is connected to one input terminal of the NOR unit D1; the other input terminal of the NOR unit D1 is used to input the input signal IN, and the output terminal is used to output the second control signal C2.

[0074] In the specific signal transmission process, when the input signal IN flips from a high level voltage to a low level voltage, the first signal generation unit enters the signal pull-up stage. The first pull-down transistor NM4 is turned off under the control of the input signal IN. The potential of the first node N1 is still at a low level potential. After being inverted by the first inverter INV1, a high-level transition signal INN_L is obtained. After being inverted again by the second inverter INV2, a low-level potential is formed and input to one input terminal of the NOR unit D1. The other input terminal of the NOR unit D1 receives the low-level input signal IN. At this time, it can be understood that both input terminals of the NOR unit D1 are "0". In the corresponding NOR logic, the output should be "1". Accordingly, the NOR unit D1 outputs a high level potential, turning on the second pull-down transistor NM5.

[0075] After the first signal generation unit enters the signal pull-up stage, the first node N1 becomes a high-level potential. The transition signal INN_L, after being flipped by the first inverter INV1, becomes a low-level potential. After being further flipped by the second inverter INV2 to form a high-level potential input to the NOR unit D1, one input terminal of the NOR unit D1 is "0" and the other input terminal is "1". In the corresponding NOR logic, the output should be "0". Accordingly, the NOR unit D1 outputs a low-level potential, and the second pull-down transistor NM5 is turned off under the control of the low-level potential. At this time, the potential of the second node N2 is pulled up to a high-level potential, thereby controlling the second pull-up transistor PM4 and the first pull-up transistor PM3 to turn off, thereby preventing the first signal generation unit from inputting the second voltage and reducing the power consumption of the first signal generation unit.

[0076] In the specific signal transmission process, when the input signal IN flips from a low level voltage to a high level voltage, the first signal generation unit enters the signal pull-down stage. The first pull-down transistor NM4 is turned on under the control of the input signal IN, and the potential of the first node N1 is pulled down to a low level potential. After being flipped by the first inverter INV1, a high-level transition signal INN_L is obtained. After being inverted again by the second inverter INV2, a low-level potential is formed and input to one input terminal of the NOR unit D1. The other input terminal of the NOR unit D1 receives the high-level input signal IN. At this time, it can be understood that one input terminal of the NOR unit D1 is "1" and the other input terminal is "0". In the corresponding NOR logic, the output should be "0". Accordingly, the NOR unit D1 outputs a low level potential, keeping the second pull-down transistor NM5 in the off state, further preventing the first signal generation unit from inputting the second voltage VDDL, and reducing the power consumption of the first signal generation unit.

[0077] As can be seen, by setting the power consumption control unit 221, the first signal generation unit can be controlled to shut down in a timely manner, that is, the second voltage VDDL is no longer input, thereby reducing the power consumption of the device.

[0078] In an optional implementation, the transition signal generation module 220 may further include a first signal compensation unit (not shown in the figure), which is used to perform signal compensation on the first signal generation unit.

[0079] In a specific example, the first signal compensation unit may include a first signal compensation transistor PM5, the source terminal of the first signal compensation transistor PM5 is used to input a second voltage, the drain terminal is connected to the first node N1, and the gate terminal is used to input a transition signal INN_L.

[0080] In the specific signal transmission process, when the first signal generation unit is in the signal pull-up phase, the first node N1 is at a high level. After being flipped by the first inverter INV1, it forms a low-level transition signal INN_L. At this time, the first signal compensation transistor PM5 is turned on based on the control of the transition signal INN_L to maintain the high-level potential state of the first node N1. Conversely, when the first signal generation unit is in the signal pull-down phase, the first node N1 is at a low level. After being flipped by the first inverter INV1, it forms a high-level transition signal INN_L. At this time, the first signal compensation transistor PM5 is turned off based on the control of the transition signal INN_L to maintain the low-level potential state of the first node N1.

[0081] In a specific example, the first signal compensation transistor is a PMOS transistor.

[0082] As can be seen, in this embodiment, while using the power consumption control unit to reduce the power consumption of the device, the first signal compensation unit is used to compensate for the signal of the power consumption control unit, so as to compensate for the device consumption of the first pull-up transistor PM3 and the first pull-down transistor NM4 or the potential deficiency caused by leakage of the device, thereby reducing possible signal transmission errors.

[0083] The output signal generation module 230 is used to generate a first output signal OTH and a second output signal OUTL based on the transition signal INN_L. Specifically, the first output signal OTH can be used to output a high-voltage output signal, and the second output signal OUTL can output a low-voltage output signal.

[0084] In an optional example, the rated voltage of the high-level voltage of the first output signal OUTH can be, for example, 3.3 volts, and the rated voltage of the high-level voltage of the second output signal OUTL can be, for example, 1.8 volts. Similarly, the rated voltage can be understood as the voltage value under ideal conditions. In actual circuits, the corresponding actual voltage may fluctuate within a preset range. The voltage within this fluctuation range can be understood as the high-level voltage of the corresponding input signal IN and the high-level voltage of the transition signal INN_L. This preset range fluctuation is, for example, less than or equal to 30%, 50%, 70%, etc. of the rated voltage. That is, taking a preset range less than or equal to 30% of the rated voltage as an example, the corresponding preset range fluctuates around the rated voltage by 30%.

[0085] In an optional implementation, the output signal generation module 230 includes a control signal generation unit, and a pull-up unit and a pull-down unit connected to the control signal generation unit; wherein, the control signal generation unit is used to generate a first control signal INP_L based on the transition signal INN_L, and the pull-up unit and the pull-down unit respectively perform signal processing based on the first control signal INP_L to generate a first output signal OTH and a second output signal OUTL.

[0086] In an optional implementation, the control signal generation unit includes a third inverter INV3; the input terminal of the third inverter INV3 is used to input the transition signal INN_L and output the first control signal INP_L; wherein, the third inverter INV3 is powered based on the second voltage VDDL.

[0087] In the specific signal transmission process, when the transition signal INN_L is a low-level voltage, the control signal generation unit corresponds to the signal pull-up stage, and the third inverter INV3 flips the transition signal INN_L to a high-level first control signal INP_L; when the transition signal INN_L is a high-level voltage, the control signal generation unit corresponds to the signal pull-down stage, and the third inverter INV3 flips the transition signal INN_L to a low-level first control signal INP_L.

[0088] In a further example, the control signal generation unit further includes a third pull-up transistor PM7, a fourth pull-up transistor PM8, a first voltage divider transistor PM9, a second voltage divider transistor NM6, a third voltage divider transistor PM10, and a fourth voltage divider transistor NM7.

[0089] The third pull-up transistor PM7, the first voltage divider transistor PM9, and the second voltage divider transistor NM6 are connected in series to the third inverter INV3. The fourth pull-up transistor PM8, the third voltage divider transistor PM10, and the fourth voltage divider transistor NM7 are connected in series to the output terminal of the third control signal C3. The gate terminals of the first voltage divider transistor PM9 and the third voltage divider transistor PM10 are connected, and the gate terminals of the second voltage divider transistor NM6 and the fourth voltage divider transistor NM7 are connected. The node between the third pull-up transistor PM7 and the first voltage divider transistor PM9 is designated as the third node N3, the node between the fourth pull-up transistor PM8 and the third voltage divider transistor PM10 is designated as the fourth node N4, and the node between the second voltage divider transistor NM6 and the third inverter INV3 is designated as the fifth node N5. The gate terminals of the third pull-up transistor PM7 and the fourth pull-up transistor PM8 are connected to the fourth node N4. The fifth node N5 and the third node N3 are used to input the first control signal INP_L.

[0090] The third control signal C3 is used to pull down the fourth node N4 to a low level during the signal pull-up phase to turn on the third pull-up transistor PM7 and the fourth pull-up transistor PM8, and to pull up the fourth node N4 to a high level during the signal pull-down phase to turn off the third pull-up transistor PM7 and the fourth pull-up transistor PM8.

[0091] Specifically, the source of the third pull-up transistor PM7 is used to input the first voltage VDDIO, and its drain is connected to the source of the first voltage divider transistor PM9 via the third node N3; the drain of the first voltage divider transistor PM9 is connected to the drain of the second voltage divider transistor NM6; and the source of the second voltage divider transistor NM6 is connected to the output of the third inverter INV3 via the fifth node N5.

[0092] The source of the fourth pull-up transistor PM8 is used to input the first voltage VDDIO, and its drain is connected to the source of the third voltage divider transistor PM10 via the fourth node N4; the drain of the third voltage divider transistor PM10 is connected to the drain of the fourth voltage divider transistor NM7; the source of the fourth voltage divider transistor NM7 is used to input the third control signal C3.

[0093] The gate terminals of the first voltage divider transistor PM9 and the third voltage divider transistor PM10 are used to input the second voltage divider voltage V. REFP This enables the first voltage divider transistor PM9 and the third voltage divider transistor PM10 to turn on; the gate terminals of the second voltage divider transistor NM6 and the fourth voltage divider transistor NM7 are used to input the first voltage divider voltage V. REFN This enables the second voltage divider transistor NM6 and the fourth voltage divider transistor NM7 to turn on.

[0094] Based on the foregoing description, the first voltage divider voltage V REFN Based on the first voltage VDDIO output from the first voltage source, a corresponding first voltage divider voltage V is generated when the first voltage source is turned on. REFN Therefore, based on the first voltage divider V REFN It can control the second voltage divider transistor NM6 and the fourth voltage divider transistor NM7 to be normally open.

[0095] In a specific example, the second voltage divider voltage V REFP Similarly, the first voltage VDDIO output from the first voltage source can be used to generate the corresponding second voltage divider V when the first voltage source is turned on. REFP Therefore, based on the second voltage divider V REFP The first voltage divider transistor PM9 and the third voltage divider transistor PM10 are controlled to be normally open.

[0096] In the specific signal transmission process, when the transition signal INN_L is a low level voltage, the control signal generation unit corresponds to the signal pull-up stage. Correspondingly, the third inverter INV3 flips the transition signal INN_L to a high level voltage first control signal INP_L, and the fifth node N5 and the third node N3 output a high level potential first control signal INP_L.

[0097] The further signal processing flow during the signal pull-up phase is the state establishment phase of the level conversion circuit, used to maintain the first control signal INP_L. The third control signal C3 can be a low-level voltage. At this time, the third control signal C3 pulls down the fourth node N4 to a low-level potential, thereby turning on the third pull-up transistor PM7 and the fourth pull-up transistor PM8, so that the third node N3 is pulled up and maintained at a high-level potential, and the fifth node N5 is maintained at a high-level potential.

[0098] In the specific signal transmission process, when the transition signal INN_L is a high-level voltage, the control signal generation unit corresponds to the signal pull-down stage. Correspondingly, the third inverter INV3 flips the transition signal INN_L to a low-level voltage, and the fifth node N5 and the third node N3 output a low-level first control signal INP_L.

[0099] The further signal processing flow in the signal pull-down stage is the state establishment stage of the level conversion circuit, used to maintain the first control signal INP_L. The third control signal C3 can be a high-level voltage. At this time, the third control signal C3 pulls the fourth node N4 to a high-level potential, thereby turning off the third pull-up transistor PM7 and the fourth pull-up transistor PM8, so that the pull-down of the third node N3 and the fifth node N5 based on the low-level voltage obtained by the flip of the third inverter INV3 remains at a low-level potential.

[0100] It should be noted that, based on the normally open state of the first voltage divider transistor PM9 and the second voltage divider transistor NM6, the signals of the fifth node N5 and the third node N3 described in this disclosure are understood to be the same first control signal INP_L. It can be understood that the signals of the fifth node N5 and the third node N3 are different in voltage value, but in the embodiments of this disclosure, they are treated as in-phase signals and used as a control signal.

[0101] In a specific example, the third pull-up transistor, the fourth pull-up transistor, the first voltage divider transistor, and the third voltage divider transistor can be PMOS transistors, while the second voltage divider transistor and the fourth voltage divider transistor can be NMOS transistors.

[0102] In a further example, the output signal generation module may further include a signal adjustment unit 231, which can generate a third control signal C3 with a preset signal length, thereby controlling the signal length of the output signal (including the first output signal OTH and the second output signal OUTL) based on the signal length of the third control signal C3.

[0103] It should be noted that the signal length refers to the length of the signal as shown in the waveform diagram. In practical scenarios, the signal length can be understood as the duration of the signal, i.e., the duration of the signal's duration. It can be understood that adjusting the signal length is equivalent to adjusting the signal's timing.

[0104] In a specific example, the signal adjustment unit 231 may include a signal buffer B1 and a NAND unit D2. The signal buffer B1 is used to delay the input signal by a preset signal length.

[0105] Specifically, the input terminal of the signal buffer B1 is used to input the second output signal OUTL, and the output terminal is connected to one input terminal of the NAND unit D2; the other input terminal of the NAND unit D2 is used to connect to the fifth node N5, and the output terminal is used to output the third control signal C3.

[0106] In the specific signal transmission process, when the transition signal INN_L changes from a high level to a low level, the corresponding second output signal OUTL changes from a high level to a low level. Due to the delay effect of the signal buffer B1, the NAND unit D2 will remain at a high level for a preset time length (corresponding to a preset signal length) at the input of the signal buffer before changing to a low level. At the input of the NAND unit D2 at the fifth node N5, after the transition signal INN_L has changed to a low level, it is flipped to a high level by the third inverter INV3. At this time, it can be understood that both inputs of the NAND unit D2 are "1", and the output should be "0" in the NAND logic. Accordingly, the low level output of the NAND unit D2 serves as the third control signal C3, turning on the third pull-up transistor PM7 and the fourth pull-up transistor PM8.

[0107] After a preset time period, the signal buffer B1 transmits the change of the second output signal OUTL to the input terminal of the NAND unit D2 corresponding to the signal buffer, so that the input terminal presents a low level potential. At this time, it can be understood that one input terminal of the two input terminals of the NAND unit D2 is "1" and the other input terminal is "0". In the corresponding NAND logic, the output should be "1". Accordingly, the NAND unit D2 outputs a high level potential as the third control signal C3, which turns off the third pull-up transistor PM7 and the fourth pull-up transistor PM8.

[0108] It is understood that the preset time length can be interpreted as the preset signal length. That is, the embodiments of this disclosure can generate a third control signal C3 with a preset signal length based on the signal adjustment unit. It should be noted that in the subsequent signal processing flow, the generation process of the first control signal INP_L is controlled by the third control signal C3, while the output signal is controlled by the first control signal INP_L. Therefore, based on the third control signal C3, a first control signal INP_L with the same preset signal length and an output signal with the same preset signal length can be generated.

[0109] It should be noted that in NAND logic, except when both inputs of NAND unit D2 are "1", the corresponding output is a low level "0", and in other cases, the output is a high level "1". This means that the third pull-up transistor PM7 and the fourth pull-up transistor PM8 are turned on only when necessary, and turned off at other times, thereby reducing the power consumption of the device.

[0110] In an optional implementation, the output signal generation module may further include a second signal compensation unit, which is used to perform signal compensation on the control signal generation unit.

[0111] For specific examples, please refer to [link / reference]. Figure 4 The second signal compensation unit may include a second signal compensation transistor PM6. The source terminal of the second signal compensation transistor PM6 is used to input the first voltage VDDIO, the drain terminal is connected to the third node N3, and the gate terminal is used to input the first output signal OUTH.

[0112] During the specific signal transmission process, when the control signal generation unit is in the signal pull-up phase, the third node N3 is at a high level, and the corresponding first output signal OTH is at a low level. At this time, the second signal compensation transistor PM6 is turned on based on the control of the first output signal OTH to maintain the high level state of the third node N3. Conversely, when the control signal generation unit is in the signal pull-down phase, the third node N3 is at a low level, and the corresponding first output signal OTH is at a high level. At this time, the second signal compensation transistor PM6 is turned off based on the control of the first output signal OTH to maintain the low level state of the third node N3.

[0113] Specifically, the second signal compensation transistor can be a PMOS transistor.

[0114] As can be seen, the embodiments of this disclosure utilize the second signal compensation unit to perform signal compensation for the control signal generation unit, in order to compensate for the device consumption of the third pull-up transistor PM7 or the potential deficiency caused by leakage current in the device, thereby reducing possible signal transmission errors.

[0115] In an optional implementation, the pull-up unit and the pull-down unit are used to generate a first output signal OTH and a second output signal OUTL. In another optional implementation, the output signal generation module may further include a voltage divider unit located between the pull-up unit and the pull-down unit to achieve voltage division of the output signal.

[0116] In a specific example, a voltage divider unit is also provided between the pull-up unit and the pull-down unit. The voltage divider unit is used to divide the voltage for the first output signal OTH and the second output signal OUTL.

[0117] Specifically, a first output terminal and a second output terminal are provided between the pull-up unit and the pull-down unit. A voltage divider unit can be set between the first output terminal that outputs the first output signal OTH and the second output terminal that outputs the second output signal OUTL to achieve the output of the first output signal OTH and the second output signal OUTL with different voltage ranges.

[0118] Specifically, in a specific example, the pull-up unit may include a fifth pull-up transistor PM11, and the pull-down unit may include a fifth pull-down transistor NM9; the voltage divider unit may include a fifth voltage divider transistor PM12 and a sixth voltage divider transistor NM8 connected in series. The pull-up unit, the voltage divider unit, and the pull-down unit are connected in sequence, with the node between the pull-up unit and the voltage divider unit designated as the sixth node N6, and the node between the voltage divider unit and the pull-down unit designated as the seventh node N7. The sixth node N6 is connected to the first output terminal for outputting the first output signal OTH, and the seventh node N7 is connected to the second output terminal for outputting the second output signal OUTL.

[0119] In a further example, the source of the fifth pull-up transistor PM11 is input to the first voltage VDDIO, its drain is connected to the fifth voltage divider transistor PM12 via the sixth node N6, and its gate is used to input the first control signal INP_L from the third node N3; the drain of the fifth voltage divider transistor PM12 is connected to the drain of the sixth voltage divider transistor NM8, and its gate is used to input the second voltage divider voltage V. REFP The source of the sixth voltage divider transistor NM8 is connected to the drain of the fifth pull-down transistor NM9 via the seventh node N7, and the gate is used to input the first voltage divider voltage V. REFN The source of the fifth pull-down transistor NM9 is grounded, and its gate is used to input the first control signal INP_L of the fifth node N5.

[0120] It is understandable that the second voltage divider voltage V is input to the gate of the fifth voltage divider transistor PM12. REFP This allows the fifth voltage divider transistor PM12 to be in a normally open state; the gate of the sixth voltage divider transistor NM8 receives the first voltage divider voltage V. REFN This allows the sixth voltage divider transistor NM8 to be in a normally open state.

[0121] During the specific signal transmission process, when the first control signal INP_L is at a high level, the fifth pull-up transistor PM11 is turned off and the fifth pull-down transistor NM9 is turned on, thereby pulling down the first output signal OTH and the second output signal OUTL to a low level; when the first control signal INP_L is at a low level, the fifth pull-up transistor PM11 is turned on and the fifth pull-down transistor NM9 is turned off, thereby pulling up the first output signal OTH and the second output signal OUTL to a high level.

[0122] The fifth pull-up transistor and the fifth voltage divider transistor can be PMOS transistors, and the fifth pull-down transistor and the sixth voltage divider transistor can be NMOS transistors.

[0123] In a further optional example, the level conversion circuit in this embodiment of the present disclosure further includes a voltage divider generation module, the voltage divider generation module being used to generate a first voltage divider V. REFN Second voltage divider V REFP It is understandable that the first voltage divider voltage V REFN Second voltage divider V REFP It is a voltage source with a preset voltage value, used to provide the corresponding voltage source for the level conversion circuit.

[0124] In a specific example, the voltage divider generation module may include a first control transistor PM1, a second control transistor NM2, a third control transistor NM1 and a fourth control transistor PM2, as well as a first voltage divider resistor R1, a second voltage divider resistor R2, a third voltage divider resistor R3 and a fourth voltage divider resistor R4.

[0125] In this configuration, the first control transistor PM1, the first voltage divider resistor R1, and the second voltage divider resistor R2 are connected in series. The third voltage divider resistor R3, the fourth voltage divider resistor R4, and the second control transistor NM2 are connected in series. The node between the first voltage divider resistor R1 and the second voltage divider resistor R2 is designated as the eighth node N8, and the node between the third voltage divider resistor R3 and the fourth voltage divider resistor R4 is designated as the ninth node N9. The third control transistor NM1 is connected to the eighth node N8, and the fourth control transistor PM2 is connected to the ninth node N9.

[0126] Specifically, the source of the first control transistor PM1 is input with a first voltage VDDIO, and its drain is connected to one end of the first voltage divider resistor R1; the other end of the first voltage divider resistor R1 is connected to one end of the second voltage divider resistor R; the other end of the second voltage divider resistor R2 is grounded; the node between the first voltage divider resistor R1 and the second voltage divider resistor R2 is designated as the eighth node N8, and this eighth node N8 is used to output the second voltage divider voltage V. REFP The drain of the third control transistor NM1 is connected to the eighth node N8, and the source is grounded.

[0127] One end of the third voltage divider resistor R3 is connected to the first voltage VDDIO, and the other end is connected to one end of the fourth voltage divider resistor R4; the other end of the fourth voltage divider resistor R4 is connected to the drain of the second control transistor NM2; the source of the second control transistor NM2 is grounded, and the node between the third voltage divider resistor R3 and the fourth voltage divider resistor R4 is designated as the ninth node N9, which is used to output the first voltage divider voltage VDDIO. REFN The source of the fourth control transistor PM2 is connected to the first voltage VDDIO, and the drain is connected to the ninth node N9.

[0128] In the specific signal processing flow, the first control transistor PM1 and the second control transistor NM2 are controlled to be in the on state and remain in this on state; when VDDIO is a higher voltage, such as 3.3V, the third control transistor NM1 and the fourth control transistor PM2 are controlled to be in the off state, generating a first voltage divider voltage V with a higher potential. REFN Second voltage divider V REFP For example, the first voltage divider V REFN It can be 1.8 volts, the second voltage divider voltage V REFP The voltage can be 1.5 volts, thus controlling the output voltage range of the second output signal OUTL to be 0-1.8V, and the first output signal OUTH to be 1.5-3.3V; when VDDIO is a lower voltage, such as 1.8V, the third control transistor NM1 and the fourth control transistor PM2 are turned on, generating a first voltage divider voltage V with a lower potential. REFN Second voltage divider V REFP For example, the first voltage divider V REFN It can be 1.8 volts, the second voltage divider voltage V REFP It can be ground voltage (0 volts), thereby controlling the output voltage range of the second output signal OUTL and the first output signal OUTH to be 0-1.8V.

[0129] It is understandable that the aforementioned voltage divider generation module can protect the device from overvoltage in overvoltage application scenarios, while not affecting normal operation under normal circumstances.

[0130] Specifically, the first and fourth control transistors can be PMOS transistors, and the second and third control transistors can be NMOS transistors.

[0131] In this embodiment of the level conversion circuit, during the generation of the output signal, a first control signal obtained based on the transition signal is used to execute the signal pull-up / pull-down processing flow respectively to generate a first output signal and a second output signal. This enables independent control of the pull-up and pull-down processes based on the first control signal, avoiding the influence of the output signal on the control signal, thereby avoiding defects such as steps in the output signal and ensuring the output quality of the high-frequency signal.

[0132] In a further example, embodiments of this disclosure also provide a chip configured with the level conversion circuit provided in embodiments of this disclosure.

[0133] In a further example, embodiments of this disclosure also provide an electronic device that includes the electronic device provided in embodiments of this disclosure.

[0134] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0135] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A level conversion circuit, characterized in that, include: A transition signal generation module is used to generate a transition signal based on an input signal, wherein the high-level voltage of the transition signal is greater than the high-level voltage of the input signal; The output signal generation module connected to the transition signal generation module is used to generate a first output signal and a second output signal based on the transition signal, wherein the high-level voltage of the first output signal is greater than the high-level voltage of the transition signal; The output signal generation module includes a control signal generation unit, and a pull-up unit and a pull-down unit connected to the control signal generation unit; wherein, the control signal generation unit is used to generate a first control signal based on the transition signal, and the pull-up unit and the pull-down unit respectively execute a signal processing flow based on the first control signal to generate a first output signal and a second output signal.

2. The level conversion circuit as described in claim 1, characterized in that, Also includes: A clamping module connected to the transition signal generation module is used to clamp the first voltage output by the first voltage source to a second voltage, wherein the second voltage is less than the first voltage. The first voltage source is used to provide the first voltage to the level conversion circuit, and the clamping module is used to provide the second voltage to the transition signal generation module.

3. The level conversion circuit as described in claim 2, characterized in that, The clamping module includes a clamping transistor. The drain of the clamping transistor receives the first voltage, the source is connected to the transition signal generation module, and the gate is used to input a first voltage divider. The first voltage divider is used to control the clamping transistor to turn on and to make the drain output a second voltage with a preset potential.

4. The level conversion circuit as described in claim 2, characterized in that, The transition signal generation module includes a first signal generation unit and a power consumption control unit; wherein, the first signal generation unit is used to generate a transition signal based on the input signal; and the power consumption control unit is used to control the first signal generation unit to input or disable the input of the second voltage based on the transition signal.

5. The level conversion circuit as described in claim 4, characterized in that, The first signal generation unit includes a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, and a first inverter; The source terminal of the first pull-up transistor is used to input the second voltage, and the drain terminal is connected to the drain terminal of the first pull-down transistor via the first node; the gate terminal of the first pull-down transistor is used to input the input signal, and the source terminal is grounded; the source terminal of the second pull-up transistor is used to input the second voltage, and the drain terminal and the gate terminal are connected and connected to the drain terminal of the second pull-down transistor via the second node. The gate terminal of the second pull-down transistor is used to input the second control signal, and the source terminal is grounded; the input terminal of the first inverter is connected to the first node; The second control signal is used to turn on the second pull-down transistor during the signal pull-up phase and turn off the second pull-down transistor during the signal pull-down phase.

6. The level conversion circuit as described in claim 4, characterized in that, The power consumption control unit includes: a NOR cell and a second inverter; The input terminal of the second inverter is used to input a transition signal, and the output terminal is connected to one input terminal of the NOR unit; the other input terminal of the NOR unit is used to input the input signal, and the output terminal is used to output a second control signal.

7. The level conversion circuit as described in claim 4, characterized in that, The transition signal generation module further includes a first signal compensation unit, which is used to perform signal compensation on the first signal generation unit. The first signal compensation unit includes a first signal compensation transistor, the source terminal of which is used to input a second voltage, the drain terminal is connected to a first node, and the gate terminal is used to input a transition signal.

8. The level conversion circuit as described in claim 1, characterized in that, The control signal generation unit includes a third inverter, a third pull-up transistor, a fourth pull-up transistor, a first voltage divider transistor, a second voltage divider transistor, a third voltage divider transistor, and a fourth voltage divider transistor. The input terminal of the third inverter is used to input the transition signal and output the first control signal; The source terminal of the third pull-up transistor is used to input the first voltage, and the drain terminal is connected to the source terminal of the first voltage divider transistor via the third node; the drain terminal of the first voltage divider transistor is connected to the drain terminal of the second voltage divider transistor. The source terminal of the second voltage divider transistor is connected to the output terminal of the third inverter via the fifth node; The source terminal of the fourth pull-up transistor is used to input a first voltage, and its drain terminal is connected to the source terminal of the third voltage divider transistor via a fourth node; the drain terminal of the third voltage divider transistor is connected to the drain terminal of the fourth voltage divider transistor; the source terminal of the fourth voltage divider transistor is used to input a third control signal. The gate terminals of the third and fourth pull-up transistors are connected to the fourth node, and the fifth and third nodes are used to output a first control signal; the gate terminals of the first and third voltage divider transistors are used to input a second voltage divider, and the gate terminals of the second and fourth voltage divider transistors are used to input a first voltage divider; the third control signal is used to pull the fourth node down to a low level during the signal pull-up phase to turn on the third and fourth pull-up transistors, and to pull the fourth node up to a high level during the signal pull-down phase to turn off the third and fourth pull-up transistors.

9. The level conversion circuit as described in claim 8, characterized in that, The output signal generation module further includes a signal adjustment unit, which generates a third control signal with a preset signal length to control the signal lengths of the first output signal and the second output signal.

10. The level conversion circuit as described in claim 9, characterized in that, The signal adjustment unit includes a signal buffer and a NAND unit, wherein the signal buffer is used to delay the input signal to the output terminal by a preset time length; The input terminal of the signal buffer is used to input the first output signal, and the output terminal is connected to one input terminal of the NAND unit; the other input terminal of the NAND unit is used to connect to the fifth node, and the output terminal is used to output the third control signal.

11. The level conversion circuit as described in claim 8, characterized in that, The output signal generation module further includes a second signal compensation unit, which is used to perform signal compensation on the control signal generation unit; The second signal compensation unit includes a second signal compensation transistor. The source terminal of the second signal compensation transistor is used to input a first voltage, the drain terminal is connected to a third node, and the gate terminal is used to input a first output signal.

12. The level conversion circuit as described in claim 8, characterized in that, The output signal generation module further includes a voltage divider unit located between the pull-up unit and the pull-down unit, which is used to divide the voltage for the first output signal and the second output signal.

13. The level conversion circuit as described in claim 12, characterized in that, The pull-up unit includes a fifth pull-up transistor, and the pull-down unit includes a fifth pull-down transistor; the voltage divider unit includes a fifth voltage divider transistor and a sixth voltage divider transistor connected in series. The source of the fifth pull-up transistor receives the first voltage, its drain is connected to the fifth voltage divider transistor via the sixth node, and its gate is used to input the first control signal of the third node; the drain of the fifth voltage divider transistor is connected to the drain of the sixth voltage divider transistor, and its gate is used to input the second voltage divider; the source of the sixth voltage divider transistor is connected to the drain of the fifth pull-down transistor via the seventh node, and its gate is used to input the first voltage divider; the source of the fifth pull-down transistor is grounded, and its gate is used to input the first control signal of the fifth node. The sixth node is connected to the first output terminal and is used to output the first output signal; the seventh node is connected to the second output terminal and is used to output the second output signal.

14. The level conversion circuit as described in claim 1, characterized in that, Also includes: A voltage divider generation module is used to generate a first voltage divider and a second voltage divider. The voltage divider generation module includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor, as well as a first voltage divider resistor, a second voltage divider resistor, a third voltage divider resistor, and a fourth voltage divider resistor. The source of the first control transistor is input with a first voltage, and its drain is connected to one end of the first voltage divider resistor; the other end of the first voltage divider resistor is connected to one end of the second voltage divider resistor; the other end of the second voltage divider resistor is grounded; the node between the first voltage divider resistor and the second voltage divider resistor is designated as the eighth node, and this eighth node is used to output the second voltage divider voltage; the drain of the third control transistor is connected to the eighth node, and its source is grounded. One end of the third voltage divider resistor is input with the first voltage, and the other end is connected to one end of the fourth voltage divider resistor; the other end of the fourth voltage divider resistor is connected to the drain of the second control transistor; the source of the second control transistor is grounded, and the node between the third and fourth voltage divider resistors is the ninth node, which is used to output the first voltage divider voltage; the source of the fourth control transistor is connected to the first voltage, and the drain is connected to the ninth node.

15. A chip, characterized in that, The chip is configured with a level conversion circuit as described in any one of claims 1 to 14.

16. An electronic device, characterized in that, Includes the chip described in claim 15.

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