Digital counting circuit and integrated circuit testing apparatus
By designing interlocking logic modules and cascaded counting modules, the system lock-up problem caused by glitches in high-frequency measurements was solved, achieving stable counting and high-precision measurement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN SHENAI SEMICON CO LTD
- Filing Date
- 2026-04-27
- Publication Date
- 2026-07-21
AI Technical Summary
In high-frequency measurements and integrated circuit testing, glitches caused by probe inductive reactance and power supply parasitics can easily cause system error lock-up, and existing technologies struggle to effectively filter out these interference signals.
The digital counting circuit employs interlocked logic modules and cascaded counting modules. By receiving edge trigger signals and timing stop signals, it generates stable enable signals to avoid glitches affecting the counting. The design of NOR gate loops and latch units ensures the accuracy of the counting.
It effectively filters out burrs and oscillation interference on the edges, avoids system lock-up, and improves the counting accuracy and stability of high-frequency measurements.
Smart Images
Figure CN122437537A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit testing technology, and in particular to a digital counting circuit and integrated circuit testing equipment. Background Technology
[0002] The IC tester time response extractor is a high-precision timing measurement module inside an automated test equipment (ATE). Its core function is to capture, identify, and digitize the precise edge moments of the chip's output signals, requiring high measurement accuracy during testing. However, during high-frequency measurements, the initial edge is prone to strong oscillating interference and noise due to probe inductance and power supply parasitics, resulting in two to multiple transitions.
[0003] In low-frequency tests, pure software algorithms can be used to filter out these glitches, but in high-frequency tests, the CPU computing power is insufficient, which not only consumes CPU cycles, but also makes it very easy to misread the interference signal as the real signal, causing the system to experience time window error and lock up. Summary of the Invention
[0004] Therefore, it is necessary to provide a digital counting circuit and integrated circuit testing equipment that is resistant to glitches and interference, in order to address the above-mentioned technical problems.
[0005] In a first aspect, this application provides a digital counting circuit, comprising:
[0006] An interlocking logic module is used to receive an edge trigger signal and a timing stop signal, and upon receiving the first edge trigger signal with a valid level, output an enable signal with a valid level and enter a locked state; upon receiving a timing stop signal with a valid level, unlock the locked state and output an enable signal with an invalid level; wherein, in the locked state, the level of the enable signal remains unchanged.
[0007] A cascaded counting module, connected to the interlock logic module, is used to receive the enable signal and perform counting when the enable signal is at a valid level.
[0008] The readout module is connected to both the cascaded counting module and the interlock logic module, and is used to latch and read the count value of the cascaded counting module when the enable signal is at an invalid level.
[0009] In one embodiment, the interlocking logic module includes:
[0010] A NOR gate loop is used to receive the edge trigger signal and the timing stop signal. When the first edge trigger signal with a valid level is received, a capture clock signal is generated based on the edge trigger signal and the timing stop signal. When the received timing stop signal is valid, a reset signal is generated.
[0011] A latch unit, connected to the NOR gate loop, is configured to output an enable signal and a feedback signal with an active level when the capture clock signal is received, and to output an enable signal with an inactive level and release the latch state when the reset signal is received.
[0012] The NOR gate loop is further configured to generate a latch clock signal when both the feedback signal and the edge trigger signal are at valid levels and the timing stop signal is at an invalid level.
[0013] The latch unit is also used to operate in the locked state according to the latch clock signal.
[0014] In one embodiment, the NOR gate loop includes:
[0015] A logic clock subunit, wherein a first input terminal of the logic clock subunit is used to receive the timing stop signal, a second input terminal of the logic clock subunit is used to receive the edge trigger signal, a third input terminal of the logic clock subunit is connected to the latch unit and is used to receive the feedback signal, and an output terminal of the logic clock subunit is connected to the latch unit. The logic clock subunit is used to generate a capture clock signal based on the edge trigger signal and the timing stop signal, and to generate a latch clock signal based on the edge trigger signal, the timing stop signal and the timing stop signal.
[0016] A reset subunit is provided, wherein the input terminal of the reset subunit is used to receive the timing stop signal, the output terminal of the reset subunit is connected to the latch unit, and the reset subunit is used to generate the reset signal when the received timing stop signal is at a valid level.
[0017] In one embodiment, the logic clock subunit includes:
[0018] The first NOT gate, the input of which is used to receive the timing stop signal;
[0019] The second NOT gate, the input of which is used to receive the edge-triggered signal;
[0020] A first NOR gate, wherein the first input terminal of the first NOR gate is connected to the output terminal of the first NOT gate, and the second input terminal of the first NOR gate is connected to the latch unit;
[0021] The second NOR gate has its first input connected to the output of the second NOT gate, and its second input connected to the latch unit.
[0022] The first OR gate has its first input connected to the output of the first NOR gate, its second input connected to the output of the second NOR gate, and its output connected to the latch unit, for outputting the capture clock signal or the latch clock signal.
[0023] In one embodiment, the reset subunit includes:
[0024] The second OR gate has a first input terminal for receiving an edge-triggered mode flag, a second terminal for receiving a timing window flag, and a third input terminal connected to the latch unit.
[0025] A first flip-flop, the clock port of which is used to receive the timing stop signal, and the input of the first flip-flop is connected to the output of the second OR gate;
[0026] The third NOT gate, wherein the input terminal of the third NOT gate is connected to the inverted output terminal of the first flip-flop;
[0027] The third NOR gate has its first input connected to its output, its second input connected to a clock control signal, and its output connected to the latch unit for outputting the reset signal.
[0028] In one embodiment, the enable signal includes a duration counting enable signal;
[0029] The latch unit includes:
[0030] A third OR gate, wherein the first input terminal of the third OR gate is used to receive a timing window flag;
[0031] The second flip-flop has its clock port connected to the output of the logic clock sub-unit, its input connected to the output of the third OR gate, its positive output connected to the third input of the logic clock sub-unit, and its negative output connected to the second input of the third OR gate.
[0032] The third flip-flop, wherein the input terminal of the third flip-flop is connected to the positive input terminal of the second flip-flop;
[0033] The fourth NOR gate has its first input connected to the inverted output of the third flip-flop, its second input connected to the clock port of the third flip-flop, and its output used to output the duration count enable signal.
[0034] In one embodiment, the enable signal further includes an event counting enable signal;
[0035] The latch unit further includes:
[0036] The fifth NOR gate, wherein the first input terminal of the fifth NOR gate is used to receive the inverted edge trigger signal, and the second input terminal of the fifth NOR gate is used to receive a function selection signal; the function selection signal is used to indicate whether the measurement duration function is enabled;
[0037] The sixth NOR gate has its first input connected to the output of the fifth NOR gate, its second input connected to the inverted output of the second flip-flop, and its output used to output the event counting enable signal.
[0038] The first input terminal of the fourth NOR gate is also used to receive the function selection signal.
[0039] In one embodiment, the cascaded counting module includes:
[0040] The first counting unit is connected to the interlock logic module and is used to count when the enable signal is at a valid level, and to output a carry flag when the count value reaches the first upper limit value.
[0041] A second counting unit, connected to the first counting unit, is used to count when the carry flag is received; wherein, the second counting upper limit value of the second counting unit is greater than the first counting upper limit value of the first counting unit.
[0042] In one embodiment, the clock frequency of the first counting unit is greater than the clock frequency of the second counting unit.
[0043] Secondly, this application also provides an integrated circuit testing device, which includes the digital counting circuit provided in any of the above embodiments.
[0044] In the aforementioned digital counting circuit and integrated circuit testing equipment, the digital counting circuit includes an interlock logic module, a cascade counting module, and a readout module. The interlock logic module, upon receiving the first edge-triggered signal with a valid level, outputs an enable signal with a valid level and enters a locked state. This locked state is only released when the received timing stop signal is valid, at which point it outputs an enable signal with an invalid level. While the interlock logic module is in the locked state, the level of the enable signal remains unchanged. This provides a stable and clean square wave signal (enable signal) to the cascade counting module, preventing errors in the counting time window due to glitches and oscillation interference on the edges, which could lead to system lockup. Attached Figure Description
[0045] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0046] Figure 1 This is a block diagram of a digital counting circuit in one embodiment;
[0047] Figure 2 This is a structural block diagram of an interlocking logic module in one embodiment;
[0048] Figure 3 This is a timing diagram of the NOR gate loop and latch unit in one embodiment;
[0049] Figure 4 This is a circuit topology diagram of an interlocking logic module in one embodiment;
[0050] Figure 5 Here is a structural block diagram of a cascaded counting module in one embodiment;
[0051] Figure 6 This is a circuit topology diagram of the first counting unit and the second counting unit in the first group of one embodiment;
[0052] Figure 7 This is a circuit topology diagram of the first counting unit and the second counting unit in one embodiment. Detailed Implementation
[0053] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0054] In one embodiment, this application provides a digital counting circuit, such as... Figure 1 As shown, it includes an interlocking logic module 100, a cascaded counting module 200, and a readout module 300.
[0055] The interlock logic module 100 is used to receive edge-triggered signals and timing stop signals. Upon receiving the first edge-triggered signal with a valid level, it outputs an enable signal with a valid level and enters a locked state. Upon receiving a timing stop signal with a valid level, it unlocks the state and outputs an enable signal with an invalid level. In the locked state, the level of the enable signal remains unchanged.
[0056] Both the edge trigger signal and the timing stop signal are provided by the front-end circuitry of the digital counting circuit. When the measured signal is a rising edge or falling edge, the front-end circuitry outputs an edge trigger signal with a valid level to the digital counting circuit to instruct it to start counting; when another measured signal is detected as a rising edge or falling edge, it outputs a timing stop signal with a valid level to the digital counting circuit to instruct it to stop counting. For example, in an integrated circuit testing scenario, one measured signal can be an excitation signal, and the other can be a response signal; alternatively, the two measured signals can be the same signal for different test time periods. The enable signal is used to instruct the subsequent circuitry of the interlock logic module 100 to start or stop counting.
[0057] Because the starting edge of the measured signal will have strong oscillation interference glitches with two to multiple jumps due to factors such as probe inductance and power supply parasitics, the interlock logic module 100 enters the locked state after receiving the first edge trigger signal with a valid level and outputting an enable signal with a valid level, until it receives a timing stop signal with a valid level.
[0058] The cascaded counting module 200 is connected to the interlocking logic module 100 and is used to receive an enable signal and to count when the enable signal is at an active level and to stop counting when the enable signal is at an inactive level.
[0059] The readout module 300 is connected to both the cascaded counting module 200 and the interlock logic module 100. It is used to latch and read the count value from the cascaded counting module 200 when the enable signal is at an invalid level. The readout module 300 can be a CPU, which can read the count value from the cascaded counting module 200 through its I / O ports.
[0060] In this embodiment, the digital counting circuit includes an interlock logic module 100, a cascaded counting module 200, and a readout module 300. When the interlock logic module 100 receives the first edge-triggered signal with a valid level, it outputs an enable signal with a valid level and enters a locked state. The locked state is released only when the received timing stop signal is valid, and an enable signal with an invalid level is output. When the interlock logic module 100 is in the locked state, the level of the enable signal remains unchanged. In this way, a stable and clean square wave signal (enable signal) can be provided to the cascaded counting module 200, avoiding errors in the counting time window caused by glitches and oscillation interference on the edge, which could lead to system lockup.
[0061] In one embodiment, such as Figure 2 As shown, the interlock logic module 100 includes a NOR gate loop 110 and a latch unit 120. The NOR gate loop 110 is connected to the latch unit 120.
[0062] The NOR gate loop 110 can be used to receive an edge trigger signal and a timing stop signal. When the first edge trigger signal with a valid level is received, a capture clock signal is generated based on the edge trigger signal and the timing stop signal. When the received timing stop signal is valid, a reset signal is generated.
[0063] The latch unit 120 can be used to output an enable signal and a feedback signal with an active level when a capture clock signal is received, and to output an enable signal with an inactive level and unlock the latch when a reset signal is received.
[0064] The NOR gate loop 110 is also used to generate a latch clock signal when both the feedback signal and the edge trigger signal are at active levels and the timing stop signal is at an inactive level.
[0065] The latch unit 120 is also used to operate in a locked state according to the latch clock signal.
[0066] The capture clock signal is essentially a rising edge signal, used to update the output signal of latch unit 120. When the clock port of latch unit 120 receives the capture clock signal, the enable signal output by latch unit 120 will be updated to an active level. The latch clock signal is essentially a high-level or low-level hold signal, or a falling edge signal. When the clock port of latch unit 120 receives the latch clock signal, the enable signal output by latch unit 120 will remain unchanged. The reset signal is used to instruct latch unit 120 to reset, so that the enable signal becomes inactive. The feedback signal is used to indicate to NOR gate loop 110 that latch unit 120 has output an active enable signal, the counting time window has been opened, and NOR gate loop 110 can output a latch clock signal.
[0067] Combination Figure 3 According to Table 1, when NOR gate loop 110 receives the first edge-triggered signal (START=1) with a valid level sent by the preceding circuit, it sends a capture clock signal to latch unit 120. After receiving the capture start signal, latch unit 120 flips its state, updates the enable signal to a valid level, and sends a feedback signal to NOR gate loop 110. After receiving the feedback signal sent by latch unit 120, NOR gate loop 110 sends a latch clock signal to latch unit 120, making latch unit 120 work in a locked state. During this period, even if NOR gate loop 110 receives a new edge-triggered signal, latch unit 120 remains in a locked state. When NOR gate loop 110 receives the first timer stop signal (STOP=1) with a valid level sent by the preceding circuit, it sends a reset signal to latch unit 120, making latch unit 120 unlocked and updating the enable signal to an invalid level.
[0068] Table 1 - Inputs and Outputs of the Interlock Logic Module
[0069]
[0070] In one embodiment, such as Figure 4 As shown, the NOR gate loop 110 includes a logic clock subunit 111 and a reset subunit 112.
[0071] The first input terminal of the logic clock subunit 111 is used to receive a timing stop signal, the second input terminal of the logic clock subunit 111 is used to receive an edge trigger signal, the third input terminal of the logic clock subunit 111 is connected to the latch unit 120 and is used to receive a feedback signal, and the output terminal of the logic clock subunit 111 is connected to the latch unit 120. The logic clock subunit 111 is used to generate a capture clock signal based on the edge trigger signal and the timing stop signal, and to generate a latch clock signal based on the edge trigger signal, the timing stop signal, and the timing stop signal.
[0072] The logic clock subunit 111 includes a first NOT gate U1, a second NOT gate U2, a first NOR gate U6, a second NOR gate U7, and a first OR gate U9. The input of the first NOT gate U1 receives a timing stop signal. The input of the second NOT gate U2 receives an edge-triggered signal. The first input of the first NOR gate U6 is connected to the output of the first NOT gate U1, and the second input of the first NOR gate U6 is connected to the latch unit 120. The first input of the second NOR gate U7 is connected to the output of the second NOT gate U2, and the second input of the second NOR gate U7 is connected to the latch unit 120. The first input of the first OR gate U9 is connected to the output of the first NOR gate U6, the second input of the first OR gate U9 is connected to the output of the second NOR gate U7, and the output of the first OR gate U9 is connected to the latch unit 120, used to output a capture clock signal or a latched clock signal.
[0073] The input terminal of the reset subunit 112 is used to receive the timing stop signal, and the output terminal of the reset subunit 112 is connected to the latch unit 120. The reset subunit 112 is used to generate a reset signal when the received timing stop signal is at an active level.
[0074] The reset subunit 112 includes a second OR gate U3, a first flip-flop U10, a third NOT gate U14, and a third NOR gate U13.
[0075] The first input of the second OR gate U3 is used to receive the edge-triggered mode flag, the second input of the second OR gate U3 is used to receive the timing window flag, and the third input of the second OR gate U3 is connected to the latch unit 120. The edge-triggered mode flag indicates whether the edge-triggered signal is valid when the measured signal is a rising edge signal or a falling edge signal. In the initial stage of testing, the edge-triggered mode flag can be configured by the readout module 300 (CPU). Afterward, the edge-triggered mode flag can be a shaped edge-triggered signal. The timing window flag is related to the operating state of the interlock logic module 100. When the interlock logic module 100 is in a locked state or a reset state, the timing window flag has different values. Thus, the CPU can determine the operating state of the interlock logic module 100 or determine whether the current counting cycle has been completed by reading the timing window flag.
[0076] The clock port of the first flip-flop U10 is used to receive the timing stop signal. The input of the first flip-flop U10 is connected to the output of the second OR gate U3. The input of the third NOT gate U14 is connected to the inverted output of the first flip-flop U10. The first input of the third NOR gate U13 is connected to the output of the third NOT gate U14, the second input of the third NOR gate U13 is connected to the clock control signal, and the output of the third NOR gate U13 is connected to the latch unit 120 for outputting a reset signal.
[0077] In one embodiment, the enable signal includes a duration counting enable signal, which is used to instruct the cascaded counting module 200 to measure duration.
[0078] The latch unit 120 includes a third OR gate U5, a second flip-flop U15, a third flip-flop U16, and a fourth NOR gate U18. The first input of the third OR gate U5 receives a timing window flag. The clock port of the second flip-flop U15 is connected to the output of the logic clock subunit 111; the input of the second flip-flop U15 is connected to the output of the third OR gate U5; the positive output of the second flip-flop U15 is connected to the third input of the logic clock subunit 111; and the negative output of the second flip-flop U15 is connected to the second input of the third OR gate U5. The input of the third flip-flop U16 is connected to the positive input of the second flip-flop U15. The first input of the fourth NOR gate U18 is connected to the negative output of the third flip-flop U16; the second input of the fourth NOR gate U18 is connected to the clock port of the third flip-flop U16; and the output of the fourth NOR gate U18 outputs a duration count enable signal.
[0079] In one embodiment, the enable signal further includes an event counting enable signal. The event counting enable signal is used to instruct the cascaded counting module 200 to record the number of valid events that occur.
[0080] The latch unit 120 also includes a fifth NOR gate U11 and a sixth NOR gate U17. The first input of the fifth NOR gate U11 receives an inverted edge-triggered signal, and the second input receives a function selection signal; the function selection signal indicates whether the measurement duration function is enabled. The first input of the sixth NOR gate U17 is connected to the output of the fifth NOR gate U11, and the second input is connected to the inverted output of the second flip-flop U15; the output of the sixth NOR gate U17 outputs an event counting enable signal. The first input of the fourth NOR gate U18 also receives the function selection signal.
[0081] In some embodiments, such as Figure 4As shown, the latch unit 120 may further include a fourth NOT gate U8 and a fifth NOT gate U12. The fourth NOT gate U8 and the fifth NOT gate U12 can be used to shape the signal output by the third OR gate U5.
[0082] In one embodiment, combined Figure 4 Describe the working principle of the interlock logic module 100:
[0083] When the function selection signal EVEN indicates that the test duration function is off, i.e., EVEN=1, the output of the fourth NOR gate U18 is always 0, that is, the duration count enable signal ICTE is always invalid.
[0084] When the function selection signal EVEN indicates that the test duration function is enabled (EVEN=0), the output of the fourth NOR gate U18 depends on the third flip-flop U16. At the initial stage of the test, both the edge-triggered signal START and the timing stop signal STOP are 0 (invalid level). At this time, the outputs of the first NOT gate U1 and the second NOT gate U2 are both 1, the outputs of the first NOR gate U6 and the second NOR gate U7 are both 0, and the output of the first OR gate U9 is 0. This means the clock port input of the second flip-flop U15 is 0, and its state remains unchanged. The initial value of the positive output of the second flip-flop U15 is 0, and the initial value of the negative output is 1. The output of the third OR gate U5 is 1, meaning the input port of the second flip-flop U15 is 1. The clock port of the third flip-flop U16 receives a high-frequency square wave signal, and the negative output updates according to the frequency of this square wave. Since the negative output of the second flip-flop U15 is 1, the event count enable signal ICEV is 0 regardless of the value of EVEN, making it an invalid signal. When the first edge-triggered signal with a valid level occurs (START=1, STOP=0), the output of the first NOT gate U1 becomes 1, the output of the second NOT gate U2 becomes 0, the output of the first NOR gate U6 becomes 0, the output of the second NOR gate U7 becomes 1, and the output of the first OR gate U9 becomes 1. This means the clock port of the second flip-flop U15 changes from 0 to 1, triggering the positive output to update to 1. Consequently, the inverting output of the third flip-flop U16 updates to 0, and the output ICTE of the fourth NOR gate U18 becomes valid (1). Simultaneously, the input of the second NOR gate U7 connected to the first flip-flop U10 updates to 1. Therefore, before STOP=1, regardless of subsequent changes in the START signal, the output of the second NOR gate U7 remains 0, and the output of the first OR gate U9 remains 0. This causes the clock port of the second flip-flop U15 to remain low, locking the output value of the second flip-flop U15 and keeping the first flip-flop U10 locked. Since the input signal of the second flip-flop U15 originates from the output signal of the first flip-flop U10, ICTE remains unchanged.
[0085] For ICEV, when the first edge-triggered signal with a valid level appears, when EVEN=1, the output of the fifth NOR gate U11 is 0. Since the inverted output of the second flip-flop U15 is updated to 0, the output of the sixth NOR gate U17 is 1, i.e., ICEV=1. When EVEN=0, the other input of the fifth NOR gate U11 is 0, the output of the fifth NOR gate U11 is 1, and the output of the sixth NOR gate U17 is 0, i.e., ICEV=0.
[0086] In one embodiment, such as Figure 5 As shown, the cascaded counting module 200 includes a first counting unit 210 and a second counting unit 220.
[0087] The first counting unit 210 is connected to the interlock logic module 100 and is used to count when the enable signal is at an active level, and to output a carry flag when the count value reaches the first upper limit value.
[0088] The second counting unit 220 is connected to the first counting unit 210 and is used to count when a carry flag is received.
[0089] The second counting upper limit value of the second counting unit 220 is greater than the first counting upper limit value of the first counting unit 210. The clock frequency of the first counting unit 210 is greater than the clock frequency of the second counting unit 220.
[0090] The first counting unit 210 can use an ECL architecture counting chip, and the second counting unit 220 can use a TTL architecture counting chip.
[0091] In this embodiment, the first counting unit 210 uses a high-frequency counting chip, and the second counting unit 220 uses a lower-frequency counting chip. The leading edge is a high-frequency ECL system counter that consumes a lot of power and generates a lot of heat, but has extremely accurate time resolution and extremely fast response. Once it is overloaded and carries, it throws the input to a multi-row, deep, slow-temperature, economical, low-heat system combined TTL counting unit. By setting this hybrid counting and metering structure, the service life of the digital counting circuit can be extended.
[0092] In one embodiment, such as Figure 6 and Figure 7 As shown, the cascaded counting module 200 may include two sets of first counting units 210 and second counting units 220.
[0093] The first counting unit 210 and the second counting unit 220 in the first group are used to receive the event counting enable signal and perform counting when the event counting enable signal is at a valid level. In the first group, the first counting unit 210 may include an ECL counting chip U19, and the second counting unit 220 may include TTL counting chips U21-U23.
[0094] The second group of first counting unit 210 and second counting unit 220 is used to receive the duration counting enable unit and perform counting when the duration counting enable unit is at an active level. In the first group, the first counting unit 210 may include an ECL counting chip U25, and the second counting unit 220 may include TTL counting chips U26-U27.
[0095] The readout module 300 can read the combined count value of the first group of first and second counting units through chip U24, and read the combined count value of the second group of first and second counting units through chip U30. Furthermore, Figure 6 The STBC signal is actually the shaped event counting enable signal ICEV, which can be used to indicate that the counting time window of the read module 300 has been closed; Figure 7 The STBC signal in the signal is actually the shaped time count enable signal ICTE, which can be used to indicate that the count time window of the read module 300 has been closed.
[0096] In one embodiment, this application also provides an integrated circuit testing device, which includes the digital counting circuit provided in any of the above embodiments.
[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0098] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A digital counting circuit, characterized in that, include: An interlocking logic module is used to receive an edge trigger signal and a timing stop signal, and upon receiving the first edge trigger signal with a valid level, output an enable signal with a valid level and enter a locked state; upon receiving a timing stop signal with a valid level, unlock the locked state and output an enable signal with an invalid level; wherein, in the locked state, the level of the enable signal remains unchanged. A cascaded counting module, connected to the interlock logic module, is used to receive the enable signal and perform counting when the enable signal is at a valid level. The readout module is connected to both the cascaded counting module and the interlock logic module, and is used to latch and read the count value of the cascaded counting module when the enable signal is at an invalid level.
2. The digital counting circuit according to claim 1, characterized in that, The interlocking logic module includes: A NOR gate loop is used to receive the edge trigger signal and the timing stop signal. When the first edge trigger signal with a valid level is received, a capture clock signal is generated based on the edge trigger signal and the timing stop signal. When the received timing stop signal is valid, a reset signal is generated. A latch unit, connected to the NOR gate loop, is configured to output an enable signal and a feedback signal with an active level when the capture clock signal is received, and to output an enable signal with an inactive level and release the latch state when the reset signal is received. The NOR gate loop is further configured to generate a latch clock signal when both the feedback signal and the edge trigger signal are at valid levels and the timing stop signal is at an invalid level. The latch unit is also used to operate in the locked state according to the latch clock signal.
3. The digital counting circuit according to claim 2, characterized in that, The NOR gate loop includes: A logic clock subunit, wherein a first input terminal of the logic clock subunit is used to receive the timing stop signal, a second input terminal of the logic clock subunit is used to receive the edge trigger signal, a third input terminal of the logic clock subunit is connected to the latch unit and is used to receive the feedback signal, and an output terminal of the logic clock subunit is connected to the latch unit. The logic clock subunit is used to generate a capture clock signal based on the edge trigger signal and the timing stop signal, and to generate a latch clock signal based on the edge trigger signal, the timing stop signal and the timing stop signal. A reset subunit is provided, wherein the input terminal of the reset subunit is used to receive the timing stop signal, the output terminal of the reset subunit is connected to the latch unit, and the reset subunit is used to generate the reset signal when the received timing stop signal is at a valid level.
4. The digital counting circuit according to claim 3, characterized in that, The logic clock subunit includes: The first NOT gate, the input of which is used to receive the timing stop signal; The second NOT gate, the input of which is used to receive the edge-triggered signal; A first NOR gate, wherein the first input terminal of the first NOR gate is connected to the output terminal of the first NOT gate, and the second input terminal of the first NOR gate is connected to the latch unit; The second NOR gate has its first input connected to the output of the second NOT gate, and its second input connected to the latch unit. The first OR gate has its first input connected to the output of the first NOR gate, its second input connected to the output of the second NOR gate, and its output connected to the latch unit, for outputting the capture clock signal or the latch clock signal.
5. The digital counting circuit according to claim 3, characterized in that, The reset subunit includes: The second OR gate has a first input terminal for receiving an edge-triggered mode flag, a second terminal for receiving a timing window flag, and a third input terminal connected to the latch unit. A first flip-flop, the clock port of which is used to receive the timing stop signal, and the input of the first flip-flop is connected to the output of the second OR gate; The third NOT gate, wherein the input terminal of the third NOT gate is connected to the inverted output terminal of the first flip-flop; The third NOR gate has its first input connected to its output, its second input connected to a clock control signal, and its output connected to the latch unit for outputting the reset signal.
6. The digital counting circuit according to claim 3, characterized in that, The enabling signal includes a duration counting enabling signal; The latch unit includes: A third OR gate, wherein the first input terminal of the third OR gate is used to receive a timing window flag; The second flip-flop has its clock port connected to the output of the logic clock sub-unit, its input connected to the output of the third OR gate, its positive output connected to the third input of the logic clock sub-unit, and its negative output connected to the second input of the third OR gate. The third flip-flop, wherein the input terminal of the third flip-flop is connected to the positive input terminal of the second flip-flop; The fourth NOR gate has its first input connected to the inverted output of the third flip-flop, its second input connected to the clock port of the third flip-flop, and its output used to output the duration count enable signal.
7. The digital counting circuit according to claim 6, characterized in that, The enable signal also includes an event counting enable signal; The latch unit further includes: The fifth NOR gate, wherein the first input terminal of the fifth NOR gate is used to receive the inverted edge trigger signal, and the second input terminal of the fifth NOR gate is used to receive a function selection signal; the function selection signal is used to indicate whether the measurement duration function is enabled; The sixth NOR gate has its first input connected to the output of the fifth NOR gate, its second input connected to the inverted output of the second flip-flop, and its output used to output the event counting enable signal. The first input terminal of the fourth NOR gate is also used to receive the function selection signal.
8. The digital counting circuit according to claim 1, characterized in that, The cascaded counting module includes: The first counting unit is connected to the interlock logic module and is used to count when the enable signal is at a valid level, and to output a carry flag when the count value reaches the first upper limit value. A second counting unit, connected to the first counting unit, is used to count when the carry flag is received; wherein, the second counting upper limit value of the second counting unit is greater than the first counting upper limit value of the first counting unit.
9. The digital counting circuit according to claim 8, characterized in that, The clock frequency of the first counting unit is greater than the clock frequency of the second counting unit.
10. An integrated circuit testing device, characterized in that, Includes the digital counting circuit as described in any one of claims 1-9.