A lock correction circuit for a dual frequency discriminator phase discriminator frequency synthesizer
By introducing a timing-based startup logic circuit and a pulse width monitoring circuit, the problems of timing sensitivity and logic lockout in the dual-frequency-phase detector frequency synthesizer are solved, realizing the stability and fast recovery capability of the frequency synthesizer, and ensuring self-healing function and noise improvement in complex environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CORELINK TECH (QINGDAO) CO LTD
- Filing Date
- 2026-04-28
- Publication Date
- 2026-07-21
AI Technical Summary
Existing dual-frequency and phase detector frequency synthesizers suffer from timing sensitivity during startup, risk of logic lockout, and dead or stuck charge pump issues, making it difficult for the frequency synthesizer to lock stably in complex environments.
By introducing timing start logic circuit, logic sequence monitoring circuit and pulse width monitoring circuit, the signal timing and pulse width are monitored, real-time verification is performed, and a reset operation is performed when an error occurs, ensuring that the frequency and phase detector works within the correct phase window and avoiding logic confusion and charge pump failure.
It improves the stability and fast recovery capability of the frequency synthesizer, ensures the self-healing function of the system in complex environments, maintains the 3dB noise improvement advantage, and prevents the system from being in a metastable state or losing lock for a long time.
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Figure CN122437538A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of frequency synthesizer technology, and more specifically to a lock-in correction circuit for a dual frequency and phase detector frequency synthesizer. Background Technology
[0002] Charge pump phase-locked loops (CP-PLLs) are widely used in radio frequency (RF) synthesizers due to their advantages such as wide acquisition range, fast locking speed, and ability to achieve zero steady-state phase error. In the front-end of modern wireless communication, radar, and IoT transceivers, RF frequency synthesizers are responsible for generating local oscillator (LO) signals. Their spectral purity (phase noise) and frequency switching speed directly determine the system's bit error rate, anti-blocking performance, and frequency agility.
[0003] To meet the increasingly complex spectrum environment and multi-mode, multi-band standards, RF synthesizers need to provide extremely low in-band phase noise and nanosecond-level fast frequency hopping capability on GHz-level carriers. The CP-PLL architecture, through the coordinated driving of a passive loop filter by a frequency-phase detector (PFD) and a charge pump (CP), achieves high linearity control of the voltage-controlled oscillator (VCO), making it the core choice for mainstream commercial RF synthesizers.
[0004] To optimize in-band phase noise, a dual PFD architecture is an efficient choice, such as... Figure 1 As shown, this architecture doubles the gain of the charge pump in the locked state by introducing a reference feedback signal FB and a delayed feedback signal FB_DELAY, thereby achieving an in-band phase noise reduction of approximately 3dB without increasing current noise. However, in engineering implementation, this dual PFD architecture presents significant robustness challenges, including:
[0005] 1. Startup timing sensitive: If the signal phase relationship is random during startup, the REF signal (reference signal) is very likely to fall outside the FB and FB_DELAY windows, resulting in incorrect frequency pulling (i.e., logic confusion).
[0006] 2. Logic lockout risk: Environmental interference may cause the edge order of FB, REF and FB_DELAY to flip, and traditional dual PFD systems have difficulty recovering to the correct lock phase on their own.
[0007] 3. Charge pump dead zone or jamming: When UP1 (from PFD1) and DN2 (from PFD2) are simultaneously in the narrow pulse reset state, the charge pump may enter the extremely low gain region or even jam the output. Summary of the Invention
[0008] To address this, this application provides a lock-in correction circuit for a dual-frequency and phase detector frequency synthesizer to solve the problems of startup timing sensitivity, logic lockout risk, and charge pump dead zone or jamming in the prior art.
[0009] To achieve the above objectives, this application provides the following technical solution:
[0010] In a first aspect, a lock-in correction circuit for a dual-frequency-phase-detector frequency synthesizer includes:
[0011] The timing start logic circuit is used to receive the delayed feedback signal of the dual frequency detector phase synthesizer, and the dual frequency detector phase synthesizer can only be activated after the rising edge of the delayed feedback signal ends.
[0012] The logic sequence monitoring circuit is used to monitor the timing logic order between the reference signal, feedback signal and delayed feedback signal of the dual frequency detector and phase detector frequency synthesizer in real time. When the timing logic order is continuously incorrect and reaches a preset first cycle number, a first trigger signal is output.
[0013] The pulse width monitoring circuit is used to monitor the pull-up pulse signal and pull-down pulse signal of the dual frequency and phase detectors in real time. When the pull-down pulse signal of one frequency and phase detector and the pull-up pulse signal of the other frequency and phase detector are both narrow pulses and continuously reach a preset second cycle number, the second trigger signal is output.
[0014] The timing start logic circuit is also connected to the output terminal of the logic sequence monitoring circuit and the output terminal of the pulse width monitoring circuit, respectively, and in response to the first trigger signal or the second trigger signal, performs a reset operation on the dual frequency and phase detector to restart the locking process.
[0015] Preferably, the timing-start logic circuit includes:
[0016] An edge-triggered D flip-flop, wherein the clock input of the edge-triggered D flip-flop is used to receive the delayed feedback signal, and the output input of the edge-triggered D flip-flop is used to indicate whether the rising edge of the delayed feedback signal has ended;
[0017] The OR gate has its first input connected to the output of the logic sequence monitoring circuit, its second input connected to the output of the pulse width monitoring circuit, and its output connected to the reset terminal of the edge-triggered D flip-flop.
[0018] Preferably, the logic sequence monitoring circuit includes:
[0019] The sequence determination circuit is used to receive the reference signal, the feedback signal and the delayed feedback signal in real time, and to verify whether the reference signal, the feedback signal and the delayed feedback signal meet the preset correct order, and to output an error indication signal when they do not meet the order.
[0020] The first counter is used to count the error indication signals. When the number of consecutive detections of the error indication signals reaches a preset first cycle number, the first trigger signal is output.
[0021] A first reset phase detector is configured to receive the first trigger signal and, in response to the first trigger signal, perform a reset operation on the dual frequency detector.
[0022] Preferably, the sequence determination circuit includes:
[0023] A delay inversion circuit is used to receive the delay feedback signal and output an inverted delayed signal of the delay feedback signal;
[0024] An AND gate is used to receive the delayed feedback signal and the inverted delayed signal of the delayed feedback signal, and to output a window pulse signal;
[0025] The first edge trigger is used to receive the feedback signal and the window pulse signal, and output the capture status of the feedback signal;
[0026] The second edge trigger is used to receive the reference signal and the window pulse signal, and output the capture status of the reference signal;
[0027] A digital judgment circuit is used to determine whether the timing logic of the feedback signal and the reference signal is correct based on the capture state of the feedback signal and the capture state of the reference signal, and outputs an error indication signal when there is an error.
[0028] Preferably, both the first edge-triggered flip-flop and the second edge-triggered flip-flop are edge-triggered D flip-flops.
[0029] Preferably, the pulse width monitoring circuit includes:
[0030] Four pulse width comparison circuits are used to receive the pull-up pulse signal and pull-down pulse signal of the dual frequency and phase detector, respectively, and output the corresponding width indication signal.
[0031] The second counter is used to output a second trigger signal when two of the four width indication signals simultaneously indicate narrow pulses and appear continuously for a preset second cycle number.
[0032] The second reset phase detector is used to receive the second trigger signal and perform a reset operation on the dual frequency detector in response to the second trigger signal.
[0033] Preferably, the pulse width comparison circuit includes:
[0034] The delay circuit is used to receive the pulse signal to be measured and output a delayed pulse signal after a preset delay time.
[0035] The comparison circuit is used to determine whether the pulse width of the pulse signal under test is less than the preset delay time based on the rising edge of the delayed pulse signal and the level state of the pulse signal under test, and outputs a width indication signal.
[0036] In a second aspect, a dual-frequency-phase-detector frequency synthesizer includes a first frequency-phase-detector, a second frequency-phase-detector, a charge pump, a loop filter, a voltage-controlled oscillator, a feedback frequency divider, a fractional modulator, and the aforementioned lock-in correction circuit for the dual-frequency-phase-detector frequency synthesizer.
[0037] The output terminals of the first and second frequency and phase detectors are electrically connected to the input terminal of the charge pump. The output terminal of the charge pump is electrically connected to the input terminal of the loop filter. The output terminal of the loop filter is electrically connected to the input terminal of the voltage-controlled oscillator. One output terminal of the voltage-controlled oscillator is electrically connected to the input terminal of the feedback frequency divider, and the other output terminal is used to output the synthesized signal. The output terminal of the fractional modulator is electrically connected to the other input terminal of the feedback frequency divider.
[0038] The locking correction circuit is electrically connected to the first frequency and phase detector, the second frequency and phase detector, and the feedback divider, respectively. It is used to receive reference signals, feedback signals, delayed feedback signals, and pull-up and pull-down pulse signals output by the first and second frequency and phase detectors, and to output reset control signals to the first and second frequency and phase detectors.
[0039] Compared with the prior art, this application has at least the following beneficial effects:
[0040] This application provides a lock-in correction circuit for a dual-frequency-phase-detector frequency synthesizer, comprising: a timing start logic circuit for receiving the delayed feedback signal of the dual-frequency-phase-detector frequency synthesizer, and enabling the dual-frequency-phase-detector of the frequency synthesizer to operate only after the rising edge of the delayed feedback signal has ended, ensuring that the reference signal is correctly included in the phase window and preventing frequency pulling errors during startup; and a logic sequence monitoring circuit for real-time monitoring of the timing logic order between the reference signal, feedback signal, and delayed feedback signal of the dual-frequency-phase-detector frequency synthesizer, and for correcting continuous errors in the timing logic order. When the error occurs and the preset first cycle number is reached, the first trigger signal is output to the timing start logic circuit to perform a reset operation, which can prevent the system from falling into metastability or losing lock. The pulse width monitoring circuit is used to monitor the pull-up pulse signal and pull-down pulse signal of the dual frequency and phase detector in real time. When the pull-down pulse signal of one frequency and phase detector and the pull-up pulse signal of the other frequency and phase detector are both narrow pulses and continuously reach the preset second cycle number, the second trigger signal is output to the timing start logic circuit to perform a reset operation, which can accurately identify narrow pulse abnormalities and trigger a reset, preventing the charge pump from entering the failure area. Attached Figure Description
[0041] To more intuitively illustrate the prior art and this application, exemplary drawings are provided below. It should be understood that the specific shapes and structures shown in the drawings should not generally be regarded as limiting conditions for implementing this application; for example, based on the technical concept disclosed in this application and the exemplary drawings, those skilled in the art are able to easily make conventional adjustments or further optimizations to the addition / reduction / classification, specific shapes, positional relationships, connection methods, size ratios, etc. of certain units (components).
[0042] Figure 1 A schematic diagram of the existing frequency detection architecture;
[0043] Figure 2 This is a schematic diagram of a frequency synthesizer for dual frequency and phase detectors, including a lock-in correction circuit, provided in Embodiment 1 of this application.
[0044] Figure 3 This is a schematic diagram of the signal timing sequence under abnormal conditions provided in Embodiment 1 of this application;
[0045] Figure 4 This is a schematic diagram of the logic sequence monitoring circuit architecture provided in Embodiment 1 of this application;
[0046] Figure 5 This is a schematic diagram of the sequence determination circuit provided in Embodiment 1 of this application;
[0047] Figure 6 This is a schematic diagram of the signal timing sequence under normal locking state provided in Embodiment 1 of this application;
[0048] Figure 7 This is a schematic diagram of the sequence determination circuit signal provided in Embodiment 1 of this application;
[0049] Figure 8 This is a schematic diagram of the pulse width monitoring circuit structure provided in Embodiment 1 of this application;
[0050] Figure 9 This is a schematic diagram of the pulse width comparison circuit provided in Embodiment 1 of this application;
[0051] Figure 10 This is a schematic diagram of pulse width anomaly provided in Embodiment 1 of this application. Detailed Implementation
[0052] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0053] In the description of this application: unless otherwise stated, "a plurality of" means two or more. The terms "first," "second," "third," etc., in this application are intended to distinguish the objects referred to and do not have any special meaning in terms of technical connotation (e.g., they should not be construed as an emphasis on importance or order). Expressions such as "including," "comprising," and "having" also mean "not limited to" (certain units, components, materials, steps, etc.).
[0054] The terms used in this application, such as "upper," "lower," "left," "right," and "middle," are generally used to indicate the general relative positional relationship for the purpose of intuitive understanding by referring to the accompanying drawings, and are not absolute limitations on the positional relationship in the actual product.
[0055] Example 1
[0056] Please see Figure 2 This embodiment provides a lock-in correction circuit for a dual frequency and phase detector frequency synthesizer, including a timing start logic circuit, a logic sequence monitoring circuit, and a pulse width monitoring circuit.
[0057] The timing start logic circuit is used to receive the delayed feedback signal FB_DELAY from the dual frequency detector phase synthesizer, and the dual frequency detector phase synthesizer can only be activated after the rising edge of the delayed feedback signal FB_DELAY ends.
[0058] Specifically, the timing-start logic circuit includes an edge-triggered D flip-flop and an OR gate. The clock input CLK of the edge-triggered D flip-flop is used to receive the delayed feedback signal FB_DELAY (the delayed feedback signal is generated by delaying the feedback signal FB). The output Q of the edge-triggered D flip-flop is used to indicate whether the rising edge of the delayed feedback signal FB_DELAY has ended. The first input of the OR gate is connected to the output DOUT1 of the logic sequence monitoring circuit, the second input of the OR gate is connected to the output DOUT2 of the pulse width monitoring circuit, and the output DOUT of the OR gate is connected to the reset input RST of the edge-triggered D flip-flop.
[0059] In summary, the timing startup protocol for sequential startup logic circuits includes:
[0060] Synchronous decision: The timing-start logic circuit samples the rising edge of the delayed feedback signal FB_DELAY through an edge-triggered D flip-flop;
[0061] Enable Delay: After the first rising edge of the delayed feedback signal FB_DELAY is detected, the timing start logic circuit forces the dual PFDs to be in a reset state through the DOUT signal.
[0062] Window capture: This mechanism ensures that when the PFD begins phase comparison, the reference signal REF is necessarily located after the timing window of the delayed feedback signal FB_DELAY, physically preventing [further issues]. Figure 3 The incorrect frequency traction solves the logical confusion that may occur during the startup of dual PFDs.
[0063] This embodiment introduces a startup controller (i.e., sequential startup logic circuit) to force the system to enable the phase-frequency detector (PFD) only after the rising edge of the delayed feedback signal FB_DELAY has been detected. This mechanism ensures that the start time is locked, and the reference signal REF can be correctly included in the phase window defined by the feedback signal FB and the delayed feedback signal FB_DELAY (generated by a dual-mode prescaler and an N-divider), fundamentally eliminating logical misalignment during the startup phase.
[0064] The logic sequence monitoring circuit is used to monitor the timing logic order between the reference signal REF, the feedback signal FB, and the delayed feedback signal FB_DELAY of the dual frequency detector and phase synthesizer in real time. When a continuous error in the timing logic order is detected and reaches a preset first cycle number, the circuit outputs a first trigger signal DOUT1 and transmits it to the timing start logic circuit. The timing start logic circuit responds to the first trigger signal DOUT1 and performs a reset operation on the dual frequency detector and phase synthesizer to restart the locking process.
[0065] For details, please refer to Figure 4The logic sequence monitoring circuit includes a sequence judgment circuit, a first counter, and a first reset phase detector.
[0066] The sequence determination circuit is used to receive the reference signal REF, the feedback signal FB, and the delayed feedback signal FB_DELAY in real time, and to verify whether the reference signal REF, the feedback signal FB, and the delayed feedback signal FB_DELAY meet the preset correct sequence. If they do not meet the sequence, an error indication signal J1 is output.
[0067] For more details, please see Figure 5 The sequential judgment circuit includes a delayed inverting circuit, an AND gate, a first edge flip-flop, a second edge flip-flop, and a digital judgment circuit.
[0068] The delay inversion circuit is used to receive the delay feedback signal FB_DELAY and output the inverted delayed signal FB_DELAYD of the delay feedback signal.
[0069] An AND gate is used to receive the delayed feedback signal FB_DELAY and the inverted delayed signal FB_DELAYD of the delayed feedback signal, and output the window pulse signal FB_DELAY_PW.
[0070] The first edge-triggered flip-flop (using an edge-triggered D flip-flop) is used to receive the feedback signal FB and the window pulse signal FB_DELAY_PW, and output the capture status FBA of the feedback signal.
[0071] The second edge-triggered flip-flop (using an edge-triggered D flip-flop) is used to receive the reference signal REF and the window pulse signal FB_DELAY_PW, and output the capture status REFA of the reference signal.
[0072] The digital judgment circuit is used to determine whether the timing logic of the feedback signal FB and the reference signal REF is correct based on the capture state FBA of the feedback signal and the capture state REFA of the reference signal, and outputs an error indication signal J1 when there is an error.
[0073] In summary, the sequence determination circuit is used to continuously monitor the signal flow direction, including:
[0074] Logic verification logic: The sequential judgment circuit verifies in real time whether the logic chain FB → REF → FB_DLY is satisfied (i.e., the preset correct order), such as... Figure 6 As shown, only the correct sequence can achieve optimal noise performance. Figure 3 The error series shown, namely the wider DN1 (i.e., the pull-down pulse signal of the first frequency and phase detector) and UP2 (i.e., the pull-up pulse signal of the second frequency and phase detector) entering the charge pump, will cause a significant deterioration in noise.
[0075] FB_DELAY Reset: The delayed feedback signal FB_DELAY serves as the end marker of the logic chain, such as... Figure 5 and Figure 7 As shown, by performing an AND gate operation between the delayed feedback signal FB_DELAY and the inverted delayed signal FB_DELAYD of the delayed feedback signal, a window pulse signal FB_DELAY_PW can be output to reset the D flip-flop.
[0076] FB and REF sequence capture: After the D flip-flops are reset, the rising edges of the feedback signal FB and the reference signal REF will pull up the corresponding D flip-flop outputs. The subsequent digital judgment circuit determines whether the logic sequence is correct by judging whether the FBA or REFA signal is pulled high first. If an erroneous sequence occurs, the error indicator signal J1 outputs a high-level signal.
[0077] The first counter is used to count the error indication signal J1. When the number of consecutive detections of the error indication signal reaches a preset first cycle number, the first trigger signal is output.
[0078] The first reset phase detector is used to receive the first trigger signal and perform a reset operation on the dual frequency phase detector in response to the first trigger signal.
[0079] In other words, the first counter of the logic sequence monitoring circuit will count continuously. If the sequence FB → REF → FB_DLY appears after M cycles, the output DOUT1 indicates that the timing-started logic circuit should perform a reset operation (e.g., Figure 4 (As shown).
[0080] In this embodiment, the logic sequence monitoring circuit monitors the timing logic of FB → REF → FB_DELAY in real time. When an error is detected in this logic sequence due to frequency jumps or interference (e.g., the reference signal REF leads the feedback signal FB), and this error continues for M reference cycles, the timing start logic circuit is automatically triggered to perform a PFD reset. After the reset, the locking process is restarted to avoid prolonged metastability or erroneous locking.
[0081] The pulse width monitoring circuit is used to monitor the pull-up pulse signal UP and pull-down pulse signal DN of the dual frequency and phase detectors in real time. When the pull-down pulse signal DN of one frequency and phase detector and the pull-up pulse signal UP of the other frequency and phase detector are both narrow pulses and continuously reach the preset second cycle number, the second trigger signal DOUT2 is output and transmitted to the timing start logic circuit. The timing start logic circuit responds to the second trigger signal DOUT2 and performs a reset operation on the dual frequency and phase detectors to restart the locking process.
[0082] For details, please refer to Figure 8The pulse width monitoring circuit includes four pulse width comparison circuits, a second counter, and a second reset phase discriminator.
[0083] The four pulse width comparison circuits are respectively used to receive the pull-up pulse signal and the pull-down pulse signal of the double frequency discriminator and phase discriminator, and output corresponding width indication signals J2.
[0084] More specifically, please refer to Figure 9 The pulse width comparison circuit includes a delay circuit and a comparison circuit:
[0085] The delay circuit is used to receive the pulse signal to be measured and output a delayed pulse signal after a preset delay time;
[0086] The comparison circuit is used to determine whether the pulse width of the pulse signal to be measured is less than the preset delay time according to the rising edge of the delayed pulse signal and the level state of the pulse signal to be measured, and output a width indication signal J2.
[0087] That is to say, the pulse width of the input Delayin signal of the pulse width comparison circuit is PW, and the delay time of the delay circuit is DELAY as the judgment window width. When the rising edge of Delayout comes, if Delayin is at a high level, it means PW>DELAY; if Delayin is at a low level, it means PW<DELAY. Through the above principle, the pulse width measurement of UP1 (i.e., the pull-up pulse signal of the first frequency discriminator and phase discriminator), DN1 (the pull-down pulse signal of the first frequency discriminator and phase discriminator), UP2 (i.e., the pull-up pulse signal of the second frequency discriminator and phase discriminator), and DN2 (the pull-down pulse signal of the second frequency discriminator and phase discriminator) can be realized. When both the DN1 and UP2 signals have extremely small pulse widths, the width indication signal J2 outputs a high-level signal.
[0088] The second counter is used to output a second trigger signal when two of the four width indication signals simultaneously indicate narrow pulses and continuously appear for a preset second period number.
[0089] The second reset phase discriminator is used to receive the second trigger signal DOUT2 and perform a reset operation on the double frequency discriminator and phase discriminator in response to the second trigger signal DOUT2.
[0090] In summary, in this embodiment, the second counting circuit of the pulse width monitoring circuit performs continuous counting. If the DN1 and UP2 signals both have extremely small pulse widths in N periods, the output DOUT2 indicates that the timing start logic circuit performs a reset operation.
[0091] Please refer to Figure 10In intermittent situations, the pulse widths of both DN1 and UP2 signals in the dual PFD structure are extremely small, causing the charge pump to fail to receive a valid signal and become stuck. This embodiment addresses this by using a pulse width monitoring circuit to dynamically monitor the pulse widths in real time. Specifically, the pulse width monitoring circuit monitors the pulse widths of the UP1 and DN1 signals of PFD1 and the UP2 and DN2 signals of PFD2. If both DN1 and UP2 signals required by the charge pump simultaneously exhibit narrow pulse reset signals, it indicates that the system has entered the charge pump dead zone or gain failure zone. If this error persists for N consecutive reference cycles, the timing start logic circuit is automatically triggered to reset the PFDs. After the reset, the locking process is restarted to prevent the system from remaining in a metastable or erroneously locked state for an extended period.
[0092] The lock-in correction circuit for a dual-frequency phase detector frequency synthesizer provided in this embodiment has the following advantages:
[0093] 1. Extremely high stability: It solves the common problems of lock loss and logical confusion in dual PFD architecture in engineering.
[0094] 2. Rapid recovery capability: Through a periodic automatic reset mechanism, the system is ensured to have self-healing capabilities in complex environments.
[0095] 3. Dynamic gain guarantee: Eliminates the risk of charge pump failure in narrow pulse conditions and maintains the theoretical noise improvement advantage of 3dB.
[0096] Example 2
[0097] This embodiment provides a dual frequency and phase detector frequency synthesizer, including a first frequency and phase detector, a second frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), a feedback frequency divider, a fractional modulator, and a lock-in correction circuit for the dual frequency and phase detector frequency synthesizer provided in Embodiment 1.
[0098] The output terminals of the first and second frequency and phase detectors are electrically connected to the input terminal of the charge pump. The output terminal of the charge pump is electrically connected to the input terminal of the loop filter. The output terminal of the loop filter is electrically connected to the input terminal of the voltage-controlled oscillator. One output terminal of the voltage-controlled oscillator is electrically connected to the input terminal of the feedback frequency divider, and the other output terminal is used to output the synthesized signal. The output terminal of the fractional modulator is electrically connected to the other input terminal of the feedback frequency divider.
[0099] The lock-in correction circuit is electrically connected to the first frequency and phase detector, the second frequency and phase detector, and the feedback divider, respectively. It is used to receive the reference signal, the feedback signal, the delayed feedback signal, and the pull-up pulse signal and pull-down pulse signal output by the first and second frequency and phase detectors, and output the reset control signal to the first and second frequency and phase detectors.
[0100] For details on the specific implementation of a lock-in correction circuit for a dual-frequency phase detector frequency synthesizer, please refer to the limitations mentioned above, which will not be repeated here.
[0101] The technical features of the above embodiments can be combined in any way (as long as there is no contradiction in the combination of these technical features). For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; these embodiments not explicitly written should also be considered to be within the scope of this specification.
Claims
1. A locking correction circuit for a dual-frequency and phase detector frequency synthesizer, characterized in that, include: The timing start logic circuit is used to receive the delayed feedback signal of the dual frequency detector phase synthesizer, and the dual frequency detector phase synthesizer can only be activated after the rising edge of the delayed feedback signal ends. The logic sequence monitoring circuit is used to monitor the timing logic order between the reference signal, feedback signal and delayed feedback signal of the dual frequency detector and phase detector frequency synthesizer in real time. When the timing logic order is continuously incorrect and reaches a preset first cycle number, a first trigger signal is output. The pulse width monitoring circuit is used to monitor the pull-up pulse signal and pull-down pulse signal of the dual frequency and phase detectors in real time. When the pull-down pulse signal of one frequency and phase detector and the pull-up pulse signal of the other frequency and phase detector are both narrow pulses and continuously reach a preset second cycle number, the second trigger signal is output. The timing start logic circuit is also connected to the output terminal of the logic sequence monitoring circuit and the output terminal of the pulse width monitoring circuit, respectively, and in response to the first trigger signal or the second trigger signal, performs a reset operation on the dual frequency and phase detector to restart the locking process.
2. The locking correction circuit for a dual-frequency and phase detector frequency synthesizer according to claim 1, characterized in that, The timing-start logic circuit includes: An edge-triggered D flip-flop, wherein the clock input of the edge-triggered D flip-flop is used to receive the delayed feedback signal, and the output input of the edge-triggered D flip-flop is used to indicate whether the rising edge of the delayed feedback signal has ended; The OR gate has its first input connected to the output of the logic sequence monitoring circuit, its second input connected to the output of the pulse width monitoring circuit, and its output connected to the reset terminal of the edge-triggered D flip-flop.
3. The locking correction circuit for a dual-frequency and phase detector frequency synthesizer according to claim 1, characterized in that, The logic sequence monitoring circuit includes: The sequence determination circuit is used to receive the reference signal, the feedback signal and the delayed feedback signal in real time, and to verify whether the reference signal, the feedback signal and the delayed feedback signal meet the preset correct order, and to output an error indication signal when they do not meet the order. The first counter is used to count the error indication signals. When the number of consecutive detections of the error indication signals reaches a preset first cycle number, the first trigger signal is output. A first reset phase detector is configured to receive the first trigger signal and, in response to the first trigger signal, perform a reset operation on the dual frequency detector.
4. The locking correction circuit for a dual frequency and phase detector frequency synthesizer according to claim 3, characterized in that, The sequence determination circuit includes: A delay inversion circuit is used to receive the delay feedback signal and output an inverted delayed signal of the delay feedback signal; An AND gate is used to receive the delayed feedback signal and the inverted delayed signal of the delayed feedback signal, and to output a window pulse signal; The first edge trigger is used to receive the feedback signal and the window pulse signal, and output the capture status of the feedback signal; The second edge trigger is used to receive the reference signal and the window pulse signal, and output the capture status of the reference signal; A digital judgment circuit is used to determine whether the timing logic of the feedback signal and the reference signal is correct based on the capture state of the feedback signal and the capture state of the reference signal, and outputs an error indication signal when there is an error.
5. The locking correction circuit for a dual-frequency and phase detector frequency synthesizer according to claim 4, characterized in that, Both the first edge-triggered flip-flop and the second edge-triggered flip-flop are edge-triggered D flip-flops.
6. The locking correction circuit for a dual frequency and phase detector frequency synthesizer according to claim 1, characterized in that, The pulse width monitoring circuit includes: Four pulse width comparison circuits are used to receive the pull-up pulse signal and pull-down pulse signal of the dual frequency and phase detector, respectively, and output the corresponding width indication signal. The second counter is used to output a second trigger signal when two of the four width indication signals simultaneously indicate narrow pulses and appear continuously for a preset second cycle number. The second reset phase detector is used to receive the second trigger signal and perform a reset operation on the dual frequency detector in response to the second trigger signal.
7. The locking correction circuit for a dual frequency and phase detector frequency synthesizer according to claim 6, characterized in that, The pulse width comparison circuit includes: The delay circuit is used to receive the pulse signal to be measured and output a delayed pulse signal after a preset delay time. The comparison circuit is used to determine whether the pulse width of the pulse signal under test is less than the preset delay time based on the rising edge of the delayed pulse signal and the level state of the pulse signal under test, and outputs a width indication signal.
8. A frequency synthesizer with dual frequency and phase detectors, characterized in that, It includes a first frequency and phase detector, a second frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a feedback frequency divider, a fractional modulator, and a lock-in correction circuit for a dual frequency and phase detector frequency synthesizer as described in any one of claims 1-7; The output terminals of the first and second frequency and phase detectors are electrically connected to the input terminal of the charge pump. The output terminal of the charge pump is electrically connected to the input terminal of the loop filter. The output terminal of the loop filter is electrically connected to the input terminal of the voltage-controlled oscillator. One output terminal of the voltage-controlled oscillator is electrically connected to the input terminal of the feedback frequency divider, and the other output terminal is used to output the synthesized signal. The output terminal of the fractional modulator is electrically connected to the other input terminal of the feedback frequency divider. The locking correction circuit is electrically connected to the first frequency and phase detector, the second frequency and phase detector, and the feedback divider, respectively. It is used to receive reference signals, feedback signals, delayed feedback signals, and pull-up and pull-down pulse signals output by the first and second frequency and phase detectors, and to output reset control signals to the first and second frequency and phase detectors.