An open loop fractional frequency divider using phase switching and split-dtc architecture

Abstract

The application discloses an open loop fractional frequency divider adopting phase switching and a Split-DTC structure, and the frequency divider comprises a quadrature frequency division module, a phase switching module, a multi-mode frequency divider module, a DTC gain calibration module and a DTC linearity calibration module.

Description

Technical Field

[0001] This invention belongs to the field of photoelectric detection technology, and specifically relates to an open-loop fractional frequency divider that employs phase switching and a Split-DTC structure. Background Technology

[0002] In modern electronic systems, phase-locked loops (PLLs) are crucial for generating high-precision clocks. To meet the clock requirements of different modules in a system-on-a-chip (SoC), fractional-division PLLs are commonly used.

[0003] The core module in a fractional phase-locked loop is the fractional frequency divider. (See...) Figure 1 Fractional frequency dividers essentially still only support integer division ratios, and the output phase accuracy remains one input clock cycle. However, first-order SDMs, by modulating the integer division ratio of the input, can achieve an average division ratio of the desired fraction, effectively realizing fractional frequency division. Figure 1 We can clearly see that there is an instantaneous phase error, so we need to compensate for this instantaneous phase error. The main methods for compensating for quantization noise in a fractional divider are: using an IDAC to compensate for the charge pump current, using a DTC to compensate for the phase of the divider output signal, or achieving fractional division steps through phase switching. Specifically, within each SDM output cycle, the digital calibration circuit calculates the difference between the current voltage division ratio and the ideal voltage division ratio to obtain the quantization error. This error is used to modulate the IDAC output current and is ultimately superimposed on the charge pump current in the PLL loop.

[0004] However, while the aforementioned technological discoveries can eliminate quantization noise to some extent, they require higher DAC resolution, leading to increased power consumption and larger chip area.

[0005] In summary, there is an urgent need for a fractional divider that can reduce power consumption and noise on the DTC link and has a small area overhead. Summary of the Invention

[0006] To address the aforementioned technical issues, this invention provides an open-loop fractional divider employing phase switching and a Split-DTC structure. While ensuring the DTC calibration effect, it reduces the dynamic range of the DTC and the power consumption and noise on the DTC link, further reducing area overhead.

[0007] In a first aspect, this application provides an open-loop fractional frequency divider employing phase switching and a Split-DTC structure, comprising: The quadrature frequency divider module is used to orthogonally divide the input differential signal by two to obtain four-phase quadrature clock signals, namely: CLK_I, CLK_Q, CLK_IN, and CLK_QN. The phase switching module is used to switch the phases of the four-phase quadrature clock signals using four clocks, and outputs two phase switching signals PS_OUT1 and PS_OUT2, wherein the phase difference between PS_OUT1 and PS_OUT2 is [missing information]. , One clock cycle; A multi-mode frequency divider module is used to divide the phase switching signal by cascading 2 / 3 frequency dividers to obtain the divided FMMD signal. A multi-mode frequency divider module is used to divide the phase switching signal by cascading 2 / 3 frequency dividers to obtain the divided FMMD signal. A first-order SDM module is used to modulate the frequency division ratio and generate the modulated frequency division ratio signal. The frequency division ratio signal Used to control the switching between DTC gain calibration and linearity calibration; The DTC gain calibration module is used to determine the gain control word and average gain control word KDTC of the four-phase clock based on the FMMD signal and the two phase switching signals. The gain control words are KDTC0, KDTC1, KDTC2, and KDTC3, respectively. The DTC linearity calibration module is used to determine the linearity-calibrated DTC control word based on the randomly selected control word and the FMMD signal. The orthogonal calibration module is used to determine the compensated DTC control word based on the gain control word and the average gain control word. This is to determine the phase-compensated frequency division signal based on the DTC control word and the FMMD signal.

[0008] In one embodiment, the orthogonal frequency division module includes: Two interconnected CML latches are used to convert the input differential signal into a four-phase quadrature clock signal; The CML-to-CMOS buffer connected to the CML latch is used to restore the four-phase quadrature clock signal to a full-swing signal.

[0009] In one embodiment, the phase switching module adopts a Gray code-encoded 4-to-1 selector structure.

[0010] In one embodiment, the multi-mode divider module is composed of cascaded 2 / 3 dividers to achieve a division ratio of 2 or 3 through control signals mod_in and P. The 2 / 3 divider consists of latches, buffers, and logic gates.

[0011] In one embodiment, the DTC gain calibration module is used to sample the FMMD output of the multi-mode divider using the PS_OUT1 signal to obtain FMMD_Temp1; sample FMMD_Temp1 using the PS_OUT2 signal to obtain FMMD_Temp2; calculate the gain control word of the four-phase clock based on the phase difference between FMMD_Temp1 and FMMD_Temp2; and sum and average the gain control words to obtain the average gain control word KDTC.

[0012] In one embodiment, the DTC linearity calibration module includes: The Split-DTC structure is used to modulate the weights to 3:2:1:1:1 and compensate for the linearity of DTC units with different weights. The BBPD phase detector is used to detect the phase difference of the output signal of the Split-DTC structure and adjust the control word, which is randomly selected by a lookup table (LUT) to control the DTC.

[0013] In one embodiment, the quadrature calibration module is used to determine the clock phase difference between the four gain control words obtained by the gain calibration module. , ; The control word corresponding to the clock phase difference is accumulated into the third DTC control word.

[0014] In one embodiment, the frequency division ratio signal The control for switching between DTC gain calibration and linearity calibration includes: when When ≤ 0.25, perform DTC gain calibration; when When the value is greater than 0.25, perform DTC linearity calibration.

[0015] In one embodiment, the Split-DTC structure includes: The MDTC module implements a 3:2:1:1:1 weight allocation. The CDTC module is used to compensate for the linearity of DTC units with different weights in the MDTC module.

[0016] In one embodiment, the phase switching module switches when two of the four-phase clocks are simultaneously at a high level.

[0017] The open-loop fractional frequency divider provided in this application, employing phase switching and a Split-DTC structure, uses an orthogonal frequency divider module to orthogonally divide the input differential signal by two to obtain four-phase orthogonal clock signals: CLK_I, CLK_Q, CLK_IN, and CLK_QN. The phase switching module uses four clock phases to switch the phases of the four-phase orthogonal clock signals, outputting two phase switching signals, PS_OUT1 and PS_OUT2, with a phase difference between PS_OUT1 and PS_OUT2. , One clock cycle; a multi-mode divider module, used to divide the phase-switching signal by cascading 2 / 3 dividers to obtain the divided FMMD signal; a first-order SDM module, used to modulate the division ratio and generate the modulated division ratio signal. The frequency division ratio signal The system is used to control the switching between DTC gain calibration and linearity calibration; the DTC gain calibration module is used to determine the gain control word and average gain control word KDTC of the four-phase clock based on the FMMD signal and the two phase switching signals, wherein the gain control words are KDTC0, KDTC1, KDTC2, and KDTC3 respectively; the DTC linearity calibration module is used to determine the linearity-calibrated DTC control word based on the randomly selected control word and the FMMD signal; the quadrature calibration module is used to determine the compensated DTC control word based on the gain control word and the average gain control word. This allows the phase-compensated frequency division signal to be determined based on the DTC control word and the FMMD signal. Phase switching reduces the dynamic range of the DTC from 1 to 0.25, lowering noise and power consumption on the DTC link. Simultaneously, when the frequency divider needs to achieve a fractional division step of 0.25, extremely low fractional spurious emissions can be achieved. Furthermore, an orthogonal calibration module is used to orthogonally calibrate the four clock phases. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram illustrating the quantization noise generation in a fractional frequency divider in existing technology; Figure 2 This is a schematic diagram of the open-loop fractional frequency divider with phase switching and Split-DTC structure disclosed in this invention; Figure 3 This is a schematic diagram of the orthogonal frequency division module disclosed in this invention; Figure 4 This is a schematic diagram of the CML to CMOS buffer disclosed in this invention; Figure 5 This is a schematic diagram of the phase switching module disclosed in this invention; Figure 6 This is a schematic diagram of the multimode frequency divider circuit disclosed in this invention; Figure 7 This is a schematic diagram of a first-order SDM disclosed in this invention; Figure 8 This is a schematic diagram of the DTC gain calibration module disclosed in this invention; Figure 9 This is a schematic diagram of the DTC linearity calibration module disclosed in this invention; Figure 10 This is a timing diagram of a fractional frequency divider provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of orthogonal calibration timing provided for an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] To make the technical problems, technical solutions, and beneficial effects of this invention clearer and more understandable, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0022] To address the shortcomings and improvement needs of existing technologies, this invention provides an open-loop fractional divider employing phase switching and a Split-DTC structure. Its purpose is to reduce the dynamic range of the DTC from 1 to 0.25 using phase switching, thereby reducing noise and power consumption on the DTC link. Simultaneously, when the divider needs to achieve a fractional division step of 0.25, it can achieve extremely low fractional spurious emissions. Furthermore, an orthogonal calibration module is used to compensate for errors generated during the switching of the four-phase clocks.

[0023] See Figure 2 , Figure 2This is a schematic diagram of the open-loop fractional frequency divider using phase switching and Split-DTC structure disclosed in this invention. The open-loop fractional frequency divider using phase switching and Split-DTC structure of this invention includes: an orthogonal frequency division module (such as...) Figure 2 middle Phase switching module (such as Figure 2 middle ), multi-mode frequency divider module (such as Figure 2 middle ), first-order SDM module (such as Figure 2 middle ), DTC gain calibration module (such as Figure 2 middle ), DTC linearity calibration module (such as Figure 2 middle ) and orthogonal calibration modules (such as Figure 2 middle ),in, The quadrature frequency divider module is used to orthogonally divide the input differential signal by two to obtain four-phase quadrature clock signals, namely: CLK_I, CLK_Q, CLK_IN, and CLK_QN. The phase switching module is used to switch the phases of the four-phase quadrature clock signals using four clocks, and outputs two phase switching signals PS_OUT1 and PS_OUT2, wherein the phase difference between PS_OUT1 and PS_OUT2 is [missing information]. , One clock cycle; A multi-mode frequency divider module is used to divide the phase switching signal by cascading 2 / 3 frequency dividers to obtain the divided FMMD signal. A first-order SDM module is used to modulate the frequency division ratio and generate the modulated frequency division ratio signal. The frequency division ratio signal Used to control the switching between DTC gain calibration and linearity calibration; The DTC gain calibration module is used to determine the gain control word and average gain control word KDTC of the four-phase clock based on the FMMD signal and the two phase switching signals. The gain control words are KDTC0, KDTC1, KDTC2, and KDTC3, respectively. The DTC linearity calibration module is used to determine the linearity-calibrated DTC control word based on the randomly selected control word and the FMMD signal. The orthogonal calibration module is used to determine the compensated DTC control word based on the gain control word and the average gain control word. This is to determine the phase-compensated frequency division signal based on the DTC control word and the FMMD signal.

[0024] In this embodiment, the orthogonal frequency division module includes: Two interconnected CML latches are used to convert the input differential signal into a four-phase quadrature clock signal; The CML-to-CMOS buffer connected to the CML latch is used to restore the four-phase quadrature clock signal to a full-swing signal.

[0025] See Figure 3 , Figure 3 This is a schematic diagram of the quadrature frequency divider module disclosed in this invention. The quadrature frequency divider module disclosed in this embodiment uses two CML latches to convert a pair of input differential clocks, i.e., differential signals, into four-phase quadrature clock signals, providing a basis for phase switching. Since the input is usually a pair of high-speed differential clocks, the latches used in this design are of CML structure. Therefore, a CML to CMOS buffer is also required. See [link to relevant documentation]. Figure 4 , Figure 4 This is a schematic diagram of the CML to CMOS buffer disclosed in this invention, which can restore the four-phase quadrature clock signal to a full-swing signal. It first uses a self-biased inverter to isolate the DC level of the latch output, and connects the input and output of the inverter through a resistor R. On the DC side, there is no current through the resistor, similar to connecting the first and second leads of the inverter together, providing a voltage approximately VDD / 2. On the AC side, adding a resistor amplifies the latch output, and then using an inverter chain to restore the output of the self-biased inverter to its full swing. In the inverter chain, a small-sized latch ensures the differential nature of the signal output by this module.

[0026] See Figure 5 , Figure 5 This is a schematic diagram of the phase switching module disclosed in this invention. The phase switching module in this embodiment is essentially a multiplexer, which can employ a Gray code-encoded 4-to-1 selector structure to ensure the stability of phase switching. Specifically, the inputs are four quadrature clock signals: CLK1, CLKQ, CLKIN, and CLKQN. The phase switching is essentially a 4-to-1 selector, which uses a cascaded 2-to-1 selector structure. To ensure the stability of the phase switching technology, Gray code encoding is used in the design. This phase switching technology generates two output signals, PSOUT1 and PSOUT2. The PSOUT1 signal needs to switch starting from the CLK1 phase. To obtain a phase-lagging PSOUT1 signal... The PS OUT2 signal requires the switching process to be initiated from the CLK Q phase. The phase difference between PSOUT1 and PS OUT2 lays an important foundation for subsequent DTC gain calibration.

[0027] See Figure 6 , Figure 6 This is a schematic diagram of the multi-mode frequency divider circuit disclosed in this invention. The multi-mode frequency divider module disclosed in this embodiment is composed of cascaded 2 / 3 dividers. The division ratio is set to 2 or 3 using the control signals mod_in and P, thereby achieving high speed and a wide division ratio. Each 2 / 3 divider consists of a latch, a buffer, and logic gates. Specifically, the entire circuit is divided into two parts: the upper part is the frequency division logic, and the lower part is the control logic. Under the control of the control logic, the frequency division logic executes a 2 or 3 division. In the control logic… The AND gate controls the selection of flip-flop 3, while P controls the selection of flip-flop 4. Only when... The control logic is only effective when both P and P are active, and the frequency division ratio is 3. When P and P are not both active, the control logic does not work, and the frequency divider's division ratio is 2.

[0028] See Figure 7 , Figure 7 This is a schematic diagram of a first-order SDM disclosed in this invention. The first-order SDM module disclosed in this embodiment can be an integrator that continuously accumulates the error signal. Considering that the dynamic range of DTC should not be too large, a first-order SDM structure is adopted.

[0029] See Figure 8 , Figure 8 This is a schematic diagram of the DTC gain calibration module disclosed in this invention. The DTC gain calibration module disclosed in this embodiment is used to sample the FMMD output of the multi-mode divider using the PS_OUT1 signal to obtain FMMD_Temp1; to sample FMMD_Temp1 using the PS_OUT2 signal to obtain FMMD_Temp2; to calculate the gain control word of the four-phase clock based on the phase difference between FMMD_Temp1 and FMMD_Temp2; and to obtain the average gain control word KDTC by adding the gain control words together. Specifically, at this time, MUX=0, and the two input signals are FMMD Temp1 and FMMD Temp2. ​​FMMD Temp1 is obtained by sampling the output FMMD of the multi-mode divider using the PS OUT1 signal generated by phase switching, and FMMD Temp2 is obtained by sampling FMMD Temp1 using the PSOUT2 signal generated by phase switching. Assume that the clock corresponding to the rising edge of FMMD Temp1 is the... Phase clock The rising edge of FMMD Temp2 corresponds to the clock of the first... Phase clock, in ideal conditions, the first Phase clock and the first The phase difference of the phase clock is However, due to the influence of manufacturing process, voltage, and temperature, there will be a certain clock deviation between the four-phase clocks. Therefore, we can obtain the following expression: Furthermore, the sum of the phase differences between the four-phase clocks still equals one clock cycle. Therefore, the sum of their clock deviations is 0, that is: Therefore, the average gain control word can be obtained. ,in .

[0030] See Figure 9 , Figure 9 This is a schematic diagram of the DTC linearity calibration module disclosed in this invention. The DTC linearity calibration module disclosed in this embodiment includes: The Split-DTC structure is used to modulate the weights to 3:2:1:1:1 and compensate for the linearity of DTC units with different weights. The Split-DTC structure includes: an MDTC module, which implements the 3:2:1:1:1 weight allocation; and a CDTC module, which is used to compensate for the linearity of DTC units with different weights in the MDTC module.

[0031] The BBPD phase detector is used to detect the phase difference of the output signal of the Split-DTC structure and adjust the control word, which is randomly selected by a lookup table (LUT) to control the DTC.

[0032] Specifically, at this point, MUX=1, and the input signals for all three DTC channels are FMMD Temp2. ​​The DTC can be divided into MDTC and CDTC. MDTC changes the traditional weighting ratio of 4:2:1:1 to 3:2:1:1:1, with each weight corresponding to a different DTC cell. CDTC compensates for the linearity of DTCs with different weights within MDTC; each DTC cell in MDTC has a corresponding CDTC control word. The linearity calibration module uses a lookup table (LUT) to... To randomly select the control word for DTC, in order to For example, after looking up the table, the control word for DTCA is 0100, and the control word for DTCB is 0011. The sum of the weights for both DTCA and DTCB is 2. However, due to poor linearity between DTCs, the output signals FAO and FBO are not aligned. BBPD is then used to phase-detect FAO and FBO. Assuming FAO leads FBO, since the DTCA control word is 0100, only the DTC cell with a weight of 2 is selected. Because FAO leads FBO, the weight of the DTC cell with a weight of 2 in DTCA is less than 2. Therefore, the control word of the CDTC corresponding to the weight of 2 is incremented by one to compensate for that weight. For DTCB, the control word is 0011, and the two selected DTC cells have a weight of 1. Since FBO lags behind FAO, the weight of DTCB is greater than 2. Therefore, the control words of the two CDTCs with a weight of 1 are decremented by one. The same operation can be performed on DTCB and DTCC. Since the control words of DTCA, DTCB, and DTCC can be iterated, each DTC cell in the MDTC can be calibrated given a sufficiently long calibration time, resulting in a final weighting of 3:2:1:1:1. To simultaneously perform gain and linearity calibration of the DTC while reducing the overall dynamic range of the DTC, the output of the SDM is used here. As a standard, when When ≤ 0.25, perform DTC gain calibration; when When the value is greater than 0.25, perform DTC linearity calibration.

[0033] Based on the above embodiments, the orthogonal calibration module provided in this embodiment is used to first determine the clock phase difference between the four gain control words obtained by the gain calibration module. , Next, the control word corresponding to the clock phase difference is accumulated into the third DTC control word.

[0034] See Figure 10 and Figure 11 , Figure 10 This is a timing diagram of a fractional frequency divider provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the orthogonal calibration timing provided in an embodiment of the present invention. Specifically, since the input pair of clocks cannot be completely differential, the resulting four-phase clocks cannot be completely orthogonal either. Therefore, an orthogonal calibration module is needed, and its timing is as follows: Figure 11 As shown. During gain calibration, we have obtained four gain control words respectively. , , , and average gain control word The four gain control words represent the phase information between the four clock phases, and the average gain control word... Represents The corresponding phase information. Ideally, when the phase switches from 0° to 90°, the phase difference between the two clocks corresponds to... control word However, in reality, the phase difference between these two clocks corresponds to... control word At this point, we can obtain the clock deviation corresponding to the two phase clocks. control word Therefore, the clock deviation between the four phase clocks is: Therefore, when phase switching is in operation, only the start phase and the end phase of the switching are needed to determine the resulting clock offset. The control word corresponding to this clock offset is then added to the DTC control word of the third channel. Since a first-order SDM is used in this case, an additional phase switching module is added. The SDM output is shown below. Furthermore, a phase of 0° is considered a complete large cycle. Theoretically, at this point... and the corresponding clock error control word However, in order to ensure the clock error control word It will not diverge; at the beginning of a large cycle, it will... That's it. At this point, the DTC control for the third channel is... To ensure that the DTC control word is not negative, a fixed control word is added here. That's all.

[0035] In this embodiment, an orthogonal frequency divider module is used to orthogonally divide the input differential signal by two to obtain a four-phase orthogonal clock signal, namely: CLK_I, CLK_Q, CLK_IN, and CLK_QN; a phase switching module is used to switch the phases of the four-phase orthogonal clock signal using four clock phases, outputting two phase switching signals PS_OUT1 and PS_OUT2, wherein the phase difference between PS_OUT1 and PS_OUT2 is [missing information]. , One clock cycle; a multi-mode divider module, used to divide the phase-switching signal by cascading 2 / 3 dividers to obtain the divided FMMD signal; a first-order SDM module, used to modulate the division ratio and generate the modulated division ratio signal. The frequency division ratio signal The system is used to control the switching between DTC gain calibration and linearity calibration; the DTC gain calibration module is used to determine the gain control word and average gain control word KDTC of the four-phase clock based on the FMMD signal and the two phase switching signals, wherein the gain control words are KDTC0, KDTC1, KDTC2, and KDTC3 respectively; the DTC linearity calibration module is used to determine the linearity-calibrated DTC control word based on the randomly selected control word and the FMMD signal; the quadrature calibration module is used to determine the compensated DTC control word based on the gain control word and the average gain control word. This allows the phase-compensated frequency division signal to be determined based on the DTC control word and the FMMD signal. Phase switching reduces the dynamic range of the DTC from 1 to 0.25, lowering noise and power consumption on the DTC link. Simultaneously, when the frequency divider needs to achieve a fractional division step of 0.25, extremely low fractional spurious emissions can be achieved. Furthermore, an orthogonal calibration module is used to orthogonally calibrate the four clock phases.

[0036] The above description discloses only one preferred embodiment of the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art will understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. An open-loop fractional frequency divider employing phase switching and a Split-DTC structure, characterized in that, include: The quadrature frequency divider module is used to orthogonally divide the input differential signal by two to obtain four-phase quadrature clock signals, namely: CLK_I, CLK_Q, CLK_IN, and CLK_QN. The phase switching module is used to switch the phases of the four-phase quadrature clock signals using four clocks, and outputs two phase switching signals PS_OUT1 and PS_OUT2, wherein the phase difference between PS_OUT1 and PS_OUT2 is [missing information]. , One clock cycle; A multi-mode frequency divider module is used to divide the phase switching signal by cascading 2 / 3 frequency dividers to obtain the divided FMMD signal. A first-order SDM module is used to modulate the frequency division ratio and generate the modulated frequency division ratio signal. The frequency division ratio signal Used to control the switching between DTC gain calibration and linearity calibration; The DTC gain calibration module is used to determine the gain control word and average gain control word KDTC of the four-phase clock based on the FMMD signal and the two phase switching signals. The gain control words are KDTC0, KDTC1, KDTC2, and KDTC3, respectively. The DTC linearity calibration module is used to determine the linearity-calibrated DTC control word based on the randomly selected control word and the FMMD signal. The orthogonal calibration module is used to determine the compensated DTC control word based on the gain control word and the average gain control word. This is to determine the phase-compensated frequency division signal based on the DTC control word and the FMMD signal.

2. The frequency divider according to claim 1, characterized in that, The orthogonal frequency division module includes: Two interconnected CML latches are used to convert the input differential signal into a four-phase quadrature clock signal; The CML-to-CMOS buffer connected to the CML latch is used to restore the four-phase quadrature clock signal to a full-swing signal.

3. The frequency divider according to claim 2, characterized in that, The phase switching module adopts a Gray code-encoded 4-to-1 selector structure.

4. The frequency divider according to claim 3, characterized in that, The multi-mode frequency divider module is composed of cascaded 2 / 3 frequency dividers, which can achieve a frequency division ratio of 2 or 3 through the control signals mod_in and P. The 2 / 3 frequency divider consists of latches, buffers and logic gates.

5. The frequency divider according to claim 4, characterized in that, The DTC gain calibration module is used to sample the FMMD output of the multi-mode divider using the PS_OUT1 signal to obtain FMMD_Temp1; to sample FMMD_Temp1 using the PS_OUT2 signal to obtain FMMD_Temp2; to calculate the gain control word of the four-phase clock based on the phase difference between FMMD_Temp1 and FMMD_Temp2; and to sum the gain control words and take the average to obtain the average gain control word KDTC.

6. The frequency divider according to claim 5, characterized in that, The DTC linearity calibration module includes: The Split-DTC structure is used to modulate the weights to 3:2:1:1:1 and compensate for the linearity of DTC units with different weights. The BBPD phase detector is used to detect the phase difference of the output signal of the Split-DTC structure and adjust the control word, which is randomly selected by a lookup table (LUT) to control the DTC.

7. The frequency divider according to claim 6, characterized in that, The orthogonal calibration module is used to determine the clock phase difference between the four gain control words obtained by the gain calibration module. , ; The control word corresponding to the clock phase difference is accumulated into the third DTC control word.

8. The frequency divider according to claim 7, characterized in that, The frequency division ratio signal The control for switching between DTC gain calibration and linearity calibration includes: when When ≤ 0.25, perform DTC gain calibration; when When the value is > 0.25, perform DTC linearity calibration.

9. The frequency divider according to claim 8, characterized in that, The Split-DTC structure includes: The MDTC module implements a 3:2:1:1:1 weight allocation. The CDTC module is used to compensate for the linearity of DTC units with different weights in the MDTC module.

10. The frequency divider according to claim 9, characterized in that, The phase switching module switches when two of the four-phase clocks are simultaneously at a high level.

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