A signal phase and frequency shift extraction hardware architecture

Abstract

The application discloses a signal phase and frequency shift extraction hardware architecture, comprising a local oscillator module, a quadrature square wave generation module, an input signal module, a signal conversion module, an analog switch mixing module, a low-pass filter module and an ADC signal acquisition module; the quadrature square wave generation module is configured to receive a local oscillator clock signal from the local oscillator module, generate two quadrature square wave signals, and input the two quadrature square wave signals to the analog switch mixing module; the signal conversion module is configured to receive a single-ended signal from the input signal module, convert the single-ended signal into a differential signal, and input the differential signal to the analog switch mixing module; and the analog switch mixing module is configured to mix the differential signal with the quadrature square wave signal to obtain two quadrature differential signals carrying phase and frequency shift information. The application directly realizes mixing and phase detection by using a full hardware simulation architecture, does not need digital processing chips such as FPGA and DSP, eliminates inherent delay caused by digital processing, and ensures that the system response time is less than or equal to 0.8 milliseconds.

Description

Technical Field

[0001] This application relates to the field of Doppler signal measurement technology, and in particular to a hardware architecture for extracting signal phase and frequency shift. Background Technology

[0002] Currently, mainstream phase and frequency shift extraction schemes are mainly divided into two categories. The first category is the digital mixing and phase detection scheme based on digital devices such as FPGAs. It mainly uses expensive digital processing chips such as FPGAs and DSPs to sample, digitally mix, filter, and calculate phase and frequency shift of the signal. The second category is the mixing and phase detection scheme based on hardware multipliers. It mainly uses a dedicated multiplier chip to realize mixing and phase detection. The multiplier multiplies the input signal with a quadrature reference signal, and then filters to extract phase and frequency shift information.

[0003] Neither of the above two solutions can simultaneously meet the general industrial requirements of low cost, low power consumption, high response speed, and moderate measurement accuracy, and they are especially unsuitable for portable ultrasonic measuring equipment and low-to-mid-range industrial flow monitoring scenarios. Summary of the Invention

[0004] The purpose of this application is to provide a hardware architecture for signal phase and frequency shift extraction, thereby solving the technical problems of complex structure and poor accuracy in existing architectures. The various technical effects of the preferred solutions among the many technical solutions provided in this application are detailed below.

[0005] To achieve the above objectives, this application provides the following technical solutions: This application provides a hardware architecture for signal phase and frequency shift extraction, including a local oscillator module, an orthogonal square wave generation module, an input signal module, a signal conversion module, an analog switch mixer module, a low-pass filter module, and an ADC signal acquisition module. The local oscillator module is connected to the orthogonal square wave generation module, the input signal module is connected to the signal conversion module, the analog switch mixer module is connected to the orthogonal square wave generation module, the signal conversion module, and the low-pass filter module, and the low-pass filter module is connected to the ADC signal acquisition module. The orthogonal square wave generation module is configured to receive a local oscillator clock signal from the local oscillator module, generate two orthogonal square wave signals, and input them to the analog switch mixer module. The signal conversion module is configured to receive a single-ended signal from the input signal module and convert the single-ended signal... The differential signal is input to the analog switch mixer module; the analog switch mixer module is configured to mix the differential signal with the orthogonal square wave signal to obtain two orthogonal differential signals carrying phase and frequency shift information; the low-pass filter module is configured to receive the orthogonal differential signal from the analog switch mixer module, filter out the local oscillator frequency and higher harmonic signals in the orthogonal differential signal to obtain a difference frequency signal carrying phase and frequency shift information, and gain the difference frequency signal to obtain a low-frequency orthogonal signal; the ADC signal acquisition module is configured to receive the low-frequency orthogonal signal from the low-pass filter module, perform analog-to-digital conversion on the low-frequency orthogonal signal, and transmit the digital signal to the MCU chip; the MCU chip extracts the phase and frequency shift of the digital signal and finally outputs the phase and frequency offset values.

[0006] In some embodiments, the quadrature square wave generation module includes a first D flip-flop U1A, a second D flip-flop U1B, and an inverter U3; the clock input pin of the first D flip-flop U1A is connected to the local oscillator module and the input terminal of the inverter U3, the data input pin of the first D flip-flop U1A is connected to its own inverted output pin, the clock input pin of the second D flip-flop U1B is connected to the output terminal of the inverter U3, and the data input pin of the second D flip-flop U1B is connected to its own inverted output pin.

[0007] In some embodiments, the signal conversion module includes an interface J4, a transformer T2, capacitors C1 and C2, and a resistor R44; the interface J4 is connected to the fourth and sixth terminals of the transformer T2, the second terminal of the transformer T2 is connected to one end of the resistor R44, the other end of the resistor R44 is connected to the power supply voltage, one end of capacitor C1, and one end of capacitor C2, and the other ends of capacitor C1 and capacitor C2 are grounded.

[0008] In some embodiments, the analog switch mixer module includes an analog switch chip U5; the first input pin of the analog switch chip U5 is connected to the output pin of the first D flip-flop U1A, the second input pin of the analog switch chip U5 is connected to the output pin of the second D flip-flop U1B, the third input pin of the analog switch chip U5 is connected to the first terminal of the transformer T2, the fourth input pin of the analog switch chip U5 is connected to the third terminal of the transformer T2, and the four output pins of the analog switch chip U5 are connected to the low-pass filter module.

[0009] In some embodiments, the low-pass filter module includes a first filtering submodule and a second filtering submodule; the first filtering submodule is used to receive the I-channel differential signal and output the I-channel signal in the low-frequency quadrature signal, and the second filtering submodule is used to receive the Q-channel differential signal and output the Q-channel signal in the low-frequency quadrature signal.

[0010] In some embodiments, the first filtering submodule includes an operational amplifier U6, resistors R20, R25, and R27, and capacitors C30, C39, and C42. The positive input terminal of the operational amplifier U6 is connected to one end of capacitor C30 and one end of resistor R20, and the other end of capacitor C30 is connected to the first output pin of the analog switch chip U5. The negative input terminal of the operational amplifier U6 is connected to one end of resistor R27, one end of resistor R25, and one end of capacitor C42. The other end of resistor R27 is connected to one end of capacitor C39, and the other end of capacitor C39 is connected to the second output pin of the analog switch chip U5. The output terminal of the operational amplifier U6 is connected to the other end of resistor R25, the other end of capacitor C42, and the ADC signal acquisition module, and is used to output the I-channel signal.

[0011] In some embodiments, the second filtering submodule includes an operational amplifier U7, resistors R38, R40, and R41, and capacitors C56, C64, and C65. The positive input terminal of the operational amplifier U7 is connected to one end of capacitor C56 and one end of resistor R38, and the other end of capacitor C56 is connected to the third output pin of the analog switch chip U5. The negative input terminal of the operational amplifier U7 is connected to one end of resistor R41, one end of resistor R40, and one end of capacitor C65. The other end of resistor R41 is connected to one end of capacitor C64, and the other end of capacitor C64 is connected to the fourth output pin of the analog switch chip U5. The output terminal of the operational amplifier U7 is connected to the other end of resistor R40, the other end of capacitor C65, and the ADC signal acquisition module, for outputting the Q-channel signal. In some embodiments, the local oscillator module is an active clock chip, and the local oscillator clock signal is a square wave signal.

[0012] In some embodiments, the first filtering submodule further includes capacitors C21, C25, and C27, and a ferrite bead FB3; one end of capacitor C21, one end of capacitor C25, one end of capacitor C27, and one end of ferrite bead FB3 are all connected to the power supply terminal of the operational amplifier U6, the other ends of capacitors C21, C25, and C27 are interconnected and grounded, and the other end of ferrite bead FB3 is connected to the power supply voltage.

[0013] In some embodiments, the second filtering submodule further includes capacitors C46, ​​C49, C53, and ferrite bead FB6; one end of capacitor C46, ​​one end of capacitor C49, one end of capacitor C53, and one end of ferrite bead FB6 are all connected to the power supply terminal of the operational amplifier U7, the other ends of capacitors C46, ​​C49, and C53 are interconnected and grounded, and the other end of ferrite bead FB6 is connected to the power supply voltage.

[0014] Implementing one of the above-mentioned technical solutions of this application has the following advantages or beneficial effects: In this application, the quadrature square wave generation module processes the local oscillator clock signal into a quadrature square wave signal, while the signal conversion module processes the single-ended signal into a differential signal. Subsequently, the analog switching mixer module mixes the quadrature square wave signal and the differential signal to obtain a quadrature differential signal. After filtering and analog-to-digital conversion, a digital signal is output. Finally, the phase and frequency offset values ​​are output by the MCU chip.

[0015] This application employs a fully hardware analog architecture to directly implement mixing and phase detection, eliminating the need for digital processing chips such as FPGAs and DSPs. This eliminates the inherent latency caused by digital processing and ensures a system response time of less than or equal to 0.8 milliseconds, which is superior to existing digital solutions. Furthermore, this application abandons FPGAs and dedicated multipliers, using general-purpose analog chips to construct the core circuit, resulting in lower construction costs and making it more suitable for low-power portable devices and low-to-mid-range industrial scenarios. In addition, this application suppresses even-order harmonics through a double-balanced mixing structure, improves signal purity by combining active filtering, and uses pure hardware timing logic to generate high-precision orthogonal square waves, ensuring a phase measurement accuracy of less than or equal to ±0.25°. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a structural block diagram of the hardware architecture for signal phase and frequency shift extraction according to an embodiment of this application; Figure 2 This is a circuit diagram of the orthogonal square wave generation module according to an embodiment of this application; Figure 3 This is a circuit diagram of the signal conversion module according to an embodiment of this application; Figure 4 This is a circuit diagram of the analog switching mixer module according to an embodiment of this application; Figure 5 This is a circuit diagram of a low-pass filter module according to an embodiment of this application.

[0017] In the diagram: 1. Hardware architecture for signal phase and frequency shift extraction; 10. Local oscillator module; 20. Orthogonal square wave generation module; 30. Input signal module; 40. Signal conversion module; 50. Analog switch mixer module; 60. Low-pass filter module; 70. ADC signal acquisition module; 61. First filtering submodule; 62. Second filtering submodule. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments and depict various exemplary embodiments that may be adopted to implement this application. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of this application disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of this application.

[0019] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0020] To illustrate the technical solutions described in this application, specific embodiments are provided below, showing only the parts related to the embodiments of this application.

[0021] like Figures 1 to 5 As shown, this application provides a hardware architecture 1 for signal phase and frequency shift extraction, including: The system comprises a local oscillator module 10, a quadrature square wave generation module 20, an input signal module 30, a signal conversion module 40, an analog switch mixer module 50, a low-pass filter module 60, and an ADC signal acquisition module 70. The local oscillator module 10 is connected to the quadrature square wave generation module 20, the input signal module 30 is connected to the signal conversion module 40, the analog switch mixer module 50 is connected to the quadrature square wave generation module 20, the signal conversion module 40, and the low-pass filter module 60, and the low-pass filter module 60 is connected to the ADC signal acquisition module 70.

[0022] In some embodiments, the quadrature square wave generation module 20 can be configured to receive the local oscillator clock signal from the local oscillator module 10, generate two quadrature square wave signals, and input them to the analog switch mixer module 50.

[0023] In some embodiments, the signal conversion module 40 may be configured to receive a single-ended signal from the input signal module 30, convert the single-ended signal into a differential signal, and input it to the analog switch mixer module 50.

[0024] In some embodiments, the analog switch mixer module 50 can be configured to mix the differential signal with the orthogonal square wave signal to obtain two orthogonal differential signals carrying phase and frequency shift information.

[0025] In some embodiments, the low-pass filter module 60 may be configured to receive the quadrature differential signal from the analog switch mixer module 50, filter out the local oscillator frequency and higher harmonic signals in the quadrature differential signal to obtain a difference frequency signal carrying phase and frequency shift information, and amplify the difference frequency signal to obtain a low-frequency quadrature signal.

[0026] In some embodiments, the ADC signal acquisition module 70 is configured to receive low-frequency quadrature signals from the low-pass filter module 60, perform analog-to-digital conversion on the low-frequency quadrature signals, obtain digital signals, and transmit them to the MCU chip. The MCU chip extracts the phase and frequency shift of the digital signals and finally outputs the phase and frequency offset values.

[0027] In some embodiments, the local oscillator module 10 can be an active clock chip, and the local oscillator clock signal can be a square wave signal. The local oscillator clock signal can be used as the clock reference for the signal phase and frequency shift extraction hardware architecture 1. The frequency of the local oscillator clock signal can be flexibly adjusted as needed, specifically in the range of 10kHz to 4MHz, with a clock jitter of less than or equal to 50ps.

[0028] In some embodiments, the quadrature square wave generation module 20 may include a first D flip-flop U1A, a second D flip-flop U1B, and an inverter U3. The clock input pin of the first D flip-flop U1A is connected to the local oscillator module 10 and the input of the inverter U3. The data input pin of the first D flip-flop U1A is connected to its own inverted output pin. The clock input pin of the second D flip-flop U1B is connected to the output of the inverter U3. The data input pin of the second D flip-flop U1B is connected to its own inverted output pin. The output pins of the first D flip-flop U1A and the second D flip-flop U1B output two quadrature square wave signals with a phase difference of 90° ± 0.25°. This provides precise control signals for the analog switching mixer module 50.

[0029] like Figure 2As shown, the CLK pin is the clock input pin, the D pin is the data input pin, and the Q pin is the output pin. The pin is the inverting output pin.

[0030] Specifically, the CLK pin of the first D flip-flop U1A receives the local oscillator clock signal, and simultaneously, the inverter U3 receives the local oscillator clock signal. After inverting the local oscillator clock signal, an inverted signal is obtained. The CLK pin of the second D flip-flop U1B receives the inverted signal. The first D flip-flop U1A's... Pins and the second D flip-flop U1B All pins are inverting output pins. By connecting the D pin to its own... The pin connection enables the local oscillator clock signal to be divided by two.

[0031] Through the aforementioned cross-feedback design, utilizing the inherent timing characteristic of the D flip-flops flipping at each clock edge, the Q signal (S1) output by the first D flip-flop U1A and the Q signal (S2) output by the second D flip-flop U1B form a strict 90° phase difference, with a phase accuracy ≤ ±0.25°. Furthermore, the mathematical expression for the orthogonal square wave signal can be: S(t) = (4 / π)[cos(ω0t) - (1 / 3)cos(3ω0t) + (1 / 5)cos(5ω0t) + ...]. The orthogonal square wave signal is a square wave formed by the superposition of odd harmonics, which can meet the control requirements of the analog switching mixer module 50, and the harmonic components can be effectively filtered out by the subsequent low-pass filter module 60.

[0032] In some embodiments, the first D flip-flop U1A and the second D flip-flop U1B can be any of SN74HC74, SGM74AC74, HD74AC74, and 74AC74D. The inverter U3 can be SN74HC04.

[0033] The orthogonal square wave generation module 20 of this application embodiment has a simple structure and can achieve stable output of high-precision orthogonal square waves.

[0034] In some embodiments, the input signal module 30 can be used to output a single-ended signal, which originates from the echo reception signal of the Doppler signal and can be from the same source as the local oscillator clock signal, thereby ensuring the accuracy of phase comparison. The signal type is a single-ended analog signal with an amplitude range of 10uV to 10mV and a frequency close to the local oscillator clock signal (with a slight frequency shift, corresponding to the phase and frequency shift of the Doppler signal).

[0035] In some embodiments, the signal conversion module 40 may include an interface J4, a transformer T2, capacitors C1 and C2, and a resistor R44. Interface J4 is connected to the fourth and sixth terminals of transformer T2, which are the primary windings of transformer T2. The secondary windings of transformer T2 include the first, second, and third terminals. The first and second terminals of transformer T2 output a differential signal. The second terminal of transformer T2 is connected to one end of resistor R44. The other end of resistor R44 is connected to one end of both the power supply voltage capacitor C1 and capacitor C2. The other ends of capacitors C1 and C2 are grounded.

[0036] Specifically, a single-ended signal can be represented as: V_in(t) = A·cos[(ω0±Δω)t + φ], Where A is the signal amplitude, ω0 is the local oscillator clock angular frequency, Δω is the angular frequency corresponding to the Doppler frequency shift, and φ is the phase shift caused by signal propagation.

[0037] The primary winding of transformer T2 receives single-ended signals, and the secondary winding of transformer T2 outputs differential signals Vout_DPL+ and Vout_DPL- to realize the conversion from single-ended signals to differential signals.

[0038] Capacitors C1 and C2 are both filter capacitors. C1 has a value of 10μF, and C2 has a value of 0.1μF. Capacitors C1 and C2 are used to filter out power supply noise. Resistor R44 is a current-limiting resistor with a resistance of 510Ω. It is used to protect the primary winding of the transformer from overcurrent damage.

[0039] Furthermore, the signal conversion module 40 of this application has the following performance parameters: common-mode rejection ratio greater than or equal to 65dB, insertion loss less than or equal to 0.5dB, temperature drift less than or equal to ±0.08% / ℃, and stable conversion performance within a wide industrial temperature range of -40℃ to 85℃, effectively suppressing environmental common-mode interference. By setting the signal conversion module 40, the anti-interference capability of the signal can be improved, and the impact of common-mode noise on subsequent mixing and phase detection can be reduced.

[0040] In some embodiments, the analog switch mixer module 50 may include an analog switch chip U5. The first input pin of the analog switch chip U5 is connected to the output pin of the first D flip-flop U1A, the second input pin of the analog switch chip U5 is connected to the output pin of the second D flip-flop U1B, the third input pin of the analog switch chip U5 is connected to the first terminal of the transformer T2, the fourth input pin of the analog switch chip U5 is connected to the third terminal of the transformer T2, and the four output pins of the analog switch chip U5 are connected to the low-pass filter module 60.

[0041] In some embodiments, the analog switch mixer module 50 may further include a ferrite bead FB4, capacitors C22, C24, and C32. One end of the ferrite bead FB4 is connected to the regulated voltage, and the other end of the ferrite bead FB4 is connected to one end of capacitors C22, C24, and C32, as well as the power supply pin of the analog switch chip U5. The other ends of capacitors C22, C24, and C32, as well as the output enable pin of the analog switch chip U5, are all connected to and grounded.

[0042] like Figure 4 As shown, pin 2 of analog switch chip U5 is the first input pin, pin 14 of analog switch chip U5 is the second input pin, pin 7 of analog switch chip U5 is the third input pin, pin 9 of analog switch chip U5 is the fourth input pin, pin 6 or pin 11 of analog switch chip U5 is the first output pin, pin 3 or pin 10 of analog switch chip U5 is the second output pin, pin 5 or pin 13 of analog switch chip U5 is the third output pin, pin 4 or pin 12 of analog switch chip U5 is the fourth output pin, pin 15 of analog switch chip U5 is the output enable pin, and pin 16 of analog switch chip U5 is the power supply pin.

[0043] The first and second output pins of the analog switch chip U5 can be used to output I-channel differential signals, and the third and fourth output pins can be used to output Q-channel differential signals, for a total of two quadrature differential signals.

[0044] Specifically, the analog switch chip U5 can be any of the following: SN74CBTLV3253, SGM3253, 74CBTLV3253PW, and CBTLV-3253. The analog switch chip U5 features low on-resistance, fast switching speed, and low power consumption, making it suitable for medium and low frequency mixing scenarios.

[0045] The analog switch chip U5 is a dual-balanced bridge structure. The four switching transistors are controlled by two orthogonal square wave signals output from the orthogonal square wave generation module 20 and their inverted signals, respectively, to alternately turn on and off the differential signal output from the signal conversion module 40. In other words, by controlling the orthogonal square wave signals, the differential signal can be multiplied (mixed) with the orthogonal square wave signal. The orthogonal differential signal V_out(t) = V_in(t) × S(t) is mathematically derived as follows: V_out(t)=(4A / π)cos[(ω0±Δω)t + φ]×[cos(ω0t) - (1 / 3)cos(3ω0t) +(1 / 5)cos(5ω0t) + ...] After expansion using the product-difference formula, the orthogonal differential signal contains a sum-frequency component and a difference-frequency component. The sum-frequency component can be represented as ω0±Δω+ω0, ω0±Δω+3ω0, ω0±Δω+5ω0, ..., which are high-frequency components and can be filtered out later. The difference-frequency component can be represented as ω0±Δω-ω0, ω0±Δω-3ω0, ω0±Δω-5ω0, ..., which are low-frequency components and carry phase offset φ and frequency offset Δf information.

[0046] The two orthogonal differential signals are I-channel differential signals (I_out_n, I_out_p) and Q-channel differential signals (Q_out_n, Q_out_p). The phase difference between the two orthogonal differential signals is 90°, which can provide a basis for subsequent phase and frequency shift calculations.

[0047] This application uses an analog switch to construct a dual-balanced bridge structure, which can replace the traditional dedicated mixer / multiplier to achieve the mixing function, and has the advantages of low cost, low power consumption and good linearity.

[0048] In some embodiments, the low-pass filter module 60 may include a first filtering submodule 61 and a second filtering submodule 62. The first filtering submodule 61 is used to receive the I-channel differential signal and output the I-channel signal in the low-frequency quadrature signal, and the second filtering submodule 62 is used to receive the Q-channel differential signal and output the Q-channel signal in the low-frequency quadrature signal.

[0049] In some embodiments, the first filtering submodule 61 may include an operational amplifier U6, resistors R20, R25, and R27, and capacitors C30, C39, and C42. The positive input terminal of operational amplifier U6 is connected to one end of capacitor C30 and one end of resistor R20, and the other end of capacitor C30 is connected to the first output pin of analog switch chip U5. The negative input terminal of operational amplifier U6 is connected to one end of resistor R27, one end of resistor R25, and one end of capacitor C42. The other end of resistor R27 is connected to one end of capacitor C39, and the other end of capacitor C39 is connected to the second output pin of analog switch chip U5. The output terminal of operational amplifier U6 is connected to the other end of resistor R25, the other end of capacitor C42, and the ADC signal acquisition module 70, for outputting an I-channel signal.

[0050] In some embodiments, the first filtering submodule 61 may further include capacitors C21, C25, and C27, and a ferrite bead FB3. One end of capacitors C21, C25, C27, and FB3 is connected to the power supply terminal of operational amplifier U6. The other ends of capacitors C21, C25, and C27 are interconnected and grounded. The other end of FB3 is connected to the power supply voltage.

[0051] In some embodiments, the second filtering submodule 62 may include an operational amplifier U7, resistors R38, R40, and R41, and capacitors C56, C64, and C65. The positive input terminal of operational amplifier U7 is connected to one end of capacitor C56 and one end of resistor R38, and the other end of capacitor C56 is connected to the third output pin of analog switch chip U5. The negative input terminal of operational amplifier U7 is connected to one end of resistor R41, one end of resistor R40, and one end of capacitor C65, and the other end of resistor R41 is connected to one end of capacitor C64, and the other end of capacitor C64 is connected to the fourth output pin of analog switch chip U5. The output terminal of operational amplifier U7 is connected to the other end of resistor R40, the other end of capacitor C65, and the ADC signal acquisition module 70, and is used to output the Q-channel signal.

[0052] In some embodiments, the second filter submodule 62 may further include capacitors C46, ​​C49, C53 and ferrite bead FB6. One end of capacitors C46, ​​C49, C53 and FB6 are connected to the power supply terminal of operational amplifier U7. The other ends of capacitors C46, ​​C49 and C53 are interconnected and grounded. The other end of FB6 is connected to the power supply voltage.

[0053] Specifically, operational amplifier U6, resistor R25, and capacitor C42, and operational amplifier U7, resistor R40, and capacitor C65 are the low-pass filtering sections of the first filtering submodule 61 and the second filtering submodule 62, respectively. Their cutoff frequency f1 is less than or equal to 20KHz, and they are used to filter out high-order harmonics, i.e. sum-frequency components, in the mixing signal.

[0054] Operational amplifier U6, resistor R20, and capacitor C30, and operational amplifier U7, resistor R38, and capacitor C56 are the high-pass filtering sections of the first filtering submodule 61 and the second filtering submodule 62, respectively. The cutoff frequency f2 is greater than or equal to 3Hz, and they are used to filter out DC drift and low-frequency noise in the signal.

[0055] After two stages of filtering, only the fundamental harmonic of the difference frequency signal is retained, and the output signals are the I-channel signal DPL_I=A·cos(±Δω·t+φ) and the Q-channel signal DPL_Q=A·sin(±Δω·t+φ).

[0056] Furthermore, operational amplifier U6, resistors R25 and R27, and capacitor C42, as well as operational amplifier U7, resistors R40 and R40, and capacitor C65, are the signal amplification sections of the first filter submodule 61 and the second filter submodule 62, respectively. At the same time, by adjusting resistors R25, R27, R40, and R41, an adjustable gain of 1 to 100 times can be achieved to amplify the signal amplitude to the ADC adaptation range.

[0057] Capacitors C21, C25, C27, C46, ​​C49, and C53 are all filter capacitors used to filter out power supply noise. Specifically, C21 is 10μF, C25 is 0.1μF, C27 is 100pF, C46 is 10μF, C49 is 0.1μF, and C53 is 100pF. Ferrite beads FB3 and FB6 can be used to absorb high-frequency noise and spike interference on the power line.

[0058] In some embodiments, the operational amplifiers U6 and U7 may be any of the following: LM324, SGM324, MS324, AiP324, and LM324.

[0059] In some embodiments, the ADC signal acquisition module 70 can be an ADC digital-to-analog converter, which can simultaneously acquire the I-channel signal (DPL_I) and Q-channel signal (DPL_Q) output by the low-pass filter module, convert them into digital signals, and transmit them to the MCU chip.

[0060] In some embodiments, the MCU chip can calculate the bit offset φ and Doppler frequency shift Δf based on the I-channel signal and the Q-channel digital signal, and can also calculate the signal amplitude A.

[0061] In some embodiments, the signal amplitude A can be expressed as: A = √(I² + Q²) In some embodiments, the signal phase can be represented as: φ = arctan(Q / I) In some embodiments, the Doppler frequency shift can be expressed as: Δf=(1 / 2π)·dφ / dt In some embodiments, the MCU chip can be any of the STM32F103, HC32F103, and GD32F103. The MCU chip does not require complex digital signal processing capabilities, only simple arithmetic operations, further reducing system cost and power consumption.

[0062] In this application, the quadrature square wave generation module 20 processes the local oscillator clock signal into a quadrature square wave signal, while the signal conversion module 40 processes the single-ended signal into a differential signal. Subsequently, the analog switching mixer module 50 mixes the quadrature square wave signal and the differential signal to obtain a quadrature differential signal. After filtering and analog-to-digital conversion, the digital signal is output, and finally the phase and frequency offset values ​​are output by the MCU chip.

[0063] This application employs a fully hardware analog architecture to directly implement mixing and phase detection, eliminating the need for digital processing chips such as FPGAs and DSPs. This eliminates the inherent latency caused by digital processing and ensures a system response time of less than or equal to 0.8 milliseconds, which is superior to existing digital solutions. Furthermore, this application abandons FPGAs and dedicated multipliers, using general-purpose analog chips to construct the core circuit, resulting in lower construction costs and making it more suitable for low-power portable devices and low-to-mid-range industrial scenarios. In addition, this application suppresses even-order harmonics through a double-balanced mixing structure, improves signal purity by combining active filtering, and uses pure hardware timing logic to generate high-precision orthogonal square waves, ensuring a phase measurement accuracy of less than or equal to ±0.25°.

[0064] This application also relates to a signal phase and frequency shift extraction method, which is applied to the above-mentioned signal phase and frequency shift extraction hardware architecture 1. The signal phase and frequency shift extraction method includes: Receive the local oscillator clock signal and generate two orthogonal square wave signals based on the local oscillator clock signal; Receive single-ended signals and convert them into differential signals; The differential signal is mixed with the orthogonal square wave signal to obtain two orthogonal differential signals carrying phase and frequency shift information. The local oscillator frequency and higher harmonic signals in the orthogonal differential signal are filtered out to obtain the difference frequency signal carrying phase and frequency shift information. The difference frequency signal is then amplified to obtain the low-frequency orthogonal signal. The low-frequency quadrature signal is converted from analog to digital to obtain a digital signal. The phase and frequency shift of the digital signal are extracted, and the phase and frequency shift values ​​are finally output.

[0065] Those skilled in the art will understand that all or part of the features / steps of the above-described method embodiments can be implemented by methods, data processing systems, or computer programs. These features may be implemented without hardware, entirely in software, or in a combination of hardware and software. The aforementioned computer program may be stored in one or more computer-readable storage media. When the computer program is executed (e.g., by a processor), it performs the steps of the above-described signal phase and frequency shift extraction method embodiments.

[0066] The aforementioned storage media capable of storing program code include: static hard disks, solid-state hard disks, random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), optical storage devices, magnetic storage devices, flash memory, magnetic disks or optical disks, and / or combinations of the above devices, that is, they can be implemented by any type of volatile or non-volatile storage devices or combinations thereof.

[0067] This application also provides a processing device embodiment, including one or more processors and a memory; wherein the memory is used to store one or more computer programs, and the one or more processors are used to execute the one or more computer programs stored in the memory, so that the processors execute the features / steps of the above-described signal phase and frequency shift extraction method embodiment.

[0068] The above description is merely a preferred embodiment of this application. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this application. Furthermore, under the teachings of this application, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this application. Therefore, this application is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this application.

Claims

1. A hardware architecture for signal phase and frequency shift extraction, characterized in that, The system includes a local oscillator module, an orthogonal square wave generation module, an input signal module, a signal conversion module, an analog switching mixer module, a low-pass filter module, and an ADC signal acquisition module. The local oscillator module is connected to the orthogonal square wave generation module, the input signal module is connected to the signal conversion module, the analog switching mixer module is connected to the orthogonal square wave generation module, the signal conversion module, and the low-pass filter module, and the low-pass filter module is connected to the ADC signal acquisition module. The quadrature square wave generation module is configured to receive the local oscillator clock signal from the local oscillator module, generate two quadrature square wave signals, and input them to the analog switch mixer module; The signal conversion module is configured to receive a single-ended signal from the input signal module, convert the single-ended signal into a differential signal, and input it to the analog switch mixer module. The analog switch mixer module is configured to mix the differential signal with the orthogonal square wave signal to obtain two orthogonal differential signals carrying phase and frequency shift information. The low-pass filter module is configured to receive the quadrature differential signal from the analog switch mixer module, filter out the local oscillator frequency and higher harmonic signals in the quadrature differential signal to obtain a difference frequency signal carrying phase and frequency shift information, and gain the difference frequency signal to obtain a low-frequency quadrature signal. The ADC signal acquisition module is configured to receive low-frequency quadrature signals from the low-pass filter module, perform analog-to-digital conversion on the low-frequency quadrature signals, obtain digital signals, and transmit them to the MCU chip. The MCU chip extracts the phase and frequency shift of the digital signals and finally outputs the phase and frequency offset values.

2. The hardware architecture for signal phase and frequency shift extraction according to claim 1, characterized in that, The quadrature square wave generation module includes a first D flip-flop U1A, a second D flip-flop U1B, and an inverter U3; the clock input pin of the first D flip-flop U1A is connected to the local oscillator module and the input terminal of the inverter U3, the data input pin of the first D flip-flop U1A is connected to its own inverted output pin, the clock input pin of the second D flip-flop U1B is connected to the output terminal of the inverter U3, and the data input pin of the second D flip-flop U1B is connected to its own inverted output pin.

3. The hardware architecture for signal phase and frequency shift extraction according to claim 2, characterized in that, The signal conversion module includes an interface J4, a transformer T2, capacitors C1 and C2, and a resistor R44. The interface J4 is connected to the fourth and sixth terminals of the transformer T2. The second terminal of the transformer T2 is connected to one end of the resistor R44. The other end of the resistor R44 is connected to the power supply voltage, one end of capacitor C1, and one end of capacitor C2. The other ends of capacitor C1 and capacitor C2 are grounded.

4. The hardware architecture for signal phase and frequency shift extraction according to claim 3, characterized in that, The analog switch mixer module includes an analog switch chip U5; the first input pin of the analog switch chip U5 is connected to the output pin of the first D flip-flop U1A, the second input pin of the analog switch chip U5 is connected to the output pin of the second D flip-flop U1B, the third input pin of the analog switch chip U5 is connected to the first end of the transformer T2, the fourth input pin of the analog switch chip U5 is connected to the third end of the transformer T2, and the four output pins of the analog switch chip U5 are connected to the low-pass filter module.

5. The hardware architecture for signal phase and frequency shift extraction according to claim 1, characterized in that, The low-pass filter module includes a first filtering submodule and a second filtering submodule; the first filtering submodule is used to receive the I-channel differential signal and output the I-channel signal in the low-frequency quadrature signal, and the second filtering submodule is used to receive the Q-channel differential signal and output the Q-channel signal in the low-frequency quadrature signal.

6. The hardware architecture for signal phase and frequency shift extraction according to claim 5, characterized in that, The first filtering submodule includes an operational amplifier U6, resistors R20, R25, and R27, and capacitors C30, C39, and C42. The positive input terminal of the operational amplifier U6 is connected to one end of capacitor C30 and one end of resistor R20, and the other end of capacitor C30 is connected to the first output pin of the analog switch chip U5. The negative input terminal of the operational amplifier U6 is connected to one end of resistor R27, one end of resistor R25, and one end of capacitor C42. The other end of resistor R27 is connected to one end of capacitor C39, and the other end of capacitor C39 is connected to the second output pin of the analog switch chip U5. The output terminal of the operational amplifier U6 is connected to the other end of resistor R25, the other end of capacitor C42, and the ADC signal acquisition module, and is used to output the I-channel signal.

7. The hardware architecture for signal phase and frequency shift extraction according to claim 5, characterized in that, The second filtering submodule includes an operational amplifier U7, resistors R38, R40, and R41, and capacitors C56, C64, and C65. The positive input terminal of the operational amplifier U7 is connected to one end of capacitor C56 and one end of resistor R38, and the other end of capacitor C56 is connected to the third output pin of the analog switch chip U5. The negative input terminal of the operational amplifier U7 is connected to one end of resistor R41, one end of resistor R40, and one end of capacitor C65. The other end of resistor R41 is connected to one end of capacitor C64, and the other end of capacitor C64 is connected to the fourth output pin of the analog switch chip U5. The output terminal of the operational amplifier U7 is connected to the other end of resistor R40, the other end of capacitor C65, and the ADC signal acquisition module, and is used to output the Q channel signal.

8. The hardware architecture for signal phase and frequency shift extraction according to claim 1, characterized in that, The local oscillator module is an active clock chip, and the local oscillator clock signal is a square wave signal.

9. The hardware architecture for signal phase and frequency shift extraction according to claim 5, characterized in that, The first filtering submodule further includes capacitors C21, C25, and C27, and a ferrite bead FB3; one end of capacitor C21, one end of capacitor C25, one end of capacitor C27, and one end of ferrite bead FB3 are all connected to the power supply terminal of the operational amplifier U6, the other ends of capacitors C21, C25, and C27 are interconnected and grounded, and the other end of ferrite bead FB3 is connected to the power supply voltage.

10. The hardware architecture for signal phase and frequency shift extraction according to claim 5, characterized in that, include: The second filtering submodule also includes capacitors C46, ​​C49, C53, and ferrite bead FB6; one end of capacitor C46, ​​one end of capacitor C49, one end of capacitor C53, and one end of ferrite bead FB6 are all connected to the power supply terminal of the operational amplifier U7, the other ends of capacitors C46, ​​C49, and C53 are interconnected and grounded, and the other end of ferrite bead FB6 is connected to the power supply voltage.

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