A multi-channel analog signal high-precision synchronous sampling device and a sampling method

Abstract

The application provides a kind of multi-channel analog signal high-precision synchronous sampling device and sampling method, the device includes acquisition module and control communication module, acquisition module includes multiple multi-channel synchronous sampling ADC, control communication module includes FPGA master control;One of multiple multi-channel synchronous sampling ADC is main ADC, the rest multi-channel synchronous sampling ADC is slave ADC, main ADC is configured as internal reference voltage output mode, slave ADC is configured as external reference mode, the reference voltage of main ADC is drawn from its own REFOUT pin, and is accessed to the REFIN pin of each slave ADC;Multiple multi-channel synchronous sampling ADC all work in parallel interface mode, the data bus of multiple multi-channel synchronous sampling ADC is connected with FPGA master control in parallel mode, and bus arbitration is carried out through CS signal.The technical scheme of the application is used to solve the technical problems of large sampling time error, complex channel switching circuit and poor matching degree between channels in the prior art.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a high-precision synchronous sampling device and sampling method for multi-channel analog signals. Background Technology

[0002] Multi-channel analog signal sampling systems can transmit large amounts of sampled data to a central processing unit or storage unit in real time for analysis and storage. They are widely used in industrial applications, such as in aircraft flight testing, where multiple channels and sensors need to be acquired in real time. These signals may include physical quantities such as acceleration, pressure, temperature, strain, and vibration. The acquired multidimensional data not only requires high precision and low latency but also needs to ensure time synchronization between channels. Even small time deviations can cause phase shifts between high-speed signals, leading to signal distortion or misinterpretation. With the increasing demand for high-precision measurements, balancing the number of sampling channels with synchronous sampling performance, and reducing sampling errors between channels while ensuring high precision, is a significant challenge facing the sensor testing field.

[0003] Traditional multi-channel / multi-chip analog sampling systems are based on two architectures: some systems use a single ADC chip plus a switch array to simulate a real multi-channel sampling system; others use multiple ADC chips and cascade / parallel them using bus protocols such as SPI / IIC to achieve multi-channel sampling.

[0004] Patent CN202411016966.4 proposes a multi-channel sampling device employing a "switch matrix + monolithic ADC" signal processing architecture. This involves using a monolithic ADC for multi-channel signal acquisition, with several input signals sequentially connected to the ADC input channels via a switch matrix, allowing the ADC to acquire signals sequentially across multiple channels. Ideally, the sampling interval between adjacent channels in this sampling system is only the ADC hold time plus the conversion time. However, in reality, switching between multiple channels using analog switches takes several microseconds to milliseconds, resulting in significant deviations in sampling times between channels. In practical applications, it's necessary to increase the ADC sampling rate and use high-multiplication oversampling to reduce ADC conversion time and thus decrease conversion delays between channels. Furthermore, due to the distributed capacitance and inductance of the transmission lines, the signal path remains in a quasi-stable state for a period after switching, leading to overshoot and glitches that severely affect sampling accuracy. In practical circuits, RC absorption and impedance matching circuits need to be designed for the signals to be sampled. These circuits have poor versatility, are difficult to debug, and cause numerous inconveniences in circuit design.

[0005] Patent CN202010115520.2 proposes a multi-channel analog signal sampling method. These low-speed ADC chips, based on standard communication interfaces such as SPI / IIC, typically lack a separate sampling trigger pin; instead, they receive sampling start commands via the data bus. Since traditional microcontroller instructions are executed sequentially, sampling start commands can only be sent sequentially to multiple ADCs, severely impacting the sampling synchronization between them.

[0006] Furthermore, while analog sampling systems containing multiple ADC chips can achieve true multi-channel sampling, eliminating time errors and signal distortion caused by channel switching, they also suffer from reference source mismatch due to the presence of multiple independent ADC chips. Differences in the reference sources between the multiple ADCs directly affect the data matching between channels. There are typically two approaches to configuring the ADC chip reference sources in these systems: one is an independent reference source mode, where each ADC uses an independent built-in / external reference source. In this approach, differences in the quality of the reference source chips lead to different reference voltages used by each ADC, resulting in poor matching between chips. For sensor sampling systems, sampling errors caused by matching differences must be compensated for through post-processing correction, posing challenges to system software design and increasing operational complexity. The other approach is an external unified reference source mode, where a single external reference source chip provides a reference voltage synchronously to multiple ADCs. This method allows each ADC to obtain a more accurate and consistent reference voltage, but it places higher demands on the external reference source chip. If a common reference chip is used, its output voltage accuracy is lower than that of the ADC's built-in reference, thus reducing the system's sampling accuracy. To achieve high-precision, high-matching sampling, expensive high-precision reference source chips are required, which puts significant cost pressure on the design. Summary of the Invention

[0007] This invention provides a high-precision synchronous sampling device and method for multi-channel analog signals, which can solve the technical problems of large sampling time error, complex channel switching circuit and poor matching degree between channels in existing multi-channel sampling devices.

[0008] According to one aspect of the present invention, a high-precision synchronous sampling device for multi-channel analog signals is provided. The device includes an acquisition module and a control and communication module. The acquisition module includes multiple multi-channel synchronous sampling ADCs, and the control and communication module includes an FPGA main controller.

[0009] In a multi-channel synchronous sampling ADC, one of the chips is the master ADC, and the other multi-channel synchronous sampling ADCs are slave ADCs. The master ADC is configured with internal reference voltage output mode, and the slave ADCs are configured with external reference mode. The reference voltage of the master ADC is led out from its own REFOUT pin and connected to the REFIN pin of each slave ADC.

[0010] All multi-chip, multi-channel synchronous sampling ADCs operate in parallel interface mode. The data buses of the multi-chip, multi-channel synchronous sampling ADCs are connected to the FPGA main controller in parallel and bus arbitration is performed through the CS signal.

[0011] Furthermore, each multi-channel synchronous sampling ADC includes a control unit, multiple independent analog front-ends, multiple independent T / H components, a CONVST signal pin, a MUX, and a SARADC. The multiple analog front-ends are connected one-to-one with the multiple T / H components, the T / H components are connected to the CONVST signal pin, the control unit is connected to the CONVST signal pin, the MUX, and the SARADC respectively, and the MUX is connected to the T / H components and the SARADC respectively.

[0012] Furthermore, after the CONVST signal pins of all multi-channel synchronous sampling ADCs are connected together, they are connected to the FPGA main controller, and all CONVST signal pins are uniformly driven by the global trigger signal generated by the FPGA main controller.

[0013] Furthermore, the length, routing method, and impedance of the signal line between the CONVST signal pin of each multi-channel synchronous sampling ADC and the FPGA main controller are kept consistent.

[0014] Furthermore, the signal lines include internal delay lines within the FPGA and external control lines outside the FPGA.

[0015] Furthermore, the multi-chip, multi-channel synchronous sampling ADC and FPGA main control adopt a symmetrical layout.

[0016] Furthermore, each multi-channel synchronous sampling ADC is assigned a separate board.

[0017] According to one aspect of the present invention, a synchronous sampling method utilizing the aforementioned multi-channel analog signal high-precision synchronous sampling device of the present invention is provided, the method comprising:

[0018] One of the multiple multi-channel synchronous sampling ADCs is used as the master ADC, and the other multi-channel synchronous sampling ADCs are used as slave ADCs. The internal reference voltage of the master ADC is used to drive the external reference voltage of the slave ADCs.

[0019] Multiple sensor data from multiple channels are acquired simultaneously using multiple multi-channel synchronous sampling ADCs.

[0020] Sensor data from multiple channels are input to the FPGA main controller via buses of the same length, with the same routing method and the same impedance.

[0021] The FPGA master controller uses the CS signal to perform bus arbitration in order to receive sensor data from each channel.

[0022] The present invention provides a high-precision synchronous sampling device and method for multi-channel analog signals. This device employs multiple ADCs with built-in on-chip synchronous sampling functions, with one ADC serving as the master ADC and the others as slave ADCs. By connecting multiple reference sources in series and using the internal reference of the master ADC to drive the external references of the multiple slave ADCs, good channel matching can be achieved and costs reduced. By connecting the data buses of the multiple multi-channel synchronous sampling ADCs in parallel to the FPGA master controller and using the CS signal for bus arbitration, a cascaded bus is realized. This enables high-time-precision synchronous sampling of multi-channel analog signals directly connected to the ADC, improving the synchronization of multi-channel sampling and enhancing the scalability of the system. Attached Figure Description

[0023] The accompanying drawings, which form part of this specification, are provided to further illustrate embodiments of the invention and, together with the textual description, explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0024] Figure 1 A block diagram of the device composition of a high-precision synchronous sampling device for multi-channel analog signals according to a specific embodiment of the present invention is shown;

[0025] Figure 2 A schematic diagram of a reference voltage connection according to a specific embodiment of the present invention is shown;

[0026] Figure 3 A schematic diagram of the internal structure of a multi-channel synchronous sampling ADC provided according to a specific embodiment of the present invention is shown;

[0027] Figure 4 A schematic diagram illustrating the connection relationship between an ADC and an FPGA according to a specific embodiment of the present invention is shown. Detailed Implementation

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0030] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0031] like Figure 1 and Figure 2 As shown, according to a specific embodiment of the present invention, a high-precision synchronous sampling device for multi-channel analog signals is provided. The device includes an acquisition module and a control and communication module. The acquisition module includes multiple multi-channel synchronous sampling ADCs, and the control and communication module includes an FPGA main controller.

[0032] In a multi-channel synchronous sampling ADC, one of the chips is the master ADC, and the other multi-channel synchronous sampling ADCs are slave ADCs. The master ADC is configured with internal reference voltage output mode, and the slave ADCs are configured with external reference mode. The reference voltage of the master ADC is led out from its own REFOUT pin and connected to the REFIN pin of each slave ADC.

[0033] All multi-chip, multi-channel synchronous sampling ADCs operate in parallel interface mode. The data buses of the multi-chip, multi-channel synchronous sampling ADCs are connected to the FPGA main controller in parallel and bus arbitration is performed through the CS signal.

[0034] This configuration provides a high-precision synchronous sampling device for multi-channel analog signals. The device employs multiple ADCs with built-in on-chip synchronous sampling capabilities, using one as the master ADC and the rest as slave ADCs. By cascading multiple reference sources and utilizing the master ADC's internal reference to drive the external references of the slave ADCs, good channel matching can be achieved, reducing costs. By connecting the data buses of the multiple multi-channel synchronous sampling ADCs in parallel to the FPGA master controller and using the CS signal for bus arbitration, a cascaded bus is implemented. This enables high-time-precision synchronous sampling of multi-channel analog signals directly connected to the ADC, improving the synchronization of multi-channel sampling and enhancing system scalability. Compared with existing technologies, the technical solution of this invention solves the technical problems of large sampling time errors, complex channel switching circuits, and poor matching between channels in existing multi-channel sampling devices.

[0035] Furthermore, such as Figure 3 As shown in the embodiment of the present invention, each multi-channel synchronous sampling ADC includes a control unit, multiple independent analog front-ends, multiple independent T / H components, a CONVST signal pin, a MUX, and a SARADC. The multiple analog front-ends are connected to the multiple T / H components one by one, the T / H components are connected to the CONVST signal pin, the control unit is connected to the CONVST signal pin, the MUX, and the SARADC respectively, and the MUX is connected to the T / H components and the SARADC respectively.

[0036] Based on the above embodiments, in this embodiment of the invention, the CONVST signal pins of all multi-channel synchronous sampling ADCs are connected together and then connected to the FPGA main controller. All CONVST signal pins are driven uniformly by a global trigger signal generated by the FPGA main controller. This configuration method enables sampling to be triggered by a single signal, improving the time synchronization accuracy between each ADC.

[0037] Furthermore, besides the ADC, other "asynchronous factors" exist. For example, inconsistent propagation paths of trigger signals can cause deviations in sampling start times. Factors such as the signal line length, routing method, and impedance of each channel can lead to phase deviations in highly phase-sensitive multiphase signals (such as multiphase AC signals) during sampling, thus affecting the normal operation of the sampling control system. To address these asynchronous factors, in this embodiment, the length, routing method, and impedance of the signal lines between the CONVST signal pin of each multi-channel synchronous sampling ADC and the FPGA main controller are kept consistent. Specifically, the signal lines include internal delay lines within the FPGA and external control lines. In addition, the multiple multi-channel synchronous sampling ADCs and the FPGA main controller are arranged symmetrically.

[0038] Furthermore, to facilitate the expansion of the number of channels, in this embodiment of the invention, each multi-channel synchronous sampling ADC is assigned an independent board. With this configuration, the number of sampling channels can be expanded simply by stacking the boards.

[0039] To gain a further understanding of the present invention, the following description is provided in conjunction with... Figures 1 to 4 The multi-channel analog signal high-precision synchronous sampling device of the present invention will be described in detail.

[0040] According to a specific embodiment of the present invention, a high-precision synchronous sampling device for multi-channel analog signals is provided, including an acquisition module and a control and communication module, the overall block diagram of which is shown below. Figure 1 As shown, the acquisition module consists of four 8-channel synchronous sampling ADCs forming a 32-channel multi-channel synchronous data sampling device, primarily responsible for acquiring the sensor's output signals. The control and communication module uses an FPGA as its control core. The FPGA, as the core unit of the data acquisition, processing, and control system, possesses powerful parallel processing capabilities and combines real-time performance with high flexibility. This invention primarily addresses the problems of large sampling time errors and low sampling accuracy in existing synchronous sampling devices by implementing the following design:

[0041] This invention uses an ADC with built-in multi-channel sampling function to form a synchronous sampling system, the internal architecture of which is as follows: Figure 3 As shown, this architecture includes independent analog front-ends and corresponding T / H components. All T / H components are controlled by a unified signal CONVST, and sampling is performed on the rising edge of the CONVST signal. The signals are then sequentially fed into a SAR-type ADC for conversion via a MUX. Although this architecture uses the same ADC core to convert all signals sequentially, the T / H circuits sample the signals simultaneously. The sampling time error across multiple channels is only a few nanoseconds, which can be considered ideal synchronous sampling at a 1MHz sampling rate.

[0042] In this invention, synchronizing multiple ADCs is achieved by using a common conversion start signal. That is, the sampling start signals CONVST of all chips are connected together, and an FPGA is used to generate a global trigger signal to drive the CONVST pins of all ADCs. After each sampling, data is read sequentially from multiple ADC devices. This technique eliminates the need for external switching circuitry, significantly improving the sampling synchronization of multi-channel systems.

[0043] To address the mismatch issue of built-in reference sources in existing synchronous sampling systems for each ADC chip, this invention employs a series-connected multi-reference-source approach to process the reference voltage signals of multiple ADCs. Specifically, as shown in... Figure 2 As shown: One ADC is selected as the master ADC (master device) and configured in internal reference voltage output mode. The other three are slave ADCs (slave devices) and configured in external reference mode. The reference voltage is led out from the REFOUT pin of the master device and connected to the REFIN pin of the slave devices as a reference voltage source, realizing the internal reference of a single ADC driving the external references of multiple ADCs. In this mode, all ADCs share a single reference voltage source, which can achieve good matching and consistency across multiple channels. While ensuring the system's sampling accuracy, it reduces the need for multiple high-precision external reference sources, thereby reducing design complexity and cost.

[0044] In multi-channel sampling systems, besides the ADC, other "asynchronous factors" exist. For example, inconsistent propagation paths of trigger signals can cause deviations in sampling start times. Factors such as signal line length, routing, and impedance for each channel can lead to phase deviations in highly phase-sensitive multiphase signals (such as multiphase AC signals) during sampling, thus affecting the normal operation of the sampling control system. Therefore, this invention incorporates targeted hardware design in its system design. Specifically, the signal line length, routing, and impedance of the CONVST signal are kept consistent to ensure consistent delays in the arrival of trigger signals at each device. Furthermore, all components are arranged symmetrically to balance parasitic circuit parameters, improve system performance, and ensure good matching between channels.

[0045] Furthermore, to improve data throughput, the ADC is designed to operate in parallel interface mode, employing a 16-bit data bus for communication with the FPGA. Simultaneously, to address the communication interface issue across multiple ADCs, a scalable bus interface mode is designed, with connection methods as follows: Figure 4 As shown, all ADC data buses are connected in parallel, greatly reducing the number of I / Os used. Multiple ADCs use the CS signal for bus arbitration to achieve time-division communication. This communication architecture has strong scalability; the ADC chips are designed as independent boards, and the number of sampling channels can be expanded simply by stacking the boards.

[0046] This device differs from existing multi-channel sampling equipment and has the following advantages:

[0047] (1) The device contains 32 analog sampling channels, each with a sampling rate of up to 1 MSa / s. The device also has high scalability, with all ADCs using a modular multiplexing design and serial communication, which can be flexibly expanded to more than 64 input channels.

[0048] (2) All sampling channels are in direct sampling mode. The input signal is directly connected to the ADC sampling channel after signal conditioning, without the need for external channel switching circuits, and there is no signal overshoot problem caused by channel switching. Under this architecture, all channels are in time-synchronized sampling mode, and the sampling time error between channels is at the nanosecond level, which significantly improves the synchronization performance.

[0049] (3) The sampling system has high matching between multiple ADC chips, which effectively reduces the channel error caused by the quality of the ADC chip and the reference source, and further improves the time accuracy and absolute sampling accuracy of synchronous sampling.

[0050] According to one aspect of the present invention, a synchronous sampling method utilizing the aforementioned multi-channel analog signal high-precision synchronous sampling device of the present invention is provided, the method comprising:

[0051] One of the multiple multi-channel synchronous sampling ADCs is used as the master ADC, and the other multi-channel synchronous sampling ADCs are used as slave ADCs. The internal reference voltage of the master ADC is used to drive the external reference voltage of the slave ADCs.

[0052] Multiple sensor data from multiple channels are acquired simultaneously using multiple multi-channel synchronous sampling ADCs.

[0053] Sensor data from multiple channels are input to the FPGA main controller via buses of the same length, with the same routing method and the same impedance.

[0054] The FPGA master controller uses the CS signal to perform bus arbitration in order to receive sensor data from each channel.

[0055] In summary, this invention provides a high-precision synchronous sampling device and method for multi-channel analog signals. The device employs multiple ADCs with built-in on-chip synchronous sampling capabilities, using one as the master ADC and the rest as slave ADCs. By cascading multiple reference sources and utilizing the internal reference of the master ADC to drive the external references of the multiple slave ADCs, good channel matching can be achieved and costs reduced. By connecting the data buses of the multiple multi-channel synchronous sampling ADCs in parallel to the FPGA master controller and using the CS signal for bus arbitration, a cascaded bus is realized. This enables high-time-precision synchronous sampling of multi-channel analog signals directly connected to the ADC, improving the synchronization of multi-channel sampling and enhancing the system's scalability. Compared with existing technologies, the technical solution of this invention can solve the technical problems of large sampling time errors, complex channel switching circuits, and poor matching between channels in existing multi-channel sampling devices.

[0056] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0057] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this invention.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-precision synchronous sampling device for multi-channel analog signals, characterized in that, The device includes a data acquisition module and a control and communication module. The data acquisition module includes multiple multi-channel synchronous sampling ADCs, and the control and communication module includes an FPGA main controller. In the multi-channel synchronous sampling ADC, one of the chips is the master ADC, and the other multi-channel synchronous sampling ADCs are slave ADCs. The master ADC is configured in internal reference voltage output mode, and the slave ADCs are configured in external reference mode. The reference voltage of the master ADC is led out from its own REFOUT pin and connected to the REFIN pin of each slave ADC. All of the multi-channel synchronous sampling ADCs described herein operate in parallel interface mode. The data buses of the multi-channel synchronous sampling ADCs described herein are connected to the FPGA main controller in parallel and are arbitrated via the CS signal.

2. The apparatus according to claim 1, characterized in that, Each of the aforementioned multi-channel synchronous sampling ADCs includes a control unit, multiple independent analog front-ends, multiple independent T / H components, a CONVST signal pin, a MUX, and a SARADC. The multiple analog front-ends are connected one-to-one with the multiple T / H components. The T / H components are connected to the CONVST signal pin. The control unit is connected to the CONVST signal pin, the MUX, and the SARADC, respectively. The MUX is connected to the T / H components and the SARADC, respectively.

3. The apparatus according to claim 2, characterized in that, After the CONVST signal pins of all multi-channel synchronous sampling ADCs are connected together, they are connected to the FPGA main controller, and all CONVST signal pins are uniformly driven by the global trigger signal generated by the FPGA main controller.

4. The apparatus according to claim 3, characterized in that, The length, routing method, and impedance of the CONVST signal pin of each multi-channel synchronous sampling ADC and the signal line between them and the FPGA main controller are kept consistent.

5. The apparatus according to claim 4, characterized in that, The signal lines include internal delay lines of the FPGA and external control lines of the FPGA.

6. The apparatus according to any one of claims 1 to 5, characterized in that, The multi-channel synchronous sampling ADC and the FPGA main controller are arranged symmetrically.

7. The apparatus according to claim 6, characterized in that, Each of the aforementioned multi-channel synchronous sampling ADCs is assigned to a separate board.

8. A synchronous sampling method using the multi-channel analog signal high-precision synchronous sampling device according to any one of claims 1 to 7, characterized in that, The method includes: One of the multiple multi-channel synchronous sampling ADCs is used as the master ADC, and the other multi-channel synchronous sampling ADCs are used as slave ADCs. The internal reference voltage of the master ADC is used to drive the external reference voltage of the slave ADCs. Multiple sensor data from multiple channels are acquired simultaneously using multiple multi-channel synchronous sampling ADCs. Sensor data from multiple channels are input to the FPGA main controller via buses of the same length, with the same routing method and the same impedance. The FPGA master controller uses the CS signal to perform bus arbitration in order to receive sensor data from each channel.

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