A high-speed alternating current sampling calculation method and system based on DFT
By using a high-speed AC sampling calculation method based on DFT, and utilizing the MCU's internal PWM timer and DMA controller, combined with the recursive discrete Fourier transform algorithm, the problems of low efficiency of CPU interrupt sampling and high cost of FPGA solutions are solved, achieving efficient and low-power synchronous sampling and data processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUHAI WANLIDA ELECTRICAL AUTOMATION
- Filing Date
- 2026-04-10
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, CPU interrupt sampling methods result in problems such as heavy CPU load, low efficiency, slow response, and high power consumption, while FPGA-based solutions are characterized by high cost and difficult development.
A high-speed AC sampling calculation method based on DFT is adopted, which uses the MCU's internal PWM timer as the time base and trigger source. The ADC module is directly started by the hardware trigger signal. Combined with the DMA controller and the recursive discrete Fourier transform algorithm, synchronous sampling and data processing without CPU intervention are realized.
It achieves efficient and low-cost synchronous sampling and data processing, reduces system power consumption, improves signal reconstruction accuracy and system stability, avoids the risk of crash due to interrupt accumulation, and reduces hardware costs.
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Figure CN122437548A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power system automation technology, specifically to a high-speed AC sampling calculation method and system based on DFT, which is applicable to applications with high real-time and accuracy requirements such as smart grids, industrial automation control, and new energy power generation. Background Technology
[0002] In power systems, high-speed, periodic sampling of analog signals such as voltage and current is the foundation of monitoring and control. Traditional implementation schemes mainly rely on two technical paths: sampling methods based on central processing unit (CPU) interrupts and sampling methods based on field programmable gate arrays (FPGAs).
[0003] The sampling method based on CPU interrupts: After the ADC completes one conversion, it generates an interrupt request. The CPU responds to the interrupt, suspends the current task, saves the execution context, enters the interrupt service routine to read the ADC conversion result, then restores the context and returns to the original task. The disadvantages of this scheme are as follows: High CPU resource consumption and low efficiency: CPU intervention is required for each sampling, and frequent context switching during high-frequency sampling leads to a sharp increase in system overhead, which seriously affects the execution efficiency of the main control program.
[0004] There is a risk of data loss: When the sampling frequency exceeds the CPU's interrupt handling capacity limit, it can lead to an accumulation of interrupt requests, which may cause system crashes or data loss.
[0005] High system power consumption: The CPU must run at high speed continuously to respond to frequent interrupts and cannot enter a low-power mode, resulting in an increase in overall power consumption.
[0006] Sampling based on Field-Programmable Gate Arrays (FPGAs): The FPGA generates the sampling timing and controls the ADC, achieving extremely high flexibility and speed. However, its drawbacks are also significant: High hardware costs: FPGA chips are much more expensive than general-purpose MCUs.
[0007] High development complexity: The development process involves hardware description languages (such as VHDL / Verilog), synthesis, placement and routing, etc., which are time-consuming and difficult.
[0008] High talent threshold: It requires compound talents with both digital circuit design and hardware description language skills.
[0009] Disadvantages in power consumption and size: Compared to MCUs, FPGAs typically have higher static and dynamic power consumption, and their peripheral circuitry may be more complex. Summary of the Invention
[0010] To address the problems of heavy CPU load, low efficiency, slow response, and high power consumption caused by existing CPU interrupt sampling methods, as well as the high cost and development difficulty of FPGA solutions, the present invention aims to provide a high-speed AC sampling calculation method and device based on DFT. By utilizing the internal hardware linkage of the MCU, CPU intervention can be minimized, thereby achieving efficient and low-cost synchronous sampling and data processing.
[0011] The present invention achieves the above objectives through the following technical solutions: A high-speed AC sampling calculation method based on DFT includes: Using the microcontroller's internal PWM timer as the time base and trigger source, and configuring it in center-aligned mode, an internal trigger signal TRGO is automatically generated when the counter reaches its peak value during operation. The TRGO signal is then connected to the external trigger input of the ADC module through the microcontroller's internal event router or trigger distribution unit. At the same time, the ADC module is configured to work in external trigger mode. In this way, the hardware trigger signal can be used to directly trigger the ADC module to start the analog-to-digital conversion event, thereby achieving automatic synchronization between the sampling time and the PWM control waveform. The ADC conversion result of the ADC module is used as the DMA request source, and the DMA controller automatically stores the ADC conversion result into the data buffer. The batch computation of data in the data buffer is triggered by an interrupt generated by the DMA controller when the data buffer is filled to half or all of its capacity; during the batch computation, the effective value of the signal is updated using a recursive discrete Fourier transform algorithm.
[0012] According to the high-speed AC sampling calculation method based on DFT provided by the present invention, in the center alignment mode, the automatic reload value ARR of the timer is set so that the counter increments from 0 to the ARR value and then decrements back to 0, forming a complete PWM cycle. Configure the timer's output compare mode so that when the counter reaches the ARR peak, an internal trigger signal TRGO is automatically generated through the hardware logic of the PWM timer. The internal trigger signal TRGO is directionally connected to the external trigger input of the ADC module through the event router or trigger distribution unit inside the microcontroller, and the ADC module is configured to external trigger mode; at the ARR value time of each PWM cycle, the internal trigger signal TRGO automatically starts the ADC to perform analog-to-digital conversion on the preset sampling channel.
[0013] According to the high-speed AC sampling calculation method based on DFT provided by the present invention, during the hardware configuration stage of the microcontroller, the internal event router or trigger distribution unit function is enabled, and the TRGO signal of the PWM timer is selected as the source trigger signal. According to the hardware interface specification of the target ADC module, configure the target address parameters in the event router or trigger distribution unit to route the TRGO signal to the external trigger input port of the ADC module. In the initialization configuration of the ADC module, its trigger source is set to external trigger mode, and the polarity of the external trigger signal is specified to match the characteristics of the TRGO signal. Verify the physical connection and logical configuration of the TRGO signal and the external trigger input of the ADC using the microcontroller's register configuration tool or software development interface. Ensure that the TRGO signal can reliably trigger the ADC to start analog-to-digital conversion when the PWM timer counts to the ARR value.
[0014] According to the high-speed AC sampling calculation method based on DFT provided by the present invention, the DMA controller is configured to enable its cyclic mode function option and set its source address to point to the data register of the ADC module, the data register being represented as ADC1->DR; at the same time, the target address is set to point to the data buffer for storing data pre-set by the user in memory, and the data buffer is set to have a fixed start address and end address. Enable the DMA request function after the ADC module completes the conversion, so that the ADC module can immediately send a data transfer request to the DMA controller after completing an analog-to-digital signal conversion operation. When the DMA controller performs a data transfer operation, writing the ADC conversion result into the data buffer, until the last memory cell of the data buffer is full, the DMA controller automatically wraps the data write address back to the starting address of the buffer according to its internal preset loop mechanism, and continues to perform the data write operation.
[0015] According to the high-speed AC sampling calculation method based on DFT provided by the present invention, the data buffer length is preset to N; In the configuration of the DMA controller, enable its transfer completion interrupt flag setting function, and set half-full and full-full interrupt trigger conditions for the data buffer transfer status. That is, when the DMA completes N / 2 data transfers, set it to the half-full interrupt flag, and when it completes N data transfers, set it to the full-full interrupt flag. During the data transfer process, the DMA controller monitors the number of data transfers in real time. Whenever the number of data transfers reaches N / 2 or N, the DMA controller automatically sets the corresponding interrupt flag based on preset conditions.
[0016] According to the high-speed AC sampling calculation method based on DFT provided by the present invention, when the DMA controller triggers an interrupt due to reaching a preset number of data transfers, the system automatically jumps to the DMA interrupt service routine for execution. In the interrupt service routine, the status of the half-full interrupt flag and the full-full interrupt flag is checked by reading from the hardware registers. If the half-full interrupt flag is detected to be set, the interrupt service routine calls the first processing function. The first processing function accesses the first half of the data in the buffer through pointer operations. The pointer range is from &adc_buffer[0] to &adc_buffer[N / 2 - 1], and performs processing operations on the first half of the data. If the full interrupt flag is detected to be set, the interrupt service routine calls the second processing function. This second processing function accesses the second half of the data in the buffer through pointer operations. The pointer range is from &adc_buffer[N / 2] to &adc_buffer[N - 1], and performs processing operations on the second half of the data. After the corresponding data processing operation is completed, the interrupt service routine clears the triggered half-full or full interrupt flag by writing to the hardware register.
[0017] The present invention provides a high-speed AC sampling calculation method based on DFT, the process of batch calculation triggered by DMA interrupt and updating the effective value of the signal using a recursive discrete Fourier transform algorithm includes: Based on the interrupt signal generated by the DMA controller when the data buffer is filled to half or full, a batch calculation operation on the data in the data buffer is triggered; specifically, when a half-full interrupt is detected, the first half of the data in the data buffer is batch calculated; when a full interrupt is detected, the second half of the data in the data buffer is batch calculated. Before the batch calculation begins, the relevant parameters are pre-initialized, including determining the number of sampling points N, rotation factor W, and decay factor K for one period, and setting the initial value of the DFT result X[n - 1] of the previous sampling point x[n - 1]. During the batch calculation process, for each current sampling point x[n], its value and the value of the corresponding sampling point x[n - N] in the previous period are obtained. The obtained values of the current sampling point x[n], the previous sampling point x[n - 1] (if it is the first sampling point, the initial value is used), the corresponding sampling point x[n - N] in the previous period, and the predetermined rotation factor W and attenuation factor K are substituted into the recursive formula X[n] = (X[n - 1] + (x[n] - x[n - N]) * W) * K to obtain the DFT result X[n] of the current sampling point x[n]. Using the calculated DFT result X[n] of the current sampling point x[n], the effective value of the signal is further updated, completing one signal effective value update calculation process based on the recursive discrete Fourier transform algorithm. In the calculation of the sampling point, the DFT result X[n] of the current sampling point x[n] obtained in this calculation is used as the DFT result X[n-1] of the previous sampling point x[n-1] when calculating the next sampling point. The above steps are repeated to continuously update the effective value of the signal.
[0018] The present invention provides a high-speed AC sampling calculation method based on DFT, which utilizes a high-speed comparator, input capture unit, or auxiliary ADC channel within a microcontroller to monitor the zero-crossing points or characteristic points of the input voltage or current signal in real time. By measuring the time interval between two consecutive zero-crossing points or the number of pulses per unit time, the real-time frequency of the current input signal is calculated. f real Alternatively, after each batch calculation is completed, the current signal frequency can be estimated using the phase information from the recursive discrete Fourier transform algorithm. The real-time frequency obtained from monitoring f real Substitute the parameters into the calculation model to automatically calculate the new configuration parameters required for the PWM timer; The parameter calculation model is based on the following relationship: to ensure a fixed number of points are collected in each period of the signal. M And maintain center alignment mode, which must meet the following requirements. T pwm =1 / f real =( ARR new +1)× T clk ,in, T clk The timer clock cycle; The value of the Automatic Reload Register (ARR) is calculated and updated based on the parameter calculation formula. ARR new =(1 / ( f real × T clk )) 1. Simultaneously, according to the requirements of the center alignment mode, the value of the comparison register CCR is dynamically adjusted to... ARR new / 2; Without stopping PWM output and ADC sampling, the calculated values can be obtained using the microcontroller's register shadow update mechanism or pre-loading function. ARR new The new CCR value is written to the preload register of the PWM timer; When a PWM timer update event occurs, the hardware automatically transfers the preloaded value to the active register, so that at the beginning of the next PWM cycle, the period and duty cycle of the PWM waveform will run according to the new frequency parameters. The PWM timer operates based on the updated ARR value, and when the counter reaches the new peak value, that is... ARR new It still generates the TRGO hardware trigger signal through the internal event router.
[0019] According to the present invention, a high-speed AC sampling calculation method based on DFT is provided, which introduces an error compensation mechanism in the recursive discrete Fourier transform algorithm: Set the trigger period for error compensation, which is based on the number of sampling points or the time interval; When the set compensation trigger condition is met, the traditional Discrete Fourier Transform (DFT) algorithm is paused or executed in parallel; the most recent... N Data sequence of sampling points x [ n N +1],…, x [ n Using the traditional DFT formula Perform full complex multiplication and addition operations on this data segment to calculate the signal spectrum reference value at that moment. X dft [ n ]; Read the results calculated by the recursive discrete Fourier transform algorithm at the same time point. X rec [ n The baseline value obtained by traditional DFT calculation; X dft [ n ] and the result of the recursive algorithm X rec [ n Compare the two and calculate the error value Δ. X = X dft [ n ] X rec [ n This error value includes both amplitude error and phase error; Based on the calculated error value Δ X Perform at least one of the following correction operations: Parameter tuning: Update key parameters in the recursive algorithm, including the rotation factor, using the error values. W and / or attenuation factor KFine-tuning using table lookup or formula methods W and K The value of makes the result of the next recursive calculation Xrec [ n +1] is closer to the true value; Result Correction: A correction factor is directly added to the subsequent results calculated by the recursive algorithm. This correction factor is derived based on the weighted average of historical errors or the proportionality coefficient of the current error. X corrected [ n ]= X rec [ n ]+ α Δ X ,in α For correction factors, 0 < α ≤1; Adjusted rotation factor W Attenuation factor K Alternatively, the corrected calculation result can be fed back into the next calculation cycle of the recursive discrete Fourier transform algorithm, serving as a new initial value or intermediate variable to continue participating in the recursion.
[0020] A high-speed AC sampling computing device based on DFT, comprising: The PWM hardware-triggered ADC synchronous sampling module is used to directly trigger the ADC module to start analog-to-digital conversion by utilizing the hardware trigger signal automatically generated by the microcontroller's internal PWM timer during operation, thereby achieving automatic synchronization between the sampling time and the PWM control waveform. The DMA automatic data transfer and buffer management module is used to take the ADC conversion result of the ADC module as the DMA request source, and the DMA controller automatically stores the conversion result into the data buffer. The data processing triggering module is used to trigger batch calculations on the data in the data buffer based on the interrupt generated by the DMA controller when the data buffer is filled to half or all. The recursive DFT fast effective value calculation module is used to update the effective value of the signal using the recursive discrete Fourier transform algorithm during batch calculation.
[0021] Therefore, compared with the prior art, the high-speed AC sampling calculation method and system based on DFT proposed in this invention have the following beneficial effects: 1. This invention uses the center-aligned peak moment of the PWM timer inside the MCU to generate a hardware trigger signal, directly starting ADC sampling, achieving precise synchronization without CPU intervention, ensuring strict synchronization between the sampling moment and the PWM control waveform, avoiding timing errors caused by software intervention, and having a large number of sampling points with high density, which significantly improves the accuracy of signal reconstruction.
[0022] 2. The hardware triggering mechanism of this invention reduces the impact of external interference on sampling timing, maintaining stable sampling performance, especially in complex electromagnetic environments, thus providing a reliable data foundation for signal processing. By configuring hardware linkage between the ADC and DMA, the ADC conversion results are automatically transferred to the circular buffer via DMA, eliminating the need for CPU intervention in the data transfer process. This frees the CPU from high-frequency data transfer tasks, allowing it to focus on more complex calculations or enter a low-power mode, thereby significantly reducing the overall system power consumption.
[0023] 3. This invention employs a batch data processing mechanism based on DMA buffer half-full / full-full interrupts, transforming high-frequency sampling tasks into low-frequency computation tasks. The CPU is only interrupted once when a certain amount of data has accumulated in the buffer (e.g., every 2.5 milliseconds), greatly reducing the interrupt frequency and allowing the CPU more continuous time to execute other tasks, resulting in smoother system response and reduced power consumption caused by frequent interrupts.
[0024] 4. This invention applies a recursive discrete Fourier transform algorithm to calculate the effective value of batch sampled data in real time, avoiding the need for traditional DFT / FFT algorithms to perform O(N²) or O(NlogN) complex multiplication and addition operations on N points in each cycle. The recursive algorithm uses the calculation result of the previous sampling point to derive the result of the current sampling point, greatly reducing the amount of computation and enabling complex calculations to be completed in a very short time, meeting the requirements for high-speed value output.
[0025] 5. This invention is based on a general-purpose MCU, eliminating the need for expensive FPGA chips. The hardware cost is significantly lower than FPGA solutions, making it suitable for large-scale deployment and application. The software development process is based on a standard peripheral library, similar to ordinary microcontroller development, with a low barrier to entry and short development cycle. Developers do not need digital circuit design or hardware description language skills to quickly complete system development, significantly shortening time to market.
[0026] 6. This invention avoids the risk of stacking crashes that may be caused by CPU interrupt sampling, and hardware coordination ensures the timeliness of sampling and the stability of the data stream. Even in high-frequency sampling scenarios, the system can still maintain stable operation and will not cause system crashes or data loss due to the accumulation of interrupt requests.
[0027] 7. This invention introduces an error compensation mechanism, periodically uses the traditional DFT algorithm to perform accurate calculations on a small segment of data, and compares the calculation results with the results of the recursive DFT algorithm. Based on the error situation, the parameters in the recursive algorithm are adjusted or the results are corrected, thereby improving the long-term stability and calculation accuracy of the algorithm and ensuring the reliability of the system under long-term operation.
[0028] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description
[0029] Figure 1 This is a flowchart of an embodiment of a high-speed AC sampling calculation method based on DFT according to the present invention.
[0030] Figure 2 This is a logic control diagram of a high-speed AC sampling calculation method based on DFT according to the present invention, under the center alignment mode.
[0031] Figure 3 This is a schematic diagram illustrating the principle of half-full / full-full interrupt trigger calculation in an embodiment of a high-speed AC sampling calculation method based on DFT of the present invention.
[0032] Figure 4 This is a logic flowchart of the interrupt service routine in an embodiment of the high-speed AC sampling calculation method based on DFT of the present invention.
[0033] Figure 5 This is a schematic diagram of an embodiment of a high-speed AC sampling computing device based on DFT according to the present invention. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0035] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0036] An Example of a High-Speed AC Sampling Calculation Method Based on DFT See Figures 1 to 4 This embodiment provides a high-speed AC sampling calculation method based on DFT, including: Using the microcontroller's internal PWM timer as the time base and trigger source, and configuring it in center-aligned mode, an internal trigger signal TRGO is automatically generated when the counter reaches its peak value during operation. The TRGO signal is then connected to the external trigger input of the ADC module through the microcontroller's internal event router or trigger distribution unit. At the same time, the ADC module is configured to work in external trigger mode. In this way, the hardware trigger signal can be used to directly trigger the ADC module to start the analog-to-digital conversion event, thereby achieving automatic synchronization between the sampling time and the PWM control waveform. The ADC conversion result of the ADC module is used as the DMA request source, and the DMA controller automatically stores the ADC conversion result into the data buffer. The batch computation of data in the data buffer is triggered by an interrupt generated by the DMA controller when the data buffer is filled to half or all of its capacity; during the batch computation, the effective value of the signal is updated using a recursive discrete Fourier transform algorithm.
[0037] In center-aligned mode, the timer's auto-reload value ARR is set so that the counter increments from 0 to the ARR value and then decrements back to 0, forming a complete PWM cycle. Configure the timer's output compare mode so that when the counter reaches the ARR peak, an internal trigger signal TRGO is automatically generated through the hardware logic of the PWM timer. The internal trigger signal TRGO is directionally connected to the external trigger input of the ADC module through the event router or trigger distribution unit inside the microcontroller, and the ADC module is configured to external trigger mode; at the ARR value time of each PWM cycle, the internal trigger signal TRGO automatically starts the ADC to perform analog-to-digital conversion on the preset sampling channel.
[0038] During the hardware configuration phase of the microcontroller, enable the internal event router or trigger distribution unit function and select the TRGO signal of the PWM timer as the source trigger signal; According to the hardware interface specification of the target ADC module, configure the target address parameters in the event router or trigger distribution unit to route the TRGO signal to the external trigger input port of the ADC module. In the initialization configuration of the ADC module, set its trigger source to external trigger mode and specify the polarity (rising edge / falling edge) of the external trigger signal to match the characteristics of the TRGO signal; Verify the physical connection and logical configuration of the TRGO signal and the external trigger input of the ADC using the microcontroller's register configuration tool or software development interface. Ensure that the TRGO signal can reliably trigger the ADC to start analog-to-digital conversion when the PWM timer counts to the ARR value.
[0039] In this embodiment, the DMA controller is configured to enable its loop mode function option and set its source address to point to the data register of the ADC module, which is represented as ADC1->DR; at the same time, the target address is set to point to the data buffer, such as the array adc_buffer[], which is set in memory by the user in advance to store data, and the data buffer is set to have a fixed start address and end address. Enabling the DMA request function after the ADC module completes a conversion allows it to immediately send a data transfer request to the DMA controller after each analog-to-digital signal conversion. The DMA controller then executes a data transfer, moving the ADC result from the register to the memory buffer. This process is entirely performed by hardware, achieving data transfer with zero CPU usage.
[0040] When the DMA controller performs a data transfer operation, it writes the ADC conversion result into the data buffer. When the last memory cell of the data buffer is full, the DMA controller automatically wraps the data write address back to the starting address of the buffer according to its internal preset loop mechanism and continues to perform data write operations, forming a circular buffer. This achieves seamless storage of continuous data streams without the need for software pointer reset.
[0041] In this embodiment, to balance real-time performance and computational load, a DMA transfer completion interrupt flag is used. The data buffer length is preset to N, where N is a positive integer, for example, N = 64; In the configuration of the DMA controller, enable its transfer completion interrupt flag setting function, and set half-full and full-full interrupt trigger conditions for the data buffer transfer status. That is, when the DMA completes N / 2 data transfers, set it to the half-full interrupt flag, and when it completes N data transfers, set it to the full-full interrupt flag. During the data transfer process performed by the DMA controller, the number of data transfers is monitored in real time. Whenever the number of data transfers reaches N / 2 or N, the DMA controller automatically sets the corresponding interrupt flag bit according to preset conditions. The system uses hardware circuitry and logic design to accurately count the number of data transmissions and automatically set the interrupt flag. This ensures that the corresponding interrupt flag is triggered promptly and accurately when the set number of transmissions is reached, providing a triggering basis for subsequent interrupt-based processing operations. This eliminates the need for software to query the transmission status in real time to balance real-time performance and computational load.
[0042] When the DMA controller triggers an interrupt due to reaching the preset number of data transfers, the system automatically jumps to the DMA interrupt service routine for execution. In the interrupt service routine, the status of the half-full interrupt flag and the full-full interrupt flag is checked by reading from the hardware registers. If the half-full interrupt flag is detected to be set, the interrupt service routine calls the first processing function. The first processing function accesses the first half of the data in the buffer through pointer operations. The pointer range is from &adc_buffer[0] to &adc_buffer[N / 2 - 1], and performs processing operations on the first half of the data. If the full interrupt flag is detected to be set, the interrupt service routine calls the second processing function. This second processing function accesses the second half of the data in the buffer through pointer operations. The pointer range is from &adc_buffer[N / 2] to &adc_buffer[N - 1], and performs processing operations on the second half of the data. After the corresponding data processing operation is completed, the interrupt service routine clears the triggered half-full or full interrupt flag by writing to the hardware register, so that the DMA controller can trigger the interrupt again according to the new data transmission situation.
[0043] As can be seen, the CPU is only interrupted once after a certain amount of data (such as 32 points) has accumulated in the buffer. This transforms the high-frequency ADC sampling interrupt into a low-frequency batch calculation task, greatly reducing the interrupt frequency and allowing the CPU to have more continuous time to execute other tasks, resulting in a smoother system response.
[0044] In this embodiment, the process of triggering batch calculation based on DMA interrupt and updating the effective value of the signal using a recursive discrete Fourier transform algorithm includes: Based on the interrupt signal generated by the DMA controller when the data buffer is filled to half or full, a batch calculation operation on the data in the data buffer is triggered; when a half-full interrupt is detected, the first half of the data in the data buffer (&adc_buffer[0] to &adc_buffer[N / 2 - 1]) is batch calculated; when a full interrupt is detected, the second half of the data in the data buffer (&adc_buffer[N / 2] to &adc_buffer[N - 1]) is batch calculated. Before the batch calculation begins, the relevant parameters are pre-initialized, including determining the number of sampling points N, rotation factor W, and decay factor K for one period, and setting the initial value of the DFT result X[n - 1] of the previous sampling point x[n - 1]. During the batch calculation process, for each current sampling point x[n], its value and the value of the corresponding sampling point x[n - N] in the previous period are obtained. The obtained values of the current sampling point x[n], the previous sampling point x[n - 1] (if it is the first sampling point, the initial value is used), the corresponding sampling point x[n - N] in the previous period, and the predetermined rotation factor W and attenuation factor K are substituted into the recursive formula X[n] = (X[n - 1] + (x[n] - x[n - N]) * W) * K to obtain the DFT result X[n] of the current sampling point x[n]. Using the calculated DFT result X[n] of the current sampling point x[n], the effective value of the signal is further updated, completing one signal effective value update calculation process based on the recursive discrete Fourier transform algorithm. In the calculation of the sampling point, the DFT result X[n] of the current sampling point x[n] obtained in this calculation is used as the DFT result X[n-1] of the previous sampling point x[n-1] when calculating the next sampling point. The above steps are repeated to continuously update the effective value of the signal. In the processing function triggered by the DMA half-full / full interrupt, a recursive DFT algorithm is applied to a batch of newly sampled data in the buffer to update the real and imaginary parts of the fundamental voltage and current (and each harmonic), thereby calculating the effective value, phase, and other parameters in real time. Since the recursive algorithm has a small computational load, it can be completed in a very short time (such as tens of microseconds), meeting the requirement of high-speed value output.
[0045] The above recursive discrete Fourier transform algorithm avoids the need for traditional DFT / FFT algorithms to perform O(N) operations on N points in each computation cycle. 2 The effective value of the signal can be updated by performing only a finite number of calculations according to the recursive formula, which can either O(NlogN) complex multiplication and addition operations or O(NlogN) complex multiplication and addition operations. This greatly reduces the amount of computation and improves the computational efficiency.
[0046] In practical applications, the microcontroller's internal PWM timer is configured to run and generate PWM waveforms to drive power devices. The PWM timer adopts a center-aligned mode, and the counter increments to a preset peak value and then decrements. An internal trigger signal is generated when the counter reaches the peak value. At the set synchronization time, i.e. the center point of the PWM cycle or other specific time configured by the register, the PWM timer hardware automatically generates the trigger pulse without software intervention; The trigger pulse is transmitted directly to the external trigger input of the ADC control unit via the event router or bus inside the microcontroller. Upon receiving a trigger signal, the ADC module immediately begins sampling and analog-to-digital conversion of the pre-selected channels, which may include single-channel or multi-channel sequences. The generation, transmission, and ADC sampling start-up process of the trigger signal are all completed by hardware. The CPU does not participate in any timing control, thereby ensuring the synchronization accuracy and determinism between the sampling time and the PWM waveform.
[0047] In this embodiment, the high-speed comparator, input capture unit, or auxiliary ADC channel inside the microcontroller is used to monitor the zero-crossing points or specific characteristic points of the input voltage or current signal in real time. By measuring the time interval between two consecutive zero-crossing points or the number of pulses per unit time, the real-time frequency of the current input signal is calculated. f real Alternatively, after each batch calculation is completed, the current signal frequency can be estimated using the phase information from the recursive discrete Fourier transform algorithm. The real-time frequency obtained from monitoring f real Substitute the parameters into the calculation model to automatically calculate the new configuration parameters required for the PWM timer; The parameter calculation model is based on the following relationship: to ensure a fixed number of points are collected in each period of the signal. M And maintain center alignment mode, which must meet the following requirements. T pwm =1 / f real =( ARR new +1)× T clk ,in, T clk The timer clock cycle; The value of the Automatic Reload Register (ARR) is calculated and updated based on the parameter calculation formula. ARR new =(1 / ( f real × T clk )) 1. Simultaneously, according to the requirements of the center alignment mode, the value of the comparison register CCR is dynamically adjusted to... ARR new / 2, to ensure that the trigger signal is always located at the geometric center of the signal cycle; Without stopping PWM output and ADC sampling, the calculated values can be obtained using the microcontroller's register shadow update mechanism or pre-loading function. ARR new The new CCR value is written to the preload register of the PWM timer; When a PWM timer update event (overflow or underflow) occurs, the hardware automatically transfers the preloaded value to the active register, so that at the beginning of the next PWM cycle, the period and duty cycle of the PWM waveform will run according to the new frequency parameters. The PWM timer operates based on the updated ARR value, and when the counter reaches the new peak value, that is... ARR new It still generates the TRGO hardware trigger signal through the internal event router; The TRGO signal directly triggers the ADC to start conversion, ensuring that the ADC's sampling time is always locked at the center point of the input signal cycle. Even under conditions of grid frequency fluctuations or inverter output frequency changes, soft synchronization between the sampling time and the measured signal can be achieved, avoiding spectrum leakage and calculation errors caused by frequency mismatch.
[0048] In this embodiment, an error compensation mechanism is introduced into the recursive discrete Fourier transform algorithm: Set the trigger period for error compensation, which is based on the number of sampling points or the time interval; for example, set it to be every fixed number of sampling points. M ( M It is a positive integer, and M ≤ N , N The number of sampling points in one cycle or the error compensation process is triggered once every fixed time window; When the set compensation trigger condition is met, the traditional Discrete Fourier Transform (DFT) algorithm is paused or executed in parallel; the most recent... N Data sequence of sampling points x [ n N +1],…, x [ n Using the traditional DFT formula Perform full complex multiplication and addition operations on this data segment to calculate the signal spectrum reference value at that moment. X dft [ n ]; Read the results calculated by the recursive discrete Fourier transform algorithm at the same time point. X rec [ n The baseline value obtained by traditional DFT calculation; X dft [ n ] and the result of the recursive algorithm X rec [ n Compare the two and calculate the error value Δ. X = X dft [ n ] X rec [ nThis error value includes both amplitude error and phase error; Based on the calculated error value Δ X Perform at least one of the following correction operations: Parameter tuning: Update key parameters in the recursive algorithm, including the rotation factor, using the error values. W and / or attenuation factor K Fine-tuning using table lookup or formula methods W and K The value of makes the result of the next recursive calculation Xrec [ n +1] is closer to the true value; Result Correction: A correction factor is directly added to the subsequent results calculated by the recursive algorithm. This correction factor is derived based on the weighted average of historical errors or the proportionality coefficient of the current error. X corrected [ n ]= X rec [ n ]+ α Δ X ,in α For correction factors, 0 < α ≤1; Adjusted rotation factor W Attenuation factor K Alternatively, the corrected calculation result can be fed back into the next calculation cycle of the recursive discrete Fourier transform algorithm, serving as a new initial value or intermediate variable to continue participating in the recursion. This suppresses calculation divergence caused by floating-point truncation error, coefficient quantization error, or signal drift accumulation, ensuring the numerical stability and high accuracy of the algorithm under long-term operation.
[0049] An embodiment of a high-speed AC sampling computing device based on DFT like Figure 5 As shown, this embodiment provides a high-speed AC sampling computing device based on DFT, comprising: The PWM hardware-triggered ADC synchronous sampling module is used to directly trigger the ADC module to start analog-to-digital conversion by utilizing the hardware trigger signal automatically generated by the microcontroller's internal PWM timer during operation, thereby achieving automatic synchronization between the sampling time and the PWM control waveform. The DMA automatic data transfer and buffer management module is used to take the ADC conversion result of the ADC module as the DMA request source, and the DMA controller automatically stores the conversion result into the data buffer. The data processing triggering module is used to trigger batch calculations on the data in the data buffer based on the interrupt generated by the DMA controller when the data buffer is filled to half or all. The recursive DFT fast effective value calculation module is used to perform batch calculations by employing a recursive discrete Fourier transform PWM hardware-triggered ADC synchronous sampling module. Furthermore, the PWM hardware-triggered ADC synchronous sampling module uses an ARM Cortex-M series MCU, such as the STM32F407, which integrates a PWM timer (TIM1) and an ADC module (ADC1). The PWM timer is configured in center-aligned mode, with a counter period of 20kHz (corresponding to a 50μs period), and an auto-reload value (ARR) of 1000. The counter increments to 1000 and then decrements to 0. When the counter reaches its peak value (ARR value), the PWM timer hardware automatically generates a trigger signal TRGO, which is connected to the external trigger input (EXTTRIG) of the ADC via the MCU's internal event router.
[0050] The PWM timer starts, generating a PWM waveform to drive the power device (such as an IGBT). When the counter reaches the ARR value, the hardware automatically generates a trigger pulse without CPU intervention. The trigger pulse is sent directly to the ADC control unit via the internal bus, and the ADC immediately starts sampling and converting the pre-selected channel (such as voltage channel UA and current channel IA). Thus, the CPU is completely uninvolved in the triggering process, avoiding interrupt delays and resource consumption.
[0051] Furthermore, the DMA automatic data transfer and buffer management module configures the DMA controller (DMA2), whose source address points to the ADC data register (ADC1->DR) and the destination address points to the circular buffer (adc_buffer
[128] ) in memory. ADC conversion is enabled to complete the DMA request, and the DMA is set to circular mode with a buffer length of 128 (corresponding to 256 sampling points / power frequency cycle).
[0052] When the ADC completes a conversion, it automatically sends a request to the DMA. The DMA controller moves the ADC result from ADC1->DR to adc_buffer without CPU intervention. When the DMA is full at the end of the buffer (adc_buffer
[127] ), it automatically wraps back to the beginning address of the buffer (adc_buffer[0]) to form a circular buffer.
[0053] Furthermore, the data processing trigger module enables DMA half-full / full-full interrupts, sets the buffer length to 128, and the half-full threshold to 64. When DMA completes 64 transfers (half-full), the half-full interrupt flag is set; when DMA completes 128 transfers (full), the full-full interrupt flag is set.
[0054] The CPU checks the flags in the interrupt service routine: If the half-full flag is valid, call the processing function to calculate the data from adc_buffer[0] to adc_buffer
[63] ; if the full flag is valid, calculate the data from adc_buffer
[64] to adc_buffer
[127] ; after processing, clear the flag and return to the main program.
[0055] Furthermore, the recursive DFT fast effective value calculation module adopts the recursive discrete Fourier transform algorithm. In the DMA interrupt service routine, the recursive DFT algorithm is applied to the new data in the buffer, and the effective value result is output to the display module or control unit.
[0056] Therefore, this device achieves high-speed, low-power, and high-precision AC sampling and calculation through the collaborative design of PWM hardware triggering, DMA automatic transfer, batch interrupt triggering, and recursive DFT algorithm. Actual measurements show that with 256 points / cycle sampling, the effective value calculation error is less than 0.1%, the CPU load rate is less than 5%, and the hardware cost is 60% lower than that of an FPGA solution, making it suitable for smart meters, motor control, and other scenarios.
[0057] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0058] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.
Claims
1. A high-speed AC sampling calculation method based on DFT, characterized in that, include: Using the microcontroller's internal PWM timer as the time base and trigger source, and configuring it in center-aligned mode, an internal trigger signal TRGO is automatically generated when the counter reaches its peak value during operation. The TRGO signal is then connected to the external trigger input of the ADC module through the microcontroller's internal event router or trigger distribution unit. At the same time, the ADC module is configured to work in external trigger mode. In this way, the hardware trigger signal can be used to directly trigger the ADC module to start the analog-to-digital conversion event, thereby achieving automatic synchronization between the sampling time and the PWM control waveform. The ADC conversion result of the ADC module is used as the DMA request source, and the DMA controller automatically stores the ADC conversion result into the data buffer. The batch computation of data in the data buffer is triggered by an interrupt generated by the DMA controller when the data buffer is filled to half or all of its capacity; during the batch computation, the effective value of the signal is updated using a recursive discrete Fourier transform algorithm.
2. The method according to claim 1, characterized in that: In center-aligned mode, the timer's auto-reload value ARR is set so that the counter increments from 0 to the ARR value and then decrements back to 0, forming a complete PWM cycle. Configure the timer's output compare mode so that when the counter reaches the ARR peak, an internal trigger signal TRGO is automatically generated through the hardware logic of the PWM timer. The internal trigger signal TRGO is directionally connected to the external trigger input of the ADC module through the event router or trigger distribution unit inside the microcontroller, and the ADC module is configured to external trigger mode; at the ARR value time of each PWM cycle, the internal trigger signal TRGO automatically starts the ADC to perform analog-to-digital conversion on the preset sampling channel.
3. The method according to claim 2, characterized in that: During the hardware configuration phase of the microcontroller, enable the internal event router or trigger distribution unit function and select the TRGO signal of the PWM timer as the source trigger signal; According to the hardware interface specification of the target ADC module, configure the target address parameters in the event router or trigger distribution unit to route the TRGO signal to the external trigger input port of the ADC module. In the initialization configuration of the ADC module, its trigger source is set to external trigger mode, and the polarity of the external trigger signal is specified to match the characteristics of the TRGO signal. Verify the physical connection and logical configuration of the TRGO signal and the external trigger input of the ADC using the microcontroller's register configuration tool or software development interface. Ensure that the TRGO signal can reliably trigger the ADC to start analog-to-digital conversion when the PWM timer counts to the ARR value.
4. The method according to claim 1, characterized in that: Configure the DMA controller, enable its cyclic mode function option, and set its source address to point to the data register of the ADC module, which is represented as ADC1->DR; at the same time, set the destination address to point to the data buffer that the user has pre-set in memory for storing data, and set the data buffer to have a fixed start address and end address; Enable the DMA request function after the ADC module completes the conversion, so that the ADC module can immediately send a data transfer request to the DMA controller after completing an analog-to-digital signal conversion operation. When the DMA controller performs a data transfer operation, writing the ADC conversion result into the data buffer, until the last memory cell of the data buffer is full, the DMA controller automatically wraps the data write address back to the starting address of the buffer according to its internal preset loop mechanism, and continues to perform the data write operation.
5. The method according to claim 4, characterized in that: The data buffer length is preset to N; In the configuration of the DMA controller, enable its transfer completion interrupt flag setting function, and set half-full and full-full interrupt trigger conditions for the data buffer transfer status. That is, when the DMA completes N / 2 data transfers, set it to the half-full interrupt flag, and when it completes N data transfers, set it to the full-full interrupt flag. During the data transfer process, the DMA controller monitors the number of data transfers in real time. Whenever the number of data transfers reaches N / 2 or N, the DMA controller automatically sets the corresponding interrupt flag based on preset conditions.
6. The method according to claim 5, characterized in that: When the DMA controller triggers an interrupt due to reaching the preset number of data transfers, the system automatically jumps to the DMA interrupt service routine for execution. In the interrupt service routine, the status of the half-full interrupt flag and the full-full interrupt flag is checked by reading from the hardware registers. If the half-full interrupt flag is detected to be set, the interrupt service routine calls the first processing function. The first processing function accesses the first half of the data in the buffer through pointer operations. The pointer range is from &adc_buffer[0] to &adc_buffer[N / 2 - 1], and performs processing operations on the first half of the data. If the full interrupt flag is detected to be set, the interrupt service routine calls the second processing function. This second processing function accesses the second half of the data in the buffer through pointer operations. The pointer range is from &adc_buffer[N / 2] to &adc_buffer[N - 1], and performs processing operations on the second half of the data. After the corresponding data processing operation is completed, the interrupt service routine clears the triggered half-full or full interrupt flag by writing to the hardware register.
7. The method according to claim 6, characterized in that, The process of batch calculation based on DMA interrupt triggering and updating the effective value of the signal using a recursive discrete Fourier transform algorithm includes: Based on the interrupt signal generated by the DMA controller when the data buffer is filled to half or full, a batch calculation operation on the data in the data buffer is triggered; specifically, when a half-full interrupt is detected, the first half of the data in the data buffer is batch calculated; when a full interrupt is detected, the second half of the data in the data buffer is batch calculated. Before the batch calculation begins, the relevant parameters are pre-initialized, including determining the number of sampling points N, rotation factor W, and decay factor K for one period, and setting the initial value of the DFT result X[n - 1] of the previous sampling point x[n - 1]. During the batch calculation process, for each current sampling point x[n], its value and the value of the corresponding sampling point x[n - N] in the previous period are obtained. The obtained values of the current sampling point x[n], the previous sampling point x[n - 1] (if it is the first sampling point, the initial value is used), the corresponding sampling point x[n - N] in the previous period, and the predetermined rotation factor W and attenuation factor K are substituted into the recursive formula X[n] = (X[n - 1] + (x[n] - x[n - N]) * W) * K to obtain the DFT result X[n] of the current sampling point x[n]. Using the calculated DFT result X[n] of the current sampling point x[n], the effective value of the signal is further updated, completing one signal effective value update calculation process based on the recursive discrete Fourier transform algorithm. In the calculation of the sampling point, the DFT result X[n] of the current sampling point x[n] obtained in this calculation is used as the DFT result X[n-1] of the previous sampling point x[n-1] when calculating the next sampling point. The above steps are repeated to continuously update the effective value of the signal.
8. The method according to any one of claims 1 to 7, characterized in that: By utilizing the high-speed comparator, input capture unit, or auxiliary ADC channel within the microcontroller, the zero-crossing points or characteristic points of the input voltage or current signal are monitored in real time. By measuring the time interval between two consecutive zero-crossing points or the number of pulses per unit time, the real-time frequency of the current input signal is calculated. f real Alternatively, after each batch calculation is completed, the current signal frequency can be estimated using the phase information from the recursive discrete Fourier transform algorithm. The real-time frequency obtained from monitoring f real Substitute the parameters into the calculation model to automatically calculate the new configuration parameters required for the PWM timer; The parameter calculation model is based on the following relationship: to ensure a fixed number of points are collected in each period of the signal. M And maintain center alignment mode, which must meet the following requirements. T pwm =1 / f real =( ARR new +1)× T clk ,in, T clk The timer clock cycle; The value of the Automatic Reload Register (ARR) is calculated and updated based on the parameter calculation formula. ARR new =(1 / ( f real × T clk )) 1. Simultaneously, according to the requirements of the center alignment mode, the value of the comparison register CCR is dynamically adjusted to... ARR new / 2; Without stopping PWM output and ADC sampling, the calculated values can be obtained using the microcontroller's register shadow update mechanism or pre-loading function. ARR new The new CCR value is written to the preload register of the PWM timer; When a PWM timer update event occurs, the hardware automatically transfers the preloaded value to the active register, so that at the beginning of the next PWM cycle, the period and duty cycle of the PWM waveform will run according to the new frequency parameters. The PWM timer operates based on the updated ARR value, and when the counter reaches the new peak value, that is... ARR new It still generates the TRGO hardware trigger signal through the internal event router.
9. The method according to claim 7, characterized in that, In the recursive discrete Fourier transform algorithm, an error compensation mechanism is introduced: Set the trigger period for error compensation, which is based on the number of sampling points or the time interval; When the set compensation trigger condition is met, the traditional Discrete Fourier Transform (DFT) algorithm is paused or executed in parallel. Select the most recent N Data sequence of sampling points x [ n N +1],…, x [ n Using the traditional DFT formula Perform full complex multiplication and addition operations on this data segment to calculate the signal spectrum reference value at that moment. X dft [ n ]; Read the results calculated by the recursive discrete Fourier transform algorithm at the same time point. X rec [ n The baseline value obtained by traditional DFT calculation; X dft [ n ] and the result of the recursive algorithm X rec [ n Compare the two and calculate the error value Δ. X = X dft [ n ] X rec [ n This error value includes both amplitude error and phase error; Based on the calculated error value Δ X Perform at least one of the following correction operations: Parameter tuning: Update key parameters in the recursive algorithm, including the rotation factor, using the error values. W and / or attenuation factor K ; Fine-tuning using table lookup or formula methods W and K The value of makes the result of the next recursive calculation Xrec [ n +1] is closer to the true value; Result Correction: A correction factor is directly added to the subsequent results calculated by the recursive algorithm. This correction factor is derived based on the weighted average of historical errors or the proportionality coefficient of the current error. X corrected [ n ]= X rec [ n ]+ α Δ X ,in α For correction factors, 0 < α ≤1; Adjusted rotation factor W Attenuation factor K Alternatively, the corrected calculation result can be fed back into the next calculation cycle of the recursive discrete Fourier transform algorithm, serving as a new initial value or intermediate variable to continue participating in the recursion.
10. A high-speed AC sampling computing device based on DFT, characterized in that, include: The PWM hardware-triggered ADC synchronous sampling module is used to directly trigger the ADC module to start analog-to-digital conversion by utilizing the hardware trigger signal automatically generated by the microcontroller's internal PWM timer during operation, thereby achieving automatic synchronization between the sampling time and the PWM control waveform. The DMA automatic data transfer and buffer management module is used to take the ADC conversion result of the ADC module as the DMA request source, and the DMA controller automatically stores the conversion result into the data buffer. The data processing triggering module is used to trigger batch calculations on the data in the data buffer based on the interrupt generated by the DMA controller when the data buffer is filled to half or all. The recursive DFT fast effective value calculation module is used to update the effective value of the signal using the recursive discrete Fourier transform algorithm during batch calculation.