Data transmission method and device applied to link-16 data link

Abstract

The application discloses a data transmission method and device applied to a Link-16 data chain, and the method comprises the following steps: performing CRC encoding on a source information bit sequence based on a target algorithm to obtain an information bit sequence provided with a check bit; performing Turbo encoding on the information bit sequence provided with the check bit to obtain a target code word; performing minimum frequency shift keying modulation on the target code word to generate a first target signal; and after the first target signal is packaged according to a standard double-pulse packaging structure of the Link-16 data chain, the first target signal is transmitted through a macro time slot; the macro time slot comprises four basic time slots cascaded in the Link-16 data chain; and one frequency point is fixedly used in each macro time slot. The data transmission method and device applied to the Link-16 data chain can improve the sensitivity of reception through narrow-band and long-time-slot design.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a data transmission method and apparatus for use in the Link-16 data link. Background Technology

[0002] The Link-16 data link is a widely used data link. In terms of channel coding, it employs 32nd-order (31,15) Reed-Solomon (RS) codes, providing strong anti-interference capabilities. For modulation, it uses a soft spread spectrum scheme of Minimum Shift Keying (MSK) concatenated Cyclic Code Shift Keying (CCSK), offering high spreading gain. However, the Link-16 data link performs poorly in terms of received data sensitivity.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a data transmission method and apparatus for the Link-16 data link, which can improve the sensitivity of reception.

[0005] To achieve the above objectives, the present invention provides a data transmission method for a Link-16 data link, applied at the sending end, the method comprising:

[0006] Based on the target algorithm, the source information bit sequence is CRC encoded to obtain an information bit sequence with a check bit.

[0007] The information bit sequence with parity bits is Turbo encoded to obtain the target codeword;

[0008] The target codeword is subjected to minimum frequency shift keying modulation to generate a first target signal;

[0009] After the first target signal is encapsulated according to the standard dual-pulse encapsulation structure of the Link-16 data link, it is transmitted through a macro time slot; the macro time slot includes four basic time slots cascaded in the Link-16 data link; each macro time slot uses a fixed frequency point.

[0010] In one embodiment of the present invention, before performing CRC encoding on the source information bit sequence based on the target algorithm to obtain the information bit sequence with check bits, the method includes:

[0011] With the goal of minimizing the relative sensitivity of the receiver, initial values ​​for symbol rate, coding efficiency, and modulation efficiency are determined; the relative sensitivity is the variable part of the receiver sensitivity.

[0012] Based on the initial values ​​of the symbol rate, coding efficiency, and modulation efficiency, the number of symbols contained in the target algorithm and the training sequence in the basic time slot is determined.

[0013] In one embodiment of the present invention, the relative sensitivity is

[0014] ;

[0015] in, This indicates the relative sensitivity; Indicates the symbol rate; Indicates coding efficiency; Indicates modulation efficiency; This indicates the demodulation signal-to-noise ratio.

[0016] In one embodiment of the present invention, the step of performing CRC encoding on the source information bit sequence using a target algorithm to obtain an information bit sequence with a check bit includes:

[0017] A binary vector of length (LenBit+1) is randomly generated and used as the CRC checksum vector; the first and last elements of the binary vector are both 1.

[0018] Randomly generate a binary bit sequence of the source information with a length of LenBit;

[0019] Based on the CRC checksum vector, the source information bit sequence is CRC encoded to obtain the transmission sequence with added check bits;

[0020] Randomly generate a binary error sequence of length (LenBit + LenCRC); LenCRC is the length of the CRC check bit vector.

[0021] The received sequence is obtained by adding the transmitted sequence modulo 2 to the error sequence;

[0022] The presence of errors in the received sequence is determined by CRC check, and the presence of errors is determined by comparing the source information bit sequence with the received sequence.

[0023] If the verification results of the two methods are the same, the transmission sequence is determined to be the information bit sequence with the check bit.

[0024] In one embodiment of the present invention, a data transmission method applied to a Link-16 data link is provided at a receiving end, the method comprising:

[0025] The second target signal is received based on a macro time slot; the second target signal is transmitted based on the method described in any one of claims 1 to 4; the macro time slot includes four basic time slots cascaded by a Link-16 data link; each macro time slot uses a fixed frequency point;

[0026] Based on the training sequences in each of the basic time slots, the second target signal is synchronized in a timing manner to obtain the third target signal;

[0027] Based on the training sequences in each of the basic time slots, the phase offset of the third target signal is estimated to obtain the fourth target signal;

[0028] Based on the log-likelihood ratio, the fourth target signal is subjected to Turbo decoding to obtain the decoded bit sequence;

[0029] Perform CRC check on the decoded bit sequence to obtain the decision bit sequence.

[0030] In one embodiment of the present invention, a data transmission device applied to a Link-16 data link includes:

[0031] The first encoding module is used to perform CRC encoding on the source information bit sequence based on the target algorithm to obtain an information bit sequence with a check bit.

[0032] The second encoding module is used to perform Turbo encoding on the information bit sequence with parity bits to obtain the target codeword;

[0033] The modulation module is used to perform minimum frequency shift keying modulation on the target codeword to generate a first target signal;

[0034] The transmitting module is used to encapsulate the first target signal according to the standard dual-pulse encapsulation structure of the Link-16 data link and transmit it through a macro time slot; the macro time slot includes four basic time slots cascaded in the Link-16 data link; each macro time slot uses a fixed frequency point.

[0035] In one embodiment of the present invention, a data transmission device applied to a Link-16 data link includes:

[0036] A receiving module is used to receive a second target signal based on a macro time slot; the second target signal is transmitted based on the method described above; the macro time slot includes four basic time slots cascaded by a Link-16 data link; each macro time slot uses a fixed frequency point.

[0037] The timing synchronization module is used to synchronize the second target signal based on the training sequence in each of the basic time slots, and to obtain the third target signal.

[0038] The phase bias estimation module is used to perform phase bias estimation on the third target signal based on the training sequence in each of the basic time slots to obtain the fourth target signal;

[0039] The decoding module is used to perform Turbo decoding on the fourth target signal based on the log-likelihood ratio to obtain the decoded bit sequence;

[0040] The verification module is used to perform CRC verification on the decoded bit sequence to obtain the decision bit sequence.

[0041] In one embodiment of the present invention, an electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the data transmission method applied to the Link-16 data link as described above.

[0042] In one embodiment of the present invention, a non-transitory computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the data transmission method applied to the Link-16 data link as described above.

[0043] In one embodiment of the present invention, a computer program product includes a computer program that, when executed by a processor, implements the steps of the data transmission method applied to the Link-16 data link as described above.

[0044] Compared with the prior art, the data transmission method and apparatus of the present invention applied to the Link-16 data link have the following advantages: Addressing the problem of insufficient sensitivity of STDP messages in the Link-16 data link, the present invention proposes a macro-slot structure design, a new CRC checksum search, and a physical layer-by-layer optimization scheme using Turbo code 2.0. It also proposes the concept of relative sensitivity as an optimization target. Through narrowband, long slot design, the receiving sensitivity index can be improved by 28dB or more. The new CRC design method achieves the best balance between error detection performance and overhead. Furthermore, by replacing the traditional RS code with a new Turbo code, higher coding gain can be obtained. Attached Figure Description

[0045] Figure 1 This is one of the schematic diagrams of the time slot structure of the Link-16 data link in related technologies;

[0046] Figure 2 This is the second schematic diagram of the time slot structure of the Link-16 data link in related technologies;

[0047] Figure 3 This is the third schematic diagram of the time slot structure of the Link-16 data link in related technologies;

[0048] Figure 4 This is the fourth schematic diagram of the time slot structure of the Link-16 data link in related technologies;

[0049] Figure 5 This is one of the flowcharts illustrating a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0050] Figure 6 This is a second schematic flowchart of a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0051] Figure 7 This is a schematic diagram of the structure of a Turbo code encoder used in a data transmission method applied to a Link-16 data link according to an embodiment of the present invention.

[0052] Figure 8 This is a schematic diagram of the structure of a component encoder used in a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0053] Figure 9 This is a schematic diagram of the structure of the macro slot of the Link-16 data link used in the data transmission method applied to the Link-16 data link according to an embodiment of the present invention;

[0054] Figure 10 This is a schematic diagram of the structure of a single basic time slot in the macro time slot of the Link-16 data link used in the data transmission method applied to the Link-16 data link according to an embodiment of the present invention;

[0055] Figure 11 This is a third flowchart illustrating a data transmission method applied to a Link-16 data link according to an embodiment of the present invention.

[0056] Figure 12 This is the fourth flowchart illustrating a data transmission method applied to a Link-16 data link according to an embodiment of the present invention.

[0057] Figure 13 This is a schematic diagram of the bit error rate for a conventional data transmission method used in the Link-16 data link;

[0058] Figure 14 This is a diagram illustrating the packet error rate of a conventional data transmission method used in the Link-16 data link.

[0059] Figure 15 This is one of the schematic diagrams illustrating the bit error rate of a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0060] Figure 16 This is one of the schematic diagrams illustrating the packet error rate of a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0061] Figure 17 This is a second schematic diagram of the bit error rate of a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0062] Figure 18 This is a second schematic diagram of the packet error rate of a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0063] Figure 19 This is a third schematic diagram of the bit error rate of a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0064] Figure 20 This is a third schematic diagram illustrating the packet error rate of a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0065] Figure 21 This is the fourth schematic diagram of the bit error rate of a data transmission method applied to a Link-16 data link according to an embodiment of the present invention;

[0066] Figure 22 This is a fourth schematic diagram illustrating the packet error rate of a data transmission method applied to a Link-16 data link according to an embodiment of the present invention.

[0067] Figure 23 This is one of the structural schematic diagrams of a data transmission device applied to a Link-16 data link according to an embodiment of the present invention;

[0068] Figure 24 This is a second schematic diagram of a data transmission device applied to a Link-16 data link according to an embodiment of the present invention;

[0069] Figure 25 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0070] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0071] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0072] To facilitate understanding of the various embodiments of the present invention, the key technologies of the Link-16 data link physical layer will be described below.

[0073] First, let's explain the slot structure of the Link-16 data link.

[0074] In the Link-16 data link standard, the total number of available frequency points is 51, the symbol rate is 5 Msps, and the duration of each hop is [duration missing]. The frequency hopping rate is approximately 76,923 hops / s. Each time slot lasts for 7.8125 ms and includes coarse synchronization. Jump, fine synchronization Jump, Header Jump. Each time slot transmits a header and several message words, where the header contains 35 bits of information and each message word contains 70 bits of information.

[0075] Figures 1 to 4 The text illustrates the message encapsulation structure per time slot of the Link-16 data link in four modes: Standard Double Pulse (STDP), Packed-2 Single Pulse (P2SP), Packed-2 Double Pulse (P2DP), and Packed-4 Single Pulse (P4SP). The symbol "" is used in the text. " indicates that the entire jump is sent twice.

[0076] STDP is a standard dual-pulse encapsulation structure, including time-variable jitter. The jitter and transmission protection together occupy 4.4585ms. This mode transmits 3 message words, occupying a total of... Jump.

[0077] P2SP uses a two-single-pulse encapsulation structure, including time-variable jitter. The jitter and transmission protection together occupy 4.4585ms. This mode transmits 6 message words, with each 3 message words occupying 93 hops, for a total of 186 hops.

[0078] P2DP uses a dual-pulse encapsulation structure, is jitter-free, and has a transmission protection period of 2.0405ms. This mode transmits 6 message words, with each 3 message words occupying a specific time. Jumps, totaling 372 jumps.

[0079] P4SP uses a 4-single-pulse encapsulation structure, is jitter-free, and has a transmission protection period of 2.0405ms. This mode transmits 12 message words, with each 3 message words occupying 93 hops, for a total of 372 hops.

[0080] The Link-16 data link standard uses RS codes. RS codes are a type of high-order BCH code (an error-correcting code) with strong error correction capabilities.

[0081] Let the codeword length, information symbol length, and check symbol length be respectively , and ,for The relationship between the code length and the order of an RS code is as follows:

[0082] (1).

[0083] In the formula, are integers and satisfy For those capable of correction The check symbol length of the erroneous RS code is .

[0084] (2).

[0085] At this time, the minimum code distance is .

[0086] The generator polynomial of the RS code is

[0087] (3).

[0088] In the formula, For Galois The fundamental element in it.

[0089] RS codes mainly employ hard-decision decoding, resulting in relatively insufficient coding gain. When soft-information decoding is used, the decoding complexity increases dramatically, making them less practical.

[0090] Because RS code can be corrected A high-order error symbol, therefore suitable for correcting burst errors, and thus used in the Link-16 data link standard. In Link-16 data link, message words... RS encoding parameters are , The coding order is The masthead RS encoding is by It is derived from the basic RS code rate matching. Specifically, 8 symbols are added before the 7 symbols in the header, and the first 8 symbols and the last 7 symbols of the codeword are deleted after encoding.

[0091] CCSK is a soft spread spectrum technique that uses coding to increase redundancy to achieve spectrum expansion. It uses a number of information bits to correspond to a pseudo-random codeword, and the expansion factor is not large and is not necessarily an integer.

[0092] The design rule for CCSK codewords is that an all-zero source bit vector corresponds to a unipolar CCSK basic codeword, and the bipolar version of this codeword has good autocorrelation. For each bit increment in the source bit vector, the CCSK codeword is cyclically shifted to the left once. At the receiving end, the autocorrelation of the CCSK codeword is used for decoding, and the CCSK codeword corresponding to the maximum correlation value is obtained through correlation operations, thereby recovering the original information.

[0093] In the Link-16 data link standard, the CCSK encoding rule maps 5 bits of one RS code symbol to a 32-bit second-order codeword sequence. The table below shows the mapping rules for CCSK soft spread spectrum in the Link-16 standard.

[0094] Table 1. Mapping rules for CCSK soft spread spectrum in the Link-16 standard.

[0095]

[0096] Among related technologies, RS codes have a short code length and mainly use hard-decision decoding, resulting in relatively insufficient coding gain. Using soft-information decoding significantly increases decoding complexity, limiting its practical value. CCSK soft spread spectrum technology offers some gain in anti-interference, but does not improve sensitivity. Sensitivity is a crucial parameter for evaluating receiver capabilities, and the Link-16 data link standard performs poorly in this regard.

[0097] like Figures 5 to 25 As shown, the data transmission method and apparatus for the Link-16 data link according to a preferred embodiment of the present invention can be implemented in the following ways.

[0098] Figure 5 This is one of the flowcharts illustrating a data transmission method applied to a Link-16 data link according to an embodiment of the present invention. The method is applied at the sending end, specifically a data transmission method applied to a Link-16 data link. Figure 5 As shown, the method may include the following steps:

[0099] Step 501: Based on the target algorithm, perform CRC encoding on the source information bit sequence to obtain an information bit sequence with a check bit;

[0100] Step 502: Perform Turbo encoding on the information bit sequence with parity bits to obtain the target codeword;

[0101] Step 503: Perform minimum frequency shift keying modulation on the target codeword to generate the first target signal;

[0102] Step 504: After encapsulating the first target signal according to the standard dual-pulse encapsulation structure of the Link-16 data link, it is transmitted through a macro time slot; the macro time slot includes four basic time slots cascaded by the Link-16 data link; each macro time slot uses a fixed frequency point.

[0103] Specifically, refer to Figure 6 At the sending end, the source information bit sequence After CRC encoding, an information bit sequence with a check bit is obtained. Information bit sequence with parity bits The codeword is obtained after Turbo encoding. ; code The transmitted signal is obtained after MSK modulation. (i.e., the first target signal).

[0104] In some feasible implementations, before performing CRC encoding on the source information bit sequence based on the target algorithm to obtain the information bit sequence with check bits, the method includes:

[0105] The initial values ​​for symbol rate, coding efficiency, and modulation efficiency are determined with the goal of minimizing the relative sensitivity of the receiver; the relative sensitivity is the variable part of the receiver sensitivity.

[0106] Based on the initial values ​​of symbol rate, coding efficiency, and modulation efficiency, the number of symbols contained in the training sequence in the target algorithm and the basic time slot is determined.

[0107] In some feasible implementations, the relative sensitivity is

[0108] ;

[0109] in, Indicates relative sensitivity; Indicates the symbol rate; Indicates coding efficiency; Indicates modulation efficiency; This indicates the demodulation signal-to-noise ratio.

[0110] It should be noted that this paper first proposes the concept of relative sensitivity as an optimization target. Based on this, a randomized search method for CRC is proposed, a suitable channel coding scheme is selected, and then the corresponding narrowband long time slot structure (i.e., the macro time slot in step 504) is designed.

[0111] In wireless communication, receiver sensitivity is calculated as follows:

[0112] .

[0113] Where -174 is the thermal noise power spectral density, and NF is the noise figure. Where is the signal bandwidth and SNR is the demodulated signal-to-noise ratio; both are measured in dB.

[0114] Among them, demodulation signal-to-noise ratio and Sampling power (SPS) and coding efficiency (Ratio of information length to codeword length) and modulation efficiency The (bit / symbol) relationship is:

[0115] .

[0116] And signal bandwidth With symbol rate and filter roll-off coefficient The relationship is

[0117] .

[0118] Substituting the above two equations into the formula for calculating receiver sensitivity, we get...

[0119] .

[0120] In this structure, the first line represents the fixed portion, and the next line represents the variable portion. The variable portion is represented as...

[0121] .

[0122] in, Defined as relative sensitivity. In physical layer signal design, optimizing receiver sensitivity is actually achieved by selecting... and , Minimize the relative sensitivity while maintaining the same parameters, i.e.

[0123] .

[0124] When selecting the above parameters, the overhead of synchronization, training, and loop prefix is ​​also implicitly selected.

[0125] In some feasible implementations, the source information bit sequence is CRC encoded using a target algorithm to obtain an information bit sequence with a check bit, including:

[0126] A random binary vector of length (LenBit+1) is generated as the CRC checksum vector; the first and last elements of the binary vector are both 1.

[0127] Randomly generate a binary source information bit sequence of length LenBit;

[0128] Based on the CRC checksum vector, the source information bit sequence is CRC encoded to obtain the transmission sequence with added check bits.

[0129] Randomly generate a binary error sequence of length (LenBit + LenCRC); LenCRC is the length of the CRC check bit vector.

[0130] The received sequence is obtained by adding the transmitted sequence modulo 2 to the error sequence.

[0131] The presence of errors in the received sequence is determined by CRC check, and the source information bit sequence is compared with the received sequence to check for errors.

[0132] If the verification results of the two methods are the same, the transmission sequence is determined to be the information bit sequence with a check bit.

[0133] It should be noted that the improved signal design aims to enhance relative sensitivity and balance performance and transmission overhead, focusing on optimizing the verification mechanism, selecting channel coding, and adapting the coding scheme.

[0134] The impact of CRC codes on link reliability mainly includes: insufficient verification capability due to excessively short check code length; wasteful overhead due to excessively long check code length; performance differences even among check codes of the same length; and ease of decryption due to the use of popular commercial standards.

[0135] This invention relates to a novel CRC check bit vector (i.e., CRC checksum vector). This invention proposes a randomized search method, or target algorithm, applicable to CRC check bit vectors of arbitrary length. Table 2 below shows the specific algorithm steps of the above randomized search method. Wherein, LenBit represents the length of the source bit sequence, LenCRC represents the length of the required CRC check bit vector, and NOT represents the number of experiments.

[0136] Table 2. CRC Code Search Method

[0137]

[0138] If the check capability of the CRC sequence is comparable to the comparison results of the source and received sequences, then the CRC sequence (referring to the transmitted sequence BitSrc with added check bits) is considered usable; otherwise, it is unusable. If the CRC sequence is usable, it can be used as the result of CRC encoding.

[0139] The above method was used to search for CRC checksum vectors of different lengths, as shown in the table below.

[0140] Table 3. CRC checksum vectors of different lengths

[0141] Check code length Check code vector 4 [1, 1, 0, 1, 1] 5 [1, 0, 1, 0, 1, 1] 6 [1, 0, 0, 1, 1, 0, 1] 7 [1, 0, 0, 1, 1, 1, 0, 1] 8 [1, 1, 1, 0, 0, 0, 1, 0, 1] 9 [1, 1, 0, 1, 0, 1, 1, 1, 1, 1] 10 [1, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1] 11 [1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 1] 12 [1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 1] 13 [1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 1] 14 [1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 1, 1, 0, 1] 15 [1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1] 16 [1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1] 17 [1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1] 18 [1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1] 19 [1, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1] 20 [1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1]

[0142] Preferably, a CRC checksum vector with a length of 11 can be selected.

[0143] The channel coding scheme in this embodiment can adopt the Turbo Code 2.0 basic structure for 5G, and the intra-code interleaving uses the LTE QPP parameters, that is, the QPP interleaving parameters corresponding to 256 information bits are as follows. , .

[0144] The general structure of a Turbo code encoder can be as follows: Figure 7 As shown. Source information bit sequence First, the first set of parity bit sequences is generated by component encoder 1 (RSC1). Meanwhile, the source sequence Sequence after interleaving within the code The second set of check bits is generated by component encoder 2 (RSC2). When the base bitrate is 1 / 3, and Each contains one output; when the base code rate is 1 / 5... and Each contains two outputs. Source sequence , and After both deletion and reuse, the required codeword length is obtained. .

[0145] The component encoder is a systematic recurrent convolutional code (RSC) commonly used in Turbo codes. The component coding structure with a base code rate of 1 / 5 is as follows: Figure 8 As shown. When the base code rate is 1 / 3, no check sequence is output. . Figure 8 The component encoder in the matrix can be described as follows:

[0146] .

[0147] The Turbo Code 2.0 component encoder employs a "tail-biting" scheme, meaning that through two rounds of encoding, the encoder's state before and after the second round of encoding is identical. The initial state of the second round can be uniquely determined by the ending state of the first round, as shown in the table below.

[0148] Table 4 State Transition Lookup Table for "Tail-Biting" RSC Component Codes

[0149]

[0150] Based on the above analysis, the encoding method involved in this invention can be summarized as follows.

[0151] The total length of the message is: , where 11 is the length of the CRC check bits.

[0152] The total length of the codeword is:

[0153] When using 1 / 5 encoding, the total code length is 1280, and each component encoder outputs two check sequences with no deletion.

[0154] When using 1 / 3 encoding, the total code length is 768, and each component encoder outputs one check sequence with no deletion.

[0155] When using 1 / 2 encoding, the total code length is 512, and each component encoder outputs one check sequence, with odd-numbered bits pruned.

[0156] When using 2 / 3 encoding, the total code length is 384. Each component encoder outputs a check sequence, and the first 3 bits are deleted every 4 bits.

[0157] This invention focuses on minimizing relative sensitivity, optimizing it from two main dimensions: the signal transmission framework and the signal processing mechanism. The time slot structure, as the fundamental carrier of signal transmission, directly affects the symbol rate, synchronization accuracy, and channel estimation performance, and is a key prerequisite for improving sensitivity. The specific improved time slot structure design is as follows.

[0158] In the STDP improvement method proposed in this embodiment of the invention, four basic time slots are cascaded into a macro time slot, that is, the duration of each macro time slot is... The four basic time slots have the same structure, such as Figure 9 As shown. Each macro time slot uses a fixed frequency, and different macro time slots use different frequencies. In the STDP standard, one header and three message words are transmitted at a time. The header contains 35 bits of information, and each message word contains 70 bits of information. The symbol rate (in Sps) is calculated as follows:

[0159] .

[0160] The structure of a single basic time slot is as follows Figure 10 As shown, the front part is The training segment (i.e., training sequence) consists of 1 symbol, followed by 2 symbols. A data segment of 1 symbol (i.e., a data sequence). The training segment serves the dual purpose of synchronization and channel estimation, and uses a Big M sequence. The data segment carries the encoded data.

[0161] Figure 11 This is the third flowchart illustrating a data transmission method applied to a Link-16 data link according to an embodiment of the present invention. This method is applied at the receiving end, specifically a data receiving method applied to a Link-16 data link. For example... Figure 11As shown, the method may include the following steps:

[0162] Step 1101: Receive the second target signal based on the macro time slot; the second target signal is transmitted based on the transmission method provided in any of the foregoing embodiments; the macro time slot includes four basic time slots cascaded by the Link-16 data link; each macro time slot uses a fixed frequency point;

[0163] Step 1102: Based on the training sequences in each basic time slot, synchronize the second target signal in a timely manner to obtain the third target signal;

[0164] Step 1103: Based on the training sequences in each basic time slot, perform phase offset estimation on the third target signal to obtain the fourth target signal;

[0165] Step 1104: Based on the log-likelihood ratio, perform Turbo decoding on the fourth target signal to obtain the decoded bit sequence;

[0166] Step 1105: Perform CRC check on the decoded bit sequence to obtain the decision bit sequence.

[0167] Specifically, refer to Figure 12 At the receiving end, the training sequence can be used to analyze the received signal. (i.e., the second target signal) is used for timing synchronization to extract useful signals. (i.e., the third target signal); the signal is then processed again using the training sequence. Perform phase bias estimation to obtain the compensated signal. (i.e., the fourth target signal); the extracted log-likelihood ratio (LLR) will be used. Inputting into a Turbo decoder yields the decoded bit sequence. ; By decoding the bit sequence After performing CRC verification, the final decision bit sequence is obtained. .

[0168] The following simulation experiments demonstrate how the above embodiments of the present invention improve receiver sensitivity.

[0169] The simulation is based on the typical operating environment of the Link-16 data link, i.e., multipath effects are not considered, only phase shift is taken into account. The simulation comprehensively considers the effects of different code rates and training sequence lengths. When calculating error performance, the following is used: Packet error rate For reference only. Base bitrate The calculation method is the ratio of the sum of the source information and CRC check bits to the total code length, while the actual code rate is calculated as follows: The CRC check bits are considered redundant, so the calculation method is the ratio of the source information to the total code length.

[0170] In contrast. Figure 13 and Figure 14 Error performance of various message encapsulation structures in a standard Link-16 data link is presented. Considering its symbol rate... Bitrate , Therefore, its relative sensitivity is .

[0171] Figure 15 and Figure 16 The invention is presented at a base code rate of [specific value]. Actual bitrate Error performance with different training sequence lengths; Figure 17 and Figure 18 The invention is presented at a base code rate of [specific value]. Actual bitrate Error performance with different training sequence lengths; Figure 19 and Figure 20 The invention is presented at a base code rate of [specific value]. Actual bitrate Error performance with different training sequence lengths; Figure 21 and Figure 22 The invention is presented at a base code rate of [specific value]. Actual bitrate Error performance for different training sequence lengths. The error performance for each training sequence length, and their corresponding relative sensitivity indices, are shown in the following four tables.

[0172] Table 5. Relative sensitivity at a base code rate of 1 / 5 and different training sequence lengths.

[0173]

[0174] Table 6. Relative sensitivity at base bitrate of 1 / 3 and different training sequence lengths

[0175]

[0176] Table 7. Relative sensitivity at base bitrate 1 / 2 and different training sequence lengths

[0177]

[0178] Table 8. Relative sensitivity at base bitrate 2 / 3 and different training sequence lengths

[0179]

[0180] The tables above compare the relative sensitivities of various base bitrates and their corresponding training sequence lengths. It's easy to see that the relative sensitivities of all parameter configurations are significantly better than the STDP message encapsulation structure of the Link-16 data link. When the training length is 64, the optimal trade-off between the required training length and overhead cost is achieved. At this point, the relative sensitivity of a base bitrate of 1 / 3 is 41.46 dB, and the relative sensitivity of a base bitrate of 1 / 5 is 41.13 dB. When hardware resources are limited, the 1 / 3 base bitrate scheme can be considered; when higher sensitivity is desired, the 1 / 5 base bitrate scheme can be considered.

[0181] The beneficial effects of this invention are that, addressing the problem of insufficient sensitivity of STDP messages in the Link-16 data link, it proposes a macro-slot structure design, a new CRC checksum search, and a physical layer-by-layer optimization scheme using Turbo code 2.0. Furthermore, it proposes the concept of relative sensitivity as an optimization target. Through narrowband, long slot design, the receiving sensitivity can be improved by 28dB or more. The new CRC design method achieves an optimal balance between error detection performance and overhead. By replacing the traditional RS code with a new Turbo code, higher coding gain can be obtained.

[0182] It should be noted that this invention proposes a new concept of "relative sensitivity" as an optimization target; proposes a macro-slot structure design, which determines the signal structure framework through narrow-band long time slots; adopts training sequence multiplexing timing synchronization and phase bias estimation to save overhead; and proposes a randomized search method for CRC check codes to balance performance and overhead.

[0183] Simulations show that the optimal configurations are a training length of 64 and base bit rates of 1 / 3 and 1 / 5, which improve relative sensitivity by 28dB compared to traditional standards. This provides an efficient technical approach for the development of the Link-16 adaptation era without changing the core communication logic.

[0184] The data transmission apparatus for the Link-16 data chain provided by the present invention will be described below. The data transmission apparatus for the Link-16 data chain described below and the data transmission method for the Link-16 data chain described above can be referred to in correspondence.

[0185] Figure 23 This is one of the structural schematic diagrams of a data transmission device applied to the Link-16 data link provided by the present invention. This device can be a transmitting end or a transmitting end may include this device. Based on the content of any of the above embodiments, as... Figure 23 As shown, the device includes a first encoding module 2301, a second encoding module 2302, a modulation module 2303, and a transmission module 2304, wherein:

[0186] The first encoding module 2301 is used to perform CRC encoding on the source information bit sequence based on the target algorithm to obtain an information bit sequence with a check bit.

[0187] The second encoding module 2302 is used to perform Turbo encoding on the information bit sequence with parity bits to obtain the target codeword;

[0188] Modulation module 2303 is used to perform minimum frequency shift keying modulation on the target codeword to generate the first target signal;

[0189] The transmitting module 2304 is used to encapsulate the first target signal according to the standard double-pulse encapsulation structure of the Link-16 data link and transmit it through a macro time slot; the macro time slot includes four basic time slots cascaded in the Link-16 data link; each macro time slot uses a fixed frequency point.

[0190] Figure 24 This is a second structural schematic diagram of a data transmission device applied to the Link-16 data link provided by the present invention. This device can be a receiving end or the receiving end may include this device. Based on the content of any of the above embodiments, as... Figure 23 As shown, the device includes a receiving module 2401, a timing synchronization module 2402, a phase offset estimation module 2403, a decoding module 2404, and a verification module 2405, wherein:

[0191] The receiving module 2401 is used to receive a second target signal based on a macro time slot; the second target signal is transmitted based on any of the aforementioned transmission methods; the macro time slot includes four basic time slots cascaded by the Link-16 data link; each macro time slot uses a fixed frequency point;

[0192] The timing synchronization module 2402 is used to synchronize the second target signal based on the training sequence in each basic time slot and to obtain the third target signal.

[0193] The phase bias estimation module 2403 is used to perform phase bias estimation on the third target signal based on the training sequence in each basic time slot to obtain the fourth target signal;

[0194] The decoding module 2404 is used to perform Turbo decoding on the fourth target signal based on the log-likelihood ratio to obtain the decoded bit sequence;

[0195] The verification module 2405 is used to perform CRC verification on the decoded bit sequence and obtain the decision bit sequence.

[0196] The data transmission device for the Link-16 data chain provided in this embodiment of the invention is used to execute the data transmission method for the Link-16 data chain described above. Its implementation method is consistent with the implementation method of the data transmission method for the Link-16 data chain provided by this invention, and can achieve the same beneficial effects, so it will not be described again here.

[0197] The data transmission device applied to the Link-16 data chain is used in the data transmission methods applied to the Link-16 data chain in the foregoing embodiments. Therefore, the descriptions and definitions in the data transmission methods applied to the Link-16 data chain in the foregoing embodiments can be used for understanding the various execution modules in the embodiments of the present invention.

[0198] Figure 25 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 25 As shown, the electronic device may include: a processor 2510, a communications interface 2520, a memory 2530, and a communication bus 2540. The processor 2510, communications interface 2520, and memory 2530 communicate with each other via the communication bus 2540. The processor 2510 can call logic instructions in the memory 2530 to execute a data transmission method applied to the Link-16 data link. This method includes: performing CRC encoding on the source information bit sequence based on a target algorithm to obtain an information bit sequence with a check bit; performing Turbo encoding on the information bit sequence with the check bit to obtain a target codeword; performing minimum shift keying modulation on the target codeword to generate a first target signal; encapsulating the first target signal according to the standard dual-pulse encapsulation structure of the Link-16 data link, and then transmitting it through a macro time slot; the macro time slot includes four cascaded Link-16 data links. The system comprises: a basic time slot; each macro time slot using a fixed frequency; or the following: receiving a second target signal based on a macro time slot; the macro time slots include four basic time slots cascaded by a Link-16 data link; each macro time slot using a fixed frequency; timing synchronization of the second target signal based on the training sequences in each basic time slot to obtain a third target signal; phase offset estimation of the third target signal based on the training sequences in each basic time slot to obtain a fourth target signal; Turbo decoding of the fourth target signal based on the log-likelihood ratio to obtain a decoded bit sequence; and CRC verification of the decoded bit sequence to obtain a decision bit sequence.

[0199] Furthermore, the logical instructions in the aforementioned memory 2530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0200] The processor 2510 in the electronic device provided in this embodiment of the invention can call the logical instructions in the memory 2530. Its implementation method is consistent with the implementation method of the data transmission method applied to the Link-16 data link provided in this invention, and can achieve the same beneficial effects. It will not be described again here.

[0201] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, wherein when the program instructions are executed by a computer, the computer is able to execute the data transmission method applied to the Link-16 data link provided by the above methods, the method comprising: performing CRC encoding on a source information bit sequence based on a target algorithm to obtain an information bit sequence with a check bit; performing Turbo encoding on the information bit sequence with the check bit to obtain a target codeword; performing minimum frequency shift keying modulation on the target codeword to generate a first target signal; and encapsulating the first target signal according to the standard dual-pulse encapsulation structure of the Link-16 data link. After receiving a target signal, the signal is transmitted via a macro time slot. The macro time slot comprises four basic time slots cascaded by a Link-16 data link. Each macro time slot uses a fixed frequency. Alternatively, the signal may include: receiving a second target signal based on the macro time slots; the macro time slots comprise four basic time slots cascaded by a Link-16 data link; each macro time slot uses a fixed frequency; timing synchronization of the second target signal based on the training sequences in each basic time slot to obtain a third target signal; phase offset estimation of the third target signal based on the training sequences in each basic time slot to obtain a fourth target signal; Turbo decoding of the fourth target signal based on the log-likelihood ratio to obtain a decoded bit sequence; and CRC verification of the decoded bit sequence to obtain a decision bit sequence.

[0202] When the computer program product provided in this embodiment of the invention is executed, it implements the above-described data transmission method applied to the Link-16 data chain. Its specific implementation method is consistent with the implementation method described in the aforementioned method embodiment, and can achieve the same beneficial effects, which will not be repeated here.

[0203] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the aforementioned data transmission methods applied to the Link-16 data link. The method includes: performing CRC encoding on a source information bit sequence based on a target algorithm to obtain an information bit sequence with a check bit; performing Turbo encoding on the information bit sequence with the check bit to obtain a target codeword; performing minimum shift keying modulation on the target codeword to generate a first target signal; encapsulating the first target signal according to the standard dual-pulse encapsulation structure of the Link-16 data link, and then transmitting it through a macro time slot; the macro time slot includes... The Link-16 data link cascades four basic time slots; each macro time slot uses a fixed frequency; or includes: receiving a second target signal based on the macro time slots; the macro time slots include the four basic time slots cascaded in the Link-16 data link; each macro time slot uses a fixed frequency; timing synchronization of the second target signal based on the training sequences in each basic time slot to obtain a third target signal; phase offset estimation of the third target signal based on the training sequences in each basic time slot to obtain a fourth target signal; Turbo decoding of the fourth target signal based on the log-likelihood ratio to obtain a decoded bit sequence; and CRC verification of the decoded bit sequence to obtain a decision bit sequence.

[0204] When the computer program stored on the non-transitory computer-readable storage medium provided in this embodiment of the invention is executed, it implements the above-described data transmission method applied to the Link-16 data link. Its specific implementation method is consistent with the implementation method described in the aforementioned method embodiments, and can achieve the same beneficial effects, so it will not be repeated here.

[0205] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0206] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0207] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0208] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0209] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

[0210] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A data transmission method applied to a Link-16 data link, characterized in that, Applied to the sending end, the method includes: Based on the target algorithm, the source information bit sequence is CRC encoded to obtain an information bit sequence with a check bit. The information bit sequence with parity bits is Turbo encoded to obtain the target codeword; The target codeword is subjected to minimum frequency shift keying modulation to generate a first target signal; After the first target signal is encapsulated according to the standard dual-pulse encapsulation structure of the Link-16 data link, it is transmitted through a macro time slot; the macro time slot includes four basic time slots cascaded in the Link-16 data link; each macro time slot uses a fixed frequency point.

2. The data transmission method applied to the Link-16 data link according to claim 1, before performing CRC encoding on the source information bit sequence based on the target algorithm to obtain the information bit sequence with check bits, the method includes: With the goal of minimizing the relative sensitivity of the receiver, initial values ​​for symbol rate, coding efficiency, and modulation efficiency are determined. The relative sensitivity is the variable part of the receiving sensitivity; Based on the initial values ​​of the symbol rate, coding efficiency, and modulation efficiency, the number of symbols contained in the target algorithm and the training sequence in the basic time slot is determined.

3. The data transmission method applied to the Link-16 data link according to claim 2, characterized in that, The relative sensitivity is ； in, This indicates the relative sensitivity; Indicates the symbol rate; Indicates coding efficiency; Indicates modulation efficiency; This indicates the demodulation signal-to-noise ratio.

4. The data transmission method applied to the Link-16 data link according to any one of claims 1 to 3, characterized in that, The step of performing CRC encoding on the source information bit sequence using the target algorithm to obtain an information bit sequence with a check bit includes: A binary vector of length (LenBit+1) is randomly generated and used as the CRC checksum vector; the first and last elements of the binary vector are both 1. Randomly generate a binary bit sequence of the source information with a length of LenBit; Based on the CRC checksum vector, the source information bit sequence is CRC encoded to obtain the transmission sequence with added check bits; Randomly generate a binary error sequence of length (LenBit + LenCRC); LenCRC is the length of the CRC check bit vector. The received sequence is obtained by adding the transmitted sequence modulo 2 to the error sequence; The presence of errors in the received sequence is determined by CRC check, and the presence of errors is determined by comparing the source information bit sequence with the received sequence. If the verification results of the two methods are the same, the transmission sequence is determined to be the information bit sequence with the check bit.

5. A data transmission method applied to a Link-16 data link, characterized in that, Applied to the receiving end, the method includes: The second target signal is received based on a macro time slot; the second target signal is transmitted based on the method described in any one of claims 1 to 4; the macro time slot includes four basic time slots cascaded by a Link-16 data link; each macro time slot uses a fixed frequency point; Based on the training sequences in each of the basic time slots, the second target signal is synchronized in a timing manner to obtain the third target signal; Based on the training sequences in each of the basic time slots, the phase offset of the third target signal is estimated to obtain the fourth target signal; Based on the log-likelihood ratio, the fourth target signal is subjected to Turbo decoding to obtain the decoded bit sequence; Perform CRC check on the decoded bit sequence to obtain the decision bit sequence.

6. A data transmission device for use in Link-16 data links, characterized in that, include: The first encoding module is used to perform CRC encoding on the source information bit sequence based on the target algorithm to obtain an information bit sequence with a check bit. The second encoding module is used to perform Turbo encoding on the information bit sequence with parity bits to obtain the target codeword; The modulation module is used to perform minimum frequency shift keying modulation on the target codeword to generate a first target signal; The transmitting module is used to encapsulate the first target signal according to the standard dual-pulse encapsulation structure of the Link-16 data link and transmit it through a macro time slot; the macro time slot includes four basic time slots cascaded in the Link-16 data link; each macro time slot uses a fixed frequency point.

7. A data transmission device for use in Link-16 data links, characterized in that, include: The receiving module is used to receive the second target signal based on the macro time slot; The second target signal is transmitted based on the method described in any one of claims 1 to 4; the macro time slot includes four basic time slots cascaded by the Link-16 data link; each macro time slot uses a fixed frequency point; The timing synchronization module is used to synchronize the second target signal based on the training sequence in each of the basic time slots, and to obtain the third target signal. The phase bias estimation module is used to perform phase bias estimation on the third target signal based on the training sequence in each of the basic time slots to obtain the fourth target signal; The decoding module is used to perform Turbo decoding on the fourth target signal based on the log-likelihood ratio to obtain the decoded bit sequence; The verification module is used to perform CRC verification on the decoded bit sequence to obtain the decision bit sequence.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the data transmission method applied to the Link-16 data chain as described in any one of claims 1 to 4, or the steps of the data transmission method applied to the Link-16 data chain as described in claim 5.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the data transmission method applied to the Link-16 data chain as described in any one of claims 1 to 4, or the steps of the data transmission method applied to the Link-16 data chain as described in claim 5.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the data transmission method applied to the Link-16 data chain as described in any one of claims 1 to 4, or the steps of the data transmission method applied to the Link-16 data chain as described in claim 5.

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