A method and device for super-high sensitivity narrow-band wireless communication by multi-channel parallel PLL tracking demodulation

Abstract

The application relates to the technical field of wireless communication, and discloses a kind of multi-path parallel PLL tracking demodulation ultra-high sensitivity narrowband wireless communication method and device, adopt "front end common use+rear end digital branch parallel" N parallel receiving architecture, only need a set of radio frequency and ADC front end, rear end is handled by N digital PLL branch parallel, greatly reduce hardware redundancy. Through the cooperation of parallel fast capture and branch PLL tracking, a general crystal oscillator can be adapted, the frequency offset of the transmitting and receiving parties can be effectively covered, and the cost can be greatly reduced. The application realizes sensitivity better than LoRa, equivalent rate, cost and power consumption lower than LoRa, and overcomes the defects of low rate and poor stability of Sigfox, to provide a kind of high-performance, low-cost, strong robustness new physical layer communication scheme for Internet of Things.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to an ultra-high sensitivity narrowband wireless communication method and apparatus for multi-channel parallel PLL tracking and demodulation. Background Technology

[0002] With the rapid development of Internet of Things (IoT) technology, Low Power Wide Area Networks (LPWAN) have become the core infrastructure for connecting everything and realizing intelligent sensing. In production and daily life, LPWAN technology is widely used in remote automatic meter reading for smart meters (water, electricity, gas, and heat meters), environmental monitoring (air quality, water quality, temperature and humidity sensor networks), asset tracking, smart agriculture (soil moisture and crop growth monitoring), and industrial automation. In these applications, communication terminals are typically battery-powered, requiring extremely low power consumption to maintain a working life of several years or even a decade. Simultaneously, the signal propagation environment is complex; for example, smart meters are often installed in basements, deep wells, or metal-shielded pipe shafts, resulting in severe signal attenuation and placing extremely high demands on receiver sensitivity (typically requiring levels of -130dBm to -145dBm). Furthermore, many applications require moderate data rates (such as hundreds of bps to tens of kbps) to transmit relatively complete status data and firmware upgrade packages, and to operate stably in the interference-prone ISM band.

[0003] While the two mainstream LPWAN technologies, LoRa and Sigfox, are widely used in the current technology field, they each have insurmountable technical defects and cannot perfectly meet all the above requirements.

[0004] Specifically, LoRa technology employs Chirp Spread Spectrum (CSS) modulation, which enhances sensitivity by setting a high spreading factor (e.g., SF=12). Its core logic is "trading bandwidth for signal-to-noise ratio": the signal energy is dispersed across a wider spectrum, and the receiver reassembles the dispersed energy through a despreading process, thereby effectively reducing the noise floor and obtaining spreading gain.

[0005] However, this indirect approach to achieving high sensitivity has inherent flaws, including:

[0006] First, the process is complex and inherently has losses: the spreading and despreading process involves complex correlation calculations, and the overlap between subcarriers will lead to signal energy leakage and secondary superposition of noise. The actual processing gain is significantly different from the theoretical Shannon limit (usually with a loss of more than 6dB).

[0007] Second, the hardware cost is high and the power consumption is huge: In order to achieve a high spreading factor, the LoRa receiver core usually needs to perform large-scale FFT operations (such as 4096-point FFT). The chip area and dynamic power consumption consumed have become a heavy burden in low-power applications, making it difficult to implement in engineering. It also continuously calculates sub-channels that obviously have no energy, wasting computing power.

[0008] Third, there is a serious conflict between data rate and sensitivity: increasing sensitivity (increasing the spreading factor) will linearly reduce the data rate, and it is difficult to achieve both simultaneously.

[0009] Fourth, limited anti-interference capability: LoRa linear frequency hopping performance will drop sharply in strong interference or narrowband blocking scenarios;

[0010] Fifth, it has stringent requirements for crystal oscillator accuracy: frequency offset will destroy the linearity of the Chirp signal and cause the loss of orthogonality. Although this can be mitigated by auxiliary means such as low data rate optimization (LDRO), it further increases the system complexity and power consumption, and still requires a high-precision crystal oscillator to ensure stability, which increases the hardware cost.

[0011] Sigfox technology is designed specifically for scenarios with extremely low throughput and extremely low power consumption. It uses ultra-narrowband (UNB) modulation and theoretically has a simpler receiver structure. However, its drawbacks are also prominent:

[0012] First, the rate is extremely low, with each message payload being only 12 bytes, which is completely unable to meet the needs of medium-speed communication.

[0013] Secondly, it uses non-coherent demodulation and has a simple method for frequency offset processing, resulting in poor demodulation stability, especially in environments with frequency drift or Doppler shift, where performance is severely degraded.

[0014] Third, it does not incorporate frequency hopping technology, so communication will fail once the working channel is interfered with, and its anti-interference capability is extremely weak; fourth, it has a single function and a fixed hardware design, making it impossible to flexibly adjust communication parameters (such as bandwidth and rate) according to specific scenarios, and its applicable scope is narrow.

[0015] Fifth, like LoRa, Sigfox still requires a certain level of crystal oscillator accuracy to maintain demodulation performance, making it difficult to adapt to lower-cost ordinary crystal oscillators.

[0016] Therefore, those skilled in the art urgently need a novel technical solution that can be applied to complex urban environments, deep coverage scenarios, and mobile Internet of Things applications. Summary of the Invention

[0017] The core technical problem solved by this invention is that the existing technology lacks a receiver architecture and communication method that can directly achieve an extremely low-noise substrate at the physical layer, possess high-efficiency signal energy harvesting capability, flexibly adapt to different rate requirements, tolerate large frequency drift caused by low-cost ordinary crystal oscillators, and actively avoid interference. Specifically, this manifests as follows:

[0018] 1) It is impossible to achieve ultra-high sensitivity (better than -143dBm) while maintaining a moderate data rate and low-cost, low-power hardware;

[0019] 2) It cannot effectively and simply solve the problems of large frequency difference between the transmitter and receiver and time-varying frequency drift caused by the use of ordinary crystal oscillators, resulting in the narrowband receiver losing lock;

[0020] 3) It is impossible to ensure the robustness of the communication link through active frequency hopping or other methods in complex interference environments.

[0021] For those skilled in the art, overcoming the aforementioned core technical challenges can break through the "impossible triangle" of current LPWAN technology—the bottleneck that makes it difficult to simultaneously achieve ultra-high sensitivity, moderate data rate, and extremely low cost / power consumption. The purpose of solving this core technical problem is to provide a truly universal, high-performance physical layer technology for the booming IoT industry, seamlessly adaptable to various scenarios from indoor metering to wide-area coverage, thereby replacing or surpassing existing solutions such as LoRa and Sigfox.

[0022] To address the aforementioned core technical issues, this invention designs an ultra-high sensitivity narrowband wireless communication method and device using multi-channel parallel PLL tracking and demodulation. The aim is to directly achieve "narrowband noise reduction + coherent demodulation" at the physical layer, utilize a multi-channel parallel receiving architecture to cover frequency offset uncertainties, achieve precise tracking through a phase-locked loop (PLL) to collect all signal energy, and integrate frequency hopping technology to resist interference. Ultimately, under the premise of adapting to ordinary crystal oscillators, it achieves comprehensive performance that surpasses existing technologies.

[0023] To achieve the above objectives, the specific technical solution of the present invention is a method for ultra-high sensitivity narrowband wireless communication with multi-channel parallel reception, comprising the following steps:

[0024] S1. Process the received signal in a unified manner to generate a shared digital baseband signal;

[0025] S2. Capture the prefix symbol sequence of the received signal, perform time-frequency synchronization, and extract the initial frequency offset and symbol synchronization information;

[0026] S3. The shared digital baseband signal is input in parallel to N parallel demodulation branches. Each demodulation branch sets its own center frequency of local digital PLL according to the initial frequency offset and the symbol synchronization information.

[0027] S4. The local digital PLL of each demodulation branch tracks and coherently demodulates its corresponding narrowband channel and outputs the demodulated signal.

[0028] S5. Based on the energy or decision result of the demodulated signal, determine the number of activated channels and the corresponding position encoding information, and restore the original data.

[0029] Preferably, step S2 specifically includes:

[0030] Fast acquisition phase: By receiving data in parallel through N narrowband branches, the channel number corresponding to the branch with the largest energy accumulation is determined as the coarse frequency offset.

[0031] Precise synchronization stage: The precise frequency value is tracked by the digital PLL of any locking branch, and the drift effect is removed by time-domain averaging to obtain the fine frequency offset value;

[0032] Symbol synchronization: Monitor the signal amplitude changes of the locked branch. When the amplitude drops sharply, it is determined to be a symbol boundary, and symbol synchronization is completed.

[0033] Preferably, the tracking and coherent demodulation process in step S4 includes:

[0034] The input signal is down-converted, subjected to fixed-coefficient half-band filtering, and subjected to coordinate transformation to extract the phase.

[0035] Perform a differential operation on the phase to demodulate the phase difference signal;

[0036] The local digital PLL performs closed-loop tracking based on the phase difference signal and outputs a baseband signal with frequency error compensation.

[0037] Preferably, the method further includes a sending step:

[0038] Modulate the data to be transmitted;

[0039] The modulated data is mapped to the corresponding channel in N channel positions through position coding;

[0040] The carrier frequency of the transmitted signal is controlled to hop between N channel positions based on a pseudo-random frequency hopping sequence.

[0041] Preferably, the bandwidth of the narrowband channel is set to 30Hz, which is preset to be sufficient to cover the frequency drift rate of a conventional crystal oscillator.

[0042] Preferably, the number N of the demodulation branches for the N parallel reception is any positive integer between 4 and 4096, configured according to the target data rate and sensitivity requirements.

[0043] Preferably, the method can obtain the processing gain directly through narrowband filtering and coherent demodulation without using spread spectrum and despreading operations during demodulation. Alternatively, spread spectrum and despreading can be performed at the RF front end as needed. In fact, this method is compatible with LoRa.

[0044] Preferably, in step S5, recovering the original data includes simultaneously parsing a first portion of data determined by "which narrowband channels or channels are activated", and a second portion of data determined by "the modulation symbols carried on the activated channels".

[0045] Preferably, the shared digital baseband signal is a single-channel, high-data-rate broadband signal, and the N parallel demodulation branches perform parallel down-conversion and narrowband extraction on the shared digital baseband signal, which is equivalent to connecting N bandpass filters in parallel in the frequency domain.

[0046] Preferably, the theoretical sensitivity model of the method is characterized by the following formula:

[0047] ;

[0048] in, For receiver noise figure, To receive the total bandwidth, The value is related to the modulation method of the narrowband signal; if it is a single carrier, then... The value is around 4dB. If it's GMSK, then... The value is 7dB. If it is GFSK, then... The value is 10dB. This formula reflects the processing gain that can be obtained by dividing the total bandwidth equally among N parallel narrowband channels.

[0049] Preferably, the present invention also discloses an ultra-high sensitivity narrowband wireless communication device for multi-channel parallel reception, the device being used to implement the method, comprising:

[0050] The shared front-end module is used to amplify, mix, convert analog to digital and filter the received radio frequency signal to generate a shared digital baseband signal;

[0051] N parallel demodulation branches are connected to the shared front-end module, and each demodulation branch is configured for:

[0052] Receive the shared digital baseband signal;

[0053] Using a local digital PLL (phase-locked loop), coherent demodulation is performed on a narrowband channel with a specified center frequency to obtain a demodulated signal;

[0054] The synchronization correction module, connected to the N parallel demodulation branches, is used to capture the prefix symbol sequence of the received signal, extract frequency synchronization information and symbol synchronization information, and provide them to the N parallel demodulation branches respectively to correct the initial frequency deviation and symbol timing deviation of each branch.

[0055] The device is compatible with ordinary precision crystal oscillators to cover the frequency deviation between the transmitter and receiver; the bandwidth of the narrowband channel is preset to cover the drift speed of a conventional crystal oscillator.

[0056] Preferably, the shared front-end module includes:

[0057] Radio frequency circuitry, used to receive and amplify the radio frequency signal;

[0058] An analog-to-digital converter (ADC) is connected to the radio frequency circuit and is used to convert analog signals into digital signals;

[0059] A digital filtering module, connected to the ADC, is used to perform preliminary noise reduction and decimation filtering on the digital signal to generate the shared digital baseband signal.

[0060] Preferably, the apparatus further includes a frequency hopping coding transmission module, the frequency hopping coding transmission module comprising:

[0061] Frequency hopping sequence generation unit, used to generate a preset pseudo-random frequency hopping sequence;

[0062] A position coding unit is used to map the information to be transmitted to at least one of N channel positions to achieve one-time encoding. Bit position encoding;

[0063] The transmitting unit is used to transmit the modulated and position-coded signal at N channel positions by frequency hopping according to the pseudo-random frequency hopping sequence.

[0064] Preferably, the frequency hopping sequence generation unit is also used to dynamically adjust the frequency hopping interval and channel selection based on the channel interference detection results.

[0065] Preferably, the location coding unit is directly associated with the channel index of the N parallel demodulation branches, using the dimension of "which branch(s) are activated" to carry information.

[0066] Preferably, each of the N parallel demodulation branches includes:

[0067] A digital mixer unit is used to downconvert the shared digital baseband signal to zero intermediate frequency;

[0068] A fixed-coefficient half-band filter unit is used to perform narrowband filtering on the down-converted signal to suppress out-of-band noise.

[0069] The coordinate transformation unit is used to transform the filtered signal from orthogonal coordinates to polar coordinates in order to extract phase information;

[0070] A phase differential unit is used to perform differential operations on the phase information to recover the original frequency or phase modulation information;

[0071] The residual frequency difference removal unit, as part of the local digital PLL, is used to track and remove residual time-varying frequency deviations in the signal;

[0072] The symbol synchronization decision unit is used to determine the symbol boundary and make the best decision on the demodulated signal based on the symbol synchronization information provided by the synchronization correction module.

[0073] Preferably, the present invention also discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method.

[0074] Compared with existing technologies (such as LoRa, Sigfox, and known parallel reception schemes), the method and apparatus of the present invention have the following non-obvious but substantial technical features:

[0075] First, this invention adopts a true N-way parallel receiving architecture of "shared front-end + parallel back-end digital branches," which differs from "single-circuit cyclic analog parallel" (which is essentially still serial processing and has a rate bottleneck) and "N sets of complete independent receiving circuits in parallel" (with huge hardware redundancy). This invention proposes that the front-end modules such as the RF circuit, ADC, and digital filtering of the receiving end (Rx) are completely shared, while only the back-end baseband processing branches such as digital mixing, filtering, demodulation, and synchronization adopt an N-way physical parallel design. This architecture of "shared bottleneck front-end and parallel low-complexity back-end" achieves true parallel reception with the lowest hardware and power consumption cost under the same degree of parallelism, which is not easily thought of by those skilled in the art under conventional thinking (either serial or full copy).

[0076] Secondly, this invention employs a frequency offset coverage mechanism based on narrowband PLL tracking demodulation and parallel fast acquisition. In existing technologies, solving crystal oscillator frequency offset either relies on high-precision crystal oscillators (high cost) or uses spread spectrum technology for indirect tolerance (complex process and loss). This invention coordinates the front-end multi-channel parallel fast acquisition (coarse frequency offset estimation, determining sub-channel number), the independent digital PLL ring in each branch of the back-end (fine frequency offset tracking and removal of residual frequency difference), and a shared synchronization correction module. The coarse acquisition covers the initial error of the crystal oscillator, the PLL ring dynamically tracks frequency drift, and the synchronization correction module uniformly coordinates symbol boundaries and frequency hopping timing. This combination, in a coordinated, closed-loop manner, enables the system to tolerate and correct time-varying transmit and receive frequency differences caused by using ordinary crystal oscillators (e.g., 20ppm), without the need for high-precision crystal oscillators or complex spread spectrum despreading processes. Its innovation lies in decomposing frequency offset processing into two levels: "channel selection (coarse)" and "PLL tracking (fine)," and utilizing hardware parallelism to achieve optimal allocation of time and resources between the two.

[0077] Finally, this invention achieves a combination of rate enhancement based on position coding and extreme noise reduction through fixed-coefficient narrowband filtering. LoRa achieves sensitivity through a high spreading factor but sacrifices rate; this invention explicitly employs position coding: mapping information to the dimension of "which" channel among N parallel branches is activated, in a single transmission. Bit information; this allows the data rate to be no longer limited solely by the symbol rate, but rather proportional to the logarithm of the parallelism N, even in extremely narrow physical bandwidths (as low as 30Hz). This idea of ​​carrying information in "frequency position" rather than simply relying on symbol modulation, combined with a hardware-friendly and predictable ultra-narrowband filter using a fixed-coefficient half-band filter, works together from two orthogonal dimensions (energy concentration and information density) to achieve a balance between ultra-high sensitivity and moderate speed. In contrast, LoRa increases the spreading factor (lengthens the symbol time) to gain sensitivity, resulting in a decrease in speed. The two approaches are opposite, and the solution of this invention is not obvious.

[0078] The ultra-high sensitivity narrowband wireless communication method and apparatus for multi-channel parallel PLL tracking demodulation reception disclosed in this invention has the following significant advantages compared with existing LoRa and Sigfox technologies:

[0079] 1. This invention achieves a comprehensive performance improvement. By adopting a physical layer scheme of "narrowband coherent demodulation + parallel PLL tracking", the actual sensitivity of this invention can reach approximately -145dBm, which is better than LoRa's -141.5dBm and Sigfox's level. At the same time, through position coding technology, the data rate can be flexibly adjusted according to the number of parallel paths N. While achieving high sensitivity, it maintains a moderate rate that is comparable to or better than LoRa, completely breaking the bottleneck of the mutual restriction between rate and sensitivity.

[0080] 2. This invention achieves a significant reduction in hardware cost and power consumption. First, through a "shared front-end + parallel back-end" architecture, it avoids redundancy in N complete receiving circuits. Second, and most importantly, through the synergistic effect of the synchronization correction module and the digital PLL ring within the branch, this invention successfully adapts to ordinary crystal oscillators (e.g., 20ppm), eliminating the need for high-precision crystal oscillators and greatly reducing material costs. For example, compared to the 4096-point FFT processing unit required for LoRa, the parallel PLL branch of this invention has significant advantages in chip area and power consumption, making it possible to implement medium-to-high speed, ultra-high sensitivity communication on low-cost, low-power IoT devices. It should be noted that FFT is a general-purpose IP without scenario-based optimization. In actual implementation, most channels are without energy, and ordinary FFT does not stop calculating invalid channels based on the scenario, leading to the problem of wasted computing resources. This invention, however, can stop calculating sub-channels without energy during implementation, achieving the goal of saving power consumption.

[0081] 3. This invention has strong environmental adaptability and robustness. It integrates frequency hopping technology and generates pseudo-random frequency hopping sequences through a frequency hopping coding and transmission module, which can actively avoid interference channels and has anti-interference capabilities far exceeding those of LoRa and Sigfox, which do not use frequency hopping. At the same time, its PLL-based tracking demodulation mechanism gives it natural resistance to frequency drift and Doppler shift. Combined with a 30Hz narrowband bandwidth design that covers the crystal oscillator drift speed, it can maintain a stable and reliable communication link whether it is buried deep underground, moving rapidly, or in an industrial environment with strong interference.

[0082] 4. The architecture of this invention is flexible and applicable to a wide range of scenarios. The number of parallel paths N (e.g., 4-4096) and the narrowband bandwidth of this invention can be flexibly adjusted as design parameters. This allows the technical solution to achieve the optimal balance between power consumption, speed and sensitivity, just like a Swiss Army knife, according to specific application requirements. It can be perfectly adapted to both extremely low-power sensor status reporting (small N value) and smart meter firmware upgrades that require medium speed and deep coverage (large N value), and its application prospects are extremely broad. Attached Figure Description

[0083] Figure 1 This is a flowchart of the method described in this invention;

[0084] Figure 2 This is a schematic diagram of the demodulation principle of the multi-channel system described in this invention;

[0085] Figure 3 This is a schematic diagram of the demodulation principle of a single Rx channel as described in this invention;

[0086] Figure 4This is a schematic diagram of the structure of the device described in this invention;

[0087] Figure 5 This is a schematic diagram of the frequency hopping coding transmission module described in this invention. Detailed Implementation

[0088] The features and embodiments of the present invention will now be described in detail with reference to the accompanying drawings;

[0089] In the technical solution of this invention, true N-channel parallel reception refers to the receiver architecture having N physically independent and parallel processing channels for the baseband processing section (especially the demodulation-related branch). This is mainly used to distinguish it from "pseudo-parallelism" achieved through time-division multiplexing or cyclic analog switching. True N-channel parallel reception is the core architectural innovation of this invention. It achieves true parallel demodulation, making it possible to simultaneously monitor N narrowband channels, and is the foundation for achieving high data rates (through position coding) and fast frequency acquisition (fast acquisition).

[0090] In the technical solution of this invention, phase-locked loop (PLL) tracking demodulation refers to each demodulation branch of the receiver containing a digital PLL. This PLL can dynamically lock the carrier frequency and phase of the input signal, achieving coherent demodulation of the signal, and can continuously track the signal even if there is frequency drift. PLL tracking demodulation is a core technical means to achieve ultra-high sensitivity. Coherent demodulation has a theoretical gain of about 3dB compared to incoherent demodulation. The tracking capability of the PLL allows the system to use a common crystal oscillator because the PLL can compensate for the frequency drift of the crystal oscillator in real time.

[0091] In the technical solution of this invention, the shared front-end + parallel back-end architecture is a hybrid receiver architecture. There is only one set of "front-end" modules for processing high-bandwidth, high-data-rate signals, such as RF and analog-to-digital converters (ADCs), serving all parallel branches. Meanwhile, there are N sets of "back-end" demodulation branches for processing low-bandwidth, narrow-band signals, operating in parallel. This architecture achieves N-channel parallel reception with minimal hardware and power consumption. Without this feature, achieving N-channel parallelism would require N times the amount of front-end hardware, which is unacceptable in terms of cost and power consumption. It is crucial to the engineering feasibility of this invention.

[0092] In the technical solution of this invention, the fixed-coefficient half-band filter is a digital filter whose coefficients are pre-calculated and fixed (non-adaptive), and the filter type is a half-band filter. It is used to efficiently extract the required ultra-narrowband signal from a relatively wide shared digital baseband signal in each demodulation branch. The fixed-coefficient half-band filter achieves the core function of "narrowband noise reduction." The fixed coefficients make its hardware implementation extremely simple and its power consumption extremely low; the characteristics of the half-band filter make it extremely efficient in decimation (reducing the sampling rate), which is key to achieving ultra-narrowband (e.g., 30Hz).

[0093] In the technical solution of this invention, positional coding is an information mapping method that uses spatial positional information—"which one or more channels are activated among N parallel narrowband channels"—to carry bit information, enabling encoding in one operation. Bit-based positional coding solves the problem of the contradiction between high sensitivity and high data rate. In extremely narrow bandwidths, the symbol rate is very low, but by increasing the number of parallel channels N, the data rate can be increased many times over by utilizing the positional dimension without sacrificing the narrowband characteristics of each signal.

[0094] In the technical solution of this invention, the time-frequency synchronization coordination mechanism is a frequency and time synchronization scheme composed of three parts: "parallel fast acquisition (determining coarse frequency offset / channel number)", "PLL tracking within each branch (fine frequency offset correction)", and "shared synchronization correction module (unifying symbol boundaries)". This time-frequency synchronization coordination mechanism provides system-level protection for ordinary crystal oscillators. Coarse acquisition solves the large-scale initial error of the crystal oscillator, PLL tracking solves time-varying frequency drift, and the shared module ensures the synchronization of all branches. The collaboration of these three components enables the entire system to operate stably.

[0095] refer to Figure 1 This document illustrates a schematic flowchart of an ultra-high sensitivity narrowband wireless communication method with multi-channel parallel reception according to one or more embodiments of this application. The method is applied to low-power wide-area Internet of Things (LPWAN) devices, such as smart water meters, environmental monitoring sensors, or asset tracking tags, which are typically battery-powered and require stable operation in complex environments with deep coverage and strong interference. The method includes the following steps: S1, generating a shared digital baseband signal; S2, performing time-frequency synchronization; S3, parallel input to N demodulation branches; S4, performing tracking and coherent demodulation; S5, recovering the original data.

[0096] In one or more embodiments, step S1 utilizes the shared front-end module of the receiver to uniformly process the radio frequency signal received by the antenna; specifically, the radio frequency circuit performs low-noise amplification and down-conversion on the signal, the analog-to-digital converter (ADC) converts it into a digital intermediate frequency signal, and then the digital filtering module performs preliminary noise reduction and extraction, finally generating a shared digital baseband signal that contains all the information within the entire receiving bandwidth.

[0097] In one or more embodiments, step S2 captures the prefix symbol sequence of the received signal through a synchronization correction module; this module is configured to:

[0098] First, by receiving and accumulating energy in parallel through N narrowband branches, the channel number corresponding to the branch with the largest energy accumulation is determined as the coarse frequency offset, thereby quickly locking the approximate frequency range of the transmitted signal.

[0099] Then, any successfully locked branch tracks a precise frequency value through its internal digital PLL, and performs time-domain averaging to remove short-time drift effects, resulting in a high-precision fine frequency offset value.

[0100] Finally, by monitoring the signal amplitude changes of the locked branch, when a sudden drop in amplitude is detected, it is determined to be a symbol boundary, thereby completing symbol synchronization.

[0101] In one or more embodiments, step S3 inputs the shared digital baseband signal in parallel to N parallel demodulation branches. Each demodulation branch sets its own local digital PLL center frequency according to the initial frequency offset and symbol synchronization information provided by the synchronization correction module in step S2; for example, the PLL of the i-th branch will be set to be locked to the center frequency of the i-th narrowband channel. superior.

[0102] In one or more embodiments, in step S4, the local digital PLL of each demodulation branch tracks and coherently demodulates the narrowband channel corresponding to its center frequency, such as... Figure 2 As shown, N channels operate in parallel, with overlapping bandwidths to ensure signal capture without omission. For each channel, as... Figure 3 The demodulation block diagram of a single Rx channel shown includes the following processes: a digital mixer down-converts the input shared signal to zero intermediate frequency; a fixed-coefficient half-band filter performs narrowband filtering on the down-converted signal to suppress out-of-band noise and achieve extreme noise reduction; a coordinate transformation unit (CORDIC) transforms the orthogonal signal to polar coordinates to extract phase information; a phase differential unit performs differential operations on the phase to recover the original modulation information; and a residual frequency difference removal unit, as part of the local digital PLL, continuously tracks and removes residual time-varying frequency deviations in the signal to achieve coherent demodulation and outputs a baseband signal compensated for frequency errors.

[0103] It should be noted that the digital mixing process is consistent with the FFT process, both of which refine from coarse to fine step by step, and the refinement process does not require full calculation, which can effectively reduce the computational energy consumption.

[0104] In one or more embodiments, step S5 determines the number of activated channels and their corresponding position coding information based on the energy or decision result of the demodulated signal, and recovers the original data. Specifically, recovering the original data includes simultaneously parsing a first portion of data (position coding data) determined by "which narrowband channels are activated", and a second portion of data (conventional modulation data) determined by "the modulation symbols carried on the activated channels".

[0105] In one or more embodiments, the method further includes a transmission step, in which the transmitting end modulates the data to be transmitted; then, the modulated data is mapped to the corresponding channel among N channel positions by a position coding unit, realizing one-time transmission. Bit encoding; finally, based on a pseudo-random frequency hopping sequence, the carrier frequency of the transmitted signal is controlled to hop between N channel positions, thereby actively avoiding interference.

[0106] In one or more embodiments, the coefficients of the fixed-coefficient half-band filter unit in step S4 are hardware-fixed according to a preset narrowband bandwidth (e.g., 30Hz); the bandwidth value of the narrowband channel is preset to be sufficient to cover the maximum frequency drift rate of a conventional crystal oscillator (e.g., 20ppm accuracy) within its temperature and lifespan range, for example, set to 30Hz; this "virtual-real combination" design achieves extreme sensitivity through an extremely narrow bandwidth while reserving sufficient bandwidth tolerance to adapt to low-cost ordinary crystal oscillators.

[0107] In one or more embodiments, the theoretical sensitivity model of the N-channel parallel reception implemented by this method is characterized by the following formula:

[0108] ;

[0109] in, This represents the thermal noise power spectral density at 290K, in dBm / Hz. This is the receiver noise figure (e.g., 3dB). For the total receive bandwidth (e.g., 125kHz). The value is related to the modulation method; if it is single-carrier modulation, then... The value is 4dB. If it is GFSK (Gaussian Frequency-Shift Keying) modulation, then The value is 10dB. When When = 4096, 10*log 10 (125000 / 4096) ≈ 14.8dB, which means that by dividing the total bandwidth equally among 4096 parallel narrowband channels, a processing gain of about 14.8dB can be obtained; this formula clearly reflects the physical essence of the "narrowband diversity" method to obtain ultra-high sensitivity.

[0110] In one or more embodiments, to ensure the reliability of time-frequency synchronization in frequency-hopping scenarios, the synchronization correction module executes an atomic process of "fast acquisition-fine synchronization-symbol synchronization" when capturing the prefix symbol sequence; this process does not rely on the intervention of an external operating system, but is completed in one go by the hardware state machine. Specifically, it includes:

[0111] First, identify the branch with the highest energy during the rapid acquisition phase;

[0112] Then, after the PLL of this branch enters the locked state, its frequency control word is immediately read and broadcast to all parallel branches;

[0113] Finally, the amplitude drop points are continuously monitored for several symbol periods to confirm the symbol boundaries. This series of operations is performed as an uninterrupted sequence, ensuring that the receiver can quickly and accurately re-establish synchronization when the channel changes rapidly.

[0114] In one or more embodiments, in response to the failure of all N parallel demodulation branches to successfully lock or demodulate the differential signal within a preset timeout period (i.e., an abnormal condition), the synchronization correction module will trigger an error handling process. This error handling process includes at least one of the following operations: reporting the communication failure to the higher-layer protocol stack, recording the current channel quality log, and resetting the state of some demodulation branches and attempting to re-acquire the signal.

[0115] In one or more embodiments, this method achieves ultra-high sensitivity reception based on a "shared front-end + parallel back-end" architecture. Compared with existing technologies, it successfully adapts to ordinary crystal oscillators through a collaborative mechanism of parallel fast acquisition and PLL tracking, solving the core problem of narrowband receiver lock-up caused by frequency drift; by combining position coding and ultra-narrowband filtering, it breaks the traditional constraint between sensitivity and data rate. This significantly improves communication stability in complex environments and greatly reduces the hardware cost of IoT terminals.

[0116] refer to Figure 4 This document illustrates a schematic structural block diagram of an ultra-high sensitivity narrowband wireless communication device with multi-channel parallel reception according to one or more embodiments of this application. The device is applied in low-power, high-sensitivity Internet of Things (IoT) communication terminals, such as wireless meter reading modules that require reliable data transmission in basements. The device includes a shared front-end module, N parallel demodulation branches, and a synchronization correction module.

[0117] In one or more embodiments, the shared front-end module is used to uniformly process the radio frequency signals received by the antenna to generate a shared digital baseband signal. Specifically, the module includes:

[0118] Radio frequency circuitry, used to receive and amplify the radio frequency signal;

[0119] An analog-to-digital converter (ADC), connected to the radio frequency circuit, is used to convert analog signals into digital signals; and

[0120] A digital filtering module, connected to the ADC, is used to perform preliminary noise reduction and decimation filtering on the digital signal, and output a single-channel, high-data-rate broadband shared digital baseband signal.

[0121] In one or more embodiments, the N parallel demodulation branches are all connected to the output of the shared front-end module. Each demodulation branch is configured to: receive the shared digital baseband signal; and use its local digital phase-locked loop (PLL) to coherently demodulate the narrowband channel at a specified center frequency to obtain a demodulated signal. These branches operate physically in parallel, forming a dense narrowband receiving network.

[0122] In one or more embodiments, the synchronization correction module is connected to the N parallel demodulation branches and is used to capture the prefix symbol sequence of the received signal, extract frequency synchronization information and symbol synchronization information, and provide them to the N parallel demodulation branches respectively to correct the initial frequency deviation and symbol timing deviation of each branch. This module is the core of realizing "parallel fast acquisition" and global synchronization. It enables the entire device to be compatible with ordinary precision crystal oscillators (such as 20ppm) and effectively covers the frequency deviation caused by the inaccuracy of the crystal oscillator between the transmitter and receiver.

[0123] In one or more embodiments, such as Figure 4 and Figure 5 As shown, the device further includes a frequency hopping coding transmission module. The frequency hopping coding transmission module includes: a frequency hopping sequence generation unit, used to generate a preset pseudo-random frequency hopping sequence, and which can dynamically adjust the frequency hopping interval and channel selection according to the channel interference detection result; and a position coding unit, used to map the information to be transmitted to at least one of N channel positions to achieve one-time frequency hopping coding transmission. The bit position encoding unit is directly associated with the channel index of the N parallel demodulation branches; the transmission unit is used to transmit the modulated and position-coded signal at N channel positions by frequency hopping according to the pseudo-random frequency hopping sequence.

[0124] In one or more embodiments, such as Figure 3 and Figure 4 As shown, each of the N parallel demodulation branches includes a series of tightly coupled signal processing units. These include:

[0125] A digital mixer unit is used to downconvert the shared digital baseband signal to zero intermediate frequency;

[0126] The fixed-coefficient half-band filter unit is used to perform narrowband filtering on the down-converted signal. Its coefficients are fixed in hardware and do not require dynamic calculation, thus suppressing out-of-band noise with extremely low power consumption.

[0127] The coordinate transformation unit is used to transform the filtered signal from orthogonal coordinates to polar coordinates in order to extract phase information;

[0128] A phase difference unit is used to perform differential operations on the phase information to demodulate the original phase difference signal;

[0129] The residual frequency difference removal unit, as part of the local digital PLL, is used to track and remove residual time-varying frequency deviations in the signal, which is the key to achieving coherent demodulation and obtaining PLL processing gain.

[0130] The symbol synchronization decision unit is used to determine the symbol boundary and make the best decision on the demodulated signal based on the symbol synchronization information provided by the synchronization correction module.

[0131] In one or more embodiments, the synchronization correction module and the residual frequency difference removal unit in each demodulation branch form a multi-level frequency tracking loop. During operation, the synchronization correction module performs "coarse synchronization": it quickly compares the energy accumulation of N parallel branches over several symbol periods and uses the index of the branch with the highest energy as a coarse frequency offset estimate. Subsequently, the module triggers the residual frequency difference removal unit of the corresponding branch, activating its internal PLL for "fine synchronization." This PLL uses a second-order loop filter, capable of simultaneously tracking frequency steps and frequency ramps. Once the PLL is locked, its calculated precise frequency offset value is fed back to the synchronization correction module, which then broadcasts it to all parallel branches to compensate for the initial frequency deviation of each branch.

[0132] In one or more embodiments, to ensure that the receiver can quickly establish synchronization at the beginning of each frequency hopping time slot in frequency hopping mode, the synchronization correction module and the N parallel demodulation branches are configured to perform a hardware-level "fast acquisition-relock" atomic operation. At the beginning of each new frequency hopping time slot, the synchronization correction module immediately presets the PLL center frequency of all branches based on the frequency offset estimate at the end of the previous time slot. Simultaneously, it no longer performs a full energy scan, but only performs energy detection on a few branches near the preset frequency. Once a valid signal is detected, the PLL of the corresponding branch is immediately switched to tracking mode. This process is completed within microseconds, ensuring the continuity of frequency hopping communication.

[0133] In one or more embodiments, in response to the synchronization correction module failing to detect valid signal energy on any preset branch during the frequency hopping protection period (abnormal condition), the module will determine that synchronization has been lost and trigger an error handling procedure. This procedure is executed by the state machine within the synchronization correction module and specifically includes: interrupting the current reception operation, reporting the "synchronization loss" error to the upper-level controller, and automatically switching to the "full-band scanning" mode to attempt to reacquire the signal.

[0134] In one or more embodiments, this device achieves true N-channel parallel reception with extremely low hardware redundancy. It successfully solves the problems of either huge hardware overhead (full parallelism) or low reception efficiency (time-division analog parallelism) in the prior art. In particular, through the multi-level synchronization mechanism of "parallel fast acquisition + branch PLL tracking", the entire device can operate stably with ordinary crystal oscillators. This is a fundamental improvement over the design of existing LPWAN receivers and greatly reduces system costs.

[0135] refer to Figure 1 and Figure 4 This application also provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor (e.g., a baseband processor that may be integrated within the device), performs the steps described in the method or any combination thereof.

[0136] In one or more embodiments, the computer-readable storage medium may be a non-volatile memory, such as Flash memory, EEPROM, or ferroelectric memory (FRAM), which is integrated within the Internet of Things (IoT) communication chip. When the chip is powered on, its internal processor core reads and executes the computer program from the storage medium.

[0137] In one or more embodiments, when a computer program is executed, the processor is configured to perform an atomic synchronization process of "fast capture-fine synchronization-symbol synchronization":

[0138] First, control N parallel demodulation branches to perform energy integration, and use a comparator to find the channel corresponding to the maximum energy value to obtain the coarse frequency offset;

[0139] Then, the PLL of the channel is turned on, and the stable frequency value output after PLL locking is used as the fine frequency offset; finally, the symbol boundary is locked by detecting the amplitude transition edge.

[0140] In one or more embodiments, the processor utilizes hardware acceleration units (such as CORDIC coprocessors and digital PLL hardware logic) within each demodulation branch to perform low-power phase extraction and tracking demodulation, rather than performing complex FFT or related operations in software; this “hardware-software combined” execution method allows the program to run at extremely low clock frequencies, thereby significantly reducing overall power consumption.

[0141] In one or more embodiments, by running a computer program in the storage medium, IoT terminal devices can achieve ultra-high sensitivity and anti-interference capabilities that surpass existing LoRa and Sigfox technologies in a low-cost and low-power manner; the storage medium, as a carrier of software, enables the technical solutions of this application to be easily burned, copied and deployed to a large number of IoT devices, and has extremely high industrial application value.

[0142] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts thereof embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A method for ultra-high sensitivity narrowband wireless communication with multi-channel parallel reception, characterized in that, Includes the following steps: S1. Process the received signal in a unified manner to generate a shared digital baseband signal; S2. Capture the prefix symbol sequence of the received signal, perform time-frequency synchronization, and extract the initial frequency offset and symbol synchronization information; S3. The shared digital baseband signal is input in parallel to N parallel demodulation branches. Each parallel demodulation branch sets its own center frequency of local digital PLL according to the initial frequency offset and the symbol synchronization information. S4. The local digital PLL of each demodulation branch tracks and coherently demodulates its corresponding narrowband channel and outputs the demodulated signal. S5. Based on the energy or decision result of the demodulated signal, determine the number of activated channels and the corresponding position encoding information, and restore the original data.

2. The method according to claim 1, characterized in that, Step S2 specifically includes: Fast acquisition phase: By receiving data in parallel through N narrowband branches, the channel number corresponding to the branch with the largest energy accumulation is determined as the coarse frequency offset. Precise synchronization stage: The precise frequency value is tracked by the digital PLL of any locking branch, and the drift effect is removed by time-domain averaging to obtain the fine frequency offset value; Symbol synchronization: Monitor the signal amplitude changes of the locked branch. When the amplitude drops sharply, it is determined to be a symbol boundary, and symbol synchronization is completed.

3. The method according to claim 1, characterized in that, The tracking and coherent demodulation process in step S4 includes: The input signal is down-converted, subjected to fixed-coefficient half-band filtering, and subjected to coordinate transformation to extract the phase. Perform a differential operation on the phase to demodulate the phase difference signal; The local digital PLL performs closed-loop tracking based on the phase difference signal and outputs a baseband signal with frequency error compensation.

4. The method according to claim 1, characterized in that, It also includes the sending step: Modulate the data to be transmitted; The modulated data is mapped to the corresponding channel in N channel positions through position coding; The carrier frequency of the transmitted signal is controlled to hop between N channel positions based on a pseudo-random frequency hopping sequence.

5. The method according to claim 1, characterized in that, The method described above can directly obtain processing gain through narrowband filtering and coherent demodulation during the demodulation process.

6. The method according to claim 1, characterized in that, The recovery of the original data in step S5 includes simultaneously parsing the first part of the data determined by "which narrowband channels or channels are activated", and the second part of the data determined by "the modulation symbols carried on the activated channels".

7. A multi-channel parallel reception ultra-high sensitivity narrowband wireless communication device, the device being used to implement the method as described in any one of claims 1 to 6, characterized in that, include: The shared front-end module is used to amplify, mix, convert analog to digital and filter the received radio frequency signal to generate a shared digital baseband signal; N parallel demodulation branches are connected to the shared front-end module, and each demodulation branch is configured for: Receive the shared digital baseband signal; Using a local digital PLL, coherent demodulation is performed on a narrowband channel with a specified center frequency to obtain a demodulated signal; The synchronization correction module, connected to the N parallel demodulation branches, is used to capture the prefix symbol sequence of the received signal, extract frequency synchronization information and symbol synchronization information, and provide them to the N parallel demodulation branches respectively to correct the initial frequency deviation and symbol timing deviation of each branch. The device is compatible with ordinary precision crystal oscillators to cover the frequency deviation between the transmitter and receiver; the bandwidth of the narrowband channel is preset to cover the drift speed of a conventional crystal oscillator.

8. The apparatus according to claim 7, characterized in that, It also includes a frequency hopping coding transmission module, which includes: Frequency hopping sequence generation unit, used to generate a preset pseudo-random frequency hopping sequence; A position coding unit is used to map the information to be transmitted to at least one of N channel positions to achieve one-time encoding. Bit position encoding; The transmitting unit is used to transmit the modulated and position-coded signal at N channel positions by frequency hopping according to the pseudo-random frequency hopping sequence.

9. The apparatus according to claim 7, characterized in that, Each of the N parallel demodulation branches includes: A digital mixer unit is used to downconvert the shared digital baseband signal to zero intermediate frequency; A fixed-coefficient half-band filter unit is used to perform narrowband filtering on the down-converted signal to suppress out-of-band noise. The coordinate transformation unit is used to transform the filtered signal from orthogonal coordinates to polar coordinates in order to extract phase information; A phase differential unit is used to perform differential operations on the phase information to recover the original frequency or phase modulation information; The residual frequency difference removal unit, as part of the local digital PLL, is used to track and remove residual time-varying frequency deviations in the signal; The symbol synchronization decision unit is used to determine the symbol boundary and make the best decision on the demodulated signal based on the symbol synchronization information provided by the synchronization correction module.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the method as described in any one of claims 1 to 6.

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