An ultra-wideband adaptive equalizer with controllable gain of all frequency points and a regulating method thereof
By introducing a limiting amplifier positive feedback loop and a multi-bandpass amplifier into the adaptive equalizer, the problem of poor performance under wide bandwidth and high gain is solved, achieving a balance between high-frequency and low-frequency performance and stable transmission of DC unbalanced data, which is suitable for digital communication systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHENGDU CORPRO TECH CO LTD
- Filing Date
- 2026-05-18
- Publication Date
- 2026-07-21
AI Technical Summary
Existing adaptive equalizers have poor overall performance under wide bandwidth and high gain conditions and cannot transmit DC unbalanced data for long periods of time, and cannot simultaneously take into account high-frequency and low-frequency performance.
A full-frequency gain controllable ultrawideband adaptive equalizer was designed. It employs a limiting amplifier with a positive feedback loop, a cascaded CTLE circuit, and multiple bandpass amplifiers. The gain and bandwidth are adjusted through an energy comparator and a digital control module to suppress reflections and interference at low frequencies with high gain, and to transmit DC unbalanced data.
It achieves a balance between high-frequency and low-frequency performance over a wide bandwidth, can transmit DC unbalanced data for extended periods, has a simple structure and is easy to adjust, and is suitable for digital communication systems in various scenarios.
Smart Images
Figure CN122437750A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of equalizer adjustment technology, and more specifically, to an ultra-wideband adaptive equalizer with controllable gain across all frequency points and its adjustment method. Background Technology
[0002] In digital communication systems, signal transmission through finite bandwidth channels can suffer from inter-symbol interference (ISI) due to the high-frequency attenuation characteristics of the physical medium. This manifests as overlap of time-domain energy between adjacent symbols, leading to distortion in the received signal amplitude and pulse width. This distortion significantly degrades the system's bit error rate performance when the transmission rate approaches the Nyquist limit. To address this issue, receivers typically employ high-frequency gain-adjustable equalizers to compensate for channel attenuation. However, because actual channel parameters exhibit time-varying characteristics (such as changes in cable characteristics due to temperature drift or impedance mismatch caused by connector aging), fixed-parameter equalization schemes struggle to maintain optimal compensation. Therefore, an adaptive mechanism with dynamic tracking capabilities is necessary.
[0003] Existing adaptive equalizer architectures based on energy detection primarily focus on high-frequency gain compensation for narrow-band signals. However, as demand increases, the frequency range of equalizer applications is widening, typically requiring equally high gain for both low and high frequencies. When a signal passes through a channel, low-frequency attenuation is significantly less than high-frequency attenuation, necessitating a longer channel length for low-speed signals compared to high-speed signals using the same chip. For existing adaptive equalizer architectures, to increase low-frequency bandwidth with a wide frequency range, the equalizer can only shift the system zero point towards lower frequencies. While this increases low-frequency gain, it also further amplifies high-frequency gain. This results in the equalizer amplifying high-frequency reflections and interference while compensating for low-frequency signal attenuation. Therefore, existing adaptive equalizers cannot simultaneously achieve high-frequency and low-frequency performance for wide-band, high-gain applications. Furthermore, for most baseband transmission systems, physical layer channel coding ensures DC-balanced data streams. However, for some applications, the transmitter coding does not guarantee DC balance, potentially mixing DC-unbalanced data within the DC-balanced data encoding. For example, SDI signals may exhibit severe DC imbalance for a period of time, which is generally referred to as pathological code. In general adaptive equalizers, the limiting amplifier needs to use AC coupling. This limiting amplifier, which suppresses low-frequency gain, cannot transmit DC unbalanced data for a long time.
[0004] Therefore, it is necessary to improve the equalizer and its adjustment method to overcome the shortcomings of the existing adaptive equalizer, which has poor overall performance and cannot transmit DC unbalanced data for a long time when applied to wide bandwidth and high gain. Summary of the Invention
[0005] The purpose of this invention is to provide an ultra-wideband adaptive equalizer with controllable gain across all frequency points and its adjustment method, which improves the shortcomings of existing adaptive equalizers in terms of poor overall performance and inability to transmit DC unbalanced data for extended periods when applied to wide bandwidth and high gain conditions.
[0006] This invention is achieved through the following technical solution: A full-frequency gain controllable ultrawideband adaptive equalizer includes an equalizer, a limiting amplifier, an energy comparator, a digital control module, and multiple bandpass amplifiers, wherein the limiting amplifier has a positive feedback loop. The positive output terminal of the equalizer is connected to the positive input terminal of the limiting amplifier, the positive input terminal of the first bandpass amplifier, and the positive input terminal of the second bandpass amplifier; the negative output terminal of the equalizer is connected to the negative input terminal of the limiting amplifier, the negative input terminal of the first bandpass amplifier, and the negative input terminal of the second bandpass amplifier. The positive and negative output terminals of the limiting amplifier are connected to the positive and negative input terminals of the third bandpass amplifier, respectively, and are also the positive and negative output terminals of the ultra-wideband adaptive equalizer. The outputs of the first bandpass amplifier, the second bandpass amplifier, and the third bandpass amplifier are respectively connected to the three inputs of the energy comparator. The output of the energy comparator is connected to the input of the digital control module, which is used to adjust the bandwidth of the limiting amplifier and multiple bandpass amplifiers according to the output of the energy comparator.
[0007] Preferably, the equalizer includes a cascaded four-stage CTLE circuit.
[0008] Preferably, the CTLE circuit includes multiple resistors, multiple transistors, a first output capacitor array, a second output capacitor array, a source degradation capacitor array, a first follower bias current array, a second follower bias current array, and multiple bias currents. The first terminal of the first resistor, the first terminal of the second resistor, the collector of the third transistor, and the collector of the fourth transistor are connected to a DC source. The base of the third transistor is connected to the second terminal of the first resistor and the collector of the first transistor, and the emitter of the first transistor is grounded through the first bias current. The base of the fourth transistor is connected to the second terminal of the second resistor and the collector of the second transistor, and the emitter of the second transistor is grounded through the second bias current. The emitter of the third transistor is the negative output terminal of the CTLE circuit and is connected to the first follower bias current array; the emitter of the fourth transistor is the positive output terminal of the CTLE circuit and is connected to the second follower bias current array. The second end of the first resistor is connected to the first output capacitor array, and the second end of the second resistor is connected to the second output capacitor array. The base of the first transistor is the positive input terminal of the CTLE circuit, and the base of the second transistor is the negative input terminal of the CTLE circuit. There is a third resistor and a source degradation capacitor array between the emitter of the first transistor and the emitter of the second transistor.
[0009] Preferably, the first output capacitor array and the second output capacitor array have the same structure, including P groups of parallel output capacitor branches, and the output capacitor branches include capacitors and switches; In the first output capacitor array, the first end of the second capacitor is connected to the second end of the first resistor, the second end of the second capacitor is connected to the first end of the third switch, and the second end of the third switch is grounded. In the second output capacitor array, the first end of the second capacitor is connected to the second end of the second resistor, the second end of the second capacitor is connected to the first end of the switch, and the second end of the third switch is grounded.
[0010] Preferably, the first follower bias current array and the second follower bias current array have the same structure, including M groups of parallel bias current branches, and the bias current branches include switches and bias currents. In the first follower bias current array, the first terminal of the fourth switch is connected to the emitter of the third transistor, the second terminal of the fourth switch is connected to the input terminal of the third bias current, and the output terminal of the third bias current is grounded. In the second follower bias current array, the first terminal of the fourth switch is connected to the emitter of the fourth transistor, the second terminal of the fourth switch is connected to the input terminal of the bias current, and the output terminal of the third bias current is grounded.
[0011] Preferably, the source degradation capacitor array includes N sets of source degradation capacitor branches connected in parallel, and each source degradation capacitor branch includes a capacitor and two switches; The first terminal of the first switch is connected to the emitter of the first transistor, the second terminal of the first switch is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to the first terminal of the second switch, and the second terminal of the second switch is connected to the emitter of the second transistor.
[0012] Preferably, the limiting amplifier includes multiple amplifiers, the first amplifier includes a fourth resistor, a fifth resistor, a fifth transistor, a sixth transistor and a fourth bias current, the second amplifier includes a seventh transistor, an eighth transistor and a fifth bias current, the third amplifier is a two-input non-inverting amplifier, and the fourth amplifier is an inverting amplifier. The first ends of the fourth and fifth resistors are connected. The second end of the fourth resistor is connected to the collector of the fifth transistor, the collector of the eighth transistor, the negative input terminal of the fourth amplifier, and the first positive input terminal of the third amplifier. The second end of the fifth resistor is connected to the collector of the sixth transistor, the collector of the seventh transistor, the positive input terminal of the fourth amplifier, and the first negative input terminal of the third amplifier. The base of the fifth transistor and the base of the sixth transistor are the positive input terminal and the negative input terminal of the limiting amplifier, respectively. The emitters of the fifth transistor and the sixth transistor are both grounded through the fourth bias current. The positive and negative output terminals of the fourth amplifier are respectively the positive and negative output terminals of the limiting amplifier, and are respectively connected to the positive and negative input terminals of the third amplifier; The positive and negative output terminals of the third amplifier are connected to the base of the eighth transistor and the base of the seventh transistor, respectively. The emitters of the seventh transistor and the eighth transistor are both grounded through the fifth bias current.
[0013] This invention also provides a method for adjusting a full-frequency gain controllable ultra-wideband adaptive equalizer, applied to the aforementioned full-frequency gain controllable ultra-wideband adaptive equalizer, the method comprising: Step S1: Adjust the gain of the equalizer, including the following steps: Initialization: Set the bandwidth of the equalizer, the limiting amplifier, the second bandpass amplifier, and the third bandpass amplifier to the maximum, turn off the first bandpass amplifier, and set the gain of the equalizer to half of the maximum gain; Gain adjustment: In each adjustment, record the output result EQ of the equalizer and the output result SL of the limiting amplifier. Compare the magnitudes of EQ and SL using an energy comparator, and adjust the gain of the equalizer using a binary method based on the comparison result. Step S2: Adjust the bandwidth of the equalizer, including the following steps: Initialization: Repeatedly set the bandwidth of the first bandpass amplifier and the bandwidth of the second bandpass amplifier from high to low. During this comparison process, keep the bandwidth of the second bandpass amplifier greater than the bandwidth of the first bandpass amplifier until the output amplitude energy of the second bandpass amplifier is greater than the output amplitude energy of the first bandpass amplifier. Then determine the current signal bandwidth as the current bandwidth of the second bandpass amplifier. Adjust bandwidth: Set all analog circuits to the current signal bandwidth.
[0014] Preferably, the gain adjustment method is as follows: A binary search method is used for adjustment, where i is the number of adjustments, and the binary search interval is [L, U], where L represents the lower bound of the current search and U is the upper bound of the current search. Define the maximum gain level of the equalizer as G. max Then, during the initial state search, G max 0 is the upper bound and 0 is the lower bound. The default gain of the equalizer is half of the maximum gain level. Step S101: During the i-th binary search, if EQ is greater than SL, then adjust the previous gain level G. i-1 This is denoted as the upper bound of the current search interval, and the lower bound of the current search interval remains consistent with the lower bound of the previous search interval; if EQ is less than SL, then the previous gain level G is adjusted. i-1 This is denoted as the lower bound of the current search interval, while the upper bound of the current search interval remains the same as the upper bound of the previous search interval. Step S102: Determine If the two adjacent gears have already been traversed, then adjust the gain of the equalizer to... Otherwise, return to step S101 to readjust.
[0015] Preferably, the bandwidth adjustment method involves performing multi-step bandwidth settings, where j represents the order of bandwidth settings, and a bandwidth search is performed. In the j-th setting, the bandwidth of the first bandpass amplifier is set to Ghz, setting the bandwidth of the second bandpass amplifier to Determine if the output of the second bandpass amplifier is greater than the output of the first bandpass amplifier. If it is greater, then the current signal bandwidth is... Exit the bandwidth search step; otherwise, exclude signals with a bandwidth of [missing value]. The possibility of proceeding to the next bandwidth setting; If all bandwidth settings have been completed and all bandwidth possibilities have been ruled out, then the current signal bandwidth is considered to be 270MHz and the bandwidth search step is exited.
[0016] The technical solution of the present invention has at least the following advantages and beneficial effects: This invention can match the circuit bandwidth by automatically detecting the signal bandwidth, thereby suppressing reflections and interference in low-frequency, high-gain applications. This invention addresses the drawback of being unable to transmit unbalanced DC data for extended periods by incorporating positive feedback into the limiting amplifier. This invention is reasonably designed, has a simple structure, and is easy to adjust. It is suitable for application in digital communication systems in different scenarios and is easy to promote and implement. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the structure of the ultra-wideband adaptive equalizer with controllable gain across all frequency points provided in Embodiment 1 of the present invention; Figure 2 for Figure 1 A circuit diagram of the equalizer in the image; Figure 3 for Figure 1 A circuit diagram of the limiting amplifier in the diagram; Figure 4 This is a flowchart illustrating the adjustment method of the full-frequency gain controllable ultra-wideband adaptive equalizer provided in Embodiment 2 of the present invention. Figure 5 This is a schematic diagram of the gain curves A1 and A2*A3 provided in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the gain curve at the output terminal of the first amplifier provided in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the output waveform of the limiting amplifier transmitting unbalanced DC data according to Embodiment 1 of the present invention; Icons: R1 - First resistor, R2 - Second resistor, R3 - Third resistor, R4 - Fourth resistor, R5 - Fifth resistor, Q1 - First transistor, Q2 - Second transistor, Q3 - Third transistor, Q4 - Fourth transistor, Q5 - Fifth transistor, Q6 - Sixth transistor, Q7 - Seventh transistor, Q8 - Eighth transistor, C1 - First capacitor, C2 - Second capacitor, Ibias1 - First bias current, Ibias2 - Second bias current, Ibias3 - Third bias current, Ibias4 - Fourth bias current, Ibias5 - Fifth bias current, A1 - First amplifier, A2 - Second amplifier, A3 - Third amplifier, A4 - Fourth amplifier, S1 - First switch, S2 - Second switch, S3 - Third switch, S4 - Fourth switch. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0019] Example 1 This embodiment provides an ultra-wideband adaptive equalizer with controllable gain across all frequency points. (See attached document.) Figure 1 It includes an equalizer, a limiting amplifier, an energy comparator, a digital control module, and multiple bandpass amplifiers. The limiting amplifier has a positive feedback loop. Both the equalizer and the limiting amplifier are bandwidth-adjustable devices.
[0020] The positive output terminal of the equalizer is connected to the positive input terminal of the limiting amplifier, the positive input terminal of the first bandpass amplifier, and the positive input terminal of the second bandpass amplifier; the negative output terminal of the equalizer is connected to the negative input terminal of the limiting amplifier, the negative input terminal of the first bandpass amplifier, and the negative input terminal of the second bandpass amplifier. The positive and negative output terminals of the limiting amplifier are connected to the positive and negative input terminals of the third bandpass amplifier, respectively, and are also the positive and negative output terminals of the ultra-wideband adaptive equalizer. The outputs of the first bandpass amplifier, the second bandpass amplifier, and the third bandpass amplifier are respectively connected to the three inputs of the energy comparator. The output of the energy comparator is connected to the input of the digital control module, which is used to adjust the bandwidth of the limiting amplifier and multiple bandpass amplifiers according to the output of the energy comparator.
[0021] In the above scheme, the gain and bandwidth of the equalizer are configurable, as are the bandwidths of the limiting amplifier and bandpass amplifier, and the structures of the bandpass amplifiers are identical. The bandwidths of the equalizer, limiting amplifier, and bandpass amplifier can all be configured to multiple bandwidth points such as 6GHz, 3GHz, 1.5GHz, 750MHz, and 135MHz. This embodiment achieves adaptive adjustment of the equalization gain by comparing the amplitude energy of the signals before and after the limiting amplifier. Furthermore, by adding a bandpass amplifier at the output of the equalizer, an additional bandwidth judgment process is incorporated to determine the bandwidth of the input signal at the current stage. This allows the equalizer to set the corresponding bandwidth when transmitting signals at different rates, avoiding high-bandwidth transmission of low-rate signals and reducing out-of-band interference and reflections.
[0022] The following describes the specific design of the equalizer and limiting amplifier. It should be noted that in the attached diagram, VIP, VIN, VOP, and VON represent the positive input, negative input, positive output, and negative output terminals, respectively.
[0023] For an example of an equalizer, please refer to [link / reference]. Figure 2 The equalizer comprises a cascaded four-stage CTLE circuit, specifically including multiple resistors, multiple transistors, a first output capacitor array, a second output capacitor array, a source degradation capacitor array, a first follower bias current array, a second follower bias current array, and multiple bias currents. This equalizer can compensate for approximately 50dB of gain at any bandwidth of 135MHz, 750MHz, 1.5GHz, 3GHz, and 6GHz. The specific structure is as follows: The first terminal of the first resistor R1, the first terminal of the second resistor R2, the collector of the third transistor Q3, and the collector of the fourth transistor Q4 are connected to the DC source VDD. The base of the third transistor Q3 is connected to the second terminal of the first resistor R1 and the collector of the first transistor Q1, and the emitter of the first transistor Q1 is grounded through the first bias current Ibias1. The base of the fourth transistor Q4 is connected to the second terminal of the second resistor R2 and the collector of the second transistor Q2. The emitter of the second transistor Q2 is grounded through the second bias current Ibias2. The emitter of the third transistor Q3 is the negative output terminal of the CTLE circuit and is connected to the first follower bias current array; the emitter of the fourth transistor Q4 is the positive output terminal of the CTLE circuit and is connected to the second follower bias current array. The second end of the first resistor R1 is connected to the first output capacitor array, and the second end of the second resistor R2 is connected to the second output capacitor array. The base of the first transistor Q1 is the positive input terminal of the CTLE circuit, and the base of the second transistor Q2 is the negative input terminal of the CTLE circuit. There is a third resistor R3 and a source degradation capacitor array between the emitter of the first transistor Q1 and the emitter of the second transistor Q2.
[0024] In this configuration, transistors Q1 and Q2 are identical input transistors, resistors R1 and R2 are identical load resistors, and transistors Q3 and Q4 are emitter followers. The emitter follower bias current array enables configurable bandwidth, and the output capacitor array, in conjunction with the emitter follower bias current array, further enhances bandwidth configurability. The source degradation capacitor array enables adjustable gain.
[0025] As a preferred embodiment, the first output capacitor array and the second output capacitor array have the same structure, including P groups of parallel output capacitor branches, and the output capacitor branches include capacitors and switches. In the first output capacitor array, the first end of the second capacitor C2 is connected to the second end of the first resistor R1, the second end of the second capacitor C2 is connected to the first end of the third switch S3, and the second end of the third switch S3 is grounded. In the second output capacitor array, the first end of the second capacitor C2 is connected to the second end of the second resistor R2, the second end of the second capacitor C2 is connected to the first end of the switch, and the second end of the third switch S3 is grounded.
[0026] Meanwhile, the first follower bias current array and the second follower bias current array have the same structure, including M groups of parallel bias current branches, and the bias current branches include switches and bias currents. In the first follower bias current array, the first terminal of the fourth switch S4 is connected to the emitter of the third transistor Q3, the second terminal of the fourth switch S4 is connected to the input terminal of the third bias current Ibias3, and the output terminal of the third bias current Ibias3 is grounded. In the second follower bias current array, the first terminal of the fourth switch S4 is connected to the emitter of the fourth transistor Q4, the second terminal of the fourth switch S4 is connected to the input terminal of the bias current, and the output terminal of the third bias current Ibias3 is grounded.
[0027] In addition, the source degradation capacitor array includes N sets of source degradation capacitor branches connected in parallel, and each source degradation capacitor branch includes a capacitor and two switches. The first terminal of the first switch S1 is connected to the emitter of the first transistor Q1, the second terminal of the first switch S1 is connected to the first terminal of the first capacitor C1, the second terminal of the first capacitor C1 is connected to the first terminal of the second switch S2, and the second terminal of the second switch S2 is connected to the emitter of the second transistor Q2.
[0028] The equalizer structure in this embodiment is based on the traditional CTLE architecture, using a source degenerate capacitor array to add zeros at low frequencies to compensate for high-frequency gain. The formula for zero is 1 / (RsCs), pole 1 is (1+gmRs / 2) / (RsCs), and pole 2 is... Where Cs is the capacitance of the source degradation capacitor, Rs is the resistance of the source degradation resistor, and gm is the transconductance of the corresponding transistor. This represents the resistance value of the load resistor. Let Cs be the capacitance value of the load capacitor. As can be seen from the formula, increasing the capacitance value Cs of the source degradation capacitor shifts the zero point to lower frequencies, but pole 2 remains unchanged. This results in an increase in the gain at high frequencies when the low-frequency gain is increased, thus amplifying the out-of-band noise at high frequencies. Therefore, in this embodiment, the equalizer incorporates multiple sets of load capacitor control (through the setting of the output capacitor array) and output current control (through the setting of the follower bias current array) to flexibly adjust the position of pole 2, thereby increasing the low-frequency gain while reducing the high-frequency gain.
[0029] As a preferred embodiment, see [reference] Figure 3 The limiting amplifier with a positive feedback loop includes multiple amplifiers. The first amplifier A1 includes a fourth resistor R4, a fifth resistor R5, a fifth transistor Q5, a sixth transistor Q6, and a fourth bias current Ibias4. The second amplifier A2 includes a seventh transistor Q7, an eighth transistor Q8, and a fifth bias current Ibias5. The third amplifier A3 is a two-input non-inverting amplifier, and the fourth amplifier A4 is an inverting amplifier. The first ends of the fourth resistor R4 and the fifth resistor R5 are connected. The second end of the fourth resistor R4 is connected to the collector of the fifth transistor Q5, the collector of the eighth transistor Q8, the negative input terminal of the fourth amplifier A4, and the first positive input terminal of the third amplifier A3. The second end of the fifth resistor is connected to the collector of the sixth transistor Q6, the collector of the seventh transistor Q7, the positive input terminal of the fourth amplifier A4, and the first negative input terminal of the third amplifier A3. The base of the fifth transistor Q5 and the base of the sixth transistor Q6 are the positive input terminal and negative input terminal of the limiting amplifier, respectively. The emitter of the fifth transistor Q5 and the emitter of the sixth transistor Q6 are both grounded through the fourth bias current Ibias4. The positive and negative output terminals of the fourth amplifier A4 are respectively the positive and negative output terminals of the limiting amplifier, and are respectively connected to the positive and negative input terminals of the third amplifier A3; The positive and negative output terminals of the third amplifier A3 are connected to the base of the eighth transistor Q8 and the base of the seventh transistor Q7, respectively. The emitters of the seventh transistor Q7 and the eighth transistor Q8 are both grounded through the fifth bias current Ibias5.
[0030] In the limiting amplifier, the third amplifier A3 is a high-gain, low-bandwidth two-input inverting amplifier, and the fourth amplifier A4 is a normal-gain, high-bandwidth inverting amplifier. The first amplifier A1 and the second amplifier A2 are high-bandwidth, low-gain inverting amplifiers, and the first amplifier A1 and the second amplifier A2 share a load resistor to achieve gain subtraction. The gains of the first amplifier A1, the second amplifier A2, and the third amplifier A3 at frequency f are A1(f), A2(f), and A3(f), respectively. In the negative feedback path formed by the first amplifier A1, the second amplifier A2, and the third amplifier A3, the gain of the output of the first amplifier A1 at frequency f is A1(f) / (A2(f)*A3(f)). Since the bandwidth of the first amplifier A1 is higher than that of the negative feedback path formed by the cascaded second amplifier A2 and the third amplifier A3, but its gain is lower, an AC curve with negative low-frequency output gain and positive high-frequency gain will be obtained at the MIP node and MIN node in the figure. The gains of the first amplifier A1 (labeled A1 in the diagram) and the negative feedback path (labeled A2*A3 in the diagram) are as follows: Figure 5 As shown, the output gain of the first amplifier (marked as A1 / (A2*A3) in the figure) is as follows: Figure 6 As shown. From Figure 6 The output loop gain of the first amplifier A1, the second amplifier A2, and the third amplifier A3 is clearly visible. The gain curves show a capacitively coupled input, where the low-frequency output is negative and the high-frequency output is positive. This suppresses low frequencies and amplifies high frequencies, exhibiting high-pass characteristics. After adding the fourth amplifier A4, it forms a positive feedback loop with the first amplifier A1, the second amplifier A2, and the third amplifier A3. The positive feedback characteristic is either a high or low output. When using a high-pass limiting amplifier to transmit unbalanced DC data, no common-mode drift occurs, allowing for normal signal transmission. The output waveform of the limiting amplifier transmitting unbalanced DC data is shown below. Figure 7 As shown.
[0031] Example 2 This embodiment provides an adjustment method for an ultra-wideband adaptive equalizer with controllable gain across all frequency points, applied to an ultra-wideband adaptive equalizer with controllable gain across all frequency points as described in the above embodiment. The adjustment method for the equalizer includes: Step S1: Adjust the gain of the equalizer, including the following steps: Initialization: Set the bandwidth of the equalizer, the limiting amplifier, the second bandpass amplifier, and the third bandpass amplifier to the maximum, turn off the first bandpass amplifier, and set the gain of the equalizer to half of the maximum gain; Gain adjustment is performed as follows: In each adjustment, the output result EQ of the equalizer and the output result SL of the limiting amplifier are recorded. The magnitudes of EQ and SL are compared using an energy comparator. Based on the comparison result, the gain of the equalizer is adjusted using a binary method. The gain adjustment method is as follows: A binary search method is used for adjustment, where i is the number of adjustments, and the binary search interval is [L, U], where L represents the lower bound of the current search and U is the upper bound of the current search. Define the maximum gain level of the equalizer as G. max Then, during the initial state search, G max The upper bound is 0, and the lower bound is 0. The default gain of the equalizer is half of the maximum gain level. For example, the maximum gain level of this equalizer is 128, and the default initial state of the equalizer gain is 64. The default search range is [0, 128]. Step S101: During the i-th binary search, if EQ is greater than SL, then adjust the previous gain level G. i-1 This is denoted as the upper bound of the current search interval, and the lower bound of the current search interval remains consistent with the lower bound of the previous search interval; if EQ is less than SL, then the previous gain level G is adjusted. i-1 This is denoted as the lower bound of the current search interval, while the upper bound of the current search interval remains the same as the upper bound of the previous search interval.
[0032] Step S102: Determine If the two adjacent gears have already been traversed, then adjust the gain of the equalizer to... Otherwise, return to step S101 to readjust.
[0033] For example, in the first adjustment, if the EQ is not less than SL, then level 64 becomes the upper bound of the adjustment range, and the gain of the equalizer is adjusted to 32. In the second adjustment, if the EQ is not less than SL, then level 32 becomes the upper bound of the adjustment range, and the search range this time is [0, 32], and the gain of the equalizer is adjusted to 16; otherwise, level 32 becomes the lower bound of the adjustment range, and the search range this time is [32, 64], and the gain of the equalizer is adjusted to 48. This process is repeated until the condition for the end of traversal in step S102 is met.
[0034] Step S2: Adjust the bandwidth of the equalizer, including the following steps: Initialization: Repeatedly set the bandwidth of the first bandpass amplifier and the bandwidth of the second bandpass amplifier from high to low values until the output of the second bandpass amplifier is greater than the output of the first bandpass amplifier, and determine the current signal bandwidth as the current bandwidth of the second bandpass amplifier; Adjust bandwidth: Set all analog circuits to the current signal bandwidth.
[0035] The bandwidth adjustment method in this step is to perform multi-step bandwidth settings, where j represents the order of bandwidth settings, and to perform a bandwidth search: In the j-th setting, the bandwidth of the first bandpass amplifier is set to Ghz, setting the bandwidth of the second bandpass amplifier to Determine if the output of the second bandpass amplifier is greater than the output of the first bandpass amplifier. If it is greater, then the current signal bandwidth is... Exit the bandwidth search step; otherwise, exclude signals with a bandwidth of [missing value]. The possibility of proceeding to the next bandwidth setting; If all bandwidth settings have been completed and all bandwidth possibilities have been ruled out, then the current signal bandwidth is considered to be 270MHz and the bandwidth search step is exited.
[0036] Here is an example: Step S201: Set the bandwidth of the first bandpass amplifier to 3 GHz and the bandwidth of the second bandpass amplifier to 6 GHz. Determine whether the output of the second bandpass amplifier is greater than the output of the first bandpass amplifier. If it is greater, the current signal bandwidth is 6 GHz; otherwise, proceed to the next step. Step S202: Set the bandwidth of the first bandpass amplifier to 1.5 GHz and the bandwidth of the second bandpass amplifier to 3 GHz. Determine whether the output of the second bandpass amplifier is greater than the output of the first bandpass amplifier. If it is greater, the current signal bandwidth is 3 GHz; otherwise, proceed to the next step. Step S203: Set the bandwidth of the first bandpass amplifier to 750MHz and the bandwidth of the second bandpass amplifier to 1.5GHz. Determine whether the output of the second bandpass amplifier is greater than the output of the first bandpass amplifier. If it is greater, the current signal bandwidth is 1.5GHz; otherwise, proceed to the next step. Step S204: Set the bandwidth of the first bandpass amplifier to 270MHz and the bandwidth of the second bandpass amplifier to 750MHz. Determine whether the output of the second bandpass amplifier is greater than the output of the first bandpass amplifier. If it is greater, the current signal bandwidth is 750MHz; otherwise, the current signal bandwidth is 270MHz.
[0037] This embodiment describes the workflow of an adaptive equalizer. In each adjustment, the gain and bandwidth are adjusted in stages to eventually stabilize both the gain and bandwidth to a suitable range.
[0038] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A full-frequency gain controllable ultra-wideband adaptive equalizer, characterized in that, It includes an equalizer, a limiting amplifier, an energy comparator, a digital control module, and multiple bandpass amplifiers, with the limiting amplifier having a positive feedback loop; The positive output terminal of the equalizer is connected to the positive input terminal of the limiting amplifier, the positive input terminal of the first bandpass amplifier, and the positive input terminal of the second bandpass amplifier; the negative output terminal of the equalizer is connected to the negative input terminal of the limiting amplifier, the negative input terminal of the first bandpass amplifier, and the negative input terminal of the second bandpass amplifier. The positive and negative output terminals of the limiting amplifier are connected to the positive and negative input terminals of the third bandpass amplifier, respectively, and are also the positive and negative output terminals of the ultra-wideband adaptive equalizer. The outputs of the first bandpass amplifier, the second bandpass amplifier, and the third bandpass amplifier are respectively connected to the three inputs of the energy comparator. The output of the energy comparator is connected to the input of the digital control module, which is used to adjust the bandwidth of the limiting amplifier and multiple bandpass amplifiers according to the output of the energy comparator.
2. The ultra-wideband adaptive equalizer with controllable gain across all frequency points according to claim 1, characterized in that, The equalizer includes a cascaded four-stage CTLE circuit.
3. The ultra-wideband adaptive equalizer with controllable gain across all frequency points according to claim 2, characterized in that, The CTLE circuit includes multiple resistors, multiple transistors, a first output capacitor array, a second output capacitor array, a source degradation capacitor array, a first follower bias current array, a second follower bias current array, and multiple bias currents. The first terminal of the first resistor, the first terminal of the second resistor, the collector of the third transistor, and the collector of the fourth transistor are connected to a DC source. The base of the third transistor is connected to the second terminal of the first resistor and the collector of the first transistor, and the emitter of the first transistor is grounded through the first bias current. The base of the fourth transistor is connected to the second terminal of the second resistor and the collector of the second transistor, and the emitter of the second transistor is grounded through the second bias current. The emitter of the third transistor is the negative output terminal of the CTLE circuit and is connected to the first follower bias current array; the emitter of the fourth transistor is the positive output terminal of the CTLE circuit and is connected to the second follower bias current array. The second end of the first resistor is connected to the first output capacitor array, and the second end of the second resistor is connected to the second output capacitor array. The base of the first transistor is the positive input terminal of the CTLE circuit, and the base of the second transistor is the negative input terminal of the CTLE circuit. There is a third resistor and a source degradation capacitor array between the emitter of the first transistor and the emitter of the second transistor.
4. The ultra-wideband adaptive equalizer with controllable gain across all frequency points according to claim 3, characterized in that, The first output capacitor array and the second output capacitor array have the same structure, including P groups of parallel output capacitor branches, and the output capacitor branches include capacitors and switches. In the first output capacitor array, the first end of the second capacitor is connected to the second end of the first resistor, the second end of the second capacitor is connected to the first end of the third switch, and the second end of the third switch is grounded. In the second output capacitor array, the first end of the second capacitor is connected to the second end of the second resistor, the second end of the second capacitor is connected to the first end of the switch, and the second end of the third switch is grounded.
5. The ultra-wideband adaptive equalizer with controllable gain across all frequency points according to claim 3, characterized in that, The first follower bias current array and the second follower bias current array have the same structure, including M groups of parallel bias current branches, and the bias current branches include switches and bias currents. In the first follower bias current array, the first terminal of the fourth switch is connected to the emitter of the third transistor, the second terminal of the fourth switch is connected to the input terminal of the third bias current, and the output terminal of the third bias current is grounded. In the second follower bias current array, the first terminal of the fourth switch is connected to the emitter of the fourth transistor, the second terminal of the fourth switch is connected to the input terminal of the bias current, and the output terminal of the third bias current is grounded.
6. The ultra-wideband adaptive equalizer with controllable gain across all frequency points according to claim 3, characterized in that, The source degradation capacitor array includes N sets of source degradation capacitor branches connected in parallel, and each source degradation capacitor branch includes a capacitor and two switches. The first terminal of the first switch is connected to the emitter of the first transistor, the second terminal of the first switch is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to the first terminal of the second switch, and the second terminal of the second switch is connected to the emitter of the second transistor.
7. The ultra-wideband adaptive equalizer with controllable gain across all frequency points according to claim 1, characterized in that, The limiting amplifier includes multiple amplifiers. The first amplifier includes a fourth resistor, a fifth resistor, a fifth transistor, a sixth transistor, and a fourth bias current. The second amplifier includes a seventh transistor, an eighth transistor, and a fifth bias current. The third amplifier is a two-input non-inverting amplifier, and the fourth amplifier is an inverting amplifier. The first ends of the fourth and fifth resistors are connected. The second end of the fourth resistor is connected to the collector of the fifth transistor, the collector of the eighth transistor, the negative input terminal of the fourth amplifier, and the first positive input terminal of the third amplifier. The second end of the fifth resistor is connected to the collector of the sixth transistor, the collector of the seventh transistor, the positive input terminal of the fourth amplifier, and the first negative input terminal of the third amplifier. The base of the fifth transistor and the base of the sixth transistor are the positive input terminal and the negative input terminal of the limiting amplifier, respectively. The emitters of the fifth transistor and the sixth transistor are both grounded through the fourth bias current. The positive and negative output terminals of the fourth amplifier are respectively the positive and negative output terminals of the limiting amplifier, and are respectively connected to the positive and negative input terminals of the third amplifier; The positive and negative output terminals of the third amplifier are connected to the base of the eighth transistor and the base of the seventh transistor, respectively. The emitters of the seventh transistor and the eighth transistor are both grounded through the fifth bias current.
8. A method for adjusting a full-frequency gain controllable ultra-wideband adaptive equalizer, applied to a full-frequency gain controllable ultra-wideband adaptive equalizer as described in any one of claims 1-7, characterized in that, The equalizer adjustment method includes: Step S1: Adjust the gain of the equalizer, including the following steps: Initialization: Set the bandwidth of the equalizer, the limiting amplifier, the second bandpass amplifier, and the third bandpass amplifier to the maximum, turn off the first bandpass amplifier, and set the gain of the equalizer to half of the maximum gain; Gain adjustment: In each adjustment, record the output result EQ of the equalizer and the output result SL of the limiting amplifier. Compare the magnitudes of EQ and SL using an energy comparator, and adjust the gain of the equalizer using a binary method based on the comparison result. Step S2: Adjust the bandwidth of the equalizer, including the following steps: Initialization: Repeatedly set the bandwidth of the first bandpass amplifier and the bandwidth of the second bandpass amplifier from high to low. During this comparison process, keep the bandwidth of the second bandpass amplifier greater than the bandwidth of the first bandpass amplifier until the output amplitude energy of the second bandpass amplifier is greater than the output amplitude energy of the first bandpass amplifier. Then determine the current signal bandwidth as the current bandwidth of the second bandpass amplifier. Adjust bandwidth: Set all analog circuits to the current signal bandwidth.
9. The adjustment method for a full-frequency gain controllable ultra-wideband adaptive equalizer according to claim 8, characterized in that, The method for adjusting the gain is as follows: A binary search method is used for adjustment, where i is the number of adjustments, and the binary search interval is [L, U], where L represents the lower bound of the current search and U is the upper bound of the current search. Define the maximum gain level of the equalizer as G. max Then, during the initial state search, G max 0 is the upper bound and 0 is the lower bound. The default gain of the equalizer is half of the maximum gain level. Step S101: During the i-th binary search, if EQ is greater than SL, then adjust the previous gain level G. i-1 This is denoted as the upper bound of the current search interval, and the lower bound of the current search interval remains consistent with the lower bound of the previous search interval; if EQ is less than SL, then the previous gain level G is adjusted. i-1 This is denoted as the lower bound of the current search interval, while the upper bound of the current search interval remains consistent with the upper bound of the previous search interval. Step S102: Determine If the two adjacent gears have already been traversed, then adjust the gain of the equalizer to... Otherwise, return to step S101 to readjust.
10. The adjustment method of a full-frequency gain controllable ultra-wideband adaptive equalizer according to claim 8, characterized in that, The bandwidth adjustment method is as follows: The bandwidth adjustment method involves performing multi-step bandwidth settings, where j represents the order of bandwidth settings, and a bandwidth search is performed. In the j-th setting, the bandwidth of the first bandpass amplifier is set to Ghz, setting the bandwidth of the second bandpass amplifier to Determine if the output of the second bandpass amplifier is greater than the output of the first bandpass amplifier. If it is greater, then the current signal bandwidth is... Exit the bandwidth search step; otherwise, exclude signals with a bandwidth of [missing value]. The possibility of proceeding to the next bandwidth setting; If all bandwidth settings have been completed and all bandwidth possibilities have been ruled out, then the current signal bandwidth is considered to be 270MHz and the bandwidth search step is exited.