A bus multi-tap data splicing system and method

Abstract

The application discloses a bus multi-shot data splicing system and method, wherein the system comprises: a transaction analysis module for dividing a read transaction based on burst length information in the received read transaction to obtain a plurality of splicing units; a read data module for receiving narrow bit data shots; determining a data position according to a data shot position index and a new transaction identifier in the narrow bit data shots, and writing the narrow bit data shots into the data position and marking a position corresponding to the data position as valid; a splicing determination unit for real-time detecting state marker bits corresponding to each data position; when the state marker bits of all data positions corresponding to the splicing unit are valid, triggering a splicing control module to perform splicing operation on each narrow bit data shot to obtain a spliced wide bit data shot; and the application can realize multi-transaction concurrency, correct splicing and ordered output of wide bit data shots under the condition of narrow bit data shot disorder or interleaving return.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and on-chip interconnect (SoC Interconnect) technology, and in particular to a bus multi-phase data splicing system and method. Background Technology

[0002] As the number of processor cores, dedicated accelerators, and various peripheral modules in a System-on-Chip (SoC) continues to increase, the frequency of data interaction and the demand for data throughput between different functional modules are constantly rising. To improve the overall performance of the SoC, high-bandwidth, high-frequency on-chip buses or inter-chip interconnect structures are typically used to achieve data transmission. However, in practical applications, some peripherals or subsystems still access data with lower bandwidth, making it impossible to fully utilize the high-bandwidth bus during single data transmissions. This leads to a decrease in effective bandwidth utilization, limiting further improvements in SoC performance.

[0003] To address the above issues, existing technologies typically employ data width converters (DWCs) or data packet splitting and reassembly modules to achieve data adaptation between buses of different widths. For example, in the AXI bus architecture, wide-bit data can be split into multiple narrow-bit data outputs, or multiple narrow-bit data can be concatenated into wide-bit data in a predetermined order, without altering the basic timing of the protocol, thus enabling data transmission across different widths.

[0004] However, existing bit-width conversion or data packet concatenation schemes typically rely on data arriving in sequence. In multi-transaction concurrent scenarios, when read data returns out of order or interleaved, it becomes difficult to effectively distinguish and reassemble data from different transactions. Existing solutions often use burst transactions as the smallest processing unit, lacking mechanisms to determine the completion of data across different transactions, making it difficult to accurately determine whether the data concatenation completion conditions are met. Furthermore, when read data returns out of order or interleaved, existing technologies typically employ direct forwarding or reordering, failing to generate single-bit wide data packets under out-of-order conditions, thus limiting bus bandwidth utilization.

[0005] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0006] This invention provides a bus multi-segment data splicing system to achieve correct splicing and orderly output of wide-segment data under conditions of multi-transaction concurrency and out-of-order or interleaved return of narrow-segment data, thereby improving the data processing efficiency and bandwidth utilization of high-width buses in complex system environments.

[0007] This bus-based multi-shot data stitching system includes: The transaction parsing module is used to divide the read transaction based on the burst length information in the received read transaction to obtain multiple splicing units; The data reading module is used to receive narrow data segments; determine the data position according to the data segment position index and new transaction identifier in the narrow data segment, write the narrow data segment into the data position, and mark the status corresponding to the data position as valid; The splicing determination unit is used to detect the status flag bits corresponding to each data position in real time. When the status flag bits of all data positions corresponding to the splicing unit are valid, the splicing control module is triggered to perform splicing operation on each narrow data frame to obtain the spliced ​​wide data frame.

[0008] In some embodiments, the transaction parsing module is further configured to receive read transactions through a first bus command interface; parse the read transactions to obtain transaction identifier information and burst length information; determine the number of narrow data blocks based on the data bit width of the first bus data interface and the data bit width of the second bus data interface; and assign corresponding splicing unit identifier information to each splicing unit.

[0009] In some embodiments, the system further includes: The identifier remapping module is used to re-encode the transaction identifier information and assign a new transaction identifier; and store the mapping relationship between the transaction identifier information and the new transaction identifier in the incomplete transaction identifier table.

[0010] In some embodiments, the identifier remapping module is further configured to send multiple narrow-bit read requests to the second bus command interface based on the splicing unit identifier information and the number of narrow-bit data snapshots.

[0011] In some embodiments, the data reading module is specifically used to receive the narrow-bit data tick through the second bus data interface; determine the corresponding linked list number based on the new transaction identifier; and determine the data position in the linked list number based on the data tick position index.

[0012] In some embodiments, the splicing control module is specifically used to splice the narrow data frames stored in the read data module into a wide data frame according to a preset data position order, and send the wide data frame and its corresponding transaction identifier information to the output interface module.

[0013] In some embodiments, the system further includes an output interface module, configured to sequentially output wide-bit data frames corresponding to each of the splicing units through the first bus data interface.

[0014] This invention also provides a bus multi-segment data splicing method to achieve correct splicing and orderly output of wide-segment data under conditions of multi-transaction concurrency and out-of-order or interleaved return of narrow-segment data, thereby improving the data processing efficiency and bandwidth utilization of high-width buses in complex system environments.

[0015] The method for splicing multi-phase data on the bus includes: The transaction parsing module divides the read transaction based on the burst length information in the received read transaction, resulting in multiple concatenation units; The data reading module receives narrow-bit data snapshots; determines the data position based on the data snapshot position index and new transaction identifier in the narrow-bit data snapshot, writes the narrow-bit data snapshot into the data position, and marks the status corresponding to the data position as valid; The splicing determination unit detects the status flag bits corresponding to each data position in real time; when the status flag bits of all data positions corresponding to the splicing unit are valid, the splicing control module is triggered to perform splicing operation on each narrow data frame to obtain the spliced ​​wide data frame.

[0016] This invention also provides a chip, including the above-described bus multi-shot data splicing system.

[0017] This invention also provides a board card, including the chip described above.

[0018] This invention also provides an electronic device, including the aforementioned circuit board.

[0019] The bus multi-segment data stitching system and method provided in this invention divides read transactions into multiple stitching units based on burst length using a transaction parsing module. Combined with a read data module, it uses data segment position indexes and new transaction identifiers to precisely locate and write narrow-bit data segments. Simultaneously, status flags mark the arrival status of each data position. This enables the data stitching system to achieve ordered organization and isolated storage of data in both position and transaction dimensions, even under conditions of concurrent multi-transactions and out-of-order or interleaved returns of narrow-bit data segments. The stitching determination unit, through real-time detection of the data position flags, triggers the stitching operation only when all narrow-bit data segments within the corresponding stitching unit have arrived. This avoids incomplete data from participating in the stitching, ensuring the integrity and correct bit order of wide-bit data segments. This improves the accuracy of data processing, the stability of the data stitching system, and bandwidth utilization efficiency in complex bus environments. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of the bus multi-shot data splicing system in an embodiment of the present invention; Figure 2 This is a timing diagram of the data splicing method in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with relevant laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.

[0022] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0023] To achieve efficient data transmission between high-width and low-width buses in scenarios involving concurrent multi-transactions and out-of-order or interleaved read data returns, this application provides a bus multi-segment data splicing system. The system divides read transactions into splicing units based on burst length using a transaction parsing module, re-encodes transaction identifiers using an identifier remapping module to support concurrent multi-transaction processing, and utilizes a read data module to locate, write, and mark the status of narrow-bit data segments based on the new transaction identifier and data segment position index. Simultaneously, a splicing determination unit detects the valid status of each data position. When splicing conditions are met, the splicing control module completes the splicing of narrow-bit data segments to wide-bit data segments according to a preset order, and outputs the data in the original transaction order through an output interface module. This achieves accurate collection and splicing of multi-segment data without depending on the data return order, improving the data utilization of the high-width bus and the data processing efficiency of the splicing system in complex scenarios.

[0024] like Figure 1 As shown, the present invention provides a bus multi-shot data stitching system comprising: The transaction parsing module is used to divide the read transaction based on the burst length information in the received read transaction, resulting in multiple concatenation units.

[0025] The data read module is used to receive narrow-bit data frames. It uses the data frame position index within the narrow-bit data frame. and new transaction identifiers Determine the data location, write the narrow bit data to the data location, and mark the corresponding status location as valid.

[0026] The splicing determination unit is used to detect the status flag bits corresponding to each data position in real time. When the status flag bits of all data positions corresponding to the splicing unit are valid, the splicing control module is triggered to splice each narrow data frame to obtain the spliced ​​wide data frame.

[0027] According to the above embodiments, the transaction parsing module divides read transactions into multiple splicing units based on burst length, and the read data module uses data snapshot position index and new transaction identifier to accurately locate and write narrow data snapshots. Simultaneously, status flags mark the arrival status of each data position, enabling the data splicing system to achieve ordered organization and isolated storage of data in both position and transaction dimensions, even with multiple concurrent transactions and out-of-order or interleaved returns of narrow data snapshots. The splicing determination unit, through real-time detection of the data position flags, triggers the splicing operation only when all narrow data snapshots within the corresponding splicing unit have arrived. This avoids incomplete data from participating in splicing, ensuring the integrity and correct bit order of wide data snapshots, which is beneficial for improving the accuracy of data processing, the stability of the data splicing system, and bandwidth utilization efficiency in complex bus environments.

[0028] In this embodiment of the invention, during the read transaction processing, the master device initiates a read transaction to the data splicing system through the first bus command interface. After receiving the read transaction, the transaction parsing module parses the read transaction to obtain the transaction identifier (Transaction ID). The starting address and burst length are specified. For example, the starting address of a read transaction in this invention is 0x40, and the burst length is 3.

[0029] The transaction parsing module determines the number of wide-bit data frames corresponding to the read transaction based on the burst length, and divides the read transaction into multiple concatenation units accordingly. For example, when the burst length is 3, it corresponds to 4 wide-bit data frames that need to be returned, so the read transaction is divided into 4 concatenation units. Each concatenation unit is logically independent, and each concatenation unit corresponds to one wide-bit data frame to be generated, and is used to complete the narrow-bit data reception, buffering, and concatenation processing of the corresponding wide-bit data frame.

[0030] In some embodiments, the transaction parsing module is further configured to receive read transactions via a first bus command interface, and to parse the read transactions to obtain transaction identification information. And burst length information. The number of narrow data segments is determined based on the data bit width of the first bus data interface and the data bit width of the second bus data interface. Corresponding splicing unit identifier information is assigned to each splicing unit.

[0031] In this embodiment of the invention, the transaction resolution module uses the new transaction identifier returned by the identifier remapping module. and splicing unit serial number Assign a corresponding splicing unit identifier to each splicing unit. The splicing unit identifier information can be represented as follows: .in, Used to identify the read transaction to which it belongs. Used to identify which concatenation unit is in the read transaction. Concatenation unit identifiers are used to distinguish the data sets corresponding to different concatenation units during subsequent data processing.

[0032] Furthermore, during the bit-width conversion process, the data bit width of the first bus data interface is 1024 bits, and the data bit width of the second bus data interface is 256 bits. Based on the data bit-width relationship between the first and second bus data interfaces, the transaction parsing module determines that a single wide-bit data frame is generated by concatenating multiple narrow-bit data frames. The corresponding relationship can be expressed as follows:

[0033] Exemplarily, in this embodiment, That is, each wide-bit data beat consists of 4 narrow-bit data beats.

[0034] Based on the aforementioned bit width relationship, this invention defines multiple narrow data bits used to generate a wide-bit data bit as a splicing unit. In other words, each splicing unit contains a fixed number of narrow data bits. After receiving the narrow data bits, they are spliced ​​according to a preset data position information order to generate the corresponding wide-bit data bit. In this embodiment, each splicing unit contains 4 narrow data bits, and the 4 narrow data bits are spliced ​​according to their position index order to generate a 1024-bit wide-bit data bit.

[0035] According to the above embodiments, the read transactions input through the first bus command interface are parsed by the transaction parsing module, extracting transaction identifier information and burst length information. The number of narrow data blocks is determined by combining the data bit width relationship between the first and second buses, thereby refining the read transaction into multiple splicing units and assigning them corresponding identifiers. This allows the data splicing system to organize and manage data at the splicing unit level. This method not only clarifies the correspondence between wide and narrow data blocks but also provides a unified identifier basis for the subsequent positioning, writing, collection, and splicing processing of narrow data blocks. This facilitates accurate data differentiation and efficient processing in the case of multiple concurrent transactions and out-of-order data returns, thereby improving the data processing capability and bus bandwidth utilization efficiency of the data splicing system.

[0036] In some embodiments, such as Figure 1 As shown, the bus multi-shot data splicing system also includes: ID Remapping Module ) used for transaction identification information Perform recoding and assign a new transaction ID. ). Transaction identification information With new transaction identifier The mapping relationship is stored in the Outstanding Transaction ID Table. ).

[0037] In this embodiment of the invention, after receiving a read transaction input from the first bus command interface, the transaction parsing module will extract the transaction identifier information from the read transaction. The information is passed to the identifier remapping module. The identifier remapping module is used to process transaction identifier information. Perform recoding to generate a new corresponding transaction identifier. .

[0038] For example, the identifier remapping module maintains a set of available identifiers to provide new transaction identifiers that are not currently occupied. When a new read transaction is received, the identifier remapping module selects a currently free new transaction identifier from the set of available identifiers. and transaction identification information With new transaction identifier Establish a mapping relationship and record the mapping relationship in the incomplete transaction identifier table.

[0039] Among them, the new transaction identifier Within the data stitching system of this invention, this new transaction identifier serves as a unique identifier to distinguish different transactions in transit, supporting concurrent processing of multiple transactions and data attribution determination in scenarios involving out-of-order return of narrow-bit data. In subsequent processing, the data stitching system uses this new transaction identifier... Narrow-bit data snapshots are positioned, written, and stitched together. Once the corresponding transaction is completed, the identifier remapping module assigns the new transaction identifier. Release and re-add to the set of available identifiers for reuse in subsequent transactions.

[0040] According to the above embodiments, by setting up an identifier remapping module to re-encode the original transaction identifier information and assign a unique new transaction identifier, and storing the mapping relationship between the two in an incomplete transaction identifier table, the data splicing system can uniquely identify and effectively distinguish each in-transit transaction in a multi-transaction concurrent scenario, thereby avoiding data confusion caused by the reuse or non-uniqueness of the original transaction identifier. Simultaneously, in the case of narrow-bit data being returned out of order or interleaved, the new transaction identifier enables accurate attribution and location of the returned data, and the original transaction identifier can be restored through the mapping relationship after subsequent splicing. This improves the data splicing system's ability to handle complex data transmission scenarios without changing the semantics of the bus protocol, and enhances the accuracy and stability of data processing.

[0041] In some embodiments, the transaction parsing module is also used to send multiple narrow-bit read requests through the second bus command interface based on the splicing unit identification information and the number of narrow-bit data frames.

[0042] In this embodiment of the invention, the transaction parsing module generates a corresponding narrow-bit read request for each concatenation unit based on the concatenation unit identifier, and combines this with the new transaction identifier generated by the identifier remapping module. and data capture location index The narrow-bit read request is identified and encoded to generate a request identifier for transmission on the second bus. This request identifier can be represented as... ,in, Used to identify the read transaction to which it belongs. Used to identify the position of the narrow data frame in the corresponding wide data frame.

[0043] After receiving a narrow-bit read request from the device side, the corresponding narrow-bit data frame is returned via the second bus data interface. During the return process, the narrow-bit data frame carries a read data identifier (Read ID, rid) corresponding to the narrow-bit read request. The read data identifier includes the new transaction identifier from the aforementioned request identifier. and data capture location index This is used to indicate the read transaction to which the narrow data patch belongs and its position in the corresponding splicing unit. Therefore, the data format returned by the second bus data interface can be represented as follows: ,in The data content captured for narrow-bit data.

[0044] Under the influence of multi-transaction concurrency and bus transmission scheduling, narrow-bit data beats may arrive out of order or in an interleaved manner during the return process. That is, the return order no longer strictly corresponds to the sending order of the narrow-bit read request, and narrow-bit data beats from different splicing units or different transactions may be returned in staggered time.

[0045] According to the above embodiments, the transaction parsing module generates and sends multiple narrow-bit read requests based on the splicing unit identifier and the number of narrow-bit data segments. This enables the data splicing system to split the original wide-bit read transactions at the splicing unit granularity and schedule them in a fine-grained manner. This establishes a mapping relationship between narrow-bit data segments and corresponding splicing units at the request stage, facilitating rapid location and aggregation during subsequent data return. This method allows each narrow-bit read request to have an independent identifier and be sent in parallel, thereby improving bus utilization and reducing waiting overhead. In scenarios with multi-transaction concurrency and complex transmission, it effectively enhances the data processing capability and throughput performance of the data splicing system and provides fundamental support for achieving efficient splicing under out-of-order return conditions.

[0046] In some embodiments, the read data module (Read Data List Array, Specifically, it is used to receive narrow-bit data frames via the second bus data interface. Based on the new transaction identifier. Determine the corresponding linked list number based on the data snapshot position index. Determine the data position within the linked list number.

[0047] In this embodiment of the invention, the data reading module It is structured as a linked list matrix to cache and manage narrow-bit data packets returned from the second bus data interface. Index in Corresponding to the data capture location index Different indexes Each corresponds to a different narrow data block in the wide data block, thus forming a multi-array buffer structure divided according to the data block position.

[0048] For example, in this embodiment, the data width of the first bus data interface is 1024 bits, and the data width of the second bus data interface is 256 bits. Therefore, each wide-bit data clock consists of four narrow-bit data clocks. Correspondingly, the data read module includes four linked list array units. to These correspond to the four data capture location indices respectively. to .

[0049] Specifically, each linked list array cell and data position index The correspondence between them is as follows: Corresponding to , Corresponding to , Corresponding to , Corresponding to .

[0050] Furthermore, each This represents a linked list array unit, where each linked list array unit contains multiple linked list structures. Each linked list is used to store different new transaction identifiers. The corresponding narrow-bit data snapshots enable isolated storage and parallel management of multiple transaction data at the same data snapshot position dimension. Specifically, the linked list control module is based on the new transaction identifier. Select the corresponding linked list and write the narrow-bit data belonging to this read transaction into the corresponding linked list. The number of linked lists is the number of in-transit transactions supported by the data splicing system (denoted as ost).

[0051] For example, in middle, Corresponding narrow bit data write , Corresponding narrow bit data write , Corresponding narrow bit data write And so on.

[0052] Each linked list Internally, data is managed using control information such as a head pointer, a tail pointer, and a flag bit (vld). The head pointer indicates the position of the data to be read, the tail pointer indicates the position of the latest written data, and the flag bit indicates whether the data at the corresponding position has been reached. This supports ordered reading and splicing of data in scenarios involving narrow-bit data that is out of order or interleaved.

[0053] Furthermore, the data reading module includes a list control module (list_ctrl) and a list memory unit (list_mem). The list control module is used for unified scheduling and control of read and write operations across all linked lists, including write control, read control, and list state management. The list memory unit stores the narrow-bit data in each linked list and is shared by multiple linked lists to improve storage resource utilization.

[0054] When the second bus data interface returns a narrow data packet, the narrow data packet carries a read data identifier, which includes a new transaction identifier. and data capture location index The linked list control module determines the transaction based on the new transaction identifier. and data capture location index Determine the data location. This is based on the new transaction identifier. Determine the corresponding linked list number Based on data capture location index Determine the index of the data location in the linked list This determines the data location. .

[0055] During the data writing process, the linked list control module allocates a corresponding storage address from the linked list storage unit to store the narrow data bits. The narrow data bits are then written to the storage unit corresponding to the storage address. Simultaneously, the tail pointer of the corresponding linked list is updated to point to the position of the most recently written data, and the flag bit corresponding to that data position is set. Set to valid to indicate that data has been arrived at that position. Additionally, the linked list control module updates the linked list counter. This is used to record the number of narrow-bit data frames received in the linked list.

[0056] According to the above embodiments, the data reading module determines the linked list number based on the new transaction identifier and determines the data position in the linked list by combining the data snapshot position index. This enables the data splicing system to simultaneously complete precise positioning in both the transaction and position dimensions during the data receiving phase, thereby establishing a mapping relationship between narrow-bit data snapshots and corresponding splicing units. In the case of multiple concurrent transactions and out-of-order or interleaved return of narrow-bit data snapshots, the above method can effectively avoid confusion between data from different transactions and ensure the orderly aggregation of data at different positions within the same transaction. This provides a reliable data organization foundation for subsequent data integrity determination and wide-bit data splicing, thereby improving the accuracy of data processing and the stability and processing efficiency of the data splicing system in complex bus environments.

[0057] In some embodiments, the splicing control module is specifically used to splice the narrow data frames stored in the data reading module into a wide data frame according to a preset data position order, and to link the wide data frame and its corresponding transaction identifier information. Send to the output interface module.

[0058] In this embodiment of the invention, during the splicing stage, when the splicing determination unit determines that all narrow-bit data segments in the linked list corresponding to any splicing unit have been reached, the splicing control module sends a read request to the linked list control module. The linked list control module then performs a read operation on the linked list storage unit based on this read request.

[0059] Specifically, the linked list control module determines the current data position to be read based on the head pointer of the corresponding linked list, and reads each narrow data bit from the linked list storage unit in sequence according to the preset order corresponding to the data bit position index. After each data read is completed, the linked list control module updates the head pointer of the linked list so that it points to the next data position to be read, thereby achieving sequential read control.

[0060] During or after data reading, the linked list control module can adjust the flag bit at the corresponding data position. Perform a clear or reset. Once all narrow-bit data bits in the linked list have been read, the linked list control module marks the linked list as idle and releases the relevant resources for reuse by subsequent transactions.

[0061] The splicing control module follows a preset data position sequence (i.e., based on...) (In the order of reading) the narrow data segments, the data segments are concatenated to form a wide data segment, and the generated wide data segment is then combined with the corresponding transaction identifier information. It is output to the output interface module.

[0062] According to the above embodiments, the splicing control module splices the narrow-bit data frames cached in the read data module according to a preset data position order. This ensures that the data splicing process does not depend on the return order of the narrow-bit data frames, but rather achieves ordered reconstruction based on the data frame position index. Therefore, even with multiple concurrent transactions and out-of-order or interleaved return of narrow-bit data frames, the correct bit order and data integrity of the wide-bit data frames can still be guaranteed. Simultaneously, by outputting the corresponding transaction identifier information after splicing, the data splicing system can restore transaction relationships without changing the original bus protocol semantics. This improves the accuracy of data processing and the stability of the system in complex bus environments, and enhances the data utilization efficiency of high-bit-width buses.

[0063] In some embodiments, such as Figure 1 As shown, the bus multi-shot data splicing system also includes an output interface module, which is used to sequentially output the wide-bit data shots corresponding to each splicing unit through the first bus data interface.

[0064] In this embodiment of the invention, the output interface module outputs the wide-bit data frames output by the splicing control module in an orderly manner according to the timing specifications and transaction protocol requirements of the first bus data interface.

[0065] Specifically, the output interface module outputs the wide-bit data beats corresponding to each splicing unit in a preset order, based on the number of wide-bit data beats determined by the burst length of the original read transaction. During the output process, the output interface module maintains control signals and data beat relationships consistent with the first bus data interface protocol, ensuring that the read data return behavior observed on the first bus side remains consistent with the semantics of the original read transaction, i.e., it manifests as multiple consecutive wide-bit read data beats corresponding to the burst length. In other words, although the narrow-bit data beats are split, received out of order, and spliced ​​internally within the data splicing system, the timing constraints and data organization methods of the original bus protocol are strictly followed during external output.

[0066] According to the above embodiments, through the above processing method, without destroying the complete semantics of the original read transaction protocol, the splicing output of multi-slot narrow-bit data to single-slot wide-bit data is realized. This enables the data splicing system to adapt to the data transmission requirements between buses of different bit widths, and to ensure the protocol consistency and timing correctness of the external interface, thereby improving the compatibility and data transmission efficiency of the data splicing system.

[0067] In some embodiments, such as Figure 2 The timing process of the data splicing system of the present invention is described as shown.

[0068] In the first cycle of clock clk (clk1 time), the first bus command interface ( Initiating a single read transaction, its burst length is Transaction identifier is This requires returning 4 wide-bit data blocks (1024 bits). After receiving the read transaction, the transaction parsing module parses it and divides it into 4 concatenation units according to the burst length, while generating 4 corresponding narrow-bit read requests (256 bits).

[0069] Furthermore, the transaction resolution module, in conjunction with the identifier remapping module, processes the original transaction identifier. Perform recoding to generate a new transaction identifier new_id, and match it with the data location index. The request identifier is combined to form the second bus. In this embodiment, The generated 4 narrow-bit read request identifiers They are: 00, 10, 20, and 30 respectively. Where 00 represents... and 10 represents and 20 represents and 30 indicates and The above four narrow-bit read requests were processed through the second bus command interface ( )according to They are issued in sequence.

[0070] During the data return phase, such as Figure 2 medium signal and As shown, the narrow-bit data returned by the second bus data interface exhibits out-of-order and interleaving phenomena. Out-of-order refers to the returned data not being sent in the exact order requested. Return. Intertwining refers to different The corresponding narrow-bit data is returned in an interleaved manner, rather than in a single... Return continuously.

[0071] For example, in the ideal case where there is no out-of-order or interleaving, the return order should be: However, in real-world scenarios, the above order is disrupted.

[0072] like Figure 2 As shown, in this embodiment, due to the bit width conversion relationship is Therefore, a wide-bit data frame needs to be generated by splicing together four narrow-bit data frames, corresponding to the setting of four... Array unit ( to ). to express to The write enable signal. correspond Narrow-bit data snapshot writing, correspond Narrow-bit data snapshot writing, correspond Narrow-bit data snapshot writing, correspond Narrow-bit data is captured and written.

[0073] like Figure 2 As shown, to These represent linked lists corresponding to different splicing units. Each linked list contains 4 data positions ( to ), respectively used to store the contents of the splicing unit to Four narrow-bit data shots. Figure 2 The labels D0, D1, D2, and D3 indicate the four narrow data frames that constitute the same wide-bit data frame. Specifically, D0 corresponds to the 0th data position, D1 corresponds to the 1st data position, D2 corresponds to the 2nd data position, and D3 corresponds to the 3rd data position.

[0074] from Figure 2 As can be seen from the timing sequence, D0, D1, D2, and D3 in different linked lists do not arrive in a strictly fixed order, but rather exhibit interleaving and disorder. For example, linked lists... In this case, D3 arrives earlier than D0, or data from different linked lists are written in an interleaved manner.

[0075] The linked list control module does not concatenate the data according to the order in which the data arrives, but rather according to the read data identifier. Carried in and Determine the data location. Among these, Used to determine the linked list number ( ), Used to determine the corresponding linked list array During the data writing process, the corresponding data position is marked with a flag. It is set to valid to indicate that data has arrived at that location.

[0076] When all narrow-bit data frames corresponding to any splicing unit have been written to the read data module (i.e., D0, D1, D2, and D3 corresponding to that splicing unit have all arrived), to Corresponding linked list in array cell to All data packets have been received, and the stitching determination unit is generated. Signal. Figure 2 middle The sequential appearance of S3, S1, S0, and S2 indicates that different splicing units were not completed in the original order, but were determined to be completed according to the actual arrival time of their data. This mechanism demonstrates that the completion determination in this application does not depend on the order of data return, but rather on whether all data positions within each splicing unit are valid.

[0077] When the splicing determination unit detects all relevant... to All array units generate After receiving the signal, it is determined that all data in the splicing unit is ready, and the splicing control module sends signals to each... to The linked list control module in the middle initiates a read request (such as...) Figure 2 As shown to ).

[0078] According to the above embodiments, through the above processing method, even when the burst length is greater than 1 and narrow-bit data fragments are returned out of order or interleaved, the present invention can still achieve precise positioning and aggregation of narrow-bit data fragments based on the data fragment position index and transaction identifier, and trigger the splicing operation when all data positions are valid, thereby ensuring the correctness of the bit order and data integrity of the generated wide-bit data fragments. Simultaneously, the output interface module outputs each wide-bit data fragment sequentially according to the original burst order, ensuring that the first bus side maintains the same order and completion semantics as the original read transaction. Based on this, the present invention decouples the data return order from the splicing process, effectively reducing the impact of out-of-order returns on system performance, and improving the data processing capability and actual bandwidth utilization efficiency of the high-bit-width bus in multi-transaction concurrent scenarios.

[0079] This application provides a bus multi-shot data stitching method, applied to the aforementioned bus multi-shot data stitching system. This bus multi-shot data stitching method is based on the same inventive concept as the bus multi-shot data stitching system in one embodiment of this application, and the principle of solving the problem is similar. Therefore, the implementation of the bus multi-shot data stitching method is the same as the implementation of the bus multi-shot data stitching system in one embodiment of this application, and repeated details will not be described again. As used below, the terms "unit" or "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the system described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0080] The method for splicing multi-phase data on the bus includes: The transaction parsing module divides the read transaction based on the burst length information in the received read transaction, resulting in multiple splicing units.

[0081] The read data module receives the narrow data bits. It determines the data position based on the data bit position index and the new transaction identifier within the narrow data bit, writes the narrow data bit to the data position, and marks the corresponding status position as valid.

[0082] The splicing determination unit monitors the status flag bits corresponding to each data position in real time. When all the status flag bits corresponding to the splicing unit are valid, the splicing control module is triggered to splice each narrow data frame to obtain the spliced ​​wide data frame.

[0083] In some embodiments, the transaction parsing module receives read transactions through the first bus command interface. It parses the read transactions to obtain transaction identifier information and burst length information. The number of narrow data chunks is determined based on the data width of the first bus data interface and the data width of the second bus data interface. Corresponding splicing unit identifier information is assigned to each splicing unit.

[0084] In some embodiments, the identifier remapping module re-encodes the transaction identifier information and assigns a new transaction identifier. The mapping relationship between the transaction identifier information and the new transaction identifier is stored in the incomplete transaction identifier table.

[0085] In some embodiments, the identifier remapping module sends multiple narrow bit read requests to the second bus command interface based on the splicing unit identifier information and the number of narrow bit data frames.

[0086] In some embodiments, the read data module receives narrow-bit data ticks via the second bus data interface. The corresponding linked list number is determined based on the new transaction identifier, and the data position within the linked list number is determined based on the data tick position index.

[0087] In some embodiments, the splicing control module splices the narrow data frames stored in the data reading module into a wide data frame according to a preset data position order, and sends the wide data frame and its corresponding transaction identifier information to the output interface module.

[0088] In some embodiments, the output interface module sequentially outputs the wide bit data frames corresponding to each splicing unit through the first bus data interface.

[0089] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0090] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0091] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0092] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0093] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0094] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A bus-based multi-shot data splicing system, characterized in that, include: The transaction parsing module is used to divide the read transaction based on the burst length information in the received read transaction to obtain multiple splicing units; The data read module is used to receive narrow-bit data frames; The data position is determined based on the data position index and new transaction identifier in the narrow data position, and the narrow data position is written into the data position. The status mark corresponding to the data position is set to valid. The splicing determination unit is used to detect the status flag bits corresponding to each data position in real time. When the status flag bits of all data positions corresponding to the splicing unit are valid, the splicing control module is triggered to perform splicing operation on each narrow data frame to obtain the spliced ​​wide data frame.

2. The system according to claim 1, characterized in that, The transaction parsing module is also used to receive read transactions through the first bus command interface; parse the read transactions to obtain transaction identification information and burst length information; determine the number of narrow data blocks based on the data bit width of the first bus data interface and the data bit width of the second bus data interface; and assign corresponding splicing unit identification information to each splicing unit.

3. The system according to claim 2, characterized in that, Also includes: The identifier remapping module is used to re-encode the transaction identifier information and assign a new transaction identifier; The mapping relationship between the transaction identifier information and the new transaction identifier is stored in the incomplete transaction identifier table.

4. The system according to claim 3, characterized in that, The identifier remapping module is also used to send multiple narrow-bit read requests to the second bus command interface based on the splicing unit identifier information and the number of narrow-bit data snapshots.

5. The system according to claim 2, characterized in that, The data reading module is specifically used to receive the narrow-bit data tick through the second bus data interface; determine the corresponding linked list number based on the new transaction identifier; and determine the data position in the linked list number based on the data tick position index.

6. The system according to claim 1, characterized in that, The splicing control module is specifically used to splice the narrow data frames stored in the read data module into a wide data frame according to the preset data position order, and send the wide data frame and its corresponding transaction identifier information to the output interface module.

7. The system according to claim 2, characterized in that, Also includes: The output interface module is used to sequentially output the wide-bit data frames corresponding to each of the splicing units through the first bus data interface.

8. A method for multi-shot data splicing on a bus, characterized in that, include: The transaction parsing module divides the read transaction based on the burst length information in the received read transaction, resulting in multiple concatenation units; The data reading module receives narrow-bit data frames; The data position is determined based on the data position index and new transaction identifier in the narrow data position, and the narrow data position is written into the data position. The status mark corresponding to the data position is set to valid. The splicing determination unit detects the status flag bits corresponding to each data position in real time; when the status flag bits of all data positions corresponding to the splicing unit are valid, the splicing control module is triggered to perform splicing operation on each narrow data frame to obtain the spliced ​​wide data frame.

9. A chip, characterized in that, The system includes the bus multi-shot data splicing system according to any one of claims 1 to 7.

10. A circuit board, characterized in that, Includes the chip described in claim 9.

11. An electronic device, characterized in that, Includes the board as described in claim 10.

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