An asn.1 bit stream parsing method, system and device across segmented cache

Abstract

The application provides an ASN.1 bit stream parsing method, system and device across segmented caches, wherein the method comprises the following steps: receiving ASN.1 encoded data to be parsed; the ASN.1 encoded data is stored in multiple cache segments; a bit stream context is established; the ASN.1 encoded data is read according to the bit stream context; when the remaining data of the current cache segment is insufficient, the next cache segment is automatically switched to; the bit stream reading is continuously performed until the ASN.1 field parsing is completed; an ASN.1 object tree is constructed according to the reading result; and the parsing result is output. By implementing the application, ASN.1 data decoding can be completed without constructing a continuous cache, the memory copy overhead is reduced, the protocol parsing performance is improved, and the application is suitable for scenarios such as LTE, 5G NR, core network signaling parsing, communication monitoring, protocol analyzer, communication control equipment and network security equipment.

Description

Technical Field

[0001] This invention relates to the field of communication protocol parsing technology, and in particular to a method, system and apparatus for parsing ASN.1 bitstream across segmented buffers, which can be applied to scenarios such as LTE, 5G NR, core network signaling parsing, communication monitoring, protocol analyzers, communication management and control equipment and network security equipment. Background Technology

[0002] In mobile communication systems, many control plane protocols use the ASN.1 (Abstract Syntax Notation One) encoding format for message encapsulation. Examples include: LTE RRC (Long Term Evolution Radio Resource Control), NR RRC (Next Radio Radio Resource Control), NAS (Non-Access Stratum), S1AP (S1 Application Protocol), NGAP (Next Generation Application Protocol), X2AP (X2 Application Protocol), and F1AP (F1 Application Protocol). These protocols typically employ PER (Packed Encoding Rules), UPER (Unaligned PER), or APER (Aligned PER) encoding methods.

[0003] Existing ASN.1 parsers typically require the data to be parsed to reside in a contiguous memory space during decoding. Therefore, upon receiving a network data packet, a buffer reassembly operation must be performed first. Network receive buffer → continuous buffer copying → ASN.1 decoding. However, in high-speed network scenarios, data is often stored in multiple segmented buffers (e.g., Segment0, Segment1, Segment2, Segment3). Existing technologies require reassembling multiple buffer segments into a continuous buffer. This process has the following problems: (1) it generates additional memory copying overhead; (2) it increases the CPU (Central Processing Unit) load; (3) it increases the buffer miss rate; (4) it reduces protocol parsing throughput; and (5) it increases parsing latency. Therefore, a method is needed to complete ASN.1 parsing without buffer reassembly. Summary of the Invention

[0004] This invention provides an ASN.1 bitstream parsing method across segmented buffers, which completes ASN.1 data decoding without constructing contiguous buffers, thereby reducing memory copying overhead and improving protocol parsing performance.

[0005] In a first aspect, the present invention provides a method for parsing ASN.1 bitstreams across segmented buffers, the method comprising: Receive ASN.1 encoded data to be parsed; the ASN.1 encoded data is stored in multiple buffer segments; Establish a bitstream context; Read ASN.1 encoded data bit by bit according to the bit stream context; Automatically switch to the next cache segment when the current cache segment has insufficient remaining data; Continue reading the bitstream until the ASN.1 field is parsed. Construct an ASN.1 object tree based on the read results; Output the parsing results.

[0006] In the above implementation, by establishing a bitstream context and automatically switching buffer segments during the reading process, ASN.1 decoding can be completed without reassembling multiple segmented buffers into a continuous buffer, which significantly reduces memory copying overhead, improves protocol parsing throughput, and reduces parsing latency.

[0007] Furthermore, the bitstream context establishment includes: establishing the following data structure: typedef struct {segment *segment; uint32_t segment_index; uint32_t byte_offset; uint32_t bit_offset; uint32_t read_length; uint32_t segment_length; AsnBitStream; Where: segment represents the cache segment linked list; segment_index represents the current cache segment index; byte_offset represents the current byte offset; bit_offset represents the current bit offset; read_length represents the length of the stream to be read; segment_length represents the length of the current cache segment.

[0008] Furthermore, the cross-segment (cache boundary) read includes: when reading n bytes of data, first calculate the number of remaining bytes in the current cache segment; if the number of remaining bytes meets the requirements, then read directly; otherwise, after reading the remaining bytes, automatically switch to the next cache segment and continue to complete the reading of the remaining bytes.

[0009] Furthermore, the automatic cross-segment switching includes: when read_length >= segment_length - byte_offset, executing segment_index++ and automatically updating segment, byte_offset, and bit_offset, thereby completing cross-cache reading.

[0010] Furthermore, the bitwise read supports cross-byte and cross-cache joint parsing: when the ASN.1 field crosses both byte boundaries and cache boundaries, the bitstream read module automatically concatenates the bit data. For example, if Segment0 is 11110010 and Segment1 is 10101111, when reading 12 bits of data, 111100101010 is automatically generated without cache reorganization.

[0011] Furthermore, the ASN.1 decoder accesses the bit stream through a unified interface: uint32_t read_bits(AsnBitStream *stream, uint32_t nbits); the decoder does not need to be aware of the number of buffer segments, the location of buffer boundaries, or the memory layout.

[0012] Secondly, the present invention also provides an ASN.1 parsing system, the system comprising: a cache management module for managing ASN.1 encoded data in multiple cache segments; a bit stream reading module for reading ASN.1 encoded data bit by bit according to the bit stream context; a cross-segment (cache boundary) switching module for detecting cache boundaries during the reading process and automatically switching to the next cache segment when the cache boundary is reached; and an ASN.1 decoding module for completing ASN.1 decoding based on the read bit data.

[0013] Thirdly, the present invention provides an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the method described in the first aspect.

[0014] Fourthly, the present invention provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the method described in the first aspect.

[0015] Fifthly, the present invention provides a computer program product that, when run on a computer, causes the computer to perform the method described in the first aspect.

[0016] Other features and advantages of this disclosure will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0017] It can be implemented in accordance with the contents of the specification. The preferred embodiments of this application are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating the ASN.1 bitstream parsing method for cross-segmented buffers provided in this embodiment of the invention; Figure 2 A schematic diagram of the structural composition of the ASN.1 bitstream parsing system with cross-segment caching provided in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating cross-segment bit reading provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structural composition of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the present invention will now be described with reference to the accompanying drawings in the embodiments of the present invention.

[0021] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0023] Example 1: A method for parsing ASN.1 bitstreams across segmented buffers Figure 1This is a flowchart illustrating the ASN.1 bitstream parsing method for cross-segment caching provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the method includes: Receive ASN.1 encoded data to be parsed; the ASN.1 encoded data is stored in multiple buffer segments; S1, Receive the ASN.1 encoded data to be parsed; S2, establish bitstream context; S3, read ASN.1 encoded data bit by bit according to the bit stream context; S4: Automatically switch to the next cache segment when the current cache segment has insufficient remaining data; S5, continue performing bitstream reading until the ASN.1 field parsing is complete; S6, construct the ASN.1 object tree based on the read results; S7 outputs the parsing results.

[0024] In the above implementation, by establishing a bitstream context and automatically switching buffer segments during the reading process, ASN.1 decoding can be completed without reassembling multiple segmented buffers into a continuous buffer, which significantly reduces memory copying overhead, improves protocol parsing throughput, and reduces parsing latency.

[0025] In this embodiment of the invention, the ASN.1 encoded data is stored in multiple buffer segments, such as Segment0, Segment1, Segment2, Segment3, etc. The ASN.1 encoded data comes from LTE RRC protocol, NR RRC protocol, NAS protocol, S1AP protocol, NGAP protocol, X2AP protocol, or F1AP protocol. The above protocols typically use PER, UPER, or APER encoding methods.

[0026] Furthermore, establishing the bitstream context in step S2 includes: establishing the following data structure: typedef struct { segment *segment; uint32_t segment_index; uint32_t byte_offset; uint32_t bit_offset; uint32_t read_length; uint32_t segment_length; AsnBitStream; Where: segment represents the cache segment linked list; segment_index represents the current cache segment index; byte_offset represents the current byte offset; bit_offset represents the current bit offset; read_length represents the length of the stream to be read; segment_length represents the length of the current cache segment.

[0027] Furthermore, the bitwise reading in step S3 includes: when reading n bytes of data, first calculate the number of remaining bytes in the current cache segment; if the number of remaining bytes meets the requirements, then read directly; otherwise, after reading the remaining bytes, automatically switch to the next cache segment and continue to complete the reading of the remaining bytes.

[0028] Furthermore, the automatic switching to the next cache segment in step S4 includes: when read_length >= segment_length - byte_offset, executing segment_index++ and automatically updating segment, byte_offset, and bit_offset, thereby completing the cross-cache segment read.

[0029] Furthermore, the bitwise read supports cross-byte and cross-cache joint parsing: when the ASN.1 field crosses both byte boundaries and cache boundaries, the bitstream read module automatically concatenates the bit data. For example, if Segment0 is 11110010 and Segment1 is 10101111, when reading 12 bits of data, 111100101010 is automatically generated without cache reorganization.

[0030] Furthermore, the ASN.1 decoder accesses the bit stream through a unified interface: uint32_t read_bits(AsnBitStream *stream, uint32_t nbits); the decoder does not need to be aware of the number of buffer segments, the location of buffer boundaries, or the memory layout.

[0031] Example 2: A system for parsing ASN.1 bitstreams across segmented buffers To implement the method corresponding to Embodiment 1 above and achieve the corresponding functions and technical effects, an ASN.1 parsing system is provided below, such as... Figure 2 As shown, the system includes: Cache management module 1 is used to manage ASN.1 encoded data in multiple cache segments; Bit stream reading module 2 is used to read ASN.1 encoded data bit by bit according to the bit stream context; The cross-segment switching module 3 is used to detect cache boundaries during the reading process and automatically switch to the next cache segment when the cache boundary is reached. ASN.1 decoding module 4 is used to complete ASN.1 decoding based on the read bit data.

[0032] In the above implementation process, through the collaborative work of each module, ASN.1 decoding can be completed without reassembling multiple segmented buffers into a continuous buffer, which significantly reduces memory copying overhead, improves protocol parsing throughput, and reduces parsing latency.

[0033] Furthermore, the bit stream reading module 2 is also used to: establish a bit stream context, which includes at least a cache segment index, a byte offset, and a bit offset.

[0034] Furthermore, the bitstream reading module 2 is also used to support cross-byte boundary reading and cross-buffer boundary reading.

[0035] Furthermore, the cross-segment switching module 3 is also used to: increment the cache segment index by 1 and update the byte offset and bit offset when the byte offset of the current cache segment is greater than or equal to the length of the current cache segment.

[0036] The ASN.1 parsing system described above can implement the method of Embodiment 1. The options in Embodiment 1 also apply to this embodiment, and will not be described in detail here.

[0037] Example 3: Apparatus for parsing ASN.1 bitstreams across segmented buffers This invention provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor runs the computer program to enable the electronic device to perform the ASN.1 bitstream parsing method across segmented buffers according to Embodiment 1.

[0038] Optionally, the aforementioned electronic device may be a server, a protocol analyzer, a communication control device, or a network security device.

[0039] Please see Figure 4 , Figure 4 This is a schematic diagram illustrating the structural composition of an electronic device provided in an embodiment of the present invention. The electronic device may include a processor 41, a communication interface 42, a memory 43, and at least one communication bus 44. The communication bus 44 is used to enable direct communication between these components. In this embodiment, the communication interface 42 is used for signaling or data communication with other node devices. The processor 41 may be an integrated circuit chip with signal processing capabilities.

[0040] The processor 41 described above can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor, or the processor 41 can be any conventional processor.

[0041] The memory 43 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc. The memory 43 stores computer-readable instructions. When these computer-readable instructions are executed by the processor 41, the device can perform the aforementioned operations. Figure 1 The various steps involved in the method implementation examples.

[0042] Optionally, the electronic device may also include a storage controller and an input / output unit. The memory 43, storage controller, processor 41, peripheral interface, and input / output unit are electrically connected directly or indirectly to each other to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses 44. The processor 41 is used to execute executable modules stored in the memory 43, such as software function modules or computer programs included in the device.

[0043] Input / output units are used to enable users to create tasks and set optional start periods or preset execution times for those tasks, facilitating user-server interaction. Input / output units can be, but are not limited to, a mouse and keyboard.

[0044] Understandable. Figure 4 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 4 The more or fewer components shown, or having the same Figure 4 The different configurations shown. Figure 4The components shown can be implemented using hardware, software, or a combination thereof.

[0045] In addition, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the ASN.1 bitstream parsing method across segmented caches as described in Embodiment 1.

[0046] This invention also provides a computer program product that, when run on a computer, causes the computer to perform the method described in the method embodiment.

[0047] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using dedicated hardware-based apparatus that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0048] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0049] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, external hard drives, ROM, RAM, magnetic disks, or optical disks.

[0050] The above description is merely an embodiment of the present invention and is not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0051] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0052] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for parsing ASN.1 bitstreams across segmented buffers, characterized in that, The method includes: Receive ASN.1 encoded data to be parsed; the ASN.1 encoded data is stored in multiple buffer segments; Establish a bitstream context; Read ASN.1 encoded data bit by bit according to the bit stream context; Automatically switch to the next cache segment when the current cache segment has insufficient remaining data; Continue reading the bitstream until the ASN.1 field is parsed. Construct an ASN.1 object tree based on the read results; Output the parsing results.

2. The method according to claim 1, characterized in that: The bitstream context includes at least: Cache segment index; Byte offset; Bit offset.

3. The method according to claim 1, characterized in that: The bitwise read supports cross-byte boundaries and cross-segment (cache boundary) reads.

4. The method according to claim 1, characterized in that: The ASN.1 encoding includes PER encoding, UPER encoding, and APER encoding.

5. The method according to claim 1, characterized in that: The automatic switching to the next cache segment includes: When the byte offset of the current cache segment is greater than or equal to the length of the current cache segment, increment the cache segment index by 1; Update the byte offset and bit offset.

6. The method according to claim 1, characterized in that: The bit-by-bit reading is implemented through a unified bit stream reading interface. The ASN.1 decoder accesses the bit stream through the interface without needing to be aware of the number of cache segments, the location of cache boundaries, or the memory layout.

7. An ASN.1 parsing system, characterized in that, The system includes: The cache management module is used to manage ASN.1 encoded data in multiple cache segments; The bit stream reading module is used to read ASN.1 encoded data bit by bit according to the bit stream context. The cross-segment (cache boundary) switching module is used to detect cache boundaries during the reading process and automatically switch to the next cache segment when the cache boundary is reached; The ASN.1 decoding module is used to complete ASN.1 decoding based on the read bit data; The modules described therein are used to perform the method according to any one of claims 1 to 6.

8. An electronic device, characterized in that, include: processor; Memory; The memory stores a program; The modules described therein are used to perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, It contains a program that, when executed, implements the method described in any one of claims 1 to 6.

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