Semiconductor device and manufacturing method, operating method, and memory system

Abstract

Embodiments of the present application provide a semiconductor device, a manufacturing method and an operating method thereof, and a memory system. The semiconductor device includes a semiconductor pillar extending along a first direction, and a gate structure located at at least one side of the semiconductor pillar along a second direction, and including a first portion and a second portion spaced apart from each other and arranged along the first direction. The second direction intersects the first direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, its manufacturing method, operating method, and memory system. Background Technology

[0002] As the integration level of semiconductor devices increases and their size and critical dimensions continue to shrink, the requirements for their reliability are becoming increasingly stringent, indicating that there is still much room for improvement in semiconductor device performance. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a semiconductor device and a method for manufacturing the same, a method for operating the same, and a memory system thereof.

[0004] In a first aspect, this application provides a semiconductor device comprising: a semiconductor pillar extending along a first direction; a gate structure located on at least one side of the semiconductor pillar along a second direction, comprising a first portion and a second portion spaced apart from each other and arranged along the first direction; the second direction intersecting the first direction.

[0005] In some embodiments, the semiconductor pillar includes a channel region, a first end portion and a second end portion located at both ends of the channel region; wherein the first portion overlaps with the channel region at least along a second direction, and the second portion overlaps with the first end portion at least along a second direction.

[0006] In some embodiments, the gate structure further includes a third portion; the first portion, the second portion, and the third portion are spaced apart from each other and arranged along a first direction; wherein the third portion overlaps at least with the second end along a second direction.

[0007] In some embodiments, the semiconductor device includes a semiconductor pillar array consisting of a plurality of semiconductor pillars located in a first region; a plurality of gate structures correspond to the plurality of semiconductor pillars; the semiconductor device further includes a word line structure extending along the row direction of the semiconductor pillar array; the word line structure extends within the first region and partially extends outside the first region; the word line structure includes a first conductive portion and a second conductive portion spaced apart from each other and arranged along a first direction; the first conductive portion extends along the row direction and includes a first portion of a row gate structure within the first region and a first end located outside the first region, the second conductive portion extends along the row direction and includes a second portion of a row gate structure within the first region and a second end located outside the first region; the first end and the second end are staggered from each other along the row direction.

[0008] In some embodiments, the first end has a first dimension along the row direction, and the second end has a second dimension along the row direction; the second end is located above the first end, and the second dimension is smaller than the first dimension.

[0009] In some embodiments, the semiconductor device further includes: a memory structure stacked with a corresponding semiconductor pillar and in contact with a first end of the corresponding semiconductor pillar; a bit line structure extending along a column direction and in contact with a second end of the corresponding semiconductor pillar; and a word line contact structure extending along a first direction and in contact with the corresponding word line structure on the side near the bit line structure.

[0010] In some embodiments, the spacing between the first portion and the second portion along the first direction is less than or equal to 10 nm.

[0011] In some embodiments, the ratio between the dimension of the second portion in the first direction and the dimension of the gate structure in the first direction ranges from 10% to 30%.

[0012] In some embodiments, the gate structure is located on one or both sides of the semiconductor pillar along the second direction, the gate structure is located on both sides of the semiconductor pillar along the second direction and on one side of the semiconductor pillar along a third direction different from the second direction, or the gate structure surrounds the semiconductor pillar; the third direction intersects with the first direction.

[0013] In some embodiments, the semiconductor device is configured such that: a first portion receives a first voltage and a second portion receives a second voltage; the first voltage and the second voltage are different, such that the semiconductor pillar is in a first state; or, the first voltage and the second voltage are the same, such that the semiconductor pillar is in a second state different from the first state.

[0014] In some embodiments, the semiconductor device is configured such that: a first portion receives a first voltage, a second portion receives a second voltage, and a third portion receives a third voltage; the first voltage is different from the second voltage and the third voltage, such that the semiconductor pillar is in a first state; or, the first voltage, the second voltage, and the third voltage are all the same, such that the semiconductor pillar is in a second state different from the first state.

[0015] In a second aspect, embodiments of this application provide a method for manufacturing a semiconductor device, the method comprising: forming a semiconductor pillar array including a plurality of semiconductor pillars; extending the semiconductor pillars along a first direction; forming a gate structure located on at least one side of the semiconductor pillars along a second direction and a word line structure extending along the row direction of the semiconductor pillar array; wherein the gate structure includes a first portion and a second portion spaced apart from each other and arranged along the first direction; the word line structure includes a first conductive portion and a second conductive portion spaced apart from each other and arranged along the first direction; the first conductive portion extends along the row direction and includes a first portion of a row gate structure located in a first region, the second conductive portion extends along the row direction and includes a second portion of a row gate structure; the second direction intersects the first direction.

[0016] In some embodiments, forming a gate structure located on at least one side of a semiconductor pillar along a second direction and a word line structure extending along the row direction of a semiconductor pillar array includes: forming a first precursor conductive structure on one side where a first end of the semiconductor pillar is located; the first precursor conductive structure is located on at least one side of a second end of the semiconductor pillar along the second direction; forming second to third conductive structures spaced apart from the first precursor conductive structure on the first precursor conductive structure; the second to third conductive structures are located on at least one side of a channel region of the semiconductor pillar along the second direction, and on at least one side of the first end of the semiconductor pillar along the second direction; wherein the first end and the second end are respectively located at both ends of the channel region; on one side where the second end of the semiconductor pillar is located, removing a portion of the first precursor conductive structure along a first direction to form a first conductive structure; the first conductive structure is located on at least one side of the second end of the semiconductor pillar along the second direction; wherein the first conductive portion corresponds to the second to third conductive structures; the second conductive portion... The portion corresponds to the first conductive structure; or, on one side where the first end of the semiconductor pillar is located, a first to a second precursor conductive structure is formed; the first to a second precursor conductive structure is located on at least one side of the second end of the semiconductor pillar along the second direction, and on at least one side of the channel region of the semiconductor pillar along the second direction; a third conductive structure is formed on the first to a second precursor conductive structure, spaced apart from the first to a second precursor conductive structure; the third conductive structure is located on at least one side of the first end of the semiconductor pillar along the second direction; wherein the first end and the second end are respectively located at both ends of the channel region; on one side where the second end of the semiconductor pillar is located, a portion of the first precursor conductive structure is removed along the first direction to form the first conductive structure; the first conductive structure is located on at least one side of the second end of the semiconductor pillar along the second direction, and on at least one side of the channel region of the semiconductor pillar along the second direction; wherein the first conductive portion corresponds to the first to a second conductive structure; the second conductive portion corresponds to the third conductive structure.

[0017] In some embodiments, forming a gate structure located on at least one side of a semiconductor pillar along a second direction and a word line structure extending along the row direction of a semiconductor pillar array includes: forming a first precursor conductive structure on one side where a first end of the semiconductor pillar is located; the first precursor conductive structure being located on at least one side of a second end of the semiconductor pillar along the second direction; forming a second conductive structure spaced apart from the first precursor conductive structure on the first precursor conductive structure; the second conductive structure being located on at least one side of a channel region of the semiconductor pillar along the second direction; wherein the first end and the second end are respectively located at both ends of the channel region; forming a third conductive structure spaced apart from the second conductive structure on the second conductive structure; the third conductive structure being located on at least one side of a channel region of the semiconductor pillar. At least one side of the first end along the second direction; on the side where the second end of the semiconductor pillar is located, a portion of the first precursor conductive structure is removed along the first direction to form a first conductive structure; the first conductive structure is located at least one side of the second end of the semiconductor pillar along the second direction; wherein, the gate structure includes a first portion, a second portion, and a third portion spaced apart from each other and arranged along the first direction; the word line structure includes a first conductive portion, a second conductive portion, and a third conductive portion spaced apart from each other and arranged along the first direction; wherein, the third conductive portion extends along the row direction and includes a third portion of a row gate structure; wherein, the first conductive portion corresponds to the second conductive structure; the second conductive portion corresponds to the third conductive structure; and the third conductive portion corresponds to the first conductive structure.

[0018] In some embodiments, the manufacturing method further includes: on one side where the second end of the semiconductor pillar is located, sequentially removing a portion of the material from a plurality of ends corresponding to the word line structure, such that the plurality of ends are staggered from each other along a first direction; wherein the plurality of ends are used to lead out the word line structure along one side of the first direction.

[0019] In some embodiments, before sequentially removing a portion of the material at the multiple ends corresponding to the word line structure, the manufacturing method further includes: forming a memory structure on one side where the first end of the semiconductor pillar is located; stacking the memory structure with the corresponding semiconductor pillar and contacting the first end of the corresponding semiconductor pillar; forming a bit line structure on one side where the second end of the semiconductor pillar is located; extending the bit line structure along the column direction and contacting the second end of the corresponding semiconductor pillar; after sequentially removing a portion of the material at the multiple ends corresponding to the word line structure, the manufacturing method further includes: forming a word line contact structure on one side where the second end of the semiconductor pillar is located; extending along a first direction and contacting the word line structure on the side near the bit line structure.

[0020] In some embodiments, the process of sequentially removing partial material from multiple ends corresponding to the word line structure includes: forming a mask covering the second end; performing multiple exposure-development-etching steps on the mask to sequentially remove partial material from each end, forming multiple ends staggered along a first direction; wherein each exposure-development-etching step removes partial material from one end; and forming a word line contact structure includes: etching along the first direction on one side where the second end of the semiconductor pillar is located to form a word line contact hole extending to the word line structure; and filling the word line contact hole with conductive material to form the word line contact structure.

[0021] Thirdly, embodiments of this application provide a memory system, the memory system comprising: a memory, the memory including any of the semiconductor devices provided in the first aspect; and a controller connected to the memory.

[0022] Fourthly, an embodiment of this application provides an operation method for a semiconductor device, the semiconductor device including a semiconductor pillar extending along a first direction and a gate structure located on at least one side of the semiconductor pillar along a second direction; the operation method includes: applying a first voltage to a first portion of the gate structure and applying a second voltage to a second portion of the gate structure; the first voltage and the second voltage are different, so that the semiconductor pillar is in a first state; or, the first voltage and the second voltage are the same, so that the semiconductor pillar is in a second state different from the first state; wherein the first portion and the second portion are spaced apart from each other and arranged along the first direction; the second direction intersects the first direction; or, applying a first voltage to the first portion of the gate structure, applying a second voltage to the second portion of the gate structure, and applying a third voltage to a third portion of the gate structure; the first voltage, the second voltage, and the third voltage are all different, so that the semiconductor pillar is in a first state; or, the first voltage, the second voltage, and the third voltage are all the same, so that the semiconductor pillar is in a second state different from the first state; wherein the first portion, the second portion, and the second portion are spaced apart from each other and arranged along the first direction; the second direction intersects the first direction.

[0023] In some embodiments, the second voltage is different from both the first voltage and the third voltage, including: the first voltage is equal to the third voltage.

[0024] In various embodiments of this application, the semiconductor device includes a semiconductor pillar extending along a first direction and a gate structure located on at least one side of the semiconductor pillar along a second direction. The gate structure includes a first portion and a second portion spaced apart from each other and arranged along the extension direction of the semiconductor pillar. For example, the first portion and the second portion can be adapted to receive different voltages separately to ensure that the semiconductor device reduces the gate-induced drain leakage current of the semiconductor device without losing or with minimal loss of the on-state current of the semiconductor device. Attached Figure Description

[0025] Figures 1A to 1D Cross-sectional schematic diagrams of some semiconductor devices provided in the embodiments of this application;

[0026] Figures 2A to 4C Plan view and cross-sectional view of some semiconductor devices provided for embodiments of this application;

[0027] Figure 5 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application;

[0028] Figures 6A to 17C A plan view and a cross-sectional view of the manufacturing process of the first semiconductor device provided in the embodiments of this application;

[0029] Figures 18A to 18F A cross-sectional schematic diagram of the manufacturing process of a second type of semiconductor device provided in an embodiment of this application;

[0030] Figures 19A to 19F A cross-sectional schematic diagram of the manufacturing process of the third type of semiconductor device provided in the embodiments of this application;

[0031] Figure 20 A schematic diagram of a memory system provided in an embodiment of this application;

[0032] Figure 21 This is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of this application. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0035] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0040] Leakage current has always been a major cause of device failure in memory device design. The leakage current of the cell transistor in memory devices is mainly due to gate-induced drain leakage current (GIDL). Therefore, how to solve GIDL is a crucial issue.

[0041] In memory devices, the gate, drain, and source of a cell transistor have overlapping regions. Specifically, the lightly doped drain (LDD) region of the drain region overlaps with the gate, and the lightly doped source (LDS) region overlaps with the source. The overlapping region between the gate and drain of a cell transistor in a memory device is crucial for balancing the off-state and on-state currents of the transistor. For example, if the gate and drain are perfectly aligned with no overlap, both the off-state and on-state currents will be small. Conversely, if there is significant overlap, both the on-state and off-state currents will be large. Therefore, a reasonable overlap between the gate and drain is necessary to balance the off-state and on-state currents. Reducing leakage current caused by GIDL (Gate-Doped Drain) is a pressing technical problem that needs to be solved.

[0042] In view of the above, embodiments of this application provide a semiconductor device and a method for manufacturing the same, a method for operating the same, and a memory system thereof.

[0043] Figures 1A to 1D Cross-sectional schematic diagrams of some semiconductor devices provided in the embodiments of this application. Figures 1A to 1D The semiconductor device shown can be understood as a semiconductor device including a semiconductor pillar. (Reference) Figures 1A to 1D According to a first aspect of the embodiments of this application, a semiconductor device is provided. Figures 1A to 1D The semiconductor device includes: a semiconductor pillar extending along a first direction; a gate structure located on at least one side of the semiconductor pillar along a second direction, including a first portion and a second portion spaced apart from each other and arranged along the first direction; the second direction intersects the first direction.

[0044] In the various embodiments of this application, the first direction can be understood as the direction of stacking of various elements, components, regions, layers or parts, or the direction of extension of semiconductor pillars. Two directions that are different from the second direction (e.g., the third direction is orthogonal to the second direction) intersect (e.g., are orthogonal to) the first direction. For example, the first direction is represented by the Z direction in the figures; the second direction is represented by the Y direction in the figures; and the third direction is represented by the X direction in the figures.

[0045] The semiconductor device provided in this application embodiment can reduce leakage current caused by GIDL without losing or with minimal loss of the on-state current of the semiconductor device.

[0046] refer to Figure 1A In some embodiments, the semiconductor pillar 106 includes a channel region CH, a first end portion SD1 located at both ends of the channel region CH, and a second end portion SD2 located at both ends of the channel region CH; wherein the first portion SD1 overlaps with the channel region CH at least along a second direction, and the second portion SD2 overlaps with the second end portion SD2 at least along a second direction.

[0047] The term "overlap" can be understood as the projections overlapping along a certain direction or in a certain plane. For example, the projections of the first part GS1 and the channel region CH along the second direction overlap, or the projections in the XZ plane overlap.

[0048] Here and below, the first end SD1 and the second end SD2 are two opposite ends of the semiconductor pillar 106. For example, the first end SD1 is the source region of the semiconductor pillar 106 and the second end SD2 is the drain region of the semiconductor pillar 106. Alternatively, the first end SD1 is the drain region of the semiconductor pillar 106 and the second end SD2 is the source region of the semiconductor pillar 106.

[0049] For example, the first portion GS1 overlaps with the projection of the LDS region and the channel region CH along the second direction, and the second portion GS2 overlaps with the projection of the LDD region along the second direction. For example, the first portion GS1 covers a portion of the gate dielectric layer 110 corresponding to the LDS region and the channel region CH, and the second portion GS2 covers at least a portion of the gate dielectric layer 110 corresponding to the LDD region, wherein the gate dielectric layer 110 is located on one side of the semiconductor pillar 106 along the second direction and extends along the first direction and covers the semiconductor pillar 106.

[0050] Compared to Figure 1B The semiconductor device shown is an improvement on the LDS of semiconductor pillars. Figure 1A The semiconductor device shown is improved by modifying the LDD of the semiconductor pillar, which is more conducive to reducing the leakage current caused by the GIDL of the semiconductor device.

[0051] refer to Figure 1BIn some embodiments, the semiconductor pillar 106 includes a channel region CH, a first end SD1 located at both ends of the channel region CH, and a second end SD2; wherein the first part SD1 overlaps with the channel region CH at least along a second direction, and the second part SD2 overlaps with the first end SD1 at least along a second direction.

[0052] For example, the first portion GS1 overlaps with the projection of the LDD region and the channel region CH along the second direction, and the second portion GS2 overlaps with the projection of the LDS region along the second direction. For example, the first portion GS1 covers a portion of the gate dielectric layer 110 corresponding to the LDD region and the channel region CH, and the second portion GS2 covers at least a portion of the gate dielectric layer 110 corresponding to the LDS region, wherein the gate dielectric layer 110 is located on one side of the semiconductor pillar 106 along the second direction and extends along the first direction and covers the semiconductor pillar 106.

[0053] refer to Figure 1C In some embodiments, the gate structure further includes a third portion GS3; the first portion GS1, the second portion GS2 and the third portion GS3 are spaced apart from each other and arranged along a first direction; wherein the third portion GS3 overlaps at least with the second end SD2 along a second direction.

[0054] For example, the first portion GS1 overlaps with the channel region CH along the second direction, the second portion GS2 overlaps with the LDS region along the second direction, and the third portion GS3 overlaps with the LDD region along the second direction. For example, the first portion GS1 covers a portion of the gate dielectric layer 110 corresponding to the channel region CH, and the second portion GS2 covers at least a portion of the gate dielectric layer 110 corresponding to the LDS region, wherein the gate dielectric layer 110 is located on one side of the semiconductor pillar 106 along the second direction and extends along the first direction and covers the semiconductor pillar 106.

[0055] In other embodiments, Figure 1D The semiconductor device shown can Figure 1C To understand this, we can interchange the positions of the second and third parts in the semiconductor device shown.

[0056] refer to Figure 1A and Figure 1B In some embodiments, the spacing between the first portion and the second portion along the first direction is less than or equal to 10 nm. (See reference...) Figure 1C and Figure 1D In some embodiments, the spacing between the first part and the second part, as well as between the first part and the third part along the first direction, is less than or equal to 10 nm.

[0057] For example, refer to Figure 1AThe first part and the second part are separated by a first spacer CO1, the first spacer CO1 having a first pitch GAP1 along the extending direction of the semiconductor pillar, the first pitch GAP1 being less than or equal to 10 nm. (Reference) Figure 1B The first part and the second part are separated by a second spacer CO2, which has a second spacing GAP2 along the extension direction of the semiconductor pillar, and the second spacing GAP2 is less than or equal to 10 nm. (Reference) Figure 1C and Figure 1D The first part, the second part, and the second part are separated by a first spacer CO1 and a second spacer CO2, respectively. The first spacer CO1 has a first spacing GAP1 along the extension direction of the semiconductor pillar, and the second spacer CO2 has a second spacing GAP2 along the extension direction of the semiconductor pillar. Both the first spacing GAP1 and the second spacing GAP2 are less than or equal to 10 nm. Preferably, the range of the first spacing GAP1 and / or the second spacing CO2 is 2 nm to 6 nm, for example, it can be 3 nm, 4 nm, or 5 nm.

[0058] refer to Figure 1A and Figure 1B In some embodiments, the ratio between the dimension of the second portion in the first direction and the dimension of the gate structure in the first direction ranges from 10% to 30%. (Reference) Figure 1C and Figure 1D In some embodiments, the ratios of the dimensions of the second and third portions in the first direction to the dimensions of the gate structure in the first direction are both in the range of 10% to 30%.

[0059] For example, refer to Figure 1A and Figure 1B The ratio of the dimension of the second part in the semiconductor pillar extension direction to the dimension of the gate structure in the semiconductor pillar extension direction is 20%. (Reference) Figure 1C and Figure 1D The ratio of the dimensions of the second and third parts in the semiconductor pillar extension direction to the dimensions of the gate structure in the semiconductor pillar extension direction is 20%.

[0060] The gate structures of the semiconductor devices shown in the various embodiments of this application are applicable to gates of any architecture and are not limited to any particular architecture. Figures 1A to 1DThe illustration shows a gate structure covering one sidewall of a semiconductor pillar. In some embodiments, the gate structure is located on one or both sides of the semiconductor pillar along the second direction, the gate structure is located on both sides of the semiconductor pillar along the second direction and on one side of the semiconductor pillar along a third direction different from the second direction, or the gate structure surrounds the semiconductor pillar; the third direction intersects the first direction. Exemplarily, the gate structure can be a back-to-back gate structure or a gate-all-around gate structure.

[0061] In some embodiments, the semiconductor device is configured such that: a first portion receives a first voltage and a second portion receives a second voltage; the first voltage and the second voltage are different, such that the semiconductor pillar is in a first state; or, the first voltage and the second voltage are the same, such that the semiconductor pillar is in a second state different from the first state.

[0062] Here and below, the term "different" should be understood adaptively according to the type of semiconductor device, and the term "same" should be understood as identical within the tolerance range allowed by the process / operation.

[0063] Taking an N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) as an example, the semiconductor pillar 106 is a P-channel metal-oxide-semiconductor. The first state is shown as the off state, and the second state is shown as the on state. When the semiconductor pillar is in the off state, the first voltage is less than the second voltage. When the semiconductor pillar is in the on state, the first voltage is equal to the second voltage.

[0064] For example, refer to Figure 1A As per Table 1, the first part receives a first voltage (e.g., -1V) and the second part receives a second voltage (e.g., 0V) to make the semiconductor pillar in the off state; the first part receives a first voltage (e.g., +1V) and the second part receives a second voltage (e.g., +1V) to make the semiconductor pillar in the on state.

[0065] Table 1

[0066]

[0067] In an optional implementation, the semiconductor device can also be a P-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) as an example, where the semiconductor pillar 106 is an N-channel metal-oxide-semiconductor. The first state is shown as the off state, and the second state is shown as the on state. When the semiconductor pillar is in the off state, the first voltage is greater than the second voltage. When the semiconductor pillar is in the on state, the first voltage is equal to the second voltage.

[0068] In some embodiments, the semiconductor device is configured such that: a first portion receives a first voltage, a second portion receives a second voltage, and a third portion receives a third voltage; the first voltage is different from the second voltage and the third voltage, such that the semiconductor pillar is in a first state; or, the first voltage, the second voltage, and the third voltage are all the same, such that the semiconductor pillar is in a second state different from the first state.

[0069] Taking an NMOSFET as an example, when the semiconductor pillar is in the off state, the first voltage is less than the second voltage and less than the third voltage (for example, if the first voltage is less than the second voltage and less than the third voltage, the second voltage and the third voltage can be equal). When the semiconductor pillar is in the on state, the first voltage, the second voltage and the third voltage are equal.

[0070] For example, refer to Figure 1D According to Table 2, the first part receives a first voltage (e.g., -1V), the second part receives a second voltage (e.g., 0V), and the third part receives a third voltage (e.g., 0V) to make the semiconductor pillar in the off state; the first part receives a first voltage (e.g., +1V), the second part receives a second voltage (e.g., +1V), and the third part receives a third voltage (e.g., +1V) to make the semiconductor pillar in the on state.

[0071] Table 2

[0072]

[0073] In an optional implementation, the semiconductor device can also be a PMOSFET. When the semiconductor pillar is in the off state, the first voltage is greater than the second voltage and greater than the third voltage (for example, if the first voltage is greater than the second voltage and greater than the third voltage, the second voltage and the third voltage can be equal). When the semiconductor pillar is in the on state, the first voltage, the second voltage and the third voltage are equal.

[0074] Compared to Figure 1A The semiconductor devices shown in Table 1 are improved only from one end (the second end) of the semiconductor pillar. Figure 1DThe semiconductor devices shown in Table 2 are improved at both ends of the semiconductor pillar (the first end and the second end), which is more conducive to reducing the leakage current caused by GIDL of the semiconductor device.

[0075] Figures 2A to 4C Plan view and cross-sectional view of some semiconductor devices provided in the embodiments of this application. Figure 2B , Figure 3B , Figure 4B They are respectively Figure 2A , Figure 3A , Figure 4A A schematic diagram of the YZ cross-section at the corresponding location of the semiconductor device. Figure 2C , Figure 3C , Figure 4C They are respectively Figure 2A , Figure 3A , Figure 4A A schematic diagram of the XZ cross section at the corresponding location of the semiconductor device. Figures 2A to 4C The semiconductor device shown can be understood as a semiconductor device including an array of semiconductor pillars. For example, Figure 2A , Figure 2B , Figure 2C The semiconductor pillars and their corresponding gate structures in the semiconductor pillar array shown can correspond to Figure 1A The semiconductor pillars shown are for understanding. Figure 3A , Figure 3B , Figure 3C The semiconductor pillars and their corresponding gate structures in the semiconductor pillar array shown can correspond to Figure 1B The semiconductor pillars shown are for understanding. Figure 4A , Figure 4B , Figure 4C The semiconductor pillars and their corresponding gate structures in the semiconductor pillar array shown can correspond to Figure 1C or Figure 1D The semiconductor pillars shown are for understanding.

[0076] It should be noted that, in order to clearly show the relative positional relationships between various components, parts, areas, layers, or partial stacks, Figure 2A , Figure 3A , Figure 4A as well as Figure 2C , Figure 3C , Figure 4C The perspective view also reveals several elements, components, areas, layers, or partial stackings. For example, Figure 2A The dielectric layer is partially omitted to show word lines, word line contact structures, metal shielding layers, metal shielding layer contact structures, bit lines, and bit line contact structures. For example, Figure 2C Part of the gate structure has been omitted to show the semiconductor pillars.

[0077] refer to Figures 2A to 3CIn some embodiments, the semiconductor device includes a semiconductor pillar array consisting of a plurality of semiconductor pillars located within a first region AR1; a plurality of gate structures correspond to the plurality of semiconductor pillars; the semiconductor device also includes a word line structure (e.g., word line WL1) extending along the row direction of the semiconductor pillar array; the word line structure extends within the first region AR1 and partially extends outside the first region; the word line structure includes a first conductive portion and a second conductive portion spaced apart from each other and arranged along a first direction, the first conductive portion extending along the row direction and including a first portion of a row gate structure located within the first region and a first end located outside the first region, the second conductive portion extending along the row direction and including a second portion of a row gate structure located within the first region and a second end located outside the first region; the first end and the second end (e.g., the first end and the second end constitute a stepped structure SS1) are staggered from each other along the row direction.

[0078] It should be noted that the reference Figures 2A to 2C The term "first conductive part" corresponds to the second to third conductive structures (see also: Figure 4C (The second conductive structure 116a and the third conductive structure 120a are understood to be connected as a whole), and the term "second conductive part" corresponds to the first conductive structure 112b. Reference Figures 3A to 3C The term "first conductive part" corresponds to the first to second conductive structures (see also: Figure 4C (The first conductive structure 112b and the second conductive structure 116a are understood to be connected as a whole), and the term "second conductive part" corresponds to the third conductive structure 120a.

[0079] It should be noted that the first region AR1 can be understood as the region where the semiconductor pillar array is located; the second region AR2 can be understood as the lead-out region of the word line structure, located outside the first region and intersecting with the first region in the row direction. In some embodiments, the interface between the second region and the first region can extend along the XZ plane and pass through the third spacing portion 126 or the fourth spacing portion 128; wherein, the third spacing portion 126 and the fourth spacing portion 128 are used to separate two word line structures between two adjacent rows of semiconductor pillars, for example, the third spacing portion 126 and the fourth spacing portion 128 are used to isolate word line WL1 and word line WL2.

[0080] refer to Figures 4A to 4CIn some embodiments, the word line WL1 includes a first conductive structure 112b, a second conductive structure 116a, and a third conductive structure 120a arranged at intervals along a first direction. The first conductive structure 112b extends along a row direction and includes a third portion of a row gate structure located within a first region and a third end located outside the first region. The second conductive structure 116a extends along a row direction and includes a first portion of a row gate structure located within the first region and a first end located outside the first region. The third conductive structure 120a extends along a row direction and includes a second portion of a row gate structure located within the first region and a second end located outside the first region. The second end, the first end, and the third end (e.g., the second end, the first end, and the third end form a stepped structure SS1) are staggered along the first direction. The second end, the first end, and the third end are respectively used to lead out the corresponding first conductive structure 112b, the second conductive structure 116a, and the third conductive structure 120a along one side of the first direction. It should be noted that, referring to... Figures 4A to 4C The term "first conductive part" corresponds to the second conductive structure 116a; the term "second conductive part" corresponds to the third conductive structure 120a; and the term "third conductive part" corresponds to the first conductive structure 112b.

[0081] refer to Figures 2A to 2C In some embodiments, the first end has a first dimension along the row direction, and the second end has a second dimension along the row direction; the second end is located above the first end, and the second dimension is smaller than the first dimension. The first end and the second end are respectively used to lead out corresponding first conductive portions and second conductive portions on the side of the semiconductor device along the first direction and close to the second end.

[0082] refer to Figures 3A to 3C In some embodiments, the first end has a first dimension along the row direction, and the second end has a second dimension along the row direction; the first end is located above the second end, and the first dimension is smaller than the second dimension. The first end and the second end are respectively used to lead out corresponding first conductive portions and second conductive portions on the side of the semiconductor device along the first direction and close to the first end.

[0083] refer to Figures 4A to 4C In some embodiments, the third end has a third dimension along the row direction, the first end is located above the second end, and the third end is located above the second end. The third dimension is smaller than the first dimension, and the first dimension is smaller than the second dimension. The second end, the first end, and the third end are respectively used to lead out corresponding second conductive parts, first conductive parts, and third conductive parts on the side of the semiconductor device along the first direction and close to the third end.

[0084] For example, refer to Figure 4A , Figure 4B and Figure 4CThe word line WL1 includes a first conductive structure 112b, a second conductive structure 116a, and a third conductive structure 120a that extend along the row direction and are spaced apart along the extension direction of the semiconductor pillars. The ends of the first conductive structure, the second conductive structure, and the third conductive structure have progressively larger dimensions along the row direction. The ends of the word line WL1 include a stepped structure SS1, which serves as a landing pad for contact structures CT11, CT12, and CT13. Contact structures CT11, CT12, and CT13 can be used to lead out the first conductive structure 112b, the second conductive structure 116a, and the third conductive structure 120a respectively on the side of the semiconductor device closest to the first conductive structure 112b.

[0085] Figures 2A to 4C In some embodiments, the semiconductor device further includes: a memory structure 204 stacked with and in contact with a first end of the corresponding semiconductor pillar 106; a bit line structure (e.g., bit line BL) extending along the column direction and in contact with a second end of the corresponding semiconductor pillar 106; and word line contact structures (e.g., word line contact structures CT1 and CT2) extending along the extension direction of the semiconductor pillar 106 and in contact with the corresponding word line structure on the side near the bit line structure.

[0086] For example, refer to Figure 4A , Figure 4B and Figure 4C The memory structure 204 contacts the source region of the corresponding semiconductor pillar 106. The bit line BL extends along the column direction of the semiconductor pillar array and contacts the drain region of the corresponding semiconductor pillar 106. The word line WL1 extends along the row direction of the semiconductor pillar array and contacts the gate structure of the corresponding semiconductor pillar 106. The contact structures CT11, CT12, and CT13 are located on the side near the bit line BL, extend along the extension direction of the semiconductor pillar 106, and respectively contact the first conductive structure 112b, the second conductive structure 116a, and the third conductive structure 120a.

[0087] The semiconductor device provided in the first aspect of this application is similar to the semiconductor device manufactured by the manufacturing method of the semiconductor device in the second aspect. For the technical features of the semiconductor device not disclosed in detail in the various embodiments of the first aspect of this application, please refer to the various embodiments of the semiconductor device manufactured by the manufacturing method of the semiconductor device in the second aspect for understanding, and will not be repeated here. Components / layers / materials / structures identified by the same reference numerals in the accompanying drawings of this application shall be understood as the same or similar components / layers / materials / structures.

[0088] In various embodiments of this application, the semiconductor device includes a semiconductor pillar extending along a first direction and a gate structure located on at least one side of the semiconductor pillar along a second direction. The gate structure includes a first portion and a second portion spaced apart from each other and arranged along the extension direction of the semiconductor pillar. For example, the first portion and the second portion can be adapted to receive different voltages separately to ensure that the semiconductor device reduces the gate-induced drain leakage current of the semiconductor device without losing or with minimal loss of the on-state current of the semiconductor device.

[0089] Figure 5 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. (Reference) Figure 5 According to a second aspect of the embodiments of this application, a method for manufacturing a semiconductor device is provided, the method comprising the following steps:

[0090] Step S101: Form a semiconductor pillar array comprising multiple semiconductor pillars; the semiconductor pillars extend along a first direction;

[0091] Step S102: Form a gate structure located on at least one side of the semiconductor pillar along the second direction and a word line structure extending along the row direction of the semiconductor pillar array; wherein, the gate structure includes a first portion and a second portion spaced apart from each other and arranged along the first direction; the word line structure includes a first conductive portion and a second conductive portion spaced apart from each other and arranged along the first direction; the first conductive portion extends along the row direction and includes a first portion of a row gate structure, the second conductive portion extends along the row direction and includes a second portion of a row gate structure; the second direction intersects the first direction.

[0092] The term "gate structure" can be understood as a component that contacts the gate dielectric layer of the sidewall of a semiconductor pillar, which can be understood as a gate layer or a gate. The term "word line structure" can be understood as a component that contacts the gate dielectric layer of the sidewall of a row of semiconductor pillars, which extends along the row direction and includes a row of gate structures corresponding to a row of semiconductor pillars and a connection between two adjacent gate structures in a row of gate structures.

[0093] In various embodiments of this application, the third direction intersects (e.g., is orthogonal) the second direction and is parallel to the surface of the substrate, while the first direction is perpendicular to the surface of the substrate. The third direction can be understood as the arrangement direction of a row of semiconductor pillars, or the direction in which a word line extends from a gate structure that contacts a row of semiconductor pillars; the second direction can be understood as the arrangement direction of a column of semiconductor pillars, or the direction in which a bit line extends from a column of semiconductor pillars; the first direction can be understood as the direction of stacking of elements, components, regions, layers, or parts, or the direction in which semiconductor pillars extend. Exemplarily, the first direction is represented by the Z direction in the figures; the second direction by the Y direction in the figures; and the third direction by the X direction in the figures.

[0094] Figures 6A to 17C A plan view and a cross-sectional view of the manufacturing process of the first semiconductor device provided in the embodiments of this application. Figure 6A , Figure 7A ... Figure 17A An XY plane schematic diagram of the manufacturing process of the first semiconductor device provided in the embodiments of this application. Figure 6B , Figure 7B ... Figure 17B They are respectively Figure 6A , Figure 7A ... Figure 17A A schematic diagram of the YZ cross section at the corresponding location of the semiconductor device. Figure 14C , Figure 15C , Figure 16C , Figure 17C They are respectively Figure 14A , Figure 15A , Figure 16A , Figure 17A A schematic diagram of the XZ cross-section at the corresponding location of the semiconductor device. For example, Figure 17A , Figure 17B , Figure 17C This can be understood as a planar schematic diagram of a semiconductor device from different perspectives under the same process step / manufacturing step. Figure 17C To and Figure 17A A schematic diagram of the XZ section at the AA section line of a semiconductor device. Figure 17B To and Figure 17A A schematic diagram of the YZ section at the BB profile line of a semiconductor device.

[0095] It should be noted that, in order to clearly show the relative positional relationships between various components, parts, regions, layers, or partial layers during the semiconductor device manufacturing process, Figure 6A , Figure 7A ... Figure 17A ,as well as, Figure 14C , Figure 15C , Figure 16C , Figure 17C The semiconductor device also reveals through a perspective view several elements, components, regions, layers, or partial stacks. For example, Figure 6A The perspective view revealed the semiconductor pillars and the metal shielding layer. Figure 17A The perspective view reveals the gate structure, semiconductor pillars, metal shielding layer, and word line contact structure. Figure 17C Perspective revealed the semiconductor pillars. For example, Figure 14A The gate structure and semiconductor pillars are shown in perspective using dashed outlines. Figure 14C Perspective revealed the semiconductor pillars.

[0096] The following is combined Figure 5 , Figures 6A to 17C The manufacturing method of the first semiconductor device provided in the embodiments of this application will be described in detail.

[0097] Perform step S101 to form a semiconductor pillar.

[0098] refer to Figure 6A and Figure 6B The semiconductor device includes a substrate 102 and an active layer located within the substrate. In some embodiments, the substrate 102 may include a silicon (Si), germanium (Ge), silicon germanide (SiGe) substrate, etc.; the substrate may also be silicon on insulator (SOI) or germanium on insulator (GOI). In some embodiments, the substrate 102 may be doped with certain impurity ions as needed. The impurity ions may be N-type impurity ions or P-type impurity ions, and the doping includes well region doping and source / drain region doping. In some specific embodiments, the active layer may include a region in the substrate 102 doped with certain impurity ions. Exemplarily, the active layer may include a P-well doped with P-type impurity ions, or an N-well doped with N-type impurity ions.

[0099] In some embodiments, semiconductor pillars 106 may be formed in the active layer using one or more patterning processes. These patterning processes include, but are not limited to, double-patterning technology (DPT), quadruple-patterning technology (QPT), or any combination thereof. Exemplarily, the semiconductor pillars 106 may be formed in a P-well as an N-channel metal-oxide-semiconductor (NMOS) or in a P-well as a P-channel metal-oxide-semiconductor (PMOS).

[0100] Multiple active regions can be formed in the active layer using the shallow trench isolation (STI) process. Figure 6A and Figure 6B (not shown) and shallow trench isolation structures that separate multiple active regions ( Figure 6A and Figure 6B (Not shown). In some embodiments, the material of the shallow trench isolation structure includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. A plurality of active regions are arranged along a third direction, each active region extending along a second direction, and adjacent active regions are spaced apart by the shallow trench isolation structure.

[0101] Multiple spaced first trenches are formed in the active region and shallow trench isolation structure using lithography-etching (LE) processes, such as self-aligned double patterning (SADP). Figure 6A and Figure 6B (Not shown), the first groove extends in a third direction.

[0102] The first isolation portion 103 is filled into the first trench using a deposition process. The material of the first isolation portion 103 includes a metal shielding layer 104 and an insulating material layer 105 surrounding the metal shielding layer 104; the metal shielding layer may extend in a third direction. Exemplarily, the material of the metal shielding layer may be titanium nitride, and the insulating material layer may be silicon oxide.

[0103] refer to Figure 6A and Figure 6B Multiple spaced second trenches TR0 are formed in the active region and shallow trench isolation structure using a photolithography-etching process. The second trenches TR0 extend in a third direction. The alternating second trenches TR0 and first trenches divide the active region into a semiconductor pillar array, which includes several columns of semiconductor pillars and several rows of active pillars. In some embodiments, the top surface of the first isolation portion 103 and the semiconductor pillars 106 further includes a capping layer 108. Exemplarily, the material of the capping layer 108 may be silicon nitride.

[0104] The etching (or removal) processes used in this article can include wet etching, dry etching, etc. For example, plasma etching. The deposition (or filling) processes used in this article can include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. For example, plasma-enhanced chemical vapor deposition (PECVD).

[0105] Step S102 is executed to form the gate structure and the word line structure.

[0106] In some embodiments, forming a gate structure located on at least one side of the semiconductor pillar along a second direction and a word line structure extending along the row direction of the semiconductor pillar array includes: a reference Figures 7A to 8BA first precursor conductive structure 112a is formed on one side of the first end of the semiconductor pillar; the first precursor conductive structure 112a is located on at least one side of the second end of the semiconductor pillar along the second direction; Reference Figures 9A to 10B A second conductive structure 116a is formed on the first precursor conductive structure, spaced apart from the first precursor conductive structure; the second conductive structure 116a is located on at least one side of the channel region of the semiconductor pillar along the second direction; wherein the first end and the second end are respectively located at both ends of the channel region; Reference Figures 11A to 12B A third conductive structure 120a, spaced apart from the second conductive structure, is formed on the second conductive structure; the third conductive structure 120a is located on at least one side of the first end of the semiconductor pillar along the second direction; Reference Figures 14A to 15C On one side of the second end of the semiconductor pillar, a portion of the first precursor conductive structure 112a is removed along a first direction to form a first conductive structure 112b; the first conductive structure 112b is located on at least one side of the second end of the semiconductor pillar along the second direction; wherein, the gate structure includes a first portion, a second portion, and a third portion spaced apart from each other and arranged along the first direction; the word line structure includes a first conductive portion, a second conductive portion, and a third conductive portion spaced apart from each other and arranged along the first direction, wherein the third conductive portion extends along the row direction and includes a third portion of a row gate structure; wherein, the first conductive portion corresponds to the second conductive structure 116a; the second conductive portion corresponds to the third conductive structure 120a; and the third conductive portion corresponds to the first conductive structure 112b.

[0107] refer to Figure 7A and Figure 7B A gate dielectric layer 110, a first precursor conductive material layer 112, and a first filler material layer 114 are sequentially deposited in the second trench TR0 using a deposition process. For example, the gate dielectric layer 110 may be made of silicon oxide, the first precursor conductive material layer 112 may be made of tungsten, and the first filler layer 114 may be made of silicon oxide.

[0108] In some embodiments, the material layer of the first precursor conductive material layer 112 may include a gate material layer and a word line material layer deposited sequentially, wherein the gate material layer 206 may be titanium nitride and the word line material layer 208 may be tungsten.

[0109] In some embodiments, the gate dielectric layer 110 and the first filler material layer 114 are formed by different deposition processes; the etch selectivity of the first filler material layer 114 relative to the gate dielectric layer 110 is greater than 30:1. For example, the gate dielectric layer 110 is formed by an ALD process, and the first filler material layer 114 is formed by a PECVD process, such that the etch selectivity of the first filler material layer 114 relative to the gate dielectric layer 110 is greater than 30:1.

[0110] It should be noted that, Figure 7B The gate dielectric layer 110, first precursor conductive material layer 112, and first filler material layer 114 shown in the second trench TR0 are merely exemplary embodiments. It is understood that, while ensuring that the first precursor conductive material layer 112 and the semiconductor pillar 106 are separated by the gate dielectric layer 110, other configurations can be adaptively varied according to process requirements. For example, compared to... Figure 7B The first precursor conductive material layer 112 shown does not contact the substrate 102 exposed in the second trench TR0. In an optional embodiment, the gate dielectric layer 110 and the first precursor conductive material layer 112 are conformally formed in the second trench TR0 by a deposition process, and the resulting first precursor conductive material layer 112 is separated from the substrate 102 exposed in the second trench TR0 by the gate dielectric layer 110 (in this case). Figure 7A and Figure 7B (Not shown).

[0111] refer to Figure 8A and Figure 8B By removing a portion of the first precursor conductive material layer 112 and a portion of the first filler material layer 114 through a back-etching process, a first groove TR1, a first precursor conductive structure 112a, and a first filler structure 114a are obtained. The first groove TR1 can be understood as the space obtained after removing a portion of the first precursor conductive material layer 112 and a portion of the first filler material layer 114 in the second trench TR0. The first precursor conductive structure 112a can be understood as the first precursor conductive material layer 112 that was not removed and is retained, and the first filler structure 114a can be understood as the first filler material layer 114 that was not removed and is retained. The specific parameters of the back-etching process can be adjusted to adjust the dimensions of the first precursor conductive structure 112a along a third direction.

[0112] refer to Figure 9A and Figure 9B A first spacer CO1, covering at least the top surface of the first precursor conductive structure 112a, is formed in the first groove TR1 using a deposition process. Then, a second conductive material layer 116 and a second filler material layer 118 are sequentially deposited, with the second conductive material layer 116 separated from the first precursor conductive structure 112a by the first spacer CO1. The dimensions of the first spacer CO1 along a third direction can be adjusted by adjusting the specific parameters of the deposition process.

[0113] In some embodiments, the first spacer CO1 is formed by an ALD process. Exemplarily, the material of the first spacer CO1 may be silicon oxide. In alternative embodiments, it may be a high-k dielectric layer with a dielectric constant greater than 3.8, or a low-k dielectric layer with a dielectric constant less than 3.8. Exemplarily, the material of the first spacer CO1 may also be hafnium oxide (HfO2).

[0114] In some embodiments, the spacing (also referred to herein as the first spacing GAP1) of the first spacer CO1 along the semiconductor pillar extension direction is less than or equal to 10 nm. Preferably, the first spacing GAP1 is less than or equal to 6 nm. Due to limitations in process complexity, the smaller the first spacing GAP1, the better, provided that the second conductive material layer 116 and the first precursor conductive structure 112a can be separated by the first spacer CO1. For example, the first spacing GAP1 ranges from 2 nm to 6 nm, and can be 3 nm, 4 nm, or 5 nm.

[0115] The processes for forming the second conductive material layer 116 and the second filler material layer 118 can be understood by referring to the processes for forming the first precursor conductive material layer 112 and the first filler material layer 114, respectively. The materials of the second conductive material layer 116 and the second filler material layer 118 can be understood by referring to the materials of the first precursor conductive material layer 112 and the first filler material layer 114, respectively.

[0116] In some embodiments, the material of the second conductive material layer 116 is the same as or similar to the material of the first precursor conductive material layer 112, which can maintain material consistency between the second conductive material layer 116 and the first precursor conductive material layer 112. In alternative embodiments, the material of the second conductive material layer 116 may be different from the material of the first precursor conductive material layer 112.

[0117] refer to Figure 10A and Figure 10B By removing a portion of the second conductive material layer 116 and a portion of the second filler material layer 118 through a back etching process, a second groove TR2, a second conductive structure 116a, and a second filler structure 118a are obtained. The second groove TR2 can be understood as the space obtained after removing a portion of the second conductive material layer 116 and a portion of the second filler material layer 118 in the first groove TR1. The second conductive structure 116a can be understood as the second conductive material layer 116 that was not removed and was retained, and the second filler structure 118a can be understood as the second filler material layer 118 that was not removed and was retained.

[0118] refer to Figure 11A and Figure 11B A second spacer CO2 is formed in the second groove TR2 by a deposition process, which at least covers the top surface of the second conductive structure 116a. A third conductive material layer 120 and a third filler material layer 122 are deposited in sequence, with the third conductive material layer 120 and the second conductive structure 116a separated by the second spacer CO2.

[0119] The formation of the second spacer CO2, the third conductive material layer 120, and the third filler material layer 122 can be understood with reference to the processes for forming the first spacer CO1, the second conductive material layer 116, and the second filler material layer 118, respectively. The materials of the second spacer CO2, the third conductive material layer 120, and the third filler material layer 122 can be understood with reference to the materials of the first spacer CO1, the second conductive material layer 116, and the second filler material layer 118, respectively. In some embodiments, the third conductive material layer 120 is made of the same or similar material as the second conductive material layer 116, maintaining material consistency between the third conductive material layer 120 and the second conductive material layer 116. In alternative embodiments, the materials of the third conductive material layer 120 and the second conductive material layer 116 may be different.

[0120] refer to Figure 12A and Figure 12B The third groove is obtained by removing part of the third conductive material layer 120 and part of the third filler material layer 122 through a back etching process. Figure 12A and Figure 12B (Not shown), a third conductive structure 120a, and a third filling structure 122a. The third groove can be understood as the space obtained after removing a portion of the third conductive material layer 120 and a portion of the third filling material layer 122 from the second groove TR2. The third conductive structure 120a can be understood as the third conductive material layer 120 that was not removed and is retained, and the third filling structure 122a can be understood as the third filling material layer 122 that was not removed and is retained. In some embodiments, a filling dielectric layer 124 is formed in the third groove. The material of the filling dielectric layer 124 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The filling dielectric layer 124, the third filling structure 122a, the second filling structure 118a, and the first filling structure 114a can be the same or similar materials. For example, the filling dielectric layer 130 and the third filling structure 122a are made of the same material, and there is no clear boundary between them. For example Figure 12B The boundaries between the filling medium layer 124, the third filling structure 122a, the second filling structure 118a, and the first filling structure 114a are not shown in the figure.

[0121] refer to Figure 13A and Figure 13BIn some embodiments, the third spacer 126 and the fourth spacer 128 may be formed by one or more patterning processes, such that the third conductive structure 120a and the second conductive structure 116a are separated into two spaced portions, and that the third spacer 126 and the fourth spacer 128 also separate the portion of the first precursor conductive structure 112a extending in a third direction into two spaced portions. The materials of the third spacer 126 and the fourth spacer 128 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0122] refer to Figure 13A and Figure 13B In some embodiments, a memory node plug 202 and a memory structure 204 may be formed on one side of the semiconductor pillar 106 by a bonding process (e.g., hybrid bonding); the memory structure 204 is stacked with the corresponding semiconductor pillar 106 and contacts the first end of the corresponding semiconductor pillar 106 through the memory node plug 202.

[0123] In some embodiments, the storage structure 204 includes a capacitor; the first electrode of the capacitor is connected to the first end of the semiconductor pillar 106 via a storage node plug 202 on the bonding surface, and the second electrode of the capacitor is connected to a common electrode. In some specific embodiments, the materials of the storage node plug 202 and the common electrode include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polycrystalline silicon, doped silicon, silicides, nitrides, or any combination thereof. The specific structures of the storage node plug 202 and the storage structure 204 in this application are not shown.

[0124] refer to Figure 14A , Figure 14B and Figure 14C The semiconductor device is flipped so that the side where the second end of the semiconductor pillar 106 is located (which can be understood as the back side of the substrate 102) is the surface to be processed.

[0125] refer to Figure 14A , Figure 14B and Figure 14C ,refer to Figure 15A , Figure 15B and Figure 15C A thinning process is used to remove a portion of the substrate 102 on one side where the second end of the semiconductor pillar 106 is located, exposing the end face of the shallow trench isolation structure. The substrates 102 on both sides of the shallow trench isolation structure form two conductive lines 102a, which can connect the two rows of semiconductor pillars 106 adjacent to each other on both sides of the shallow trench isolation structure.

[0126] Continue to refer to Figure 15A , Figure 15B and Figure 15CRemove part of the shallow trench isolation structure to expose the first precursor conductive structure 112a (reference). Figure 14A , Figure 14B and Figure 14C The end face of the first precursor conductive structure 112a is subjected to a back etching process to remove part of the first precursor conductive structure 112a, resulting in a recessed space. Figure 15A , Figure 15B and Figure 15C (Not shown) and a first conductive structure 112b, which can be understood as a first precursor conductive structure 112a that is not removed and is retained. In some embodiments, a filling dielectric layer 130 is formed in the recessed space, the filling dielectric layer 130 being located at least between the two conductive lines 102a. Exemplarily, the material of the filling dielectric layer 130 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0127] Continue to refer to Figure 15A , Figure 15B and Figure 15C In some embodiments, the two word lines WL1 and WL2 are in the second trench TR0 (reference). Figure 6A and Figure 6B The word lines WL1 and WL2 are spaced apart from each other and can respectively couple two rows of semiconductor pillars 106 adjacent to both sides of the second trench TR0. For example, word lines WL1 and WL2 respectively include a first conductive structure 112b, a second conductive structure 116a and a third conductive structure 120a.

[0128] In some embodiments, the ratios between the dimensions of the first conductive structure 112b and the third conductive structure 120a in the semiconductor pillar extension direction and the dimensions of the word line in the semiconductor pillar extension direction are both in the range of 10% to 30%. For example, the ratios between the dimensions of the first conductive structure 112b and the third conductive structure 120a in the semiconductor pillar extension direction and the dimensions of the word line WL1 in the semiconductor pillar extension direction are both 20%.

[0129] Continue to refer to Figure 15A , Figure 15B and Figure 15C In some embodiments, an adhesion layer can be sequentially formed on the conductive line 102a using a self-aligned bit line process. Figure 15A , Figure 15B and Figure 15C (not shown), metal layer ( Figure 15A , Figure 15B and Figure 15C (Not shown). In some embodiments, the bit line BL includes a conductive line 102a, an adhesive layer, and a metal layer, wherein the material of the adhesive layer may be titanium nitride, and the material of the metal layer may be tungsten.

[0130] In some embodiments, the manufacturing method further includes: on one side where the second end of the semiconductor pillar is located, sequentially removing a portion of the material from a plurality of ends corresponding to the word line structure, such that the plurality of ends are staggered from each other along a first direction; wherein the plurality of ends are used to lead out the word line structure along one side of the first direction.

[0131] refer to Figure 16A , Figure 16B and Figure 16C In some embodiments, a portion of the material at the ends of the first conductive structure 112b, the second conductive structure 116a, and the third conductive structure 120a can be removed sequentially using a photolithography-etching process, such that multiple ends are staggered along the semiconductor pillar extension direction by a stepped structure (e.g., stepped structure SS1 and stepped structure SS2), with stepped structure SS1 and stepped structure SS2 located at the ends of word lines WL1 and WL2. In some embodiments, stepped structure SS1 and stepped structure SS2 are located at opposite ends in the second trench TR0 along a third direction.

[0132] In some embodiments, the process of sequentially removing partial material from multiple ends corresponding to the word line structure includes: forming a mask covering the second end; performing multiple exposure-development-etching steps on the mask to sequentially remove partial material from each end, forming multiple ends staggered along a first direction; wherein each exposure-development-etching step removes partial material from one end; and forming a word line contact structure includes: etching along the first direction on one side where the second end of the semiconductor pillar is located to form a word line contact hole extending to the word line structure; and filling the word line contact hole with conductive material to form the word line contact structure.

[0133] refer to Figure 16A , Figure 16B and Figure 16CA mask is formed on one side of the semiconductor pillar 106 at its second end using a photolithography-etching process. The mask undergoes three exposure-development-etching steps to sequentially remove material from the ends of the first conductive structure 112b, the second conductive structure 116a, and the third conductive structure 120a, resulting in multiple staggered stepped structures SS1 and SS2 with their ends offset along the semiconductor pillar's extension direction. Stepped structures SS1 and SS2 are located at the ends of word lines WL1 and WL2, respectively. Exemplarily, the three exposure-development-etching steps include: a first exposure-development-etching step, removing material from the end of the first conductive structure 112b; a second exposure-development-etching step, removing material from the end of the second conductive structure 116a and the end of the first conductive structure 112b; and a third exposure-development-etching step, removing material from the end of the third conductive structure 120a, the end of the second conductive structure 116a, and the end of the first conductive structure 112b.

[0134] refer to Figure 17A , Figure 17B and Figure 17C By using a photolithography-etching process, word line contact holes extending to the corresponding first conductive structure 112b, second conductive structure 116a, and third conductive structure 120a are formed in the filled dielectric layer 132 along the extension direction of the semiconductor pillar on one side where the second end is located. Figure 17A , Figure 17B and Figure 17C (Not shown); A conductive material is filled into the word line contact holes to form a word line contact structure CT1 corresponding to word line WL1 and a word line contact structure CT2 corresponding to word line WL2. Word line contact structure CT1 includes contact structures CT11, CT12, and CT13 respectively connected to the first conductive structure 112b, the second conductive structure 116a, and the third conductive structure 120a of word line WL1. Word line contact structure CT2 includes contact structures CT21, CT22, and CT23 respectively connected to the first conductive structure 112b, the second conductive structure 116a, and the third conductive structure 120a of word line WL2. The materials for word line contact structures CT1 and CT2 include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. The material for the filling dielectric layer 132 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The filling dielectric layer 130 and the filling dielectric layer 132 can be the same or similar materials. For example, the filling dielectric layer 130 and the filling dielectric layer 132 are made of the same material, and there is no clear boundary between the filling dielectric layer 130 and the filling dielectric layer 132. Figure 17CThe boundary between the filling medium layer 130 and the filling medium layer 132 is not shown in the figure.

[0135] refer to Figure 17A , Figure 17B and Figure 17C In some embodiments, a bit line contact structure (CTBL) and a metal shielding layer contact structure (CTMS) are formed on one side of the second end of the semiconductor pillar using a photolithography-etching process. Exemplarily, the bit line contact structure (CTBL) and the metal shielding layer contact structure (CTMS) can be formed simultaneously during the photolithography-etching process of the word line contact structure. The materials for the bit line contact structure (CTBL) and the metal shielding layer contact structure (CTMS) include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicides, nitrides, or any combination thereof.

[0136] It should be noted that the term "first conductive part" in the manufacturing process of the first semiconductor device provided in the embodiments of this application can correspond to... Figure 17A , Figure 17B and Figure 17C The second conductive structure 116a shown; the term "second conductive part" can correspond to Figure 17A , Figure 17B and Figure 17C The third conductive structure 120a shown; the term "third conductive part" can correspond to Figure 17A , Figure 17B and Figure 17C The first conductive structure 112b is shown.

[0137] Figures 18A to 18F This is a cross-sectional schematic diagram of the manufacturing process of a second type of semiconductor device provided in an embodiment of this application.

[0138] The following is combined Figure 5 , Figures 18A to 18F The manufacturing method of the second semiconductor device provided in the embodiments of this application will be described in detail.

[0139] In some embodiments, forming a gate structure located on at least one side of the semiconductor pillar along a second direction and a word line structure extending along the row direction of the semiconductor pillar array includes: a reference Figure 18A and Figure 18B A first precursor conductive structure is formed on one side of the first end of the semiconductor pillar; the first precursor conductive structure is located on at least one side of the second end of the semiconductor pillar along a second direction; Reference Figure 18C and Figure 18DA second to third conductive structure is formed on the first precursor conductive structure, spaced apart from the first precursor conductive structure; the second to third conductive structures are located on at least one side of the channel region of the semiconductor pillar along a second direction, and on at least one side of the first end of the semiconductor pillar along the second direction; wherein the first end and the second end are respectively located at both ends of the channel region; Reference Figure 18E and Figure 18F On one side of the second end of the semiconductor pillar, a portion of the first precursor conductive structure is removed along a first direction to form a first conductive structure; the first conductive structure is located on at least one side of the second end of the semiconductor pillar along a second direction; wherein, the first conductive portion corresponds to the second to third conductive structures; and the second conductive portion corresponds to the first conductive structure.

[0140] Here, the first conductive structure can be understood as... Figure 17B The first conductive structure 112b shown, and the second to third conductive structures can be understood as... Figure 17B The second conductive structure 116a and the third conductive structure 120a shown are extended and connected to form a whole.

[0141] It should be noted that, Figure 18A , Figure 18B , Figure 18C You can refer to them separately. Figure 7B , Figure 8B , Figure 9B To understand; Figure 18D You can refer to Figure 12B To understand, it is necessary to... Figure 12B The semiconductor device shown failed to form a second spacer portion CO2, and... Figure 12B The second conductive structure 116a and the third conductive structure 120a shown are understood as a connected whole. Figure 18E and Figure 18F You can refer to Figure 14B and Figure 15B To understand, it is necessary to... Figure 14B and Figure 15B The semiconductor device shown failed to form a second spacer portion CO2, and... Figure 14B and Figure 15B The second conductive structure 116a and the third conductive structure 120a shown are understood as a connected whole.

[0142] Figures 19A to 19F This is a cross-sectional schematic diagram of the manufacturing process of a third type of semiconductor device provided in an embodiment of this application.

[0143] The following is combined Figure 5 , Figures 19A to 19F The manufacturing method of the third semiconductor device provided in the embodiments of this application will be described in detail.

[0144] In some embodiments, forming a gate structure located on at least one side of the semiconductor pillar along a second direction and a word line structure extending along the row direction of the semiconductor pillar array includes: a reference Figure 19A and Figure 19B A first and second precursor conductive structures are formed on one side of the first end of the semiconductor pillar; the first and second precursor conductive structures are located on at least one side of the second end of the semiconductor pillar along the second direction, and on at least one side of the channel region of the semiconductor pillar along the second direction; Reference Figure 19C and Figure 19D A third conductive structure, spaced apart from the first and second precursor conductive structures, is formed on the first and second precursor conductive structures; the third conductive structure is located on at least one side of the first end of the semiconductor pillar along the second direction; wherein the first end and the second end are respectively located at both ends of the channel region; Reference Figure 19E and Figure 19F On one side of the second end of the semiconductor pillar, a portion of the first to second precursor conductive structures is removed along the first direction to form the first to second conductive structures; the first to second conductive structures are located on at least one side of the second end of the semiconductor pillar along the second direction, and on at least one side of the channel region of the semiconductor pillar along the second direction; wherein, the first conductive portion corresponds to the first to second conductive structures; and the second conductive portion corresponds to the third conductive structure.

[0145] Here, the first and second conductive structures can be understood as... Figure 17B The first conductive structure 112b and the second conductive structure 116a shown are extended and connected to form a whole. The third conductive structure can be understood as... Figure 17B The third conductive structure 120a is shown.

[0146] It should be noted that, Figure 19A You can refer to this. Figure 7B To understand; Figure 19B , Figure 19C Figure 19D You can refer to Figure 10B , Figure 11B and Figure 12B To understand, it is necessary to... Figure 10B , Figure 11B and Figure 12B The first spacer CO1 was not formed in the semiconductor device shown, and... Figure 10B , Figure 11B and Figure 12B The first precursor conductive structure 112a and the second conductive structure 116a shown are understood as a connected whole. Figure 19E You can refer to Figure 14B To understand, it is necessary to... Figure 14B The first spacer CO1 was not formed in the semiconductor device shown, and... Figure 14BThe first precursor conductive structure 112a and the second conductive structure 116a shown are understood as a connected whole. Figure 19F You can refer to Figure 15B To understand, it is necessary to... Figure 15B The first spacer CO1 was not formed in the semiconductor device shown, and... Figure 15B The first conductive structure 112b and the second conductive structure 116a shown are understood as a connected whole. In some embodiments, before sequentially removing portions of material from the multiple ends corresponding to the word line structures, the manufacturing method further includes: referring to... Figure 13A and Figure 13B A memory structure is formed on one side where the first end of the semiconductor pillar is located; the memory structure is stacked with the corresponding semiconductor pillar and contacts the first end of the corresponding semiconductor pillar; Reference Figure 16A , Figure 16B and Figure 16C A bit line structure is formed on one side where the second end of the semiconductor pillar is located; the bit line structure extends along the column direction and contacts the second end of the corresponding semiconductor pillar; after sequentially removing a portion of the material from multiple ends corresponding to the word line structure, the manufacturing method further includes: referencing Figure 17A , Figure 17B and Figure 17C A word line contact structure is formed on one side where the second end of the semiconductor pillar is located; the word line contact structure extends along the first direction and contacts the word line structure on the side close to the bit line structure.

[0147] Figures 6A to 19F The semiconductor device manufacturing method shown is illustrated in the architecture of a vertical gate dynamic random access memory (DRAM), with the gate structures of adjacent transistors arranged back-to-back as an example (a case where the gate structure covers one sidewall of a semiconductor pillar). Figures 6A to 19F The semiconductor devices shown are not intended to limit the embodiments of this application. In some embodiments, the gate structure is located on one or both sides of the semiconductor pillar along the second direction, the gate structure is located on both sides of the semiconductor pillar along the second direction and on one side of the semiconductor pillar along a third direction different from the second direction, or the gate structure surrounds the semiconductor pillar; the third direction intersects the first direction. Exemplarily, the gate structure can be a single-sided gate type, for example, the gate structure is located on one side of the semiconductor pillar along the second direction; the gate structure can be a dual-gate type, for example, the gate structure is located on both sides of the semiconductor pillar along the second direction; the gate structure can also be a gate-all-around type, the gate structure surrounds the semiconductor pillar.

[0148] The semiconductor device manufactured by the semiconductor device manufacturing method provided in this application is similar to the device in some embodiments of the first aspect above. For technical features not disclosed in detail in the embodiments of this application, please refer to the above embodiments for understanding, and will not be repeated here.

[0149] Figure 20 This is a schematic diagram of a memory system provided in an embodiment of this application.

[0150] According to a third aspect of the embodiments of this application, a memory system is provided, with reference to... Figure 20 The memory system 30 includes: a memory 10, which includes any of the semiconductor devices provided in the first aspect; and a controller 20 connected to the memory 10.

[0151] Here, a semiconductor device can be a memory or a part of a memory. The following explanation uses a semiconductor device as an example of a memory.

[0152] In some embodiments, the memory provided in this application includes various types of memory. For example, DRAM, Static Random Access Memory (SRAM), Phase-Change Memory (PCM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).

[0153] In some specific embodiments, the memory includes DRAM, and the memory cell includes a capacitor; the capacitor includes a pillar-shaped second electrode, a dielectric covering the sidewalls and bottom of the second electrode, and a first electrode covering the dielectric. In practical applications, the second electrode may be connected to the source of a transistor in a transistor array, and the first electrode may be connected to a reference voltage, which may be ground or other voltages. The capacitor represents logical "1" and "0" by the amount of charge stored within it.

[0154] Figure 21 This is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of this application. Figure 21The right side shows the circuitry of a memory cell in a DRAM. A DRAM comprises at least one DRAM die, and each DRAM die includes a memory cell array. The memory cell array contains multiple memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T and a capacitor C. The primary function of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cell array uses row and column addresses to specify addresses. By specifying the intersection of the row and column (by specifying the row and column addresses of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform read, write, or refresh operations on the stored data.

[0155] Figure 21 The left side shows the memory cell array and some peripheral circuitry in a DRAM. It's important to note that the row decoding circuit, in response to an address input to it, selects a word line to choose the row of the memory cell to access. The row decoding circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decoding circuit selects one or more bit lines to input our output data into a portion of the row of the memory cell corresponding to the selected word line.

[0156] In some embodiments, the memory includes a resistive random access memory (RRAM), and the memory cell includes an adjustable resistor connected between a bit line and the source of a transistor in the semiconductor structure; or, the adjustable resistor is connected between a bit line and the drain of a transistor in the semiconductor structure, and the adjustable resistor is used to adjust the resistance value of the memory cell to represent logical "0" and "1" by the bit line voltage provided by the bit line. It should be noted that only some common memories are exemplified here, and the scope of protection of this application is not limited thereto; any memory containing the transistors provided in the embodiments of this application falls within the scope of protection of this application.

[0157] According to a fourth aspect of the present application, an operation method for a semiconductor device is provided. The semiconductor device includes a semiconductor pillar extending along a first direction and a gate structure located on at least one side of the semiconductor pillar along a second direction. The operation method includes: applying a first voltage to a first portion of the gate structure and applying a second voltage to a second portion of the gate structure; the first voltage and the second voltage are different, such that the semiconductor pillar is in a first state; or, the first voltage and the second voltage are the same, such that the semiconductor pillar is in a second state different from the first state; wherein the first portion and the second portion are spaced apart from each other and arranged along the first direction; the second direction intersects the first direction; or, applying a first voltage to a first portion of the gate structure, applying a second voltage to a second portion of the gate structure, and applying a third voltage to a third portion of the gate structure; the first voltage, the second voltage, and the third voltage are all different, such that the semiconductor pillar is in a first state; or, the first voltage, the second voltage, and the third voltage are all the same, such that the semiconductor pillar is in a second state different from the first state; wherein the first portion, the second portion, and the second portion are spaced apart from each other and arranged along the first direction; the second direction intersects the first direction.

[0158] In some embodiments, the second voltage is different from both the first voltage and the third voltage, including: the first voltage is equal to the third voltage.

[0159] The semiconductor device operation method provided in this application uses a device similar to the device in some embodiments of the first aspect above. For technical features not disclosed in detail in this application, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0160] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0161] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor pillars, extending along a first direction; The gate structure, located on at least one side of the semiconductor pillar along a second direction, includes a first portion and a second portion spaced apart from each other and arranged along the first direction; the second direction intersects the first direction.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor pillar includes a channel region, a first end and a second end located at both ends of the channel region; Wherein, the first portion overlaps at least with the channel area along the second direction, and the second portion overlaps at least with the first end along the second direction.

3. The semiconductor device according to claim 2, characterized in that, The gate structure further includes a third portion; the first portion, the second portion, and the third portion are spaced apart from each other and arranged along the first direction; The third portion overlaps at least with the second end along the second direction.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device includes a semiconductor pillar array consisting of a plurality of semiconductor pillars located in a first region; the plurality of gate structures correspond to the plurality of semiconductor pillars; The semiconductor device further includes a word line structure extending along the row direction of the semiconductor pillar array; the word line structure extends within the first region and partially extends outside the first region; the word line structure includes a first conductive portion and a second conductive portion spaced apart from each other and arranged along the first direction; the first conductive portion extends along the row direction and includes a first portion of a row of the gate structure located within the first region and a first end located outside the first region; the second conductive portion extends along the row direction and includes a second portion of a row of the gate structure located within the first region and a second end located outside the first region; The first end and the second end are offset from each other along the row direction.

5. The semiconductor device according to claim 4, characterized in that, The first end has a first dimension along the row direction, and the second end has a second dimension along the row direction; the second end is located above the first end, and the second dimension is smaller than the first dimension.

6. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: The storage structure is stacked with the corresponding semiconductor pillar and contacts the first end of the corresponding semiconductor pillar; Bit line structure, extending along the column direction and contacting the second end of the corresponding semiconductor pillar; The word line contact structure extends along the first direction and contacts the corresponding word line structure on the side close to the bit line structure.

7. The semiconductor device according to claim 1, characterized in that, The spacing between the first part and the second part along the first direction is less than or equal to 10 nm.

8. The semiconductor device according to claim 3, characterized in that, The ratio of the dimension of the second portion in the first direction to the dimension of the gate structure in the first direction ranges from 10% to 30%.

9. The semiconductor device according to claim 1, characterized in that, The gate structure is located on one or both sides of the semiconductor pillar along the second direction; the gate structure is located on both sides of the semiconductor pillar along the second direction and on one side of the semiconductor pillar along a third direction different from the second direction; or the gate structure surrounds the semiconductor pillar; the third direction intersects with the first direction.

10. The semiconductor device according to claim 2, characterized in that, The semiconductor device is configured as follows: The first part receives a first voltage, and the second part receives a second voltage; the first voltage and the second voltage are different, so that the semiconductor pillar is in a first state; Alternatively, the first voltage is the same as the second voltage, so that the semiconductor pillar is in a second state different from the first state.

11. The semiconductor device according to claim 3, characterized in that, The semiconductor device is configured as follows: The first part receives a first voltage, the second part receives a second voltage, and the third part receives a third voltage; the first voltage is different from the second voltage and the third voltage, so that the semiconductor pillar is in a first state; Alternatively, the first voltage, the second voltage, and the third voltage are all the same, so that the semiconductor pillar is in a second state different from the first state.

12. A method for manufacturing a semiconductor device, characterized in that, include: Forming a semiconductor pillar array comprising multiple semiconductor pillars; The semiconductor pillar extends along a first direction; A gate structure is formed on at least one side of the semiconductor pillar along a second direction, and a word line structure extends along the row direction of the semiconductor pillar array; wherein the gate structure includes a first portion and a second portion spaced apart from each other and arranged along the first direction; the word line structure includes a first conductive portion and a second conductive portion spaced apart from each other and arranged along the first direction; the first conductive portion extends along the row direction and includes a row of the first portion of the gate structure, the second conductive portion extends along the row direction and includes a row of the second portion of the gate structure; the second direction intersects the first direction.

13. The manufacturing method according to claim 12, characterized in that, Forming a gate structure located on at least one side of the semiconductor pillar along a second direction and a word line structure extending along the row direction of the semiconductor pillar array includes: A first precursor conductive structure is formed on one side of the first end of the semiconductor pillar; the first precursor conductive structure is located on at least one side of the second end of the semiconductor pillar along the second direction; A second to third conductive structure is formed on the first precursor conductive structure, spaced apart from the first precursor conductive structure; the second to third conductive structures are located on at least one side of the channel region of the semiconductor pillar along the second direction, and on at least one side of the first end of the semiconductor pillar along the second direction; wherein the first end and the second end are respectively located at both ends of the channel region; On one side of the second end of the semiconductor pillar, a portion of the first precursor conductive structure is removed along the first direction to form a first conductive structure; the first conductive structure is located on at least one side of the second end of the semiconductor pillar along the second direction; wherein, the first conductive portion corresponds to the second to third conductive structures; the second conductive portion corresponds to the first conductive structure; or, A first and a second precursor conductive structure are formed on one side of the first end of the semiconductor pillar; the first and a second precursor conductive structure are located on at least one side of the second end of the semiconductor pillar along the second direction, and on at least one side of the channel region of the semiconductor pillar along the second direction; A third conductive structure is formed on the first and second precursor conductive structures, spaced apart from the first and second precursor conductive structures; the third conductive structure is located on at least one side of the first end of the semiconductor pillar along the second direction; wherein the first end and the second end are respectively located at both ends of the channel region; On one side of the second end of the semiconductor pillar, a portion of the first to second precursor conductive structures is removed along the first direction to form a first to second conductive structure; the first to second conductive structures are located on at least one side of the second end of the semiconductor pillar along the second direction, and on at least one side of the channel region of the semiconductor pillar along the second direction; wherein, the first conductive portion corresponds to the first to second conductive structure; and the second conductive portion corresponds to the third conductive structure.

14. The manufacturing method according to claim 12, characterized in that, Forming a gate structure located on at least one side of the semiconductor pillar along a second direction and a word line structure extending along the row direction of the semiconductor pillar array includes: A first precursor conductive structure is formed on one side of the first end of the semiconductor pillar; the first precursor conductive structure is located on at least one side of the second end of the semiconductor pillar along the second direction; A second conductive structure is formed on the first precursor conductive structure and spaced apart from the first precursor conductive structure; the second conductive structure is located on at least one side of the channel region of the semiconductor pillar along the second direction; wherein the first end and the second end are respectively located at both ends of the channel region; A third conductive structure is formed on the second conductive structure and spaced apart from the second conductive structure; the third conductive structure is located on at least one side of the first end of the semiconductor pillar along the second direction; On one side of the second end of the semiconductor pillar, a portion of the first precursor conductive structure is removed along the first direction to form a first conductive structure; the first conductive structure is located on at least one side of the second end of the semiconductor pillar along the second direction. The gate structure includes a first portion, a second portion, and a third portion that are spaced apart from each other and arranged along the first direction; the word line structure includes a first conductive portion, a second conductive portion, and a third conductive portion that are spaced apart from each other and arranged along the first direction; wherein the third conductive portion extends along the row direction and includes a third portion of a row of the gate structure. Wherein, the first conductive part corresponds to the second conductive structure; the second conductive part corresponds to the third conductive structure; and the third conductive part corresponds to the first conductive structure.

15. The manufacturing method according to any one of claims 13 or 14, characterized in that, The manufacturing method further includes: On one side where the second end of the semiconductor pillar is located, a portion of the material at multiple ends corresponding to the word line structure is removed sequentially, such that the multiple ends are staggered from each other along the first direction; wherein, the multiple ends are used to lead out the word line structure along one side of the first direction.

16. The manufacturing method according to claim 15, characterized in that, Before sequentially removing portions of material from the multiple ends corresponding to the character line structure, the manufacturing method further includes: A memory structure is formed on one side of the first end of the semiconductor pillar; the memory structure is stacked with the corresponding semiconductor pillar and is in contact with the first end of the corresponding semiconductor pillar. A bit line structure is formed on one side where the second end of the semiconductor pillar is located; the bit line structure extends along the column direction and contacts the corresponding second end of the semiconductor pillar. After sequentially removing portions of material from the multiple ends corresponding to the character line structure, the manufacturing method further includes: A word line contact structure is formed on one side of the second end of the semiconductor pillar; the word line contact structure extends along the first direction and contacts the word line structure on the side close to the bit line structure.

17. The manufacturing method according to claim 16, characterized in that, Sequentially remove portions of material from multiple ends corresponding to the character line structure, including: Form a mask covering the second end; The mask is subjected to multiple exposure-development-etching steps to sequentially remove a portion of the material at each of the ends, forming the plurality of ends that are staggered from each other along the first direction; wherein each exposure-development-etching step removes a portion of the material at one of the ends; Forming a character line contact structure includes: On one side where the second end of the semiconductor pillar is located, an etching is performed along the first direction to form a word line contact hole extending to the word line structure; The word line contact structure is formed by filling the word line contact hole with conductive material.

18. A memory system, characterized in that, include: The memory includes a semiconductor device as described in any one of claims 1 to 11; The controller is connected to the memory.

19. A method of operating a semiconductor device, characterized in that, The semiconductor device includes a semiconductor pillar extending along a first direction and a gate structure located on at least one side of the semiconductor pillar along a second direction; the operation method includes: A first voltage is applied to a first portion of the gate structure, and a second voltage is applied to a second portion of the gate structure; the first voltage and the second voltage are different, so that the semiconductor pillar is in a first state; or, the first voltage and the second voltage are the same, so that the semiconductor pillar is in a second state different from the first state; wherein the first portion and the second portion are spaced apart from each other and arranged along the first direction; the second direction intersects the first direction; or, A first voltage is applied to a first portion of the gate structure, a second voltage is applied to a second portion of the gate structure, and a third voltage is applied to a third portion of the gate structure; the first voltage, the second voltage, and the third voltage are all different, so that the semiconductor pillar is in a first state; or, the first voltage, the second voltage, and the third voltage are all the same, so that the semiconductor pillar is in a second state different from the first state; wherein the first portion, the second portion, and the third portion are spaced apart from each other and arranged along the first direction; the second direction intersects the first direction.

20. The operating method according to claim 19, characterized in that, The second voltage is different from both the first voltage and the third voltage, including: the first voltage is equal to the third voltage.

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