Semiconductor device

Abstract

A semiconductor device is provided that includes a bit line extending in a first direction; semiconductor patterns including a first material spaced apart from each other in the first direction, and the first semiconductor pattern includes a first end and a second end in a second direction, the first end connected to the bit line; a word line extending in a third direction and located on a first side of the semiconductor pattern in the first direction; a data storage pattern including a first electrode connected to the second end of the semiconductor pattern, a second electrode spaced apart from the first electrode, and a dielectric layer between the first electrode and the second electrode; and an etch stop layer between the word line and the first electrode and contacting the semiconductor pattern, and the etch stop layer includes a second material different from the material of the semiconductor pattern.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0007915, filed on January 20, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device. Background Technology

[0003] Technologies that can improve the integration level of semiconductor devices are needed. For two-dimensional (2D) semiconductor devices, the integration level is mainly determined by the area occupied by a unit memory cell, and in this respect, the integration level can depend on the level of fine patterning technology. Summary of the Invention

[0004] Fine patterning techniques require expensive equipment. Therefore, even with increased integration density in 2D semiconductor devices, the achievable integration level remains limited. This paper therefore discusses 3D semiconductor memory devices with 3D-arranged memory cells.

[0005] This disclosure attempts to provide a semiconductor device that can increase the surface area of ​​a data storage pattern by utilizing a separation distance along the vertical direction of the semiconductor pattern and can increase the contact area between the semiconductor pattern and the data storage pattern.

[0006] Embodiments of this disclosure provide a semiconductor device comprising: a bit line extending in a first direction; a plurality of semiconductor patterns spaced apart from each other in the first direction, the plurality of semiconductor patterns including a first semiconductor pattern, the first semiconductor pattern including a first end and a second end along a dimension of the first semiconductor pattern in a second direction different from the first direction, wherein the first end is connected to the bit line; a word line structure extending upward in a third direction different from the first and second directions, wherein the word line structure is on a first side of the first semiconductor pattern, the first side facing the first direction, wherein the first semiconductor pattern includes a first material; a data storage pattern including a first electrode connected to a second end of the first semiconductor pattern, a second electrode spaced apart from the first electrode, and a dielectric layer between the first electrode and the second electrode; and an etch stop layer between the word line structure and the first electrode of the data storage pattern, wherein the etch stop layer contacts the first semiconductor pattern and includes a second material different from the first material, wherein the length of the first electrode of the data storage pattern in the first direction is greater than the length of the first semiconductor pattern in the first direction.

[0007] Another embodiment of this disclosure provides a semiconductor device comprising: a bit line extending in a first direction; a plurality of semiconductor patterns spaced apart from each other in the first direction, the plurality of semiconductor patterns including a first semiconductor pattern, the first semiconductor pattern including a first end and a second end along a dimension of the first semiconductor pattern in a second direction different from the first direction, wherein the first end is connected to the bit line; a word line extending upward in a third direction different from the first and second directions, wherein the word line is on a first side of the first semiconductor pattern, the first side facing the first direction, wherein the first semiconductor pattern includes a first material; a data storage pattern including a first electrode connected to a second end of the first semiconductor pattern, a second electrode spaced apart from the first electrode, and a dielectric layer between the first electrode and the second electrode; and a semiconductor layer located between the word line and the first electrode of the data storage pattern, wherein the semiconductor layer is in contact with the first semiconductor pattern, and wherein the semiconductor layer includes the first material.

[0008] Another embodiment of this disclosure provides a semiconductor device comprising: a bit line extending in a first direction; a plurality of semiconductor patterns spaced apart from each other in the first direction, the plurality of semiconductor patterns including a first semiconductor pattern, the first semiconductor pattern including a first end and a second end along a dimension of the first semiconductor pattern in a second direction different from the first direction, wherein the first end is connected to the bit line; a word line structure extending upward in a third direction different from the first and second directions, wherein the word line structure is on a first side of the first semiconductor pattern, the first side facing the first direction, wherein the first semiconductor pattern includes a first material; and a data storage pattern including a first electrode connected to a second end of the first semiconductor pattern, a second electrode spaced apart from the first electrode, and a dielectric layer between the first electrode and the second electrode, wherein the length of the first electrode of the data storage pattern in the first direction is greater than the length of the first semiconductor pattern in the first direction, and wherein the first electrode includes a first surface facing the first direction and a second surface facing the opposite direction to the facing direction of the first surface, wherein the first surface and the second surface of the first electrode do not overlap with the word line structure in the second direction.

[0009] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, the method comprising: providing an initial stack, the initial stack including: a bit line extending in a first direction; an initial semiconductor pattern having one end connected to the bit line in a second direction different from the first direction and spaced apart in the first direction; and a word line extending upward in a third direction different from the first and second directions and located on one side of the initial semiconductor pattern in the first direction; growing a semiconductor material layer on the other end of the initial semiconductor pattern in the second direction using a selective epitaxial growth (SEG) method; removing the semiconductor material layer and a portion of the initial semiconductor pattern; forming a first electrode in the space where the semiconductor material layer and a portion of the initial semiconductor pattern have been removed; forming a dielectric layer on the first electrode; and forming a second electrode on the dielectric layer to form a data storage pattern.

[0010] Providing an initial stack may include: forming initial semiconductor patterns spaced apart in a first direction; forming word lines on one side of the initial semiconductor patterns in a second direction; and forming bit lines at one end of the initial semiconductor patterns in the second direction.

[0011] Forming an initial semiconductor pattern may include: alternately stacking a sacrificial layer and an active layer on a substrate; patterning the sacrificial layer and the active layer to form a first trench extending in a second direction; forming a first initial fill pattern within the first trench; forming a second trench extending upward in a third direction at one end of the active layer in the second direction; removing the sacrificial layer exposed through the second trench on one side in the second direction; forming a second initial fill pattern within the second trench; forming a third trench extending upward in a third direction at the other end of the active layer in the second direction; removing another sacrificial layer exposed through the third trench; and forming a third initial fill pattern within the third trench.

[0012] Providing an initial stack may include: forming an initial semiconductor pattern; removing a second initial fill pattern; forming a gate insulating layer and word lines between the initial semiconductor patterns spaced apart along a first direction; forming a word line separation layer between the word lines; forming a bit line at one end of the initial semiconductor pattern in a second direction; removing a third initial fill pattern; forming a capping pattern covering the other end of the word lines in the second direction; and forming an etch stop layer at the other end of the capping pattern in the second direction.

[0013] The initial semiconductor pattern can pass through the etch stop layer and be exposed on one side in the second direction, while the first initial fill pattern can be located on both sides of the initial semiconductor pattern in the third direction. A semiconductor material layer can be grown in the space surrounded by the initial semiconductor pattern, the etch stop layer and the first initial fill pattern by a selective epitaxial growth method that uses the initial semiconductor pattern as a seed.

[0014] Semiconductor material layers can be grown on the top surface in a first direction, the bottom surface in a first direction, and the other end in a second direction of the initial semiconductor pattern.

[0015] The semiconductor material layer can contact a heterogeneous interface having semiconductor patterns, etch stop layers, and a first initial fill pattern, which include different materials.

[0016] When a portion of the semiconductor material layer and the initial semiconductor pattern is removed, a portion of the semiconductor material layer may remain on the surface of the etch stop layer in the second direction to form a semiconductor layer located between the word line and the first electrode of the data storage pattern.

[0017] Forming a data storage pattern may include: forming a fourth initial fill pattern between initial semiconductor patterns on a surface where a semiconductor material layer is formed; removing a portion of the semiconductor material layer and the initial semiconductor on the surface; forming a first electrode in the space surrounded by the first initial fill pattern and the fourth initial fill pattern where the semiconductor material layer and a portion of the initial semiconductor pattern have been removed; removing the first initial fill pattern and the fourth initial fill pattern; forming a dielectric layer on the first electrode; and forming a second electrode on the dielectric layer.

[0018] A first electrode can be formed in a space surrounded by a first initial filling pattern and a fourth initial filling pattern according to the shape of a thin film, and a dielectric layer can be formed on the inner and outer surfaces of the first electrode according to the shape of a thin film; and a second electrode can be formed to fill the inner and outer spaces between the dielectric layer of the first electrode.

[0019] A semiconductor device according to one or more embodiments can increase the surface area of ​​a data storage pattern by utilizing a separation distance in the vertical direction of the semiconductor pattern, and can also increase the contact area between the semiconductor pattern and the data storage pattern. Attached Figure Description

[0020] Figure 1 This is a perspective view showing a portion of a semiconductor device according to an embodiment.

[0021] Figure 2 It is along Figure 1 A sectional view taken by line A-A'.

[0022] Figure 3 It is along Figure 1 The sectional view taken by line B-B'.

[0023] Figure 4 This illustrates another implementation method along... Figure 1 A sectional view taken by line A-A'.

[0024] Figure 5This illustrates another implementation method along... Figure 1 The sectional view taken by line B-B'.

[0025] Figure 6 This illustrates another implementation method along... Figure 1 A sectional view taken by line A-A'.

[0026] Figure 7 This illustrates another implementation method along... Figure 1 A sectional view taken by line A-A'.

[0027] Figures 8 to 30 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment, arranged in the order of the manufacturing process.

[0028] Figures 31 to 38 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment, arranged in the process sequence. Detailed Implementation

[0029] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the present disclosure. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein.

[0030] The accompanying drawings and descriptions are to be regarded as illustrative in nature rather than restrictive. The same reference numerals throughout the specification refer to the same elements.

[0031] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. The terms "on" or "above" mean placed on or below the target portion, and do not necessarily mean placed on the upper side of the target portion based on the direction of gravity.

[0032] Furthermore, throughout the specification, the direction perpendicular to the upper surface of the substrate is described as the first direction D1, while two directions parallel to the upper surface of the substrate and intersecting each other are described as the second direction D2 and the third direction D3, respectively. For example, the second direction D2 and the third direction D3 may be perpendicular to each other. As an example, the second direction D2 and the third direction D3 may each be perpendicular to the first direction D1.

[0033] In the following text, refer to Figures 1 to 3 The following describes a semiconductor device according to an embodiment.

[0034] Figure 1 This is a perspective view showing a portion of a semiconductor device according to an embodiment. Figure 2 It is along Figure 1A sectional view taken by line A-A'. Figure 3 It is along Figure 1 The sectional view taken by line B-B'.

[0035] Reference Figures 1 to 3 The semiconductor device may include memory cells arranged in three dimensions. The memory cells may be arranged in a first direction D1, a second direction D2, and a third direction D3. For example, the memory cells may be stacked in the first direction D1.

[0036] Each memory cell can be connected to a bit line BL and a word line WL. The bit line BL can extend along a first direction D1. Memory cells stacked on the first direction D1 can be connected together to a single bit line BL. Multiple bit lines BL can be spaced apart along a third direction D3. Word lines WL can extend along a third direction D3. Memory cells arranged on the first direction D1 can be connected together to a single word line WL. Multiple word lines WL can be spaced apart along the first direction D1.

[0037] Figure 1 A memory cell and its connected bit line BL and word line WL are shown. For clarity and simplicity, Figure 1 Other memory units are omitted. Figure 1 Only what will be shown later Figure 2 A unit of the stacked structure SS described in the text.

[0038] Figure 2 Two memory cells are shown stacked on the first direction D1 and connected together to a single bit line BL. Figure 2 It shows Figure 1 The memory cells spaced apart in the first direction D1 are omitted. For example, the stacked structure SS may include a first layer L1 and a second layer L2 sequentially stacked on the substrate 110. The first layer L1 and the second layer L2 may be stacked in the first direction D1 perpendicular to the substrate 110. The first layer L1 and the second layer L2 may each include a semiconductor pattern 200, a word line WL located on one side of the semiconductor pattern 200 in the first direction D1, and a data storage pattern DS connected to the semiconductor pattern 200. Figure 2 In this diagram, the stacked structure SS is shown as comprising two layers, but is not limited thereto. In some embodiments, the stacked structure SS may include more layers.

[0039] In addition, Figure 2 In this diagram, each layer of the stacked structure SS is shown as including one memory cell, but is not limited thereto. In some embodiments, each layer of the stacked structure SS may include multiple cells. For example, each layer of the stacked structure SS may also include... Figure 2 The memory cell shown is a mirror-symmetric memory cell in the second direction D2. For example, with Figure 2 The stacked structure SS, which is mirror-symmetric to the stacked structure, can also be located on the substrate 110 along the second direction D2. The stacked structure SS and the stacked structure mirror-symmetric to the stacked structure SS can form a pair. The pair of stacked structures can share the second electrode 330 of the data storage pattern DS, which will be described later.

[0040] For example, the stacked structure SS may be located on the substrate 110. For example, the substrate 110 may include silicon, germanium, or silicon-germanium. The stacked structure SS may constitute a memory cell array of a semiconductor device.

[0041] In some embodiments, peripheral circuitry for operating the memory cell array may be located on substrate 110. Additionally, wiring electrically connected to bit lines BL and word lines WL may be located on top of the stacked structure SS, and this wiring may be connected to the peripheral circuitry.

[0042] Bit line BL may be located on one side of the stacked structure SS in the second direction D2. Bit line BL may extend in the first direction D1. For example, bit line BL may be linear or cylindrical extending in the first direction D1.

[0043] Bit line BL can contact one side of semiconductor pattern 200 in the second direction D2. Bit line BL can be electrically connected to semiconductor pattern 200.

[0044] Bit line BL may include a conductive material. The conductive material may include a doped semiconductor material (such as doped silicon or doped germanium), a conductive metal nitride (such as titanium nitride or tantalum nitride), a metal (such as tungsten, titanium or tantalum), a metal semiconductor compound (such as tungsten silicide, cobalt silicide or titanium silicide), or a combination thereof.

[0045] In some embodiments, the first interlayer insulating layer may be located on one side of the stacked structure SS in the second direction D2. The first interlayer insulating layer may extend in a first direction D1 perpendicular to the substrate 110. Alternatively, the first interlayer insulating layer may extend along a third direction D3. Bit lines BL may be located on one side of the first interlayer insulating layer in the second direction D2. Alternatively, the first interlayer insulating layer may be located between bit lines BL spaced apart along the third direction D3. The bit lines BL spaced apart along the third direction D3 can be insulated from each other by the first interlayer insulating layer.

[0046] For example, the first interlayer insulating layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbon oxide layer, a silicon carbon nitride layer, a silicon carbon oxynitride layer, or a combination thereof.

[0047] The word line WL may extend along a third direction D3. The word line WL may have a linear shape extending along the third direction D3. The word line WL may have a first word line WL1 passing over the semiconductor pattern 200 in a first direction D1 and a second word line WL2 passing under the semiconductor pattern 200 in the first direction D1. In other words, the first word line WL1 and the second word line WL2 may be spaced apart from each other in the first direction D1, with the semiconductor pattern 200 between the first word line WL1 and the second word line WL2. In some embodiments, the word line WL extends along a third direction D3, and in areas not crossing the semiconductor pattern 200, the first word line WL1 and the second word line WL2 may merge. The word line WL may surround the semiconductor pattern 200.

[0048] The word line (WL) may include a conductive material. For example, the conductive material may include a semiconductor material, a conductive metal nitride, a metal, a metal semiconductor compound, or a combination thereof.

[0049] The spacer 140 may be located between the word line WL and the bit line BL. The spacer 140 may include an insulating material that can separate the bit line BL and the word line WL in the second direction D2 and can insulate the bit line BL and the word line WL from each other.

[0050] For example, spacer 140 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbon oxide layer, a silicon nitride layer, a silicon oxycarbon nitride layer, or a combination thereof.

[0051] The gate insulating layer Gox may be located between the word line WL and the semiconductor pattern 200. The gate insulating layer Gox may also be located between the spacer 140 and the semiconductor pattern 200. In some embodiments, the gate insulating layer Gox may surround the word line WL and the spacer 140. The gate insulating layer Gox may cover the upper surface, sides, and bottom surface of the word line WL. The gate insulating layer Gox may cover the upper surface and bottom surface of the spacer 140.

[0052] The gate insulating layer Gox can contact the bit line BL. A portion of the bottom surface of the gate insulating layer Gox covering the spacer 140 and the bottom surface of the word line WL can contact the bit line BL. In some embodiments, a portion of the upper surface of the gate insulating layer Gox covering the spacer 140 and the upper surface of the word line WL can also contact the bit line BL.

[0053] The gate insulating layer Gox may have a first gate insulating layer Gox1 located between the first word line WL1 and the semiconductor pattern 200, and a second gate insulating layer Gox2 located between the second word line WL2 and the semiconductor pattern 200. The semiconductor pattern 200 may be spaced apart from the first word line WL1 by the first gate insulating layer Gox1. The semiconductor pattern 200 may be spaced apart from the second word line WL2 by the second gate insulating layer Gox2. In some embodiments, the first gate insulating layer Gox1 and the second gate insulating layer Gox2 may meet each other on opposite sides of the semiconductor pattern 200 in a third direction D3. Therefore, the gate insulating layer Gox may surround the semiconductor pattern 200.

[0054] The gate insulating layer Gox may include a high dielectric layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. For example, the high dielectric layer may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0055] The stacked structure SS may include multiple layers, and a word line separation layer 150 may be located between two adjacent layers of the stacked structure SS. The word line separation layer 150 may be located between a first layer L1 and a second layer L2. Word lines WL and semiconductor patterns 200 of each layer may be located on the word line separation layer 150. The word lines WL of the upper layer and the lower layer may be spaced apart by the word line separation layer 150 in a first direction D1. In the first direction D1, the semiconductor patterns 200 of the upper layer and the lower layer may be spaced apart by the word line separation layer 150 in the first direction D1. The word line separation layer 150 may extend along the word lines WL in a third direction D3.

[0056] One end of the word line separation layer 150 in the second direction D2 can be connected to the bit line BL. The other end of the word line separation layer 150 in the second direction D2 can be connected to the capping pattern 145.

[0057] The word line separation layer 150 may include an insulating material, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbonate layer, a silicon nitride layer, or a silicon oxycarbonate layer.

[0058] In some embodiments, the word line separation layer 150 may include a separation pad and a separation filler layer located between the separation pads. The separation pad may conformally cover the upper and lower surfaces of the word line WL in a first direction D1, and the separation filler layer may fill the space between the separation pads. The separation pad and the separation filler layer may each include an insulating material.

[0059] Semiconductor pattern 200 can be located in each layer of the stacked structure SS.

[0060] One end of the semiconductor pattern 200 in the second direction D2 can be connected to the bit line BL. The other end of the semiconductor pattern 200 in the second direction D2 can be connected to the data storage pattern DS.

[0061] Multiple semiconductor patterns 200 may be arranged spaced apart along the extension direction of the bit line BL in a first direction D1. Additionally, the multiple semiconductor patterns 200 may be arranged spaced apart along a third direction D3, following the spacing direction of the bit line BL. For example, the length of the semiconductor pattern 200 in the third direction D3 may be greater than the length of the semiconductor pattern 200 in the first direction D1, and the spacing distance of the semiconductor patterns 200 in the first direction D1 may be greater than the spacing distance of the semiconductor patterns 200 in the third direction D3.

[0062] Semiconductor pattern 200 may be located between the first gate insulating layer Gox1 and the second gate insulating layer Gox2. Semiconductor pattern 200 may be surrounded by the gate insulating layer Gox. Semiconductor pattern 200 may be surrounded by word line WL, with the gate insulating layer Gox located between the semiconductor pattern 200 and the word line WL. Semiconductor pattern 200 may be located between the first word line WL1 and the second word line WL2.

[0063] At least a portion of the semiconductor pattern 200 may overlap with the word line WL in the first direction D1. At least a portion of the semiconductor pattern 200 may overlap with the spacer 140 and the capping pattern 145 in the first direction D1.

[0064] Furthermore, the other end of the semiconductor pattern 200 in the second direction D2 may overlap with the etch stop layer 130 in the first direction D1. The other end of the semiconductor pattern 200 in the second direction D2 may directly contact the etch stop layer 130. The upper and lower surfaces of the semiconductor pattern 200 in the first direction D1 may contact the etch stop layer 130 at its other end in the second direction D2. The other end of the semiconductor pattern 200 in the second direction D2 and the etch stop layer 130 may form coplanar surfaces. Therefore, the other end of the semiconductor pattern 200 in the second direction D2 may contact the first electrode 310 of the data storage pattern DS through the etch stop layer 130. The first electrode 310 of the data storage pattern DS may simultaneously contact both the other end of the semiconductor pattern 200 in the second direction D2 and the etch stop layer 130.

[0065] Semiconductor pattern 200 may include one or more semiconductor materials. For example, semiconductor pattern 200 may include single-crystal silicon. In some embodiments, semiconductor pattern 200 may include oxide semiconductor materials. The oxide semiconductor material may be a combination of at least two or more of In, Ga, Zn, Al, Sn, and Hf, but is not limited thereto. The oxide semiconductor material may also include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, or Mn in its composition. For example, semiconductor pattern 200 may include IGZO (indium gallium zinc oxide), ITZO (indium tin zinc oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ZTO (zinc tin oxide), ZnON (zinc oxynitride), ZZTO (zinc zinc tin oxide), SnO (tin oxide), HIZO (hafnium indium zinc oxide), GZTO (gallium zinc tin oxide), AZTO (aluminum zinc tin oxide), YGZO (ytterbium gallium zinc oxide), IGO (indium gallium oxide), or combinations thereof.

[0066] Semiconductor pattern 200 may have impurity regions and channel regions between them. The impurity regions may correspond to the source / drain regions of a memory cell transistor. The impurity regions may be regions in semiconductor pattern 200 that have already been doped with impurities. The impurity regions may have n-type conductivity or p-type conductivity. The impurity regions may be located adjacent to both ends of semiconductor pattern 200 in the second direction D2.

[0067] The capping pattern 145 may be located on one or both sides of the semiconductor pattern 200 in the first direction D1. The capping pattern 145 may be in contact with the semiconductor pattern 200 on one or both sides in the first direction D1. The capping pattern 145 may be arranged alternately with the semiconductor pattern 200 in the first direction D1.

[0068] The cap pattern 145 may extend along the letter line WL in the third direction D3. The cap pattern 145 may extend along the letter line separation layer 150 in the third direction D3.

[0069] For example, the capping pattern 145 may have a first capping portion 146 and a second capping portion 147. The first capping portion 146 may be located on both sides of the second capping portion 147 in the first direction D1.

[0070] The capping portion 146 may be located between the word line WL and the data storage pattern DS in the second direction D2. The capping portion 146 may also be located between the word line WL and the etch stop layer 130 in the second direction D2. The first capping portion 146 may be located between the first word line WL1 and the etch stop layer 130 in the second direction D2, and the first capping portion 146 may also be located between the second word line WL2 and the etch stop layer 130 in the second direction D2. In other words, one side of the first capping portion 146 in the second direction D2 may contact the first word line WL1 and the second word line WL2. Additionally, one side of the first capping portion 146 in the second direction D2 may also contact the gate insulating layer Gox. The other side of the first capping portion 146 in the second direction D2 may contact the etch stop layer 130.

[0071] The second cap portion 147 may be located between the word line separation layer 150 and the data storage pattern DS in the second direction D2. The second cap portion 147 may also be located between the word line separation layer 150 and the etch stop layer 130 in the second direction D2. In other words, one side of the second cap portion 147 in the second direction D2 may contact the word line separation layer 150, and the other side of the second cap portion 147 in the second direction D2 may contact the etch stop layer 130.

[0072] The capping pattern 145 may include an insulating material. For example, the capping pattern 145 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

[0073] The etch stop layer 130 may be located between the word line WL and the first electrode 310 of the data storage pattern DS. The etch stop layer 130 may also be located between the capping pattern 145 and the first electrode 310 of the data storage pattern DS. One side of the etch stop layer 130 in the second direction D2 may contact the capping pattern 145. The etch stop layer 130 may conformally cover the other side of the capping pattern 145 in the second direction D2. In other words, the etch stop layer 130 may be a thin film with a uniform thickness along the surface shape of the other side of the capping pattern 145 in the second direction D2.

[0074] The etch stop layer 130 is accessible to the data storage pattern DS on the other side of the second direction D2. The etch stop layer 130 is also accessible to the first electrode 310 of the data storage pattern DS on the other side of the second direction D2. The etch stop layer 130 is also accessible to the dielectric layer 320 of the data storage pattern DS on the other side of the second direction D2 that does not contact the first electrode 310. The etch stop layer 130 may not contact the second electrode 330 of the data storage pattern DS.

[0075] The etch stop layer 130 may have a portion above the semiconductor pattern 200 in the first direction D1 and a portion below the semiconductor pattern 200 in the first direction D1. In other words, the etch stop layers 130 may be arranged spaced apart in the first direction D1, and the semiconductor pattern 200 is located between the etch stop layers 130.

[0076] Furthermore, the etch stop layer 130 may overlap with the other end of the semiconductor pattern 200 in the second direction D2 in the first direction D1. The etch stop layer 130 may directly contact the other end of the semiconductor pattern 200 in the second direction D2. The etch stop layer 130 may contact the upper and lower surfaces of the semiconductor pattern 200 in the first direction D1 at the other end in the second direction D2. The etch stop layer 130 and the other end of the semiconductor pattern 200 in the second direction D2 may form a coplanar surface. As a result, the other end of the semiconductor pattern 200 in the second direction D2 may contact the first electrode 310 of the data storage pattern DS through the etch stop layer 130. In other words, one side of the first electrode 310 of the data storage pattern DS in the second direction D2 may simultaneously contact the other end of the semiconductor pattern 200 in the second direction D2 and the etch stop layer 130.

[0077] The etch stop layer 130 may comprise a material different from that of the semiconductor pattern 200. For example, the etch stop layer 130 may comprise a material that is etch-selective relative to the material of the semiconductor pattern 200. Therefore, the etch stop layer 130 may not include the semiconductor material that the semiconductor pattern 200 may comprise, such as single-crystal silicon or oxide semiconductor material. For example, the etch stop layer 130 may comprise silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbon oxynitride, or combinations thereof.

[0078] Therefore, one side of the first electrode 310 of the data storage pattern DS in the second direction D2 can contact a heterogeneous interface having a semiconductor pattern 200 and an etch stop layer 130 comprising different materials.

[0079] Additionally, the etch stop layer 130 may include elements described later. Figure 16 The material of the first initial fill pattern PF1 can be different from that of silicon nitride. For example, when the first initial fill pattern PF1 comprises silicon nitride, the etch stop layer 130 may comprise silicon oxide. However, this is not a limitation, and the materials of the etch stop layer 130 and the first initial fill pattern PF1 may comprise a variety of materials, as long as they have etch selectivity relative to each other.

[0080] Therefore, as Figure 16 The following description is provided by Figure 16 In the space surrounded by the initial semiconductor pattern 170, the etch stop layer 130, and the first initial fill pattern PF1, Figure 16The semiconductor material layer 251 can be grown only on the surface of the initial semiconductor pattern 170 by a selective epitaxial growth method.

[0081] The data storage pattern DS can be electrically connected to the semiconductor pattern 200. The data storage pattern DS is a memory element capable of storing data, for example, it can be a memory element utilizing a capacitor, a memory element utilizing a magnetic tunnel junction pattern, or a memory element utilizing a variable resistor body containing a phase change material.

[0082] For example, the data storage pattern DS can be a capacitor. The data storage pattern DS may include a first electrode 310, a second electrode 330 spaced apart from the first electrode 310, and a dielectric layer 320 between the first electrode 310 and the second electrode 330.

[0083] The first electrode 310 may have a first sidewall 311, a second sidewall 312, a third sidewall 313, a fourth sidewall 314, and a fifth sidewall 315.

[0084] The first sidewall 311 may be located on one side of the data storage pattern DS in the second direction D2. For example, the first sidewall 311 may have a surface parallel to the first direction D1 and the third direction D3. The first sidewall 311 may contact the coplanar surfaces of the semiconductor pattern 200 and the etch stop layer 130. The first sidewall 311 may primarily overlap with the second electrode 330 in the second direction D2. The first sidewall 311 may contact one side of each of the second sidewall 312, the third sidewall 313, the fourth sidewall 314, and the fifth sidewall 315 in the second direction D2.

[0085] The second sidewall 312 and the third sidewall 313 may be arranged spaced apart from each other in the first direction D1. Each of the second sidewall 312 and the third sidewall 313 may contact one side and the other side of the first sidewall 311 in the first direction D1. Each of the second sidewall 312 and the third sidewall 313 may extend from the first sidewall 311 in the second direction D2. For example, the second sidewall 312 and the third sidewall 313 may have surfaces parallel to the second direction D2 and the third direction D3. Each of the second sidewall 312 and the third sidewall 313 may be alternately arranged with the second electrode 330 in the first direction D1. In other words, the second sidewall 312 and the third sidewall 313 may primarily overlap with the second electrode 330 in the first direction D1.

[0086] The fourth sidewall 314 and the fifth sidewall 315 may be arranged separately from each other in the third direction D3. Each of the fourth sidewall 314 and the fifth sidewall 315 may contact one side and the other side of the first sidewall 311 in the third direction D3. Each of the fourth sidewall 314 and the fifth sidewall 315 may contact one side and the other side of the second sidewall 312 and the third sidewall 313 in the third direction D3, respectively. Each of the fourth sidewall 314 and the fifth sidewall 315 may extend from the first sidewall 311 in the second direction D2. Furthermore, each of the fourth sidewall 314 and the fifth sidewall 315 may extend between the second sidewall 312 and the third sidewall 313 in the first direction D1. For example, the fourth sidewall 314 and the fifth sidewall 315 may have surfaces parallel to the first direction D1 and the second direction D2. Each of the fourth sidewall 314 and the fifth sidewall 315 may be arranged alternately with the second electrode 330 in the third direction D3. In other words, the fourth sidewall 314 and the fifth sidewall 315 can mainly overlap with the second electrode 330 on the third direction D3.

[0087] For example, the first electrode 310 may have an inner space surrounded by a first sidewall 311, a second sidewall 312, a third sidewall 313, a fourth sidewall 314, and a fifth sidewall 315. In other words, the first electrode 310 may have a cylindrical shape extending in the second direction D2. The inner space of the first electrode 310 may also be used to arrange the second electrode 330, thereby further increasing the surface area of ​​the data storage pattern DS.

[0088] The second electrode 330 may have an interior 331, an exterior 332, and a connecting portion 333.

[0089] The interior 331 may be located within the first electrode 310. The interior 331 may be inserted into and surrounded by the first electrode 310. For example, the interior 331 may be located in an inner space surrounded by the first sidewall 311, second sidewall 312, third sidewall 313, fourth sidewall 314, and fifth sidewall 315 of the first electrode 310, and may be inserted into the inner space of the first electrode 310, which may be cylindrical. The interior 331 may extend along the second sidewall 312, third sidewall 313, fourth sidewall 314, and fifth sidewall 315 of the first electrode 310 in a second direction D2.

[0090] The outer portion 332 may be located outside the first electrode 310. The outer portion 332 may surround the first electrode 310. For example, the outer portion 332 may be located outside the inner space surrounded by the first sidewall 311, second sidewall 312, third sidewall 313, fourth sidewall 314, and fifth sidewall 315 of the first electrode 310, and may be located within the outer space of the first electrode 310, which is, for example, cylindrical. The outer portion 332 may extend along the second sidewall 312, third sidewall 313, fourth sidewall 314, and fifth sidewall 315 of the first electrode 310 in the second direction D2.

[0091] The connection portion 333 may be located on the other side of the first electrode 310 in the second direction D2. The connection portion 333 may connect the outer portion 332 and the inner portion 331. The connection portion 333 may contact the outer portion 332 on the other side of the second direction D2, and the connection portion 333 may be located on the other side of the inner portion 331 in the second direction D2. The connection portion 333 may extend along the stacked structure SS in the first direction D1 to connect multiple outer portions 332 and inner portions 331. In this way, the data storage pattern DS of multiple layers stacked in the first direction D1 can share a single second electrode 330.

[0092] The first electrode 310 and the second electrode 330 may each include a metallic material such as titanium, tantalum, tungsten, copper or aluminum, a conductive metal nitride such as titanium nitride or tantalum nitride, or a doped semiconductor material such as doped silicon or doped germanium.

[0093] The dielectric layer 320 may be located between the first electrode 310 and the second electrode 330. The dielectric layer 320 may conformally cover the top of the first electrode 310. In other words, the dielectric layer 320 may be a thin film with a uniform thickness along the surface shape of the other side of the first electrode 310 in the second direction D2.

[0094] The dielectric layer 320 may cover both the inner and outer surfaces of the first electrode 310. In other words, the dielectric layer 320 may cover the other side of the first sidewall 311 of the first electrode 310 in the second direction D2. The dielectric layer 320 may cover one side and the other side of the second sidewall 312 and the third sidewall 313 of the first electrode 310 in the first direction D1. The dielectric layer 320 may cover one side and the other side of the fourth sidewall 314 and the fifth sidewall 315 of the first electrode 310 in the third direction D3.

[0095] The dielectric layer 320 located within the first electrode 310 can be surrounded by the first electrode 310. The dielectric layer 320 located outside the first electrode 310 can surround the first electrode 310. The dielectric layer 320 located outside the first electrode 310 can be surrounded by the second electrode 330.

[0096] For example, dielectric layer 320 may include a dielectric material, a ferromagnet, a semi-ferromagnet, or a combination thereof. The dielectric material may include a high dielectric constant material. For example, the dielectric material may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0097] As later Figures 18 to 24 As described above, the first electrode 310 of the data storage pattern DS can be formed in the area where the data storage pattern DS has been removed. Figure 18In a portion of the space of the initial semiconductor pattern 170, the semiconductor pattern 200 and the first electrode 310 of the data storage pattern DS are self-aligned. However, since the length W1_310 of the first electrode 310 of the data storage pattern DS along the first direction D1 is limited by the length W1_200 of the semiconductor pattern 200 along the first direction D1, the increase in the surface area of ​​the data storage pattern DS is restricted. On the other hand, the length of the semiconductor pattern 200 along the third direction D3 is greater than the length along the first direction D1, and the separation distance of the semiconductor pattern 200 along the first direction D1 is greater than the separation distance along the third direction D3. In other words, the semiconductor device needs to increase the surface area of ​​the data storage pattern DS by utilizing the separation distance of the semiconductor pattern 200 along the first direction D1.

[0098] As described above, the semiconductor device includes an etch stop layer 130 that directly contacts the semiconductor pattern 200, such that the other side of the semiconductor pattern 200 in the second direction D2 can be connected to the first electrode 310 of the data storage pattern DS via the etch stop layer 130. In other words, one side of the first electrode 310 of the data storage pattern DS in the second direction D2 can contact a heterogeneous interface having a semiconductor pattern 200 and an etch stop layer 130 comprising different materials.

[0099] As later Figure 16 As described above, the semiconductor material layer 251 can be grown only on the surface of the initial semiconductor pattern 170 within the space surrounded by the initial semiconductor pattern 170, the etch stop layer 130, and the first initial fill pattern PF1 using a selective epitaxial growth method. Therefore, by increasing the length of the initial semiconductor pattern 170 along the first direction D1, and then forming the first electrode 310 of the data storage pattern DS in the space where the increased length of the initial semiconductor pattern 170 along the first direction D1 has been removed, the surface area of ​​the data storage pattern DS can be increased. In other words, since the semiconductor device includes the etch stop layer 130, and the initial semiconductor pattern 170 and the etch stop layer 130 form a heterogeneous interface, the semiconductor material layer 251 can be grown only on the surface of the initial semiconductor pattern 170 using a selective epitaxial growth method.

[0100] Therefore, the length W1_310 of the first electrode 310 of the data storage pattern DS in the first direction D1 can be greater than the length W1_200 of the semiconductor pattern 200 in the first direction D1. By utilizing the separation distance of the semiconductor pattern 200 along the first direction D1, the surface area of ​​the data storage pattern DS can be increased in the semiconductor device.

[0101] Here, the length W1_310 of the first electrode 310 of the data storage pattern DS in the first direction D1 can be the shortest distance in the first direction D1 from the bottom surface of the second sidewall 312 of the first electrode 310 to the top surface of the third sidewall 313 of the first electrode 310 in the first direction D1. Alternatively, the length W1_310 of the first electrode 310 of the data storage pattern DS in the first direction D1 can be the shortest distance in the first direction D1 from the bottom of the first sidewall 311 of the first electrode 310 to the top of the first sidewall 311 in the first direction D1. Additionally, the length W1_200 of the semiconductor pattern 200 in the first direction D1 can be the shortest distance in the first direction D1 from the bottom surface of the semiconductor pattern 200 to the top surface of the semiconductor pattern 200 in the first direction D1.

[0102] For example, the length W1_310 of the first electrode 310 of the data storage pattern DS in the first direction D1 can be greater than 1.1 times the length of the semiconductor pattern 200 in the first direction D1. For example, it can be 1.2 times or more, 1.5 times or more, 2.0 times or more, 2.5 times or more, 3.0 times or more, 3.5 times or more, 4.0 times or more, or 4.5 times or more, and it can be 5 times or less. For example, it can be 4.5 times or less, 4.0 times or less, 3.5 times or less, 3.0 times or less, 2.5 times or less, 2.0 times or less, 1.5 times or less, or 1.2 times or less. For example, it can be greater than 1.1 times and less than or equal to 5 times. In other words, the increased length W1_310 of the first electrode 310 of the data storage pattern DS in the first direction D1 is not the horizontal length of the thin film, but can be several times larger than the length W1_200 of the semiconductor pattern 200 in the first direction D1.

[0103] The length W1_310 of the first electrode 310 in the first direction D1 can be 0.5 times or greater than the length W3_310 of the first electrode 310 in the third direction D3, for example, it can be 1.0 times or greater, 1.5 times or greater, 2.0 times or greater, 2.5 times or greater, 3.0 times or greater, 3.5 times or greater, 4.0 times or greater, or 4.5 times or greater, and it can be 5.0 times or less, for example, 4.5 times or less, 4.0 times or less, 3.5 times or less, 3.0 times or less, 2.5 times or less, 2.0 times or less, 1.5 times or less, or 1.0 times or less, for example, it can be from 0.5 times to 5.0 times. In other words, the aspect ratio of the length W1_310 of the first electrode 310 in the first direction D1 to the length W3_310 of the first electrode 310 in the third direction D3 can be from 0.5 to 5.0. The semiconductor device can increase the surface area of ​​the data storage pattern DS by utilizing the separation distance according to the first direction D1 of the semiconductor pattern 200.

[0104] Here, the length W3_310 of the first electrode 310 of the data storage pattern DS in the third direction D3 can be the shortest distance in the third direction D3 from one side of the fourth sidewall 314 of the first electrode 310 in the third direction D3 to the other side of the fifth sidewall 315 of the first electrode 310 in the third direction D3. Alternatively, the length W3_310 of the first electrode 310 of the data storage pattern DS in the third direction D3 can be the shortest distance in the third direction D3 from one side of the first sidewall 311 in the third direction D3 to the other side of the first sidewall 311 in the third direction D3.

[0105] As described above, since the semiconductor device includes an etch stop layer 130, an initial semiconductor pattern 170, and the etch stop layer 130 forming a heterogeneous interface, and by selectively epitaxially growing a semiconductor material layer 251 only on the surface of the initial semiconductor pattern 170 to increase the length of the initial semiconductor pattern 170 in the first direction D1, the two opposing surfaces of the first electrode 310 of the data storage pattern DS in the first direction D1 do not overlap with the word line WL in the second direction D2. For example, the bottom surface of the second sidewall 312 of the first electrode 310 in the first direction D1 does not overlap with the first word line WL1 of the word line WL in the second direction D2. Furthermore, the upper surface of the third sidewall 313 of the first electrode 310 in the first direction D1 does not overlap with the second word line WL2 of the word line WL in the second direction D2.

[0106] For example, the two sides of the first electrode 310 of the data storage pattern DS in the first direction D1 may overlap with the word line separation layer 150 in the second direction D2. For example, the bottom surface of the second sidewall 312 of the first electrode 310 in the first direction D1 may overlap with the word line separation layer 150 in the second direction D2. In addition, the upper surface of the third sidewall 313 of the first electrode 310 in the first direction D1 may overlap with the word line separation layer 150 in the second direction D2.

[0107] Furthermore, the two sides of the first electrode 310 of the data storage pattern DS in the first direction D1 may not overlap with the semiconductor pattern 200 in the second direction D2. For example, the bottom surface of the second sidewall 312 of the first electrode 310 in the first direction D1 may not overlap with the semiconductor pattern 200 in the second direction D2. In addition, the upper surface of the third sidewall 313 of the first electrode 310 in the first direction D1 may not overlap with the semiconductor pattern 200 in the second direction D2.

[0108] As described above, in the space surrounded by the initial semiconductor pattern 170, the etch stop layer 130, and the first initial fill pattern PF1, a semiconductor material layer 251 is grown only on the surface of the initial semiconductor pattern 170 via a selective epitaxial growth method. The semiconductor material layer 251 can be grown only on the upper and lower surfaces of the initial semiconductor pattern 170 in the first direction D1, and no semiconductor material layer 251 may be grown in the space between the initial semiconductor patterns 170 in the third direction D3. Therefore, as the length of the initial semiconductor pattern 170 increases along the first direction D1, the nodes of the first electrode 310 of the data storage pattern DS can be separated. In other words, the semiconductor material layer 251 formed on the surface of the initial semiconductor pattern 170 and the semiconductor material layer 251 formed on the surface of another adjacent initial semiconductor pattern 170 may not be connected to each other and may be spaced apart along the initial semiconductor pattern 170.

[0109] In the following text, refer to Figures 4 to 7 The following describes a semiconductor device according to various embodiments.

[0110] Figure 4 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 5 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0111] Figure 4 and Figure 5 The implementation methods shown are the same as Figure 2 and Figure 3The embodiments shown are essentially the same, therefore explanations of these parts will be omitted and the differences will be mainly described. Additionally, the same reference numerals are used for the same components as in the previous embodiments.

[0112] exist Figure 2 and Figure 3 In the data storage pattern DS, the first electrode 310 may have an inner space surrounded by a first sidewall 311, a second sidewall 312, a third sidewall 313, a fourth sidewall 314 and a fifth sidewall 315, and may be, for example, cylindrical.

[0113] Reference Figure 4 and Figure 5 The first electrode 310 of the data storage pattern DS does not have an inner space surrounded by the first sidewall 311, the second sidewall 312, the third sidewall 313, the fourth sidewall 314 and the fifth sidewall 315, but instead shows a cylindrical shape in which the inner space is also filled by the first electrode 310.

[0114] For example, the first electrode 310 may have a first surface, a second surface BS_310, a third surface US_310, a fourth surface, a fifth surface, and a sixth surface.

[0115] The first and sixth surfaces may be arranged spaced apart from each other in the second direction D2. The first surface may be located on one side of the data storage pattern DS in the second direction D2. The sixth surface may be located on the other side of the data storage pattern DS in the second direction D2. For example, the first and sixth surfaces may be parallel to the first direction D1 and the third direction D3. The first surface may contact the coplanar surfaces of the semiconductor pattern 200 and the etch stop layer 130. The sixth surface may contact the connection portion 333 of the second electrode 330. The first surface may contact one side of each of the second surface BS_310, the third surface US_310, the fourth surface, and the fifth surface in the second direction D2. The sixth surface may contact the other side of each of the second surface BS_310, the third surface US_310, the fourth surface, and the fifth surface in the second direction D2.

[0116] The second surface BS_310 and the third surface US_310 may be arranged to be spaced apart from each other in the first direction D1. The second surface BS_310 and the third surface US_310 may respectively contact one side and the other side of the first surface and the sixth surface in the first direction D1. The second surface BS_310 and the third surface US_310 may each extend between the first surface and the sixth surface in the second direction D2. For example, the second surface BS_310 and the third surface US_310 may be parallel to the second direction D2 and the third direction D3.

[0117] The fourth and fifth surfaces may be arranged to be spaced apart from each other in the third direction D3. Each of the fourth and fifth surfaces may contact one side and the other side of the third direction D3 of the first and sixth surfaces, respectively. Each of the fourth and fifth surfaces may contact one end and the other end of the third direction D3 of the second surface BS_310 and the third surface US_310, respectively. Each of the fourth and fifth surfaces may extend in the second direction D2 between the first and sixth surfaces. Additionally, each of the fourth and fifth surfaces may extend in the first direction D1 between the second surface BS_310 and the third surface US_310. For example, the fourth and fifth surfaces may be parallel to the first direction D1 and the second direction D2.

[0118] For example, the space surrounded by the first surface, second surface BS_310, third surface US_310, fourth surface, fifth surface, and sixth surface of the first electrode 310 may be completely filled with the same material. In other words, the first electrode 310 may have a cylindrical shape extending in the second direction D2.

[0119] The second electrode 330 may have an outer portion 332 and a connecting portion 333.

[0120] In other words, since the first electrode 310 does not have an internal space, the second electrode 330 may not have an interior 331.

[0121] The outer surface 332 may be located outside the first electrode 310. The outer surface 332 may surround the first electrode 310. For example, the outer surface 332 may contact the second surface BS_310, the third surface US_310, the fourth surface, and the fifth surface of the first electrode 310. The outer surface 332 may extend along the second surface BS_310, the third surface US_310, the fourth surface, and the fifth surface of the first electrode 310 in the second direction D2.

[0122] The connection portion 333 may be located on the other side of the first electrode 310 in the second direction D2. The connection portion 333 may contact the sixth surface of the first electrode 310 on the other side of the second direction D2. The connection portion 333 may contact the external portion 332 on the other side of the second direction D2. The connection portion 333 may connect multiple external portions 332 by extending along the stacked structure SS in the first direction D1. As a result, the data storage pattern DS of multiple layers stacked in the first direction D1 may share a single second electrode 330.

[0123] The dielectric layer 320 may be located between the first electrode 310 and the second electrode 330. The dielectric layer 320 may conformally cover the first electrode 310. In other words, the dielectric layer 320 may be a thin film with a uniform thickness along the other side of the first electrode 310 in the second direction D2.

[0124] The dielectric layer 320 may cover the exterior of the first electrode 310. In other words, the dielectric layer 320 may cover one side of the second surface BS_310 of the first electrode 310 in the first direction D1. The dielectric layer 320 may cover one side of the third surface US_310 of the first electrode 310 in the first direction D1. The dielectric layer 320 may cover one side of the fourth surface of the first electrode 310 in the third direction D3. The dielectric layer 320 may cover the other side of the fifth surface of the first electrode 310 in the third direction D3. The dielectric layer 320 may cover the other side of the sixth surface of the first electrode 310 in the second direction D2.

[0125] The dielectric layer 320 may surround the first electrode 310. The dielectric layer 320 may be surrounded by the second electrode 330.

[0126] Figure 6 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 7 It corresponds to Figure 4 along Figure 1 A sectional view taken by line A-A'.

[0127] Figure 6 and Figure 7 The implementation methods shown are the same as Figure 2 and Figure 4 The embodiments shown are essentially the same, so explanations of these parts will be omitted and the differences will be explained primarily. Additionally, the same reference numerals are used for the same components as in the previous embodiments.

[0128] Reference Figure 6 and Figure 7 Semiconductor layer 250 may be located between word line WL and first electrode 310 of data storage pattern DS. Semiconductor layer 250 may be located between etch stop layer 130 and first electrode 310 of data storage pattern DS. One surface of semiconductor layer 250 in the second direction D2 may contact etch stop layer 130. Semiconductor layer 250 may conformally cover another surface of etch stop layer 130 in the second direction D2. In other words, semiconductor layer 250 may be a thin film with a uniform thickness along the surface shape of the other side of etch stop layer 130 in the second direction D2.

[0129] Another surface of the semiconductor layer 250 in the second direction D2 may contact the data storage pattern DS. The other surface of the semiconductor layer 250 in the second direction D2 may contact the first electrode 310 of the data storage pattern DS.

[0130] The semiconductor layer 250 may overlap with the dielectric layer 320 or the second electrode 330 of the data storage pattern DS in the first direction D1. The semiconductor layer 250 may overlap with the first electrode 310 of the data storage pattern DS in the second direction D2.

[0131] Semiconductor layer 250 may have an upper semiconductor layer portion located above semiconductor pattern 200 in the first direction D1 and a lower semiconductor layer portion located below semiconductor pattern 200 in the first direction D1. In other words, semiconductor layers 250 may be arranged spaced apart in the first direction D1, and semiconductor pattern 200 is located between semiconductor layers 250.

[0132] Furthermore, the semiconductor layer 250 may overlap with the other end of the semiconductor pattern 200 in the second direction D2 in the first direction D1. The semiconductor layer 250 may directly contact the other end of the semiconductor pattern 200 in the second direction D2. The semiconductor layer 250 may contact the upper and lower surfaces of the semiconductor pattern 200 in the first direction D1 at the other end in the second direction D2. The semiconductor layer 250 and the other end of the semiconductor pattern 200 in the second direction D2 may form a coplanar surface. Therefore, the other side of the semiconductor pattern 200 in the second direction D2 may contact the first electrode 310 of the data storage pattern DS through the semiconductor layer 250. In other words, one side of the first electrode 310 of the data storage pattern DS in the second direction D2 may simultaneously contact the other end of the semiconductor pattern 200 in the second direction D2 and the semiconductor layer 250.

[0133] Semiconductor layer 250 may comprise the same material as semiconductor pattern 200. Therefore, semiconductor layer 250 may comprise a semiconductor material. For example, semiconductor layer 250 may comprise single-crystal silicon. In some embodiments, semiconductor layer 250 may comprise an oxide semiconductor material. The oxide semiconductor material may be combined with at least two or more of In, Ga, Zn, Al, Sn, and Hf, but is not limited thereto. The oxide semiconductor material may also include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, or Mn in its composition. For example, the semiconductor pattern 200 may include IGZO (indium gallium zinc oxide), ITZO (indium tin zinc oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ZTO (zinc tin oxide), ZnON (zinc oxynitride), ZZTO (zinc zinc tin oxide), SnO (tin oxide), HIZO (hafnium indium zinc oxide), GZTO (gallium zinc tin oxide), AZTO (aluminum zinc tin oxide), YGZO (ytterbium gallium zinc oxide), IGO (indium gallium oxide), or combinations thereof.

[0134] As will be later Figure 22As described, when a portion of the initial semiconductor pattern 170 and the semiconductor material layer 251 is removed, a portion of the semiconductor material layer 251 may remain on the surface of the etch stop layer 130 in the second direction D2, forming a semiconductor layer 250 located between the word line WL and the first electrode 310 of the data storage pattern DS and in contact with the semiconductor pattern 200.

[0135] The semiconductor layer 250 is connected between the semiconductor pattern 200 and the first electrode 310 of the data storage pattern DS, which can increase the contact area between the semiconductor pattern 200 and the first electrode 310 of the data storage pattern DS.

[0136] In the following text, refer to Figures 8 to 38 This will describe a method for manufacturing semiconductor devices.

[0137] Figures 8 to 30 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment, arranged in the order of the manufacturing process. Figures 8 to 30 The manufacturing process is shown. Figures 1 to 3 Methods for developing semiconductor devices.

[0138] Figure 8 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 9 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0139] Reference Figure 8 and Figure 9 A sacrificial layer SAL and an active layer ACL can be alternately stacked on a substrate 110. Each of the sacrificial layer SAL and the active layer ACL can include a semiconductor material. The sacrificial layer SAL can include a material that is etch-selective relative to the active layer ACL. Therefore, during subsequent removal processes of the sacrificial layer SAL, the active layer ACL can be retained or partially removed even when the sacrificial layer SAL is removed. For example, the active layer ACL can include silicon (Si), germanium (Ge), or silicon-germanium (SiGe), and the sacrificial layer SAL can include one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe) that is different from the active layer ACL. For example, the active layer ACL can include silicon (Si), and the sacrificial layer SAL can include silicon-germanium (SiGe). The thickness of the sacrificial layer SAL can be greater than the thickness of the active layer ACL.

[0140] Figure 10 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 11 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0141] Reference Figure 10 and Figure 11 An initial semiconductor pattern 170 is formed spaced apart in the first direction D1.

[0142] First, the sacrificial layer SAL and the active layer ACL can be patterned to form a first trench TR1. The first trench TR1 can extend in a second direction D2 and can be formed to be spaced apart from each other along the second direction D2 and the third direction D3. The first trench TR1 is formed in the first direction D1 from the uppermost sacrificial layer SAL or the uppermost active layer ACL to the substrate 110, thereby allowing a portion of the upper surface of the substrate 110 to be exposed to the outside.

[0143] By forming the first trench TR1, the remaining sacrificial layer SAL after patterning can form the first sacrificial pattern, and the remaining active layer ACL after patterning can form the initial active pattern. The first sacrificial pattern and the initial active pattern may include regions extending in the second direction D2 between the first trenches TR1 spaced apart from each other in the third direction D3, and regions extending in the third direction D3 that intersect with the regions extending in the second direction D2.

[0144] After the first trench TR1 is formed, a first initial fill pattern PF1 may fill the first trench TR1. The first initial fill pattern PF1 may cover the upper surface of the exposed substrate 110. The initial fill pattern PF1 may be spaced apart from each other in a second direction D2 and a third direction D3 by an initial active pattern and a first sacrificial pattern. For example, the first initial fill pattern PF1 may include an insulating material.

[0145] Next, after forming the first initial fill pattern PF1, a second trench TR2 can be formed. The second trench TR2 can be formed on one side of the first sacrificial pattern and the initial active pattern in the second direction D2, and can extend along the third direction D3.

[0146] For example, the second trench TR2 can be formed by patterning a portion of a region extending in the third direction D3 between the first sacrificial pattern and the initial active pattern on a plane. In some embodiments, a portion of the upper part of the substrate 110 may be removed when forming the second trench TR2.

[0147] By forming the second trench TR2, the remaining initial active pattern after patterning can constitute an active pattern. The second trench TR2 exposes one side of the first sacrificial pattern, the active pattern, and the first initial fill pattern PF1 in the second direction D2. The second trench TR2 exposes part of the upper surface of the substrate 110.

[0148] After the second trench TR2 is formed, one side of the first sacrificial pattern exposed through the second trench TR2 in the second direction D2 can be selectively removed by a selective etching process. The remaining first sacrificial pattern after removal by the selective etching process can constitute the second sacrificial pattern. During the selective etching process, a portion of each of the first initial fill patterns PF1 can be removed together, thereby exposing a portion of the upper surface of the substrate 110. The sidewalls of the initial fill patterns PF1 in the second direction D2 can be aligned with the sidewalls of the second sacrificial patterns in the second direction D2.

[0149] By selectively removing one side of the first sacrificial pattern in the second direction D2, a first internal region can be formed between adjacent active patterns along the first direction D1.

[0150] For example, selectively removing one side of the first sacrificial pattern exposed through the second trench TR2 in the second direction D2 may include: forming a mask pattern on the first initial fill pattern PF1 and the active pattern, and removing a portion of the first initial fill pattern PF1 and the first sacrificial pattern on one side of the second direction D2 by a selective etching process.

[0151] After selectively removing one side of the first sacrificial pattern exposed through the second trench TR2 in the second direction D2, a second initial fill pattern PF2 may fill the first internal region and the exposed upper surface of the substrate 110. The second initial fill pattern PF2 may surround and cover active patterns that do not vertically overlap with the second sacrificial pattern. The second initial fill pattern PF2 may comprise a single film or composite film containing an insulating material. As an example, the second initial fill pattern PF2 may comprise silicon oxide, silicon nitride, or a combination thereof. For example, the second initial fill pattern PF2 may comprise a material that can have etch selectivity relative to the first initial fill pattern PF1.

[0152] Next, after forming the second initial fill pattern PF2, a third trench TR3 may be formed. The third trench TR3 may be formed on the opposite side of the second sacrificial pattern and the active pattern in the second direction D2, and the third trench TR3 may extend along the third direction D3. For example, the third trench TR3 may be formed by patterning the second sacrificial pattern and the active pattern extending in the third direction D3, thereby exposing a portion of the upper surface of the substrate 110. In some embodiments, the third trench TR3 is formed, and a portion of the substrate 100 corresponding to the third trench TR30 on top may be removed.

[0153] By selective etching, the remaining active pattern after removal can form the initial semiconductor pattern 170. The third trench TR3 can expose the other side of the initial semiconductor pattern 170 in the second direction D2.

[0154] After the third trench TR3 is formed, all the second sacrificial patterns can be removed by an etching process. Therefore, a second inner region can be formed between adjacent initial semiconductor patterns 170 along the first direction D1. The second inner region can vertically overlap with the regions of the initial semiconductor patterns 170 that do not overlap with the second initial fill pattern PF2.

[0155] In some implementations, the first initial fill pattern PF1 can be removed together with the second sacrificial pattern. All of the first initial fill pattern PF1 can be removed by an etching process. However, as will be discussed later... Figure 16 As described in the text, in order to grow a semiconductor material layer 251 only on the surface of the initial semiconductor pattern 170 in the space surrounded by the initial semiconductor pattern 170, the etch stop layer 130 and the first initial fill pattern PF1, the first initial fill pattern PF1 may not be removed.

[0156] After removing the second sacrificial pattern, a third initial fill pattern PF3 may be formed to fill the interior of the second internal region and the third trench TR3. The third initial fill pattern PF3 may comprise a single film or composite film containing insulating material. As an example, the third initial fill pattern PF3 may comprise silicon oxide, silicon nitride, or a combination thereof.

[0157] Figure 12 It is along the corresponding Figure 2 of Figure 1 A sectional view taken by line A-A'. Figure 13 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0158] Reference Figure 12 and Figure 13 An initial stack is formed comprising an initial semiconductor pattern 170 of a bit line BL extending in a first direction D1 (one end of which is connected to the bit line BL and spaced apart in the first direction D1) and a word line WL extending in a third direction D3 and located on one side of the initial semiconductor pattern 170 in the first direction D1.

[0159] First, the second initial fill pattern PF2 can be removed. Therefore, a portion of the upper surface of the substrate 110, a portion of one side of the initial semiconductor pattern 170 in the second direction D2, and a portion of one side of the third initial fill pattern PF3 in the second direction D2 can be exposed. For example, the second initial fill pattern PF2 can be removed by a selective etching process.

[0160] After removing the second initial fill pattern PF2, a gate insulating layer Gox and an initial gate electrode layer PGL can be sequentially formed in the first internal region. Each gate insulating layer Gox can cover a portion of the initial semiconductor pattern 170 with a uniform thickness, and the initial gate electrode layer PGL can cover the gate insulating layer Gox with a uniform thickness. The initial gate electrode layer PGL can be formed with a uniform thickness along the upper and bottom surfaces of the initial semiconductor patterns 170 spaced apart in the first direction D1 and along one side of the third initial fill pattern PF3 in the second direction D2. In addition, the initial gate electrode layer PGL can surround the initial semiconductor patterns 170 spaced apart in the third direction D3 and can extend in the third direction D3.

[0161] For example, forming the gate insulating layer Gox and the initial gate electrode layer PGL may include: forming the gate insulating layer Gox on one side of the exposed initial semiconductor pattern 170 and the third initial fill pattern PF3 in the second direction D2 by a deposition process; forming the initial gate electrode layer PGL on the gate insulating layer Gox by a deposition process; forming a word line separation layer 150 between the initial gate electrode layers PGL by a deposition process; and patterning portions of the gate insulating layer Gox and the initial gate electrode layer PGL. In other words, the initial gate electrode layer PGL may fill a portion of the region between the initial semiconductor patterns 170 spaced apart in the first direction D1, and the word line separation layer 150 may fill the remaining region.

[0162] In some embodiments, when a portion of the initial gate electrode layer PGL is patterned, one side of the initial gate electrode layer PGL in the second direction D2 may be more recessed than the side of the word line separation layer 150 in the second direction D2, and spacers 140 may be formed in the space where the initial gate electrode layer PGL is recessed.

[0163] For example, the gate insulating layer Gox and the initial gate electrode layer PGL can be formed using PVD (physical vapor deposition), CVD (chemical vapor deposition), or ALD (atomic layer deposition) processes. For example, the etching process can be a wet etching process.

[0164] After the gate insulating layer Gox and the initial gate electrode layer PGL are formed, the buried insulating pattern can be used to fill the first internal region and the region where the second initial fill pattern PF2 has been removed by the deposition process.

[0165] After the buried insulating pattern is formed, a bit line BL may be formed to pass through the buried insulating pattern and contact one side of the initial semiconductor pattern 170 in the second direction D2. For example, forming the bit line BL may include: patterning the buried insulating pattern to form a trench; and forming a bit line BL that fills the trench.

[0166] Figure 14It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 15 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0167] Reference Figure 14 and Figure 15 The initial gate electrode layer PGL is separated to form the word line WL, a capping pattern 145 is formed to cover the other end of the word line WL in the second direction D2, and an etch stop layer 130 is formed at the other end of the capping pattern 145 in the second direction D2.

[0168] First, the third initial fill pattern PF3 can be removed. For example, the third initial fill pattern PF3 can be removed by a selective etching process.

[0169] After removing the third initial fill pattern PF3, the gate insulating layer Gox can be separated. For example, a portion of the gate insulating layer Gox that previously contacted the third initial fill pattern PF3 on one side in the second direction D2 can be removed and separated by an etching process. Thus, the gate insulating layers Gox can be spaced apart from each other in the first direction D1 and the third direction D3, and can surround the corresponding initial semiconductor pattern 170.

[0170] After removing a portion of the gate insulating layer Gox, the initial gate electrode layer PGL can be separated to form word lines WL. For example, a portion of the initial gate electrode layer PGL that previously contacted the removed gate insulating layer Gox can be removed and separated by an etching process. Therefore, the word lines WL can be spaced apart from each other in the first direction D1, and the word lines WL can extend in the third direction D3 across the initial semiconductor pattern 170 and the gate insulating layer Gox spaced apart in the third direction D3. The word lines WL can be separated from each other in the first direction D1 by a word line separation layer 150, and can surround the corresponding initial semiconductor pattern 170 and gate insulating layer Gox.

[0171] Next, a capping pattern 145 can be formed to cover the letter line WL and the letter line separation layer 150 on the other side in the second direction D2.

[0172] A capping pattern 145 can be formed to make the surfaces of the letter line WL and the letter line separation layer 150 on opposite sides in the second direction D2 flat.

[0173] An etch stop layer 130 may be formed on the other side of the cap pattern 145 in the second direction D2. The etch stop layer 130 may be formed to conformally cover the other surface of the cap pattern 145 in the second direction D2.

[0174] For example, a capping pattern 145 and an etch stop layer 130 can be formed by a deposition process.

[0175] Figure 16 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 17 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0176] Reference Figure 16 and Figure 17 A semiconductor material layer 251 is grown on the other side of the initial semiconductor pattern 170 in the second direction D2.

[0177] The other end of the initial semiconductor pattern 170 in the second direction D2 may be exposed in the space where the third initial fill pattern PF3 has been removed. For example, the other side of the initial semiconductor pattern 170 in the second direction D2 may pass through the etch stop layer 130 and be exposed. The first initial fill pattern PF1 may be located on both sides of the exposed initial semiconductor pattern 170 in the third direction D3. The exposed initial semiconductor pattern 170 on both sides of the third direction D3 may contact the first initial fill pattern PF1.

[0178] A semiconductor material layer 251 can be grown in the space surrounded by the initial semiconductor pattern 170, the etch stop layer 130 and the first initial fill pattern PF1 using the selective epitaxial growth (SEG) method with the initial semiconductor pattern 170 as a seed.

[0179] At this time, the initial semiconductor pattern 170, the etch stop layer 130, and the first initial fill pattern PF1 may comprise different materials. In other words, the initial semiconductor pattern 170, the etch stop layer 130, and the first initial fill pattern PF1 may form a heterogeneous interface. Therefore, by utilizing a selective epitaxial growth method, a semiconductor material layer 251 can be formed only on the upper and lower surfaces of the initial semiconductor pattern 170 in the first direction D1.

[0180] The growth semiconductor material layer 251 may not be grown on the surface of the etch stop layer 130 and the surface of the first initial fill pattern PF1. Therefore, only the length of the initial semiconductor pattern 170 in the first direction D1 needs to be increased.

[0181] Furthermore, since no semiconductor material layer 251 is grown on the surface of the first initial filling pattern PF1, the semiconductor material layer 251 formed on the surface of one initial semiconductor pattern 170 and the semiconductor material layer 251 formed on the surface of another initial semiconductor pattern 170 arranged adjacent to the one initial semiconductor pattern 170 in the first direction D1 can not be connected to each other along the surface of the first initial filling pattern PF1, but can be spaced apart from each other in the first direction D1. In this way, the nodes of the first electrode 310 of the data storage pattern DS can be separated.

[0182] For example, a selective epitaxial growth (SEG) method may include a process of introducing a source gas into the space exposed between the etch stop layer 130 and the first initial fill pattern PF1 on the other side of the initial semiconductor pattern 170 in the second direction D2, by removing the space where the third initial fill pattern PF3 has been removed. For example, the interior of the chamber housing the substrate 110 may be adjusted to a pressure below atmospheric pressure using a vacuum pump or similar device, and the substrate 110 may be heated to a predetermined temperature. After heating the substrate 110, a source gas is introduced into the space exposed on the other side of the initial semiconductor pattern 170 in the second direction D2. Here, the source gas may include a source gas for forming the semiconductor material layer 251, such as a silicon source gas, a germanium source gas, or a combination thereof. The source gas may be thermally decomposed to generate silicon nuclei, germanium nuclei, or silicon-germanium (SiGe) nuclei. Therefore, the silicon nuclei, germanium nuclei, or silicon-germanium nuclei may bond to dangling bonds on the surface of the initial semiconductor pattern 170, and thus be adsorbed onto the surface of the initial semiconductor pattern 170, thereby growing the semiconductor material layer 251.

[0183] Figure 18 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 19 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0184] Reference Figure 18 and Figure 19 A fourth initial filling pattern PF4 can be formed between the initial semiconductor pattern 170 on the surface of which a semiconductor material layer 251 is formed.

[0185] As described above, the semiconductor material layer 251 formed on the surface of an initial semiconductor pattern 170 and the semiconductor material layer 251 formed on the surface of another initial semiconductor pattern 170 arranged along the first direction D1 adjacent to the one initial semiconductor pattern 170 are not connected to each other, and since they are spaced apart from each other in the first direction D1, an empty space can be formed between the initial semiconductor patterns 170 on which the semiconductor material layer 251 is formed, and the fourth initial filling pattern PF4 can fill the empty space.

[0186] For example, a fourth initial fill pattern PF4 can be formed by a deposition process. The initial fill pattern PF4 may comprise a single film or a composite film containing an insulating material. For example, the fourth initial fill pattern PF4 may comprise silicon oxide, silicon nitride, or a combination thereof.

[0187] Figure 20 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 21 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'. Figure 22 This illustrates another implementation method along... Figure 1 A sectional view taken by line A-A'.

[0188] Reference Figure 20 and Figure 21 Remove a portion of the initial semiconductor pattern 170 and semiconductor material layer 251.

[0189] For example, a portion of the initial semiconductor pattern 170 and the semiconductor material layer 251 can be selectively removed using a selective etching process. The remaining initial semiconductor pattern 170 after removal by the selective etching process can form the semiconductor pattern 200. In addition, a portion of the initial semiconductor pattern 170 and the semiconductor material layer 251 can be removed, and an empty space can be formed in the space surrounded by the first initial fill pattern PF1 and the fourth initial fill pattern PF4.

[0190] For example, a selective etching process can be a timed etching process that lasts for an appropriate amount of time until the semiconductor material layer 251 is completely removed and the etch stop layer 130 is exposed. Therefore, the semiconductor pattern 200 and the etch stop layer 130 can form a coplanar surface on the other side of the second direction D2.

[0191] However, when the initial semiconductor pattern 170 and a portion of the semiconductor material layer 251 are removed, a portion of the semiconductor material layer 251 may remain on another surface of the etch stop layer 130 in the second direction D2 due to timed etching.

[0192] Therefore, as Figure 22 As shown, a semiconductor layer 250 can be formed on another surface of the etch stop layer 130 in the second direction D2. This other surface of the semiconductor layer 250 in the second direction D2 can contact the first electrode 310 of the data storage pattern DS, and the semiconductor layer 250 can directly contact the other end of the semiconductor pattern 200 in the second direction D2. In other words, the semiconductor layer 250 and the other end of the semiconductor pattern 200 in the second direction D2 can be coplanar and can contact the first electrode 310 of the data storage pattern DS. The semiconductor layer 250 connects the semiconductor pattern 200 and the first electrode 310 of the data storage pattern DS, thereby increasing the contact area between them.

[0193] Figure 23 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 24 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0194] Reference Figure 23 and Figure 24 The first electrode 310 forms the data storage pattern DS in the space where a portion of the initial semiconductor pattern 170 and semiconductor material layer 251 has been removed.

[0195] As described above, a portion of the initial semiconductor pattern 170 and the semiconductor material layer 251 is removed, and an empty space can be formed in the space surrounded by the first initial fill pattern PF1 and the fourth initial fill pattern PF4.

[0196] A first electrode 310 for data storage pattern DS can be formed in the space surrounded by the first initial fill pattern PF1 and the fourth initial fill pattern PF4. The first electrode 310 can be conformally formed in the empty space surrounded by the first initial fill pattern PF1 and the fourth initial fill pattern PF4. In other words, the first electrode 310 can be formed as a thin film of uniform thickness along the surface shape within the empty space surrounded by the first initial fill pattern PF1 and the fourth initial fill pattern PF4. Furthermore, the first electrode 310 can be conformally formed on the coplanar surface formed by the semiconductor pattern 200 and the etch stop layer 130.

[0197] For example, the first electrode 310 can be deposited via an ALD process, but is not limited thereto.

[0198] Figure 25 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 26It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0199] Reference Figure 25 and Figure 26 It can remove the first initial fill pattern PF1 and the fourth initial fill pattern PF4.

[0200] For example, the first initial fill pattern PF1 and the fourth initial fill pattern PF4 can be removed by a selective etching process. By removing the first initial fill pattern PF1 and the fourth initial fill pattern PF4, the outer surface of the first electrode 310 can be exposed.

[0201] Figure 27 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 28 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0202] Reference Figure 27 and Figure 28 A dielectric layer 320 is formed on the surface of the first electrode 310.

[0203] A dielectric layer 320 may be formed on the inner and outer surfaces of the first electrode 310. In addition, the dielectric layer 320 may be formed on another surface of the etch stop layer 130 between the first electrodes 310 in the second direction D2.

[0204] A dielectric layer 320 may be conformally formed on the first electrode 310. In other words, the dielectric layer 320 may be formed as a thin film having a uniform thickness that conforms to the surface shape of the first electrode 310.

[0205] For example, a dielectric layer 320 can be deposited using an ALD process, but it is not limited to this.

[0206] Figure 29 It corresponds to Figure 2 along Figure 1 A sectional view taken by line A-A'. Figure 30 It corresponds to Figure 3 along Figure 1 The sectional view taken by line B-B'.

[0207] Reference Figure 29 and Figure 30 A second electrode 330 is formed on the dielectric layer 320.

[0208] A second electrode 330 may be formed to fill the internal and external spaces between the dielectric layer 320 of the first electrode 310 and the first electrode 310. Additionally, a second electrode 330 may be formed to fill the spaces where the third initial filler pattern PF3 has been removed.

[0209] For example, the second electrode 330 can be formed by PVD or CVD processes, but is not limited thereto.

[0210] Figures 31 to 38 This is a cross-sectional view showing a method for manufacturing a semiconductor device in process order, illustrating another embodiment.

[0211] Figures 31 to 38 The manufacturing process is shown. Figure 4 and Figure 5 Methods for developing semiconductor devices.

[0212] Figure 31 It corresponds to Figure 23 along Figure 1 A sectional view taken by line A-A'. Figure 32 It corresponds to Figure 24 along Figure 1 The sectional view taken by line B-B'. Figure 33 It corresponds to Figure 25 along Figure 1 A sectional view taken by line A-A'. Figure 34 It corresponds to Figure 26 along Figure 1 The sectional view taken by line B-B'. Figure 35 It corresponds to Figure 27 along Figure 1 A sectional view taken by line A-A'. Figure 36 It corresponds to Figure 28 along Figure 1 The sectional view taken by line B-B'. Figure 37 It corresponds to Figure 29 along Figure 1 A sectional view taken by line A-A'. Figure 38 It corresponds to Figure 30 along Figure 1 The sectional view taken by line B-B'.

[0213] Figures 31 to 38 The implementation methods shown are the same as Figures 23 to 30 The embodiments shown are essentially the same, therefore explanations of these parts will be omitted, and the differences will be explained primarily. Additionally, the same reference numerals are used for the same components as in the previous embodiments.

[0214] Reference Figures 31 to 38When the first electrode 310 of the data storage pattern DS is formed in the space where a portion of the initial semiconductor pattern 170 and the semiconductor material layer 251 has been removed, the first electrode 310 can be formed to fill the empty space surrounded by the first initial filling pattern PF1 and the fourth initial filling pattern PF4. In other words, the first electrode 310 is not conventionally formed in the empty space, and therefore, the inner space of the first electrode 310 is not formed.

[0215] The first initial fill pattern PF1 and the fourth initial fill pattern PF4 are removed, and a dielectric layer 320 is formed on the surface of the first electrode 310. The dielectric layer 320 may be formed conformally on the first electrode 310. However, the dielectric layer 320 is formed on the outer surface of the first electrode 310, but not on the inner surface of the first electrode 310.

[0216] A second electrode 330 is formed on the dielectric layer 320. The second electrode 330 may be formed to fill the outer space between the first electrode 310 and the dielectric layer 320 therebetween. Additionally, the second electrode 330 may be formed to fill the space where the third initial fill pattern PF3 has been removed. However, the second electrode 330 for filling the inner space between the first electrode 310 and the dielectric layer 320 therebetween is not formed.

[0217] While this specification contains numerous specific implementation details, these details should not be considered as limiting the scope of any invention or claim, but rather as descriptions of features characteristic of particular embodiments of a particular invention. Specific features described in the context of different embodiments in this specification can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, although features may have been described above as functioning in a particular combination, in some cases one or more features in the combination can be removed from the combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

[0218] The above detailed description of the embodiments of this disclosure is not intended to limit the scope of this disclosure. On the contrary, various modifications and improvements made by those skilled in the art using the basic concepts of this disclosure as defined in the appended claims also fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: Bit lines extending in the first direction; A plurality of semiconductor patterns spaced apart from each other in a first direction, the plurality of semiconductor patterns including a first semiconductor pattern, the first semiconductor pattern including a first end and a second end along a dimension of the first semiconductor pattern in a second direction different from the first direction, wherein the first end is connected to the bit line; A word line structure extending upward in a third direction different from the first direction and the second direction, wherein the word line structure is on a first side of the first semiconductor pattern, the first side facing the first direction, wherein the first semiconductor pattern includes a first material; Data storage pattern, which includes: A first electrode is connected to a second end of the first semiconductor pattern. The second electrode is spaced apart from the first electrode, and A dielectric layer is disposed between the first electrode and the second electrode; and An etch stop layer is provided between the word line structure and the first electrode of the data storage pattern, wherein the etch stop layer contacts the first semiconductor pattern and comprises a second material different from the first material. Wherein, the length of the first electrode of the data storage pattern in the first direction is greater than the length of the first semiconductor pattern in the first direction.

2. The semiconductor device according to claim 1, wherein, The length of the first electrode of the data storage pattern in the first direction is greater than 1.1 times the length of the first semiconductor pattern in the first direction and less than or equal to 5 times the length of the first semiconductor pattern in the first direction.

3. The semiconductor device according to claim 1, wherein, The length of the first electrode of the data storage pattern in the first direction is 0.5 to 5.0 times the length of the first electrode of the data storage pattern in the third direction.

4. The semiconductor device according to claim 1, wherein, A first side of the first electrode of the data storage pattern is in contact with a heterogeneous interface, wherein the first side faces the second direction, and wherein the heterogeneous interface includes at least a portion of the first semiconductor pattern and at least a portion of the etch stop layer.

5. The semiconductor device according to claim 1, wherein, The first semiconductor pattern extends through the etch stop layer and connects to the first electrode of the data storage pattern.

6. The semiconductor device according to claim 1, wherein, The word line structure includes: The first word line located above the first semiconductor pattern in the first direction, and The second letter line located below the first semiconductor pattern in the first direction.

7. The semiconductor device according to claim 1, further comprising: A gate insulating layer between the first semiconductor pattern and the word line structure.

8. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: The first plurality of word line structures, comprising the word line structures, are located on a first side of the plurality of semiconductor patterns. The second plurality of word line structures are located on the second side of the plurality of semiconductor patterns, wherein the first side of the plurality of semiconductor patterns faces the first direction and the second side of the plurality of semiconductor patterns faces the opposite direction to the first direction. A word line separation layer is provided between each word line structure in the first plurality of word line structures and the corresponding word line structure in the second plurality of word line structures.

9. The semiconductor device according to claim 8, further comprising: The cover pattern is located on a first side of the first semiconductor pattern in the first direction and between the first letter line and the etch stop layer in the second direction.

10. The semiconductor device according to claim 9, wherein, The sealing pattern includes: The first capping portion, located in the second direction between the letter line structure and the etch stop layer, and The second cover portion is located between the word line separation layer and the etch stop layer in the second direction.

11. The semiconductor device according to claim 1, further comprising: A spacer, which is located in the second direction between the word line structure and the bit line.

12. The semiconductor device according to claim 1, wherein, The first electrode of the data storage pattern includes: A first sidewall is located on a first side of the data storage pattern, the first side facing the second direction; A second sidewall facing the first direction and a third sidewall facing the opposite direction to the second sidewall, the third sidewall being spaced apart from the second sidewall in the first direction, and both the second and third sidewalls contacting the first sidewall; and A fourth sidewall facing the third direction and a fifth sidewall facing the opposite direction of the fourth sidewall, the fifth sidewall being spaced apart from the fourth sidewall in the third direction, the fourth sidewall and the fifth sidewall being in contact with the first sidewall, the second sidewall and the third sidewall.

13. The semiconductor device according to claim 1, wherein, The first electrode of the data storage pattern includes: a first surface facing the second direction and a sixth surface spaced apart from the first surface in the second direction and facing the first surface in the opposite direction. A second surface facing the first direction and a third surface spaced apart from the second surface in the first direction and facing the second surface in the opposite direction, the second surface and the third surface contacting the first surface and the sixth surface; and Facing the third-direction fourth surface and the fifth surface which is spaced apart from the fourth surface in the third-direction direction and faces the fourth surface in the opposite direction, the fourth surface and the fifth surface are in contact with the first surface, the second surface, the third surface and the sixth surface.

14. A semiconductor device, comprising: Bit lines extending in the first direction; A plurality of semiconductor patterns spaced apart from each other in the first direction, the plurality of semiconductor patterns including a first semiconductor pattern, the first semiconductor pattern including a first end and a second end along a dimension of the first semiconductor pattern in a second direction different from the first direction, wherein the first end is connected to the bit line; A word line extending upward in a third direction different from the first direction and the second direction, wherein the word line is on a first side of the first semiconductor pattern, the first side facing the first direction, wherein the first semiconductor pattern comprises a first material; Data storage pattern, which includes: A first electrode is connected to a second end of the first semiconductor pattern. The second electrode is spaced apart from the first electrode, and A dielectric layer, which is located between the first electrode and the second electrode, and A semiconductor layer is located between the word line and the first electrode of the data storage pattern, wherein the semiconductor layer is in contact with the first semiconductor pattern, and wherein the semiconductor layer comprises the first material.

15. The semiconductor device according to claim 14, wherein, The length of the first electrode of the data storage pattern in the first direction is greater than the length of the first semiconductor pattern in the first direction.

16. The semiconductor device according to claim 14, wherein, The semiconductor layer includes: The upper semiconductor layer portion is located above the first semiconductor pattern in the first direction; and The lower semiconductor layer portion is located below the first semiconductor pattern in the first direction.

17. The semiconductor device of claim 14, further comprising: An etch stop layer is located in the second direction between the word line and the first electrode of the data storage pattern, wherein the etch stop layer is in contact with the first semiconductor pattern, and wherein the etch stop layer comprises a second material different from the first material. The semiconductor layer is located in the second direction between the etch stop layer and the first electrode of the data storage pattern.

18. A semiconductor device, comprising: Bit lines extending in the first direction; A plurality of semiconductor patterns spaced apart from each other in the first direction, the plurality of semiconductor patterns including a first semiconductor pattern, the first semiconductor pattern including a first end and a second end along a dimension of the first semiconductor pattern in a second direction different from the first direction, wherein the first end is connected to the bit line; A word line structure extending upward on a third direction different from the first direction and the second direction, wherein the word line structure is on a first side of the first semiconductor pattern, the first side facing the first direction, wherein the first semiconductor pattern includes a first material; and Data storage pattern, which includes: A first electrode is connected to a second end of the first semiconductor pattern. The second electrode is spaced apart from the first electrode, and A dielectric layer is located between the first electrode and the second electrode. Wherein, the length of the first electrode of the data storage pattern in the first direction is greater than the length of the first semiconductor pattern in the first direction, and The first electrode includes a first surface facing a first direction and a second surface facing the opposite direction to the first surface, wherein the first surface and the second surface of the first electrode do not overlap with the word line structure in the second direction.

19. The semiconductor device according to claim 18, wherein, The first and second surfaces of the first electrode of the data storage pattern do not overlap with the first semiconductor pattern in the second direction.

20. The semiconductor device according to claim 18, wherein, The semiconductor device further includes: The first plurality of word line structures, comprising the word line structures, are located on a first side of the plurality of semiconductor patterns. The second plurality of word line structures are located on the second side of the plurality of semiconductor patterns, wherein the first side of the plurality of semiconductor patterns faces the first direction and the second side of the plurality of semiconductor patterns faces the opposite direction to the first direction. A word line separation layer, which is located between each word line structure in the first plurality of word line structures and the corresponding word line structure in the second plurality of word line structures. Wherein, the first and second surfaces of the first electrode of the data storage pattern overlap with the word line separation layer in the second direction.

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