An insulated gate bipolar transistor device and method of fabrication thereof

By introducing a stepped gate oxide structure and a central P+ injection protection zone in the JFET region into the SiC IGBT device, the latch-up problem during short circuit is solved, the short-circuit withstand capability and switching speed of the device are improved, and the losses are reduced.

CN122438348APending Publication Date: 2026-07-21INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
Filing Date
2025-01-21
Publication Date
2026-07-21

AI Technical Summary

Technical Problem

Traditional planar gate SiC IGBT devices are prone to latch-up during short circuits, leading to device burnout. This is mainly due to a large amount of hole current flowing through the hole path below the N+ source region and the high short-circuit saturation current.

Method used

The device employs a stepped gate oxide structure and a central P+ injection protection zone in the JFET region. By guiding hole current through the P-base region, the Miller capacitance of the device is reduced, and the short-circuit withstand capability is improved. Furthermore, the gate oxide is protected by the P-type well region and the heavily doped protection zone, providing a bypass for hole current.

Benefits of technology

It significantly reduces the latch-up current of the device, improves the short-circuit sustaining time, increases the switching speed of the device, reduces losses, and maintains the breakdown voltage and gate oxide electric field strength of the device.

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Abstract

The application relates to an insulated gate bipolar transistor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The application solves the problem that, in a traditional device, a large number of hole currents flow through a hole path below a source region when a short circuit occurs, and then a latch-up occurs to cause the device to burn. The device comprises, from bottom to top, a collector region, a buffer region, a drift region, a central buried base region prepared in the center of a cell of the drift region, a current expansion layer, a P-type well region and a JFET region located above the current expansion layer, an emitter contact region and two source regions located in the center of the P-type well region, a protection region located between the two P-type well regions and in the center of the JFET region, a stepped gate oxide with a slope connected between the top and the bottom of the stepped gate oxide, the top and the slope being located above a heavily doped protection region, and the bottom extending towards a heavily doped emitter contact region to expose the top surfaces of the heavily doped emitter contact region and part of the heavily doped source region, a polysilicon layer and an interlayer dielectric. The hole current is bypassed and guided to improve the short-circuit resistance of the device.
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