A high-k dual-gate indium tin zinc oxide thin film transistor and a preparation method thereof

Abstract

The application discloses a high-K dual-gate indium tin zinc oxide thin film transistor and a preparation method thereof. The application proposes a method of metal thermal oxidation, evaporates nanoscale metal Y or Al on the surface of the ITZO thin film transistor, and then performs thermal oxidation to form a thermal oxidation protective layer. The thermal oxidation protective layer with a thickness of only 2-10 nm can effectively prevent water from damaging the ITZO film in the atomic layer deposition process, and thus the preparation of the dual-gate structure ITZO thin film transistor is realized. Meanwhile, the thermal oxidation protective layer is a material with a high K value and can be used to constitute a top-gate dielectric layer. Due to the high unit area capacitance density of the bottom-gate dielectric layer and the top-gate dielectric layer, the gate control capability of the ITZO thin film transistor controlled by the dual-gate is enhanced, and the subthreshold swing is as low as 63 mV dec ‑1 , which is close to the theoretical limit value.

Description

Technical Field

[0001] This invention belongs to the field of thin-film transistor fabrication technology, specifically relating to a method for fabricating high-K dual-gate indium tin zinc oxide thin-film transistors using a combination of metal thermal oxidation and atomic layer deposition techniques. Background Technology

[0002] Zinc oxide-based metal oxide thin-film transistors (TFTs) possess advantages such as high mobility, low off-current, ease of large-area fabrication, and good mechanical flexibility, and have been studied and applied in various fields including sensors, displays, storage, and proximity computing. Among them, indium tin zinc oxide (ITZO) thin-film transistors (TFTs) can achieve a mobility of 10-100 cm⁻¹. 2 V -1 s -1 ITZO TFTs exhibit excellent bias and thermal bias stability. The development and application of ITZO TFTs are expected to further improve the performance of zinc oxide metal oxide thin-film transistors and expand their application scenarios. Currently, the fabrication technology of bottom-gate ITZO TFTs is relatively mature; however, the fabrication of top-gate and dual-gate ITZO TFTs still has shortcomings, which are detrimental to the interconnect design and fabrication of complex three-dimensional structures in large-area applications. In current research, plasma-enhanced chemical vapor deposition (PECVD) or pulsed laser deposition (PLD) techniques are commonly used to fabricate top-gate or dual-gate ITZO TFTs. However, the key performance indicators of gate oxide films deposited by PECVD and PLD, such as step coverage, film uniformity, and dielectric constant, are inferior to those of films prepared by atomic layer deposition (ALD). Therefore, it is necessary to deposit gate oxides with a thickness exceeding 100 nm to reduce gate leakage, which undoubtedly greatly weakens the gate control capability of the device. High-k gate oxide films prepared by ALD have good step coverage, high density, and good dielectric properties, making them an ideal technical route for improving the performance of the gate dielectric layer of ITZO TFTs. However, the ALD fabrication process can damage the ITZO film, leading to a decrease in device performance.

[0003] Patent CN117276350B discloses a method for fabricating a dual-gate ITZO TFT, which uses an organic self-assembled layer as a sputtering barrier layer and prepares zirconium oxide as the gate dielectric layer via magnetron sputtering. Due to insufficient film density produced by magnetron sputtering, the thickness of the top gate dielectric layer is 250–650 nm to reduce gate leakage. However, this excessively thick gate dielectric layer results in insufficient gate control capability, leading to a subthreshold swing of 150 mV dec for the ITZO TFT. -1 Unable to approach 60 mV dec -1 The theoretical limit. Summary of the Invention

[0004] This invention discloses a method for fabricating dual-gate ITZO TFTs using a combination of metal thermal oxidation (MTO) and atomic layer deposition (ALD). This technique solves the problem of threshold voltage drift or difficulty in turn-off caused by damage to ITZO TFTs during the ALD fabrication process. High-k dual-gate ITZO TFTs exhibit excellent gate control capabilities, with subthreshold swing approaching the theoretical limit. ALD deposition typically employs two methods: one is precursor-water reaction deposition of oxide films, and the other is precursor-oxygen plasma reaction deposition of oxide films. In the precursor-water reaction method, the -OH groups in the water can cause threshold voltage drift or even prevent turn-off of the ITZO TFT. In the precursor-oxygen plasma reaction method, the high-power oxygen plasma can damage the ITZO film, causing the device to fail to turn off. Therefore, this invention passivates the ITZO TFT using MTO and forms a dense nanoscale oxide protective layer on its surface, solving the problem of device performance degradation during the top gate dielectric layer fabrication of ITZO TFTs using ALD technology.

[0005] This invention is achieved through the following technical solution:

[0006] This invention provides a dual-gate indium tin zinc oxide thin-film transistor (ITZO TFT). The top gate dielectric layer of the ITZO TFT is a stacked structure of thermally oxidized oxide and atomically deposited oxide. The thermally oxidized metal oxide forms the first top gate dielectric layer, and the atomically deposited oxide forms the second top gate dielectric layer. The thermally oxidized metal oxide completely covers the transistor, and the atomically deposited oxide covers the thermally oxidized oxide on top of it. Specifically, a dense metal layer (one of aluminum and yttrium) is deposited on the surface of the bottom gate ITZO TFT and thermally oxidized to form a dense oxide protective layer. Then, the top gate dielectric layer of the ITZO TFT is fabricated using ALD technology, and finally, the top gate electrode is deposited to form the dual-gate ITZO TFT.

[0007] The fabrication steps of the dual-gate ITZO TFT described in this invention are as follows: (1) Electrode material is prepared on a substrate and patterned using a metal mask to form a bottom gate electrode layer; (2) An oxide thin film material is deposited on top of the bottom gate electrode layer using ALD to form a bottom gate dielectric layer; (3) An ITZO thin film was prepared on the bottom gate dielectric layer by radio frequency magnetron sputtering, and patterned using a metal mask to form an active layer; the active layer was annealed at 300-350℃ for 2-3 h in an air environment. (4) A magnetron sputtering deposition source and drain electrode are deposited on top of the ITZO thin film, and a metal mask is used for patterning to form a bottom gate structure ITZO TFT; (5) A metal layer is deposited on top of the bottom gate structure ITZO TFT thin film, and thermally oxidized in an air environment at 250-350℃ for 0.5-1.5 h to form a thermal oxidation protective layer, which serves as the first top gate dielectric layer; (6) An oxide thin film material is deposited using ALD above the thermal oxidation protective layer as the second top gate dielectric layer; (7) Aluminum is prepared above the second top gate dielectric layer as the top gate electrode, and patterned using a metal mask to obtain a dual-gate indium tin zinc oxide thin film transistor (i.e., dual-gate ITZO TFT).

[0008] Preferably, the substrate in step (1) is one of glass, silicon wafer, or polyimide film. The thickness of the glass or silicon wafer is 0.5-1 cm, and the thickness of the polyimide film is 3-1000 μm.

[0009] Preferably, the electrode material in steps (1) and (7) is one of aluminum, titanium, gold, platinum, molybdenum, tungsten, indium tin oxide, and nickel.

[0010] Preferably, the bottom / top gate electrode in steps (1) and (7) is prepared by one of radio frequency magnetron sputtering, thermal evaporation coating, or electron beam evaporation coating, and the thickness of the bottom gate electrode layer is 30-100 nm.

[0011] Preferably, the oxide film material in steps (2) and (6) is one of aluminum oxide, hafnium oxide, zirconium oxide, and tantalum oxide.

[0012] Preferably, the thickness of the bottom / top gate dielectric layer in steps (2) and (6) is 20-100 nm.

[0013] Preferably, in step (3), an ITZO thin film is prepared by radio frequency magnetron sputtering, and the thickness of the ITZO thin film is 20-60 nm; the annealing temperature in step (3) is 300-350 °C and the annealing time is 2-3 h.

[0014] Preferably, the source and drain electrodes in step (4) are one or more of indium tin oxide, molybdenum, aluminum and nickel stacked together, with a thickness of 50-200 nm.

[0015] Preferably, the metal layer in step (5) is one of aluminum or yttrium, and the preparation method is one of thermal evaporation coating or electron beam evaporation coating, with a thickness of 2-10 nm.

[0016] Preferably, the metal layer in step (5) is formed into a thermal oxidation protective layer by thermal oxidation, the thermal oxidation atmosphere is one or more combinations of air, oxygen and ozone, the thermal oxidation temperature is 250-350℃, and the thermal oxidation time is 0.5-1.5 h.

[0017] This invention proposes a method for fabricating high-k dual-gate ITZO TFTs using a combination of metal thermal oxidation and ALD technology. This invention has the following advantages: 1. This invention uses a metal thermal oxidation method to passivate the channel of an ITZO TFT. Nanoscale Y or Al metals are deposited on the surface of the ITZO thin-film transistor by vapor deposition, followed by thermal oxidation to form an ultrathin and dense oxide protective layer. This thermally oxidized protective layer, only 2-10 nm in size, effectively prevents water damage to the ITZO thin film during the ALD process, ensuring that the performance of the ITZO TFT is not affected during the ALD deposition of the top gate dielectric layer, thereby realizing the fabrication of a dual-gate ITZO thin-film transistor.

[0018] 2. This invention proposes an ultra-thin and dense thermal oxidation protective layer made of a material with a high K value, which can be used as the first top gate dielectric layer of an ITZO TFT and has good interfacial contact with the second top gate dielectric layer deposited by ALD, ensuring that the entire top gate dielectric layer has a high capacitance density per unit area. Figure 3 Figure b shows the capacitance density; the dielectric layer of Y₂O₃ and Al₂O₃, totaling 25 nm, has a capacitance density of 353 nF / cm⁻¹. 2 (The calculated K value is 9.98), thus realizing an ITZO TFT with excellent dual-gate control capability.

[0019] 3. The subthreshold swing of the dual-gate ITZO TFT proposed in this invention ( SS ) is 63 mV dec -1 It is close to the theoretical limit.

[0020] In summary, the method for fabricating dual-gate ITZO TFTs using a combination of metal thermal oxidation and atomic layer deposition proposed in this invention solves the problem of the difficulty in fabricating dual-gate ITZO TFTs with high capacitance density per unit area. This technology improves the gate control capability of ITZO TFTs, enabling the device to achieve higher gate density. SS Approaching the theoretical limit. The present invention fabricates a dual-gate controlled n-type thin-film transistor, achieving enhanced performance of a single n-type transistor by fabricating a gate dielectric layer (insulating layer) and a gate electrode at the bottom and top of the transistor. Attached Figure Description

[0021] The invention will now be further described with reference to the accompanying drawings.

[0022] To make the contents of this invention clearer, they will be shown in the accompanying drawings. The dimensions shown are not strictly scaled to the actual dimensions of the devices.

[0023] Figure 1 This is a schematic diagram of the structure of a dual-gate ITZO TFT prepared according to an embodiment of the present invention.

[0024] Explanation of reference numerals in the attached figures: 100 is the substrate; 200 is the bottom gate electrode layer; 300 is the bottom gate dielectric layer; 400 is the active layer of the ITZO thin film transistor; 501 is the source electrode of the ITZO thin film transistor; 502 is the drain electrode of the ITZO thin film transistor; 600 is the thermal oxidation protection layer, which also serves as the first top gate dielectric layer; 700 is the second top gate dielectric layer; 800 is the top gate electrode layer.

[0025] Figure 2 The curves shown are (a) bottom gate transfer characteristics and (b) capacitance of the bottom gate dielectric layer of the ITZO TFT in Example 1.

[0026] Figure 3 The curves shown are (a) top gate transfer characteristics and (b) capacitance of the top gate dielectric layer of the ITZO TFT in Example 1.

[0027] Figure 4 The curves show the dual-gate transfer characteristics of the ITZO TFT in Example 1.

[0028] Figure 5 The image shows the dual-gate output characteristic curve of the ITZO TFT in Example 1.

[0029] Figure 6 This represents the subthreshold swing of the dual-gate test of the ITZO TFT in Example 1.

[0030] Figure 7 The curves show the dual-gate transfer characteristics of the ITZO TFT in Example 2.

[0031] Figure 8 The image shows the transfer characteristic curves of the ITZO TFT in Comparative Example 1.

[0032] Figure 9 The image shows the transfer characteristic curves of the ITZO TFT in Comparative Example 2.

[0033] Figure 10 The figure shows the transfer characteristic curves of the ITZO TFT in Comparative Example 3. Detailed Implementation

[0034] The technical solution of the present invention will be further described in detail below with reference to specific embodiments. It should be understood that the following embodiments are merely illustrative and explanatory of the present invention, and should not be construed as limiting the scope of protection of the present invention. All technologies implemented based on the above content of the present invention are covered within the scope of protection intended by the present invention. Unless otherwise stated, the raw materials and reagents used in the following embodiments are commercially available products, or can be prepared by known methods.

[0035] Example 1 A dual-gate ITZOTFT (device structure as follows) Figure 1As shown, its structure consists of a substrate 100, a bottom gate electrode layer 200, a bottom gate dielectric layer 300, and an active layer 400 stacked sequentially from bottom to top. The source electrode 501 and the drain electrode 502 are on the same layer and are disposed above the active layer 400. A channel exists between the source electrode 501 and the drain electrode 502. A thermal oxidation protection layer (first top gate dielectric layer) 600, a second top gate dielectric layer 700, and a top gate electrode layer 800 are stacked sequentially above the active layer 400. Substrate 100 is a glass substrate; gate electrode layer 200 is composed of aluminum with a thickness of 50 nm; gate dielectric layer 300 is composed of Al2O3 with a thickness of 40 nm; active layer 400 is composed of ITZO with a thickness of 30 nm; active layer 400 is a patterned ITZO thin film; source electrode 501 and drain electrode 502 are both composed of metallic Mo with a thickness of 150 nm; the length and width of the channel between source electrode 501 and drain electrode 502 are both 300 μm; thermal oxidation protective layer (first top gate dielectric layer) 600 is composed of Y2O3; top gate dielectric layer 700 is composed of Al2O3 with a thickness of 20 nm; top gate electrode layer 800 is composed of Al with a thickness of 80 nm.

[0036] The fabrication steps of the above dual-gate ITZOTFT are as follows: (1) Select a glass substrate with dimensions of 1 cm × 1 cm × 0.5 cm as the substrate. Clean the substrate with water and isopropanol for 20 min each, and dry it in a drying oven at 90℃ for 20 min. (2) Using thermal evaporation deposition method, a 50 nm thick Al layer is deposited on the substrate as the bottom gate electrode layer by patterning with a metal mask; (3) A 40 nm thick Al2O3 layer was deposited over the entire surface of the gate electrode using ALD as the bottom gate dielectric layer; (4) Using radio frequency magnetron sputtering technology, a 30 nm thick ITZO thin film is prepared above the bottom gate dielectric layer by patterning with a metal mask, which serves as the active layer of the ITZOTFT. (5) Anneal the entire device in air at 350°C for 3 h; (6) Using magnetron sputtering technology, a 150 nm thick layer of metal Mo is prepared above the active layer of the ITZO TFT by patterning a metal mask, which serves as the source and drain electrodes of the ITZO TFT, resulting in a bottom gate structure ITZO TFT with an aspect ratio of 300 μm / 300 μm. (7) Using thermal evaporation deposition method, deposit 2 nm of metal Y on the obtained bottom gate ITZO TFT, and then thermally oxidize it in air atmosphere at 250°C for 0.5 h to form thermal oxidation protective layer Y2O3, which serves as the first top gate dielectric layer; (8) A 20 nm thick Al2O3 layer is deposited on top of the first top gate dielectric layer Y2O3 using ALD as the second top gate dielectric layer; (9) A thermal evaporation deposition method is used above the second top gate dielectric layer. A metal mask is used to pattern the deposition of an 80 nm thick Al layer as the top gate electrode layer to obtain a dual-gate ITZO TFT.

[0037] The bottom gate (BG) transfer characteristic curves and bottom gate dielectric layer capacitance of the above dual-gate ITZO TFT are shown in the figures below. Figure 2 a and Figure 2 As shown in b, the top gate (TG) transfer characteristic curve and the top gate dielectric layer capacitance are respectively as follows: Figure 3 a and Figure 3 As shown in b, the relative permittivity of the bottom gate (BG) dielectric layer is 8.8, while that of the top gate (TG) dielectric layer is 9.98. The TG dielectric layer is thinner, resulting in a higher capacitance density per unit area and stronger gate control capability for ITZO TFTs compared to BG. From... Figure 3 It can be concluded that the oxide film of the gate dielectric layer has the characteristics of being "ultra-thin and dense," with a high capacitance density and better performance. The dual-gate (DG) transfer characteristic curves of the above dual-gate ITZOTFT are shown below. Figure 4 As shown, the dual-gate (DG) output characteristic curve is as follows: Figure 5 As shown. The threshold voltage of this device ( V th The current switching ratio is -0.38 V, and the current switching ratio is ( I on / I off ) is 3.5 × 10 7 Dual-gate ITZO TFT SS like Figure 6 As shown, thanks to the excellent electrostatic control capability of the dual-gate system, its minimum subthreshold swing is... SS min = 63 mV dec -1 Approaching the theoretical limit of 60mV dec -1 .

[0038] Example 2 Similar to the preparation method in Example 1, the metal Y in step (7) was replaced with metal Al with a thickness of 3 nm, and thermally oxidized in air at 300°C for 1 hour to form a thermally oxidized protective layer Al2O3. Then, steps (8) and (9) were completed to obtain a dual-gate ITZOTFT (device structure as shown in the figure). Figure 1 (As shown). The dual-gate transfer characteristic curve of the dual-gate ITZO TFT prepared in this embodiment is shown in the figure. Figure 7 As shown, the ITZO thin-film transistor... V thIt is -0.58 V. SS 63 mV dec -1 , I on / I off 3.6×10 7 ITZO TFTs maintain good electrical performance.

[0039] Comparative Example 1 The preparation method is the same as in Example 1, except that the thermal oxidation protective layer of metallic Y in step (7) is omitted. Its transfer characteristic curve is shown below. Figure 8 As shown, during the Al2O3 preparation process by ALD, the ITZO thin film is directly exposed to water, causing the ITZO TFT to lose its switching characteristics.

[0040] Comparative Example 2 The preparation method is the same as in Example 1, except that the thickness of metal Y in step (7) is changed to 1 nm. Its transfer characteristic curve is shown below. Figure 9 As shown, during the Al2O3 preparation process by ALD, the protective layer thickness after thermal oxidation of 1 nm metallic Y is insufficient to protect the ITZO film, resulting in the difficulty of turning off the ITZO TFT.

[0041] Comparative Example 3 Referring to steps (1)–(7) of the preparation method in Example 1, the thickness of metal Y in step (7) is changed to 15 nm. Its transfer characteristic curve is shown below. Figure 10 As shown, since 15 nm metallic Y cannot be completely thermally oxidized, metallic Y directly connects the source and drain electrodes to form a conductive channel, making it difficult for the ITZO TFT to be turned off.

[0042] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for fabricating a dual-gate indium tin zinc oxide thin-film transistor, characterized in that, The gate dielectric layer of the dual-gate indium tin zinc oxide thin-film transistor is prepared by a combination of metal thermal oxidation and atomic layer deposition techniques. The top gate dielectric layer of the dual-gate indium tin zinc oxide thin film transistor is a stacked structure of thermally oxidized metal oxide and atomic layer deposition oxide. The thermally oxidized metal oxide completely covers the transistor, and the atomic layer deposition oxide covers the thermally oxidized oxide. The metal is one of aluminum and yttrium.

2. The method for fabricating a dual-gate indium tin zinc oxide thin-film transistor according to claim 1, characterized in that, Specifically, the following steps are included: (1) Deposit electrode material on the substrate to form a bottom gate electrode layer; (2) An oxide thin film material is deposited above the bottom gate electrode layer using atomic layer deposition technology to form a bottom gate dielectric layer; (3) Deposit an ITZO thin film over the bottom gate dielectric layer, pattern it using a metal mask to form the active layer of the ITZO thin film transistor; anneal in an air environment; (4) Deposit source and drain electrodes on top of the ITZO thin film, and pattern them using a metal mask to form a bottom gate structure ITZO thin film transistor; (5) A metal layer is deposited above the bottom gate structure ITZO thin film transistor, and thermally oxidized in an air environment to form a thermal oxidation protective layer, which serves as the first top gate dielectric layer; (6) An oxide thin film material is deposited above the first top gate dielectric layer using atomic layer deposition technology to form a second top gate dielectric layer; (7) Deposit electrode material over the second top gate dielectric layer to form the top gate electrode; This yields a dual-gate indium tin zinc oxide thin-film transistor.

3. The method for fabricating a dual-gate indium tin zinc oxide thin-film transistor according to claim 2, characterized in that, The substrate in step (1) is one of glass, silicon wafer, or polyimide film; The electrode material in step (1) is one of aluminum, titanium, gold, platinum, molybdenum, tungsten, indium tin oxide, and nickel. It is prepared by one of the following methods: radio frequency magnetron sputtering, thermal evaporation coating, and electron beam evaporation coating. The thickness of the bottom gate electrode layer is 30-100 nm.

4. The method for fabricating a dual-gate indium tin zinc oxide thin-film transistor according to claim 2, characterized in that, The oxide thin film material in step (2) is one of aluminum oxide, hafnium oxide, zirconium oxide, and tantalum oxide, and the thickness of the bottom gate dielectric layer is 20-200 nm.

5. The method for fabricating a dual-gate indium tin zinc oxide thin-film transistor according to claim 2, characterized in that, Step (3) uses radio frequency magnetron sputtering to prepare ITZO thin films with a thickness of 20-60 nm; the annealing temperature in step (3) is 300-350℃ and the annealing time is 2-3 h.

6. The method for fabricating a dual-gate indium tin zinc oxide thin-film transistor according to claim 2, characterized in that, In step (4), the source and drain electrodes of the ITZO thin film transistor are prepared by magnetron sputtering. The source and drain electrodes are made of one or more of the following materials: indium tin oxide, molybdenum, and titanium nitride, with a thickness of 50-200 nm.

7. The method for fabricating a dual-gate indium tin zinc oxide thin-film transistor according to claim 2, characterized in that, The deposition method of the metal layer in step (5) is one of thermal evaporation, electron beam evaporation, or magnetron sputtering. The material of the metal layer is one of aluminum or yttrium, and the thickness is 2-10 nm. In step (5), the metal layer is formed into a thermal oxidation protective layer by thermal oxidation. The thermal oxidation atmosphere is one of air, oxygen, or ozone. The thermal oxidation temperature is 250-350℃ and the thermal oxidation time is 0.5-1.5 h.

8. The method for fabricating a dual-gate indium tin zinc oxide thin-film transistor according to claim 2, characterized in that, The oxide thin film material in step (6) is one of aluminum oxide, hafnium oxide, zirconium oxide, and tantalum oxide, and the thickness of the top gate dielectric layer is 20-200 nm.

9. The method for fabricating a dual-gate indium tin zinc oxide thin-film transistor according to claim 2, characterized in that, The electrode material in step (7) is aluminum metal, which is prepared by one of the following methods: radio frequency magnetron sputtering, thermal evaporation coating, or electron beam evaporation coating. The thickness of the top gate electrode is 30-100 nm.

10. A dual-gate indium tin zinc oxide thin-film transistor prepared by the preparation method according to any one of claims 1-9.

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