A ferroelectric regulated two-dimensional heterojunction transistor and a preparation method thereof

Abstract

The application belongs to the technical field of two-dimensional heterojunction devices, and relates to a ferroelectric regulated two-dimensional heterojunction transistor and a preparation method thereof. The two-dimensional heterojunction transistor comprises a bottom gate electrode, a ferroelectric layer, a palladium diselenide nanosheet, a black phosphorus nanosheet, a source electrode and a drain electrode. The thickness of the palladium diselenide nanosheet is 40-70 nm, and the thickness of the black phosphorus nanosheet is 15-30 nm. In the preparation, the bottom gate electrode is first subjected to surface cleaning, then the ferroelectric layer is prepared on the bottom gate electrode, and then the PPC-assisted dry transfer of the palladium diselenide nanosheet and the black phosphorus nanosheet is adopted, the source electrode and the drain electrode are deposited, and finally the product is obtained by covering a top insulating layer. The product can obtain a significant negative differential transconductance effect and a higher peak-to-valley current ratio under a low gate electrode voltage and a source-drain bias, has low power consumption, high gain and excellent logic regulation capacity. The PPC-assisted dry transfer process effectively reduces the interface organic residue and Fermi level pinning effect.

Description

Technical Field

[0001] This invention belongs to the field of two-dimensional heterojunction device technology, specifically relating to a ferroelectrically controlled two-dimensional heterojunction transistor and its fabrication method. Background Technology

[0002] With the rapid development of artificial intelligence, edge computing, the Internet of Things, and new information processing systems, traditional integrated circuits based on the von Neumann architecture face problems such as high power consumption and limited computing efficiency. Negative differential resistors and negative differential transconductance devices, due to their unique transport characteristics of decreasing current with increasing voltage under specific bias conditions, have shown significant application value in multi-valued logic circuits, frequency multipliers, high-frequency oscillators, in-memory computing circuits, neuromorphic computing, and low-power information processing systems, and have therefore attracted widespread attention.

[0003] However, existing two-dimensional heterojunction negative differential transconductance devices still face serious performance bottlenecks in practical applications. First, traditional two-dimensional heterojunction devices mainly rely on the external gate electrode electric field to achieve band reconfiguration and carrier type conversion at the heterojunction interface. However, the gate electrode has limited control efficiency over two-dimensional materials, and usually requires a large gate electrode voltage and source-drain bias voltage to induce a significant negative differential transconductance effect. This results in high power consumption of the devices, making it difficult to meet the low-voltage operation requirements of ultra-low-power microelectronic devices. For example, in reference 1 (Gate-Tunable van der Waals Photodiodes with an Ultrahigh Peak-to-Valley Current Ratio. Small. 2023, 19, 2300010.), a heterojunction was constructed using black phosphorus / molybdenum distelluride. At a gate voltage of 60V, a source-drain voltage of 1.0V was required to achieve a peak-to-valley current ratio (PVCR) of approximately 30. In reference 2 (Van der Waals heterojunctions with negative differential transconductance for broadband photodetection, multi-valued logic, and artificial neuron. InfoMat. 2025; 7(10): e70028.), a heterojunction was constructed using black phosphorus / indium selenide. At a gate voltage of 60V, a source-drain voltage as high as 1.4V was required to achieve a PVCR of 43.5.

[0004] Secondly, due to the mismatch in carrier transport capabilities across the heterojunction, limited interface barrier modulation capabilities, Fermi level pinning effect, and insufficient gate electrode modulation efficiency, it is often difficult to obtain a high peak-to-valley current ratio, which limits its application in logic circuits and analog computing. For example, in reference 3 (Light-Regulated Anti-Ambipolar Transport with Multi-Logic States in Metal-WSe2-Metal Transistor. Adv. Electron. Mater. 2022, 8, 2200649.), a PVCR of 40 is achieved only under illumination with a source-drain voltage of 2V; in reference 4 (Band Structure Engineering of WSe2 Homo-Junction Interfaces via ThicknessControl. Adv. Mater. Interfaces. 2022, 9, 2101763.), a PVCR of approximately 10V is achieved only with a source-drain voltage of 1V under a gate voltage of 60V.

[0005] Furthermore, some two-dimensional heterojunction devices are constructed using unipolar semiconductors, resulting in a limited range of conduction state transitions. Limited transport modulation is achieved only through band bending or barrier height changes at the heterojunction interface, making it difficult to achieve dynamic carrier type transitions from hole to electron transport. This leads to stringent conditions for the generation of negative differential transconductance (NDE) effects, making it difficult to meet the high-stability NDE response requirements of low-power multi-valued logic and neuromorphic computing applications. During the fabrication of two-dimensional heterojunction devices, commonly used dry transfer processes (such as PMMA-assisted transfer) easily leave high-molecular-weight organic residues on the surface of the two-dimensional material and at the heterojunction interface, leading to interface contamination and increased trapped state density. This, in turn, causes Fermi level pinning, significantly reducing the ability of the applied gate electrode electric field to control the band structure, and resulting in poorer device consistency and decreased cycle stability.

[0006] Therefore, it is of great significance to study a ferroelectrically controlled two-dimensional heterojunction transistor and its fabrication method to solve the problems existing in the prior art. Summary of the Invention

[0007] The purpose of this invention is to solve the problems existing in the prior art and to provide a ferroelectrically controlled two-dimensional heterojunction transistor and its fabrication method.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] A ferroelectrically controlled two-dimensional heterojunction transistor includes a bottom gate electrode, a ferroelectric layer, palladium diselenide nanosheets, black phosphorus nanosheets, a source electrode, and a drain electrode.

[0010] A ferroelectric layer covers the upper surface of the bottom gate electrode;

[0011] Palladium diselenide nanosheets cover a localized area on the upper surface of the ferroelectric layer;

[0012] Local regions of black phosphorus nanosheets cover local regions of the upper surface of palladium diselenide nanosheets, and the remaining regions of black phosphorus nanosheets cover local regions of the upper surface of the ferroelectric layer.

[0013] The source electrode is in contact with the upper surface of the palladium diselenide nanosheet and is located on one side of the black phosphorus nanosheet.

[0014] The drain electrode is in contact with the upper surface of the black phosphorus nanosheet and is located on one side of the palladium diselenide nanosheet.

[0015] The thickness of palladium diselenide nanosheets is 40-70 nm (room temperature band gap less than 0.3 eV), and the thickness of black phosphorus nanosheets is 15-30 nm (room temperature band gap 0.2-0.6 eV).

[0016] This invention utilizes palladium diselenide nanosheets and black phosphorus nanosheets to construct a bipolar van der Waals heterojunction. Both black phosphorus nanosheets and palladium diselenide nanosheets are bipolar two-dimensional semiconductor materials with strong in-plane lattice anisotropy. They are bonded by weak van der Waals forces, overcoming the lattice mismatch and dangling bond defects that are unavoidable in traditional three-dimensional bulk semiconductor contacts. This results in a pure charge transport interface that is sensitive to external electric fields. The intrinsic bipolarity of this material combination means that under the drive of electric fields in different directions, the two layers can simultaneously accumulate the same type of charge carriers, forming pp or nn-type channels, or under a specific bias, they can transform into complementary conductive states, forming a pn heterojunction, thereby achieving a negative differential transconductance effect.

[0017] This invention also introduces a ferroelectric layer beneath the heterojunction. Utilizing the non-volatile remanent polarization of ferroelectric materials, a stable polarization electric field is established near the heterojunction interface, enabling continuous control over the carrier type, carrier concentration, and Fermi level position of black phosphorus nanosheets and palladium diselenide nanosheets. When the polarization direction of the ferroelectric layer faces the two-dimensional material, positive bound charges are generated on the surface of the ferroelectric layer, causing electron accumulation in the black phosphorus and palladium diselenide nanosheets and driving the heterojunction to transition to the n-mode conductivity state. When the polarization direction of the ferroelectric layer faces away from the two-dimensional material, negative bound charges are generated on the surface of the ferroelectric layer, causing hole accumulation in the heterojunction and driving the heterojunction to transition to the p-mode conductivity state. The non-volatile polarization field provided by the ferroelectric layer replaces the traditional continuous gate voltage control method. It can continuously control the carrier concentration and Fermi level position in the two-dimensional materials on both sides of the heterojunction under low bias conditions, so that the band arrangement at the heterojunction interface is pre-formed to facilitate carrier transport. This enables the device to achieve negative differential transconductance response at lower source-drain bias, thereby meeting the low-power operation requirements of low-power logic circuits, multi-valued logic circuits, and neuromorphic computing systems.

[0018] Palladium diselenide nanosheets exhibit a significant thickness-dependent bandgap characteristic, with the bandgap decreasing sharply from approximately 1.3 eV in the monolayer state towards near 0 eV in the bulk state as the number of layers increases. When the thickness is controlled within 40-70 nm, the palladium diselenide nanosheets are in a narrow bandgap semiconductor state close to the bulk state. At this point, the material possesses extremely high intrinsic electron concentration and excellent electron conductivity, which can significantly reduce the carrier injection barrier at the source / drain contact electrode and heterojunction interface, thereby providing a sufficiently strong channel current. When the thickness of the palladium diselenide nanosheets is less than 40 nm, the widening of the bandgap severely limits its electron transport capability, resulting in a severe order-of-magnitude mismatch with the channel current of black phosphorus nanosheets. This, in turn, greatly suppresses the current peak of the heterojunction in the intermediate voltage range, leading to a weakening or even disappearance of the negative differential transconductance effect. Conversely, when the thickness of the palladium diselenide nanosheets exceeds 70 nm, the material exhibits excessive half-metallic properties, resulting in increased leakage current and deteriorated turn-off characteristics of the overall device.

[0019] The band structure of black phosphorus nanosheets also exhibits a significant thickness dependence, with the band gap decreasing as the thickness increases. Within the thickness range of 10-30 nm, black phosphorus nanosheets not only maintain a narrow band gap of approximately 0.3 eV to achieve low-barrier hole injection and efficient transport, preserving their intrinsic advantage of high hole mobility, but more importantly, they can effectively overcome the strong electrostatic shielding effect inherent in excessively thick two-dimensional materials. Within this thickness window, the electric field generated by the back-gate voltage can fully penetrate the entire black phosphorus nanosheet, achieving efficient modulation of the Fermi level position, and the black phosphorus nanosheets exhibit obvious bipolar characteristics. If the thickness of the black phosphorus nanosheets exceeds 30 nm, the bulk black phosphorus nanosheets cause the gate electrode to lose its effective control over the band alignment state of the heterojunction interface, resulting in the black phosphorus nanosheets exhibiting strong unipolar hole transport characteristics, thereby weakening the heterojunction's conductivity state transition capability and preventing the formation of clear and sharp current peaks and valleys with the palladium diselenide nanosheets. If the thickness of the black phosphorus nanosheets is less than 10 nm, the thickness difference between the black phosphorus nanosheets and the palladium diselenide nanosheets will be too large, which will make it difficult to form heterojunctions.

[0020] Within the aforementioned thickness range, changes in the gate electrode voltage can drive the black phosphorus nanosheet / palladium diselenide nanosheet heterojunction to continuously switch between different conductivity states. When a negative gate voltage is applied, both the black phosphorus nanosheets and palladium diselenide nanosheets are dominated by hole transport, and the heterojunction exhibits a homopolar conductivity state. As the gate voltage increases in the positive direction, the heterojunction interface gradually forms a heteropolar conductivity state where electrons and holes coexist. The interface barrier increases and a carrier depletion effect occurs, leading to a decrease in channel current. When the gate voltage increases further, the black phosphorus nanosheets gradually shift from hole-dominated transport to electron-dominated transport, the heterojunction reforms into a homopolar conductivity state, the interface barrier decreases, the electron transport capability is enhanced, and the channel current increases again.

[0021] During continuous gate voltage scanning, the device channel current exhibits a non-monotonic variation characteristic of first increasing, then decreasing, and then increasing again with the gate voltage, thus forming a negative differential transconductance effect. This negative differential transconductance effect essentially originates from the synergistic effect of the high hole mobility of black phosphorus nanosheets and the high electron mobility of palladium diselenide nanosheets, as well as the reversible conversion between the same-polarity and opposite-polarity conduction states of the heterojunction driven by the gate electrode electric field. By optimizing the thickness of the black phosphorus nanosheets and palladium diselenide nanosheets, the current difference between different conduction states can be significantly enhanced, and the peak-to-valley current ratio can be improved, thereby obtaining stable and significant negative differential transconductance characteristics.

[0022] As a preferred technical solution:

[0023] The ferroelectrically controlled two-dimensional heterojunction transistor described above has a silicon wafer as its bottom gate electrode.

[0024] The ferroelectrically controlled two-dimensional heterojunction transistor described above has a ferroelectric layer that is a thin ferroelectric film with a thickness of 80-120 nm, and is made of polyvinylidene fluoride (PVDF) and its copolymers, hafnium zirconium oxide (HZO), lead zirconate titanate (PZT), bismuth ferrite (BFO), or barium titanate (BTO).

[0025] The ferroelectrically controlled two-dimensional heterojunction transistor described above has a root mean square (RMS) surface roughness of less than 5 nm for palladium diselenide nanosheets or black phosphorus nanosheets.

[0026] In the ferroelectrically controlled two-dimensional heterojunction transistor described above, the overlapping area of ​​the black phosphorus nanosheets and palladium diselenide nanosheets is greater than 225 μm. 2 .

[0027] As described above, in a ferroelectrically controlled two-dimensional heterojunction transistor, the source electrode or drain electrode is composed of a metal layer on the upper layer and a single or multiple layer of graphene nanosheets on the lower layer, or is composed of only a metal layer; the metal is aluminum, chromium, gold, chromium gold, aluminum gold, or platinum; the single or multiple layer of graphene nanosheets can form ohmic contacts with palladium diselenide nanosheets or black phosphorus nanosheets to reduce the potential barrier for electron injection.

[0028] The ferroelectrically controlled two-dimensional heterojunction transistor described above also includes a top insulating layer; the top insulating layer simultaneously covers the upper surfaces of the source electrode, palladium diselenide nanosheets, black phosphorus nanosheets, and drain electrode; the material of the top insulating layer is an organic polymer material or an inorganic insulating material, used to isolate the influence of oxygen, moisture, and other pollutants in the environment on the two-dimensional material heterojunction.

[0029] As described above, a ferroelectrically controlled two-dimensional heterojunction transistor can generate a significant negative differential transconductance effect under a source-drain bias voltage of no more than 0.6V, effectively reducing device power consumption. The negative differential transconductance effect is manifested as follows: under a fixed source-drain bias voltage, the source-drain current exhibits a non-monotonic change characteristic of first increasing and then decreasing with the increase of the back gate voltage, causing the transfer characteristic curve to form obvious current peaks and current valleys.

[0030] The ferroelectrically controlled two-dimensional heterojunction transistor exhibits a peak-to-valence current ratio (PVCR) of no less than 43 at a source-drain bias of 0.4V, demonstrating excellent signal amplification and multi-valued logic control capabilities, with a peak current of 1.2 × 10⁻⁶. -7 ~2.7×10 -7 A, the on / off ratio is greater than 4.3 × 10 2 .

[0031] This invention also provides a method for fabricating a ferroelectrically controlled two-dimensional heterojunction transistor as described above, comprising the following steps:

[0032] (a) Clean the surface of the bottom gate electrode;

[0033] (b) Fabricating a ferroelectric layer on the bottom gate electrode;

[0034] (c) Palladium diselenide nanosheets are coated on a local area of ​​the upper surface of the ferroelectric layer by dry transfer, and then black phosphorus nanosheets are coated on a local area of ​​the upper surface of the palladium diselenide nanosheets and a local area of ​​the upper surface of the ferroelectric layer by dry transfer.

[0035] (d) A source electrode is formed on the upper surface of the palladium diselenide nanosheet in the region on one side of the black phosphorus nanosheet, and a drain electrode is formed on the upper surface of the black phosphorus nanosheet in the region on one side of the palladium diselenide nanosheet.

[0036] (e) A top insulating layer is applied to the upper surfaces of the source electrode, palladium diselenide nanosheets, black phosphorus nanosheets, and drain electrode.

[0037] As a preferred technical solution:

[0038] As described above, the dry transfer method uses a carrier composed of a PPC (polypropylene carbonate) membrane and a PDMS (polydimethylsiloxane) substrate. In use, the PPC membrane is aligned with the two-dimensional material and heat-assisted pickup is performed at 30-60°C. After the transfer is completed, the sample is heated to 80-130°C to soften the PPC membrane and separate it from the two-dimensional material.

[0039] The preparation steps of the carrier used in dry transfer are as follows:

[0040] (a) PPC is added to an organic solvent and magnetically stirred to dissolve the PPC completely, resulting in a uniform and transparent PPC solution, wherein the mass ratio of PPC to organic solvent is 1:5-10.

[0041] (b) A PPC solution is dropped onto the surface of a silicon wafer and a PPC film is formed by spin coating;

[0042] The spin coating process includes a low-speed spin coating stage and a high-speed spin coating stage. The low-speed spin coating stage has a rotation speed of 500 rpm and a duration of 10 s, while the high-speed spin coating stage has a rotation speed of 2500 rpm and a duration of 60 s.

[0043] (c) Heat-treat the PPC membrane at 80-130℃ for 1-10 min to remove residual solvent;

[0044] (d) Use polyimide tape, polyester tape or other flexible support tape to pick up the PDMS film, and then use the PDMS film to peel the PPC film from the silicon wafer surface to form a tape / PDMS / PPC structure from top to bottom, which is the carrier used for dry transfer.

[0045] Existing dry transfer processes tend to leave behind high-molecular-weight organic impurities at the van der Waals heterojunction interface, thereby pinning the interfacial Fermi level and severely weakening the sensitivity of the external electric field to band reconfiguration. This invention avoids this problem. Compared with traditional PMMA-assisted transfer processes, PPC has lower interfacial adsorption energy and lower heat release temperature, and can be desorbed entirely through thermal softening after transfer. This significantly reduces the organic polymer residues on the surface of the two-dimensional material and at the heterojunction interface. The reduction of interfacial residues effectively lowers the density of trapped states and the Fermi level pinning effect.

[0046] Beneficial effects:

[0047] (1) A ferroelectrically controlled two-dimensional heterojunction transistor of the present invention adopts a palladium diselenide / black phosphorus bipolar two-dimensional van der Waals heterostructure. By optimizing the material thickness and heterojunction interface quality, the dynamic reconstruction of the heterojunction band structure is achieved by ferroelectric control. It can obtain significant negative differential transconductance effect and high peak-to-valley current ratio under low source-drain bias voltage and gate electrode voltage, and exhibits excellent low power consumption characteristics and high signal amplification capability.

[0048] (2) A ferroelectrically controlled two-dimensional heterojunction transistor of the present invention can generate a significant negative differential transconductance effect under low source-drain bias and gate electrode voltage conditions, and obtain a high peak-to-valley current ratio, while having low power consumption, high gain and excellent logic control capability.

[0049] (3) The fabrication method of field-effect transistor based on ferroelectric control bipolar two-dimensional heterojunction. The PPC-assisted dry transfer process effectively reduces the organic residue at the interface and the Fermi level pinning effect, improves the interface cleanliness, and makes the device have good application value in low-power logic, multi-valued logic and neuromorphic computing. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the structure of a ferroelectrically controlled two-dimensional heterojunction transistor according to the present invention;

[0051] Figure 2 This is a photograph of the palladium diselenide nanosheet / black phosphorus nanosheet heterostructure prepared in Example 1 of this invention.

[0052] Figure 3 The transfer curve of the ferroelectrically controlled two-dimensional heterojunction transistor prepared in Example 1 of the present invention is shown under the condition of a source-drain voltage of 0.4V.

[0053] Figure 4 The transfer curve of the two-dimensional heterojunction transistor in Comparative Example 1 is shown under the condition of a source-drain voltage of 1.0V.

[0054] Figure 5The transfer curve of the two-dimensional heterojunction transistor in Comparative Example 2 is shown under the condition of a source-drain voltage of 1.0V.

[0055] Figure 6 The transfer curve of the two-dimensional heterojunction transistor in Comparative Example 3 is shown under the condition of a source-drain voltage of 1.0V.

[0056] Figure 7 The transfer curve of the two-dimensional heterojunction transistor in Comparative Example 4 is shown at a source-drain voltage of 1.2V.

[0057] Figure 8 The transfer curve of the two-dimensional heterojunction transistor in Comparative Example 5 is shown under the condition of a source-drain voltage of 1.0V.

[0058] Among them, 1 is the bottom gate electrode; 2 is the ferroelectric layer; 3 is the palladium diselenide nanosheet; 4 is the black phosphorus nanosheet; 5 is the drain electrode; 6 is the source electrode; and 7 is the top insulating layer. Detailed Implementation

[0059] The present invention will be further described below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0060] The test methods involved in the performance indicators in the embodiments and comparative examples of this invention are as follows:

[0061] Peak-to-valley current ratio, peak current, and on / off ratio were tested using a semiconductor parameter analysis system. The testing instrument was a Keithley 4200A-SCS semiconductor parameter analysis system from Tektronix, USA, and the testing environment was room temperature. First, the fabricated two-dimensional heterojunction transistor was placed on a probe stage, with the three ends of the probe stage contacting the bottom gate electrode, source electrode, and drain electrode, respectively. A unidirectional scanning voltage from negative to positive was applied to the gate electrode of the fabricated two-dimensional heterojunction transistor, and the source-drain bias voltage was gradually increased to obtain the gate electrode voltage-source-drain current curves under different source-drain bias voltages. When the source-drain bias voltage reached 1.2V and no significant negative differential transconductance effect was observed, or when the gate electrode current of the two-dimensional heterojunction transistor exceeded 1×10⁻⁶, the test was considered complete. -6 Stop applying source / drain bias voltage at time A.

[0062] Peak current is defined as the maximum source-drain current value in the negative differential transconductance region of the gate electrode voltage-source-drain current curve measured under fixed source-drain bias conditions.

[0063] Valley current is defined as the minimum source-drain current value that appears after the peak current in the gate voltage-source-drain current curve measured under fixed source-drain bias conditions, located in the negative differential transconductance region.

[0064] Peak-to-valley current ratio (PVCR) is calculated using the following formula:

[0065] ;

[0066] Among them, I peak For peak current, I valley This is the valley current.

[0067] The on / off ratio is defined as the ratio of the maximum to the minimum source / drain current measured within the gate voltage curve.

[0068] ;

[0069] Among them, I max I represents the maximum source-drain current in the gate voltage-source-drain current curve. min This represents the minimum source / drain current in the gate voltage-source / drain current curve.

[0070] Example 1

[0071] A method for fabricating a ferroelectrically controlled two-dimensional heterojunction transistor, such as... Figure 1 As shown, it includes the following steps:

[0072] (1) Select a silicon wafer as the bottom gate electrode 1, and then use acetone, isopropanol and deionized water to ultrasonically clean the bottom gate electrode 1 for 10 minutes, and blow away the residual moisture on the surface with a nitrogen gun.

[0073] (2) A ferroelectric thin film was prepared on the upper surface of the bottom gate electrode 1 using P(VDF-TrFE) (manufacturer: Arkema, brand name: Piezotech Materials) by spin coating, and then annealed at 135°C to obtain a ferroelectric layer 2 with a thickness of 80 nm.

[0074] (3) Preparation of the carrier used in dry transfer;

[0075] (a) PPC is added to an organic solvent and magnetically stirred at room temperature for 2 hours to fully dissolve PPC, resulting in a uniform and transparent PPC solution, wherein the mass ratio of PPC to organic solvent is 1:5.

[0076] (b) A PPC solution is dropped onto the surface of a silicon wafer (note: this silicon wafer is not the silicon wafer of step (1)) and a PPC film is formed by spin coating;

[0077] The spin coating process includes a low-speed spin coating stage and a high-speed spin coating stage. The low-speed spin coating stage has a rotation speed of 500 rpm and a duration of 10 s, while the high-speed spin coating stage has a rotation speed of 2500 rpm and a duration of 60 s.

[0078] (c) The PPC membrane was heat-treated at 80°C for 4 min to remove residual solvent;

[0079] (d) A PDMS film is applied using polyimide tape, and then the PPC film is peeled off from the silicon wafer surface using the PDMS film, forming a tape / PDMS / PPC structure from top to bottom, which is the carrier used for dry transfer.

[0080] (4) Dry transfer of palladium diselenide nanosheets and black phosphorus nanosheets:

[0081] The carrier obtained in step (3) was mounted on a micro-transfer platform. Under an optical microscope, palladium diselenide nanosheets with a thickness of 40 nm were selected. The PPC film and palladium diselenide nanosheets were aligned and slowly brought into contact. Heat-assisted pickup was performed at 40 °C to detach the palladium diselenide nanosheets from the original tape and attach them to the surface of the PPC film. Then, palladium diselenide nanosheets 3 were transferred to a local area on the upper surface of the ferroelectric layer 2. Then, black phosphorus nanosheets 4 with a thickness of 15 nm were covered on the local area on the upper surface of the palladium diselenide nanosheets 3 and the local area on the upper surface of the ferroelectric layer 2 using the same method.

[0082] The surface roughness root mean square value of palladium diselenide nanosheet 3 is 3 nm; the surface roughness root mean square value of black phosphorus nanosheet 4 is 3 nm; and the area of ​​the overlapping region between black phosphorus nanosheet 4 and palladium diselenide nanosheet 3 is 230 μm. 2 ;

[0083] The palladium diselenide nanosheet / black phosphorus nanosheet heterojunction structure constructed from palladium diselenide nanosheets and black phosphorus nanosheets is as follows: Figure 2 As shown;

[0084] (5) Electron beam evaporation is used to deposit metal on the upper surface of palladium diselenide nanosheet 3 in the region on one side of black phosphorus nanosheet 4 to form source electrode 6, and then electron beam evaporation is used to deposit metal on the upper surface of black phosphorus nanosheet in the region on one side of palladium diselenide nanosheet to form drain electrode 5; the deposition rate is 0.5 Å / s; the metal is aluminum;

[0085] (6) A top insulating layer 7 (made of organic polymer material) is covered on the upper surface of the source electrode 6, palladium diselenide nanosheet 3, black phosphorus nanosheet 4, and drain electrode 5 to obtain a ferroelectrically regulated two-dimensional heterojunction transistor.

[0086] The ferroelectrically controlled two-dimensional heterojunction transistor finally fabricated exhibits a significant negative differential transconductance effect at a source-drain bias of 0.4V (applied voltage from -15V to +15V); Figure 3 As shown, the ferroelectrically controlled two-dimensional heterojunction transistor has a peak-to-valence current ratio of 43 and a peak current of 1.2 × 10⁻⁶ at a source-drain bias of 0.4 V. -7A, the switching ratio is 4.4 × 10 2 It exhibits a significant negative differential transconductance effect.

[0087] Comparative Example 1

[0088] A two-dimensional heterojunction transistor is basically the same as in Embodiment 1, except that step (2) is omitted, i.e., it does not contain a ferroelectric layer.

[0089] A semiconductor parameter analysis system was used to gradually increase the source-drain bias voltage by applying a voltage from -60V to +60V to the gate electrode of a two-dimensional heterojunction transistor without a ferroelectric layer. When the source-drain bias voltage was below 0.8V, the device did not exhibit a significant negative differential transconductance effect; when the source-drain bias voltage increased to 1.0V, the device began to exhibit a significant negative differential transconductance effect, such as... Figure 4 As shown, the peak-to-valley current ratio is 15, and the peak current is 9.6 × 10⁻⁶. -9 A.

[0090] Comparing Comparative Example 1 and Example 1, it can be seen that after introducing the ferroelectric layer, Example 1 achieves a significant negative differential transconductance effect and a higher peak-to-valley current ratio with only lower gate electrode voltage and source-to-drain bias. This is because ferroelectric materials possess a localized field of GV / m, and the ferroelectric layer can generate an extremely strong non-volatile polarization field, thereby continuously and effectively controlling the carrier concentration and Fermi level position in black phosphorus nanosheets and palladium diselenide nanosheets, resulting in an energy level arrangement at the heterojunction interface that is conducive to carrier transport and band reconfiguration. The accumulation of electrons or holes generated by ferroelectric polarization reduces the external electric field strength required for the heterojunction's conduction state transition, enabling the device to switch between different conduction states under lower gate voltage and source-to-drain bias conditions. Simultaneously, the ferroelectric layer enhances the current difference between different conduction states of the heterojunction, increasing the interval between current peaks and valleys, thereby significantly improving the peak-to-valley current ratio and reducing device power consumption.

[0091] Therefore, the ferroelectric layer not only reduces the turn-on voltage of the negative differential transconductance effect, but also enhances the bandgap control capability and carrier transport control capability of the heterojunction interface, enabling the device to obtain a more significant negative differential transconductance response at a lower operating voltage.

[0092] Comparative Example 2

[0093] A two-dimensional heterojunction transistor is basically the same as in Example 1, except that the palladium diselenide nanosheets in step (4) are replaced with molybdenum distellide nanosheets of the same thickness.

[0094] Using a semiconductor parameter analysis system, the source-drain bias voltage of the two-dimensional heterojunction transistor fabricated in this example was gradually increased while applying a voltage from -15V to +15V to the gate electrode. When the source-drain bias voltage was below 0.8V, the device did not exhibit significant negative differential transconductance behavior; when the source-drain bias voltage increased to 1.0V, the device exhibited a weak negative differential transconductance effect, such as... Figure 5 As shown, the peak-to-valley current ratio is 6, and the peak current is 9 × 10⁻⁶. -9 A.

[0095] Comparing Comparative Example 2 and Example 1, it can be seen that when using palladium diselenide nanosheets to construct a heterojunction, the device can achieve a more significant negative differential transconductance effect at a lower source-drain bias voltage, and exhibits a higher peak-to-valley current ratio and a larger peak current. This is because palladium diselenide nanosheets are a bipolar two-dimensional semiconductor material with a thickness-dependent narrow bandgap characteristic. Within a thickness range of 40–70 nm, it possesses high electron concentration and excellent electron transport capability, enabling wider Fermi level tuning under ferroelectric polarization fields, thereby effectively promoting reversible transitions between the pp, pn, and nn conduction states of the heterojunction. In contrast, molybdenum distelluride nanosheets have a larger bandgap and lower electron transport capability under the same thickness conditions, and their interfacial carrier transfer efficiency is lower when formed into a heterojunction with black phosphorus nanosheets. During gate voltage modulation, the molybdenum ditelluride nanosheets have a weak ability to accumulate electrons on the side, which leads to a reduction in the degree of band reconfiguration at the heterojunction interface. This results in insufficient conversion between the same polarity conduction state and the opposite polarity conduction state, thereby weakening the carrier depletion effect.

[0096] Comparative Example 3

[0097] A two-dimensional heterojunction transistor is basically the same as in Example 1, except that the thickness of the palladium diselenide nanosheet in step (4) is 35 nm.

[0098] Using a semiconductor parameter analysis system, the source-drain bias voltage of the two-dimensional heterojunction transistor fabricated in this example was gradually increased while applying a voltage from -15V to +15V to the gate electrode. When the source-drain bias voltage was below 0.8V, the device did not exhibit significant negative differential transconductance behavior; when the source-drain bias voltage increased to 1.0V, the device exhibited a weak negative differential transconductance effect, such as... Figure 6 As shown, the peak-to-valley current ratio is 3, and the peak current is 1.5 × 10⁻⁶. -9 A.

[0099] Comparing Comparative Example 3 and Example 1, it can be observed that when the thickness of the palladium diselenide nanosheets is less than the range defined in this invention, the operating voltage required for the device to achieve the negative differential transconductance effect increases significantly, while the peak-to-valley current ratio decreases sharply, and the negative differential transconductance characteristics are severely weakened. This is because palladium diselenide is a two-dimensional semiconductor material with a significant thickness dependence, and its band gap increases rapidly as the thickness decreases. When the thickness of the palladium diselenide nanosheets is reduced to 35 nm, its band gap is wider than that of palladium diselenide in Example 1, leading to a decrease in the intrinsic electron concentration of the material, a weakening of electron transport capability, and an increase in the electron injection barrier between the source electrode and the heterojunction interface, thereby significantly reducing the channel current.

[0100] Meanwhile, as the thickness of the palladium diselenide nanosheets decreases, the carrier transport capacity matching between them and the black phosphorus nanosheets is disrupted. The black phosphorus nanosheets maintain a high hole transport capacity, while the electron transport capacity on the palladium diselenide nanosheet side decreases significantly, resulting in a large imbalance between carrier concentration and transport capacity on both sides of the heterojunction. During gate voltage modulation, the amplitude of the heterojunction interface barrier change decreases, making it difficult to form a significant carrier depletion effect and current valley, thus significantly reducing the difference between the peak and valley current values ​​and drastically lowering the peak-to-valley current ratio.

[0101] Furthermore, due to the reduced electron transport capability, the built-in electric field generated by the polarization of the ferroelectric layer is insufficient to effectively induce sufficient electron accumulation on the palladium diselenide nanosheet side, thus weakening the band reconfiguration at the heterojunction interface. In order to drive the heterojunction to complete the conduction state transition and form an observable negative differential transconductance response, a larger source-drain bias voltage is required to enhance carrier injection and interfacial electric field effects. Therefore, the device only exhibits a weak negative differential transconductance effect at a relatively high source-drain bias voltage of 1.0 V.

[0102] Comparative Example 4

[0103] A two-dimensional heterojunction transistor is basically the same as in Example 1, except that the thickness of the palladium diselenide nanosheet in step (4) is 75 nm.

[0104] Using a semiconductor parameter analysis system, a voltage ranging from -15V to +15V was applied to the gate electrode of the two-dimensional heterojunction transistor fabricated in this example, and the source-drain bias voltage was gradually increased. When the source-drain bias voltage increased to 1.2V, the device exhibited an extremely high off-state current value. No significant current peaks or valleys were observed throughout the gate voltage scan, and no negative differential transconductance effect was generated. Figure 7 As shown.

[0105] Comparing Comparative Example 4 and Example 1, it can be seen that when the thickness of the palladium diselenide nanosheets exceeds the limits defined in this invention, the gate electrode control capability of the device decreases significantly, and the negative differential transconductance is severely suppressed or even completely disappears. This is because as the thickness of the palladium diselenide nanosheets further increases, its band structure gradually approaches the bulk phase. At this time, the material band gap further decreases and approaches the half-metal state, and the free carrier concentration increases significantly, keeping the channel in a high conductivity state. Although a higher carrier concentration is beneficial to improving conductivity, it also leads to a significant increase in the device's off-state current, making it difficult for the gate electrode electric field to effectively control the channel carrier concentration, thereby weakening the device's switching capability, and making it difficult for the heterojunction to form obvious current peaks and valleys.

[0106] Comparative Example 5

[0107] A two-dimensional heterojunction transistor is basically the same as in Example 1, except that the thickness of the black phosphorus nanosheet in step (4) is 35 nm.

[0108] Using a semiconductor parameter analysis system, the source-drain bias voltage was gradually increased while applying a voltage from -15V to +15V to the gate electrode of the two-dimensional heterojunction transistor fabricated in this example. When the source-drain bias voltage increased to 1.0V, the device exhibited a weak negative differential transconductance effect, such as... Figure 8 As shown.

[0109] Comparing Comparative Example 5 and Example 1, it can be observed that the difference between the peak and valley current values ​​is significantly reduced, the peak-to-valley current ratio decreases significantly, and the negative differential transconductance region narrows. When the thickness of the black phosphorus nanosheets exceeds the range defined in this invention, the negative differential transconductance performance of the device significantly degrades. This is because as the thickness of the black phosphorus nanosheets increases, its hole transport characteristics gradually strengthen while its bipolar transport characteristics weaken, allowing the black phosphorus to maintain a hole-dominated transport state over a wider gate voltage range. Due to the suppression of the electron transport component, the transition process from hole-dominated to electron-dominated transport in black phosphorus becomes insufficient, thereby weakening the switching capability of the heterojunction's conductivity state. This significantly reduces the amplitude of the potential barrier change formed at the heterojunction interface. The strong room-temperature thermal excitation caused by the narrowing bandgap and the interband defect-assisted tunneling charge flow directly fill the current valley of the transfer characteristic curve, resulting in a persistently high valley current in the device.

[0110] Example 2

[0111] A method for fabricating a ferroelectrically controlled two-dimensional heterojunction transistor includes the following steps:

[0112] (1) Select a silicon wafer as the bottom gate electrode, and then use acetone, isopropanol and deionized water to ultrasonically clean the bottom gate electrode for 10 minutes in sequence, and blow away the residual moisture on the surface with a nitrogen gun.

[0113] (2) A ferroelectric thin film was prepared on the upper surface of the bottom gate electrode using P(VDF-TrFE) (manufacturer: Arkema, brand name: Piezotech Materials) by spin coating, and then annealed at 135°C to obtain a ferroelectric layer with a thickness of 100 nm.

[0114] (3) Preparation of the carrier used in dry transfer;

[0115] (a) PPC is added to an organic solvent and magnetically stirred at room temperature for 2 hours to fully dissolve PPC, resulting in a uniform and transparent PPC solution, wherein the mass ratio of PPC to organic solvent is 1:7.

[0116] (b) A PPC solution is dropped onto the surface of a silicon wafer (note: this silicon wafer is not the silicon wafer of step (1)) and a PPC film is formed by spin coating;

[0117] The spin coating process includes a low-speed spin coating stage and a high-speed spin coating stage. The low-speed spin coating stage has a rotation speed of 500 rpm and a duration of 10 s, while the high-speed spin coating stage has a rotation speed of 2500 rpm and a duration of 60 s.

[0118] (c) The PPC membrane was heat-treated at 100°C for 6 minutes to remove residual solvent;

[0119] (d) A PDMS film is applied using polyimide tape, and then the PPC film is peeled off from the silicon wafer surface using the PDMS film, forming a tape / PDMS / PPC structure from top to bottom, which is the carrier used for dry transfer.

[0120] (4) Dry transfer of palladium diselenide nanosheets and black phosphorus nanosheets:

[0121] The carrier obtained in step (3) was mounted on a micro-transfer platform. Under an optical microscope, palladium diselenide nanosheets with a thickness of 50 nm were selected. The PPC film and palladium diselenide nanosheets were aligned and slowly brought into contact. Heat-assisted pickup was performed at 40 °C to detach the palladium diselenide nanosheets from the original tape and attach them to the surface of the PPC film. Then, the palladium diselenide nanosheets were transferred to a local area on the upper surface of the ferroelectric layer. The same method was then used to cover the local area on the upper surface of the palladium diselenide nanosheets and the local area on the upper surface of the ferroelectric layer with black phosphorus nanosheets with a thickness of 20 nm.

[0122] The surface roughness root mean square value of palladium diselenide nanosheets is 3 nm; the surface roughness root mean square value of black phosphorus nanosheets is 3 nm; the area of ​​the overlapping region between the black phosphorus nanosheets and palladium diselenide nanosheets is 250 μm. 2 ;

[0123] (5) Electron beam evaporation was used to deposit metal on the upper surface of the palladium diselenide nanosheet located on one side of the black phosphorus nanosheet to form a source electrode, and then electron beam evaporation was used to deposit metal on the upper surface of the black phosphorus nanosheet located on one side of the palladium diselenide nanosheet to form a drain electrode; the deposition rate was 0.5 Å / s; the metal was chromium.

[0124] (6) A top insulating layer (made of organic polymer material) is covered on the upper surface of the source electrode, palladium diselenide nanosheet, black phosphorus nanosheet and drain electrode to obtain a ferroelectrically regulated two-dimensional heterojunction transistor.

[0125] The finally fabricated ferroelectrically controlled two-dimensional heterojunction transistor exhibits a significant negative differential transconductance effect at a source-drain bias of 0.4V (applied voltage from -15V to +15V); the peak-to-valence current ratio of the ferroelectrically controlled two-dimensional heterojunction transistor at a source-drain bias of 0.4V is 45, and the peak current is 2.0 × 10⁻⁶. -7 A, the switching ratio is 5.1 × 10 2 .

[0126] Example 3

[0127] A method for fabricating a ferroelectrically controlled two-dimensional heterojunction transistor includes the following steps:

[0128] (1) Select a silicon wafer as the bottom gate electrode, and then use acetone, isopropanol and deionized water to ultrasonically clean the bottom gate electrode for 10 minutes in sequence, and blow away the residual moisture on the surface with a nitrogen gun.

[0129] (2) A ferroelectric thin film was prepared on the upper surface of the bottom gate electrode using P(VDF-TrFE) (manufacturer: Arkema, brand name: Piezotech Materials) by spin coating, and then annealed at 135°C to obtain a ferroelectric layer with a thickness of 110 nm.

[0130] (3) Preparation of the carrier used in dry transfer;

[0131] (a) PPC is added to an organic solvent and magnetically stirred at room temperature for 2 hours to fully dissolve the PPC, resulting in a uniform and transparent PPC solution, wherein the mass ratio of PPC to organic solvent is 1:8.

[0132] (b) A PPC solution is dropped onto the surface of a silicon wafer (note: this silicon wafer is not the silicon wafer of step (1)) and a PPC film is formed by spin coating;

[0133] The spin coating process includes a low-speed spin coating stage and a high-speed spin coating stage. The low-speed spin coating stage has a rotation speed of 500 rpm and a duration of 10 s, while the high-speed spin coating stage has a rotation speed of 2500 rpm and a duration of 60 s.

[0134] (c) The PPC membrane was heat-treated at 120°C for 8 minutes to remove residual solvent;

[0135] (d) Use polyester tape to pick up PDMS film, and then use PDMS film to peel PPC film off from silicon wafer surface, forming tape / PDMS / PPC structure from top to bottom, which is the carrier used for dry transfer;

[0136] (4) Dry transfer of palladium diselenide nanosheets and black phosphorus nanosheets:

[0137] The carrier obtained in step (3) was mounted on a micro-transfer platform. Under an optical microscope, palladium diselenide nanosheets with a thickness of 60 nm were selected. The PPC film and palladium diselenide nanosheets were aligned and slowly brought into contact. Heat-assisted pickup was performed at 40 °C to allow the palladium diselenide nanosheets to detach from the original tape and adhere to the surface of the PPC film. Then, the palladium diselenide nanosheets were transferred to a local area on the upper surface of the ferroelectric layer. The same method was then used to cover the local area on the upper surface of the palladium diselenide nanosheets and the local area on the upper surface of the ferroelectric layer with black phosphorus nanosheets with a thickness of 25 nm.

[0138] The surface roughness root mean square value of palladium diselenide nanosheets is 3 nm; the surface roughness root mean square value of black phosphorus nanosheets is 3 nm; the area of ​​the overlapping region between black phosphorus nanosheets and palladium diselenide nanosheets is 300 μm. 2 ;

[0139] (5) Electron beam evaporation was used to deposit metal on the upper surface of the palladium diselenide nanosheet located on one side of the black phosphorus nanosheet to form a source electrode, and then electron beam evaporation was used to deposit metal on the upper surface of the black phosphorus nanosheet located on one side of the palladium diselenide nanosheet to form a drain electrode; the deposition rate was 0.5 Å / s; the metal was gold.

[0140] (6) A top insulating layer (made of inorganic insulating material) is covered on the upper surface of the source electrode, palladium diselenide nanosheet, black phosphorus nanosheet and drain electrode to obtain a ferroelectrically regulated two-dimensional heterojunction transistor.

[0141] The finally fabricated ferroelectrically controlled two-dimensional heterojunction transistor exhibits a significant negative differential transconductance effect at a source-drain bias of 0.4V (applied voltage from -15V to +15V); the peak-to-valence current ratio of the ferroelectrically controlled two-dimensional heterojunction transistor at a source-drain bias of 0.4V is 50, and the peak current is 2.2 × 10⁻⁶. -7 A, the switching ratio is 7.3 × 10 2 .

[0142] Example 4

[0143] A method for fabricating a ferroelectrically controlled two-dimensional heterojunction transistor includes the following steps:

[0144] (1) Select a silicon wafer as the bottom gate electrode, and then use acetone, isopropanol and deionized water to ultrasonically clean the bottom gate electrode for 10 minutes in sequence, and blow away the residual moisture on the surface with a nitrogen gun.

[0145] (2) A ferroelectric thin film was prepared on the upper surface of the bottom gate electrode using P(VDF-TrFE) (manufacturer: Arkema, brand name: Piezotech Materials) by spin coating, and then annealed at 135°C to obtain a ferroelectric layer with a thickness of 120 nm.

[0146] (3) Preparation of the carrier used in dry transfer;

[0147] (a) PPC is added to an organic solvent and magnetically stirred at room temperature for 2 hours to fully dissolve PPC, resulting in a uniform and transparent PPC solution, wherein the mass ratio of PPC to organic solvent is 1:10.

[0148] (b) A PPC solution is dropped onto the surface of a silicon wafer (note: this silicon wafer is not the silicon wafer of step (1)) and a PPC film is formed by spin coating;

[0149] The spin coating process includes a low-speed spin coating stage and a high-speed spin coating stage. The low-speed spin coating stage has a rotation speed of 500 rpm and a duration of 10 s, while the high-speed spin coating stage has a rotation speed of 2500 rpm and a duration of 60 s.

[0150] (c) The PPC membrane was heat-treated at 130°C for 10 min to remove residual solvent;

[0151] (d) Use polyester tape to pick up PDMS film, and then use PDMS film to peel PPC film off from silicon wafer surface, forming tape / PDMS / PPC structure from top to bottom, which is the carrier used for dry transfer;

[0152] (4) Dry transfer of palladium diselenide nanosheets and black phosphorus nanosheets:

[0153] The carrier obtained in step (3) was mounted on a micro-transfer platform. Under an optical microscope, palladium diselenide nanosheets with a thickness of 70 nm were selected. The PPC film and palladium diselenide nanosheets were aligned and slowly brought into contact. Heat-assisted pickup was performed at 40 °C to detach the palladium diselenide nanosheets from the original tape and attach them to the surface of the PPC film. Then, the palladium diselenide nanosheets were transferred to a local area on the upper surface of the ferroelectric layer. The same method was then used to cover the local area on the upper surface of the palladium diselenide nanosheets and the local area on the upper surface of the ferroelectric layer with black phosphorus nanosheets with a thickness of 30 nm.

[0154] The surface roughness root mean square value of palladium diselenide nanosheets is 3 nm; the surface roughness root mean square value of black phosphorus nanosheets is 3 nm; the area of ​​the overlapping region between black phosphorus nanosheets and palladium diselenide nanosheets is 400 μm. 2 ;

[0155] (5) Electron beam evaporation was used to deposit metal on the upper surface of the palladium diselenide nanosheet located on one side of the black phosphorus nanosheet to form a source electrode, and then electron beam evaporation was used to deposit metal on the upper surface of the black phosphorus nanosheet located on one side of the palladium diselenide nanosheet to form a drain electrode; the deposition rate was 0.5 Å / s; the metal was chromium gold.

[0156] (6) A top insulating layer (made of inorganic insulating material) is covered on the upper surface of the source electrode, palladium diselenide nanosheet, black phosphorus nanosheet and drain electrode to obtain a ferroelectrically regulated two-dimensional heterojunction transistor.

[0157] The finally fabricated ferroelectrically controlled two-dimensional heterojunction transistor exhibits a significant negative differential transconductance effect at a source-drain bias of 0.4V (applied voltage from -15V to +15V); the peak-to-valence current ratio of the ferroelectrically controlled two-dimensional heterojunction transistor at a source-drain bias of 0.4V is 52, and the peak current is 2.7 × 10⁻⁶. -7 A, the switching ratio is 9.2 × 10 2 .

[0158] In the above embodiments and comparative examples, the conditions not specifically limited (such as the source of PPC, the source of PDMS film, the source of organic polymer materials, the source of inorganic insulating materials, etc.) are all experimentally verified conditions that are unrelated to the performance of the listed ferroelectrically regulated two-dimensional heterojunction transistors.

Claims

1. A ferroelectrically controlled two-dimensional heterojunction transistor, characterized in that, It includes a bottom gate electrode, a ferroelectric layer, palladium diselenide nanosheets, black phosphorus nanosheets, a source electrode, and a drain electrode; A ferroelectric layer covers the upper surface of the bottom gate electrode; Palladium diselenide nanosheets cover a localized area on the upper surface of the ferroelectric layer; Local regions of black phosphorus nanosheets cover local regions of the upper surface of palladium diselenide nanosheets, and the remaining regions of black phosphorus nanosheets cover local regions of the upper surface of the ferroelectric layer. The source electrode is in contact with the upper surface of the palladium diselenide nanosheet and is located on one side of the black phosphorus nanosheet. The drain electrode is in contact with the upper surface of the black phosphorus nanosheet and is located on one side of the palladium diselenide nanosheet. The thickness of palladium diselenide nanosheets is 40-70 nm, and the thickness of black phosphorus nanosheets is 15-30 nm. Ferroelectrically controlled two-dimensional heterojunction transistors can generate negative differential transconductance at a source-drain bias voltage not exceeding 0.6V. The ferroelectrically controlled two-dimensional heterojunction transistor exhibits a peak-to-valence current ratio of no less than 43 at a source-drain bias of 0.4V, with a peak current of 1.2 × 10⁻⁶. -7 ~2.7×10 -7 A, the on / off ratio is greater than 4.3 × 10 2 .

2. The ferroelectrically controlled two-dimensional heterojunction transistor according to claim 1, characterized in that, The bottom gate electrode is a silicon wafer.

3. The ferroelectrically controlled two-dimensional heterojunction transistor according to claim 1, characterized in that, The ferroelectric layer is a ferroelectric thin film with a thickness of 80-120 nm, and the material is polyvinylidene fluoride and its copolymers, zirconium hafnium oxide, lead zirconate titanate, bismuth ferrite or barium titanate.

4. The ferroelectrically controlled two-dimensional heterojunction transistor according to claim 1, characterized in that, The root mean square value of the surface roughness of palladium diselenide nanosheets or black phosphorus nanosheets is less than 5 nm.

5. A ferroelectrically controlled two-dimensional heterojunction transistor according to claim 1, characterized in that, The overlapping area of ​​the black phosphorus nanosheets and palladium diselenide nanosheets is greater than 225 μm. 2 .

6. A ferroelectrically controlled two-dimensional heterojunction transistor according to claim 1, characterized in that, The source or drain electrode consists of a metal layer on top and graphene nanosheets on the bottom, or it consists of only a metal layer; the metal is aluminum, gold, chromium gold, aluminum gold, or platinum.

7. A ferroelectrically controlled two-dimensional heterojunction transistor according to claim 1, characterized in that, It also includes a top insulating layer; the top insulating layer covers the upper surfaces of the source electrode, palladium diselenide nanosheets, black phosphorus nanosheets, and drain electrode; the material of the top insulating layer is an organic polymer material or an inorganic insulating material.

8. A method for fabricating a ferroelectrically regulated two-dimensional heterojunction transistor as described in any one of claims 1 to 7, characterized in that, Includes the following steps: (a) Clean the surface of the bottom gate electrode; (b) Fabricating a ferroelectric layer on the bottom gate electrode; (c) Palladium diselenide nanosheets are coated on a local area of ​​the upper surface of the ferroelectric layer by dry transfer, and then black phosphorus nanosheets are coated on a local area of ​​the upper surface of the palladium diselenide nanosheets and a local area of ​​the upper surface of the ferroelectric layer by dry transfer. (d) A source electrode is formed on the upper surface of the palladium diselenide nanosheet in the region on one side of the black phosphorus nanosheet, and a drain electrode is formed on the upper surface of the black phosphorus nanosheet in the region on one side of the palladium diselenide nanosheet. (e) A top insulating layer is applied to the upper surfaces of the source electrode, palladium diselenide nanosheets, black phosphorus nanosheets, and drain electrode.

9. The method according to claim 8, characterized in that, The carrier used in the dry transfer process consists of a PPC membrane and a PDMS substrate.

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