Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a semiconductor device on the substrate, a first doped well and a second doped well in the substrate, wherein the first doped well and the second doped well are of different doping types, a sealing ring on the substrate and coupled with the first doped well and the second doped well, wherein the sealing ring surrounds the semiconductor device, and a pad coupled with the sealing ring and located at an end of the sealing ring away from the substrate.

Description

[0001] This application is a divisional application of Chinese patent application filed on May 16, 2022, with application number 202210530598.X and entitled "Semiconductor Structure and Method of Fabrication Thereof". Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0003] In the semiconductor chip manufacturing process, multiple chips are typically integrated onto a single wafer and manufactured simultaneously. Afterward, the chips are diced from the wafer, packaged, and used in integrated circuits.

[0004] In semiconductor chip placement design, a sealing ring (SR, also known as an isolation ring) is typically placed around the semiconductor device. The sealing ring reduces mechanical damage from the dicing process and moisture intrusion, and also reduces damage to the internal circuitry of the semiconductor device from electrostatic discharge. Therefore, how to form a high-quality sealing ring is a problem that urgently needs to be solved. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for fabricating the same.

[0006] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: Base; Semiconductor devices are located on the substrate; A first doped well and a second doped well are located in the substrate; wherein the first doped well and the second doped well have different doping types; A sealing ring, located on the substrate, is coupled to the first doped well and the second doped well; wherein the sealing ring surrounds the semiconductor device; The pad, coupled to the sealing ring, is located at the end of the sealing ring that is relatively far from the substrate.

[0007] According to a second aspect of the present disclosure, a storage system is provided, comprising: A memory, including the aforementioned semiconductor structure; A memory controller, coupled to the memory and configured to control the memory.

[0008] According to a third aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, the method comprising: Provide a base; A first doped well and a second doped well are formed in the substrate; wherein the first doped well and the second doped well have different doping types; A semiconductor device is formed on the substrate; A sealing ring is formed on the substrate; wherein the sealing ring is coupled to the first doped well and the second doped well, and surrounds the semiconductor device; A pad coupled to the sealing ring is formed at one end of the sealing ring that is relatively far from the substrate.

[0009] The pads can be electrically connected to the doped wells in the substrate via a sealing ring. If the doped well is a p-type doped well, during the formation of the pad, the holes in the p-type doped well attract electrons, promoting the loss of electrons and oxidation into ions during processes such as chemical mechanical polishing or cleaning, resulting in a collapse defect on the pad surface. If the doped well is an n-type doped well, the free electrons in the n-type doped well are released to the vicinity of the pad through the sealing ring, inhibiting the electron loss and oxidation process of the pad, thus reducing the amount of material removed from the pad surface and causing a raised defect on the pad surface.

[0010] In this embodiment, a first doped well and a second doped well are disposed in the substrate, and the first and second doped wells have different doping types. A sealing ring is coupled to the first and second doped wells. During the formation of the pad, compared to a pad formed only with a doped well of one doping type, the holes and free electrons between the first and second doped wells of this disclosure attract each other to form a balanced state. This can reduce the promoting effect of holes in the first or second doped well on the oxidation process of the pad, or reduce the inhibiting effect of free electrons on the oxidation process of the pad. This reduces the probability of surface collapse or surface protrusion defects in the pad during processes such as planarization or cleaning, thereby improving the yield of the semiconductor structure. Attached Figure Description

[0011] Figure 1 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment; Figure 2a This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment; Figure 2b This is an electron microscope image of a semiconductor structure according to an exemplary embodiment; Figure 2c This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment; Figures 3a to 3e This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure; Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure; Figure 5 This is a system block diagram including a memory according to an embodiment of the present disclosure; Figure 6a This is a schematic diagram illustrating a memory card including a memory according to an embodiment of the present disclosure; Figure 6b This is a schematic diagram illustrating a solid-state drive (SSD) including memory according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram illustrating a memory including peripheral circuitry according to an embodiment of the present disclosure; Figure 8 This is a block diagram of a memory including peripheral circuitry according to an embodiment of the present disclosure; Figure 9 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figures 10a to 10e This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figures 11a to 11b This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0012] The technical solution of this disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] In this disclosure, the terms "first," "second," etc., are used to distinguish similar objects, and not to describe a specific order or sequence.

[0014] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces. Furthermore, a layer may comprise multiple sublayers.

[0015] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0016] It should be noted that although this specification describes the embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0017] Figure 1 This is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment. (Refer to...) Figure 1 As shown, the semiconductor structure 100 includes: Substrate 101; Semiconductor device 102 is located on substrate 101; A doped well 103 is located in the substrate 101; A sealing ring 104 is located on the substrate 101 and coupled to the doped well 103; wherein the sealing ring 104 surrounds the semiconductor device 102; Pad 105 is coupled to sealing ring 104 and is located at the end of sealing ring 104 that is relatively far away from substrate 101.

[0018] For example, the constituent materials of the substrate 101 may include: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

[0019] It should be emphasized that the substrate 101 in this embodiment is a film layer structure with a certain thickness, which may include a bare wafer or an epitaxial layer. For example, the substrate 101 is a bare wafer that has not undergone processes such as coating or etching (e.g., a bare silicon wafer). Alternatively, the substrate 101 is an epitaxial layer grown on the surface of a bare wafer. The material of the epitaxial layer may be the same as or different from the material of the bare wafer, and the bare wafer may be removed in a certain fabrication process.

[0020] In the semiconductor chip manufacturing process, multiple semiconductor structures are integrated onto a single wafer. After fabrication, the wafer is diced to obtain the semiconductor chip, which is then packaged and used in integrated circuits. During semiconductor chip manufacturing, processes such as dicing, plasma etching, ion implantation, and plasma activation can accumulate large amounts of static charge at the semiconductor device, causing discharge that may damage the device and reduce its yield.

[0021] Therefore, during chip design, a sealing ring 104 is usually designed to surround the semiconductor device 102 to reduce mechanical damage and moisture intrusion to the semiconductor device 102 during the dicing process, shield external electromagnetic interference, and reduce damage to the device from electrostatic discharge.

[0022] The sealing ring 104 is coupled to the doped well 103 in the substrate 101, and the doped well 103 is grounded to ground the sealing ring 104. The grounded sealing ring 104 can better release static charge and reduce the damage of static charge discharge to the semiconductor device 102.

[0023] For example, the doped well 103 may include a p-type doped well or an n-type doped well. It should be emphasized that the doping type of a doped well 103 is only one type.

[0024] For example, the constituent materials of a p-type doped well include p-type semiconductor materials. In a p-type doped well, the hole concentration is much greater than the free electron concentration; holes are the majority carriers, and free electrons are the minority carriers; conductivity is mainly achieved through holes.

[0025] For example, the constituent materials of an n-type doped well include n-type semiconductor materials. In an n-type doped well, the concentration of free electrons is much greater than the concentration of holes; free electrons are the majority carriers, and holes are the minority carriers. Conductivity is mainly achieved by free electrons.

[0026] For example, the materials used to compose the pads 105 and the sealing ring 104 include, but are not limited to, conductive materials such as copper, aluminum, nickel, tungsten, silver, gold, and titanium. The pads 105 can be used for bonding and / or coupling with other semiconductor structures or semiconductor devices.

[0027] During the fabrication of pad 105, processes such as chemical mechanical polishing (CMP) and cleaning are performed. During these processes (e.g., cleaning with deionized water), the surface of pad 105 is oxidized by a chemical solution to achieve surface planarization. However, in actual fabrication, surface collapse or protrusion of pad 105 may occur, reducing the bonding and / or coupling performance of pad 105 and decreasing the stability of semiconductor device 102. Details are described below.

[0028] When the sealing ring 104 is coupled to the p-type doped well, the pad 105 is coupled to the p-type doped well through the sealing ring 104. During chemical mechanical polishing, cleaning, or other processes on the pad 105, holes in the p-type doped well attract electrons to the pad 105 through the sealing ring 104, promoting the electron loss oxidation process of the pad 105. This results in excessive corrosion of the pad 105, causing issues such as… Figure 2a The surface of pad 105 shown is collapsed, which is a defect.

[0029] Specifically, Figure 2b The image shown is an electron microscope (EM) schematic of the surface of pad 105 after chemical mechanical polishing, when the sealing ring 104 is coupled to the p-type doped well. (Refer to...) Figure 2bAs shown in the figure, the surface height of pad 105 is represented by different gray values; the darker the gray value, the lower the surface height of pad 105. The area shown in the dashed box in the figure is the area of ​​pad 105 coupled to sealing ring 104. The surface height of pad 105 in this area is lower than that of pad 105 in other areas, indicating that the pad 105 coupled to the p-type doped well has surface collapse defects after chemical mechanical polishing.

[0030] When the sealing ring 104 is coupled to the n-type doped well, the pad 105 is coupled to the n-type doped well through the sealing ring 104. During chemical mechanical polishing and cleaning processes on the pad 105, free electrons in the n-type doped well are released through the sealing ring 104 to the vicinity of the pad 105, suppressing the electron loss oxidation process of the pad 105. This results in insufficient removal of electrons from the surface of the pad 105, causing... Figure 2c The surface of pad 105 shown has a raised defect.

[0031] Figure 3a This is a schematic diagram illustrating a semiconductor structure according to an embodiment of the present disclosure. (Refer to...) Figure 3a As shown, the semiconductor structure 200 includes: 210 substrate; Semiconductor device 220 is located on substrate 210; The first doped well 231 and the second doped well 232 are located in the substrate 210; wherein the first doped well 231 and the second doped well 232 have different doping types; A sealing ring 240 is located on the substrate 210 and coupled to the first doped well 231 and the second doped well 232; wherein, the sealing ring 240 surrounds the semiconductor device 220; The pad 250 is coupled to the sealing ring 240 and is located at the end of the sealing ring 240 that is relatively far away from the substrate 210.

[0032] Specifically, refer to Figure 3b As shown, in the semiconductor structure 200, the sealing ring 240 includes a continuous wall structure surrounding the semiconductor device 220, and there is a certain distance between the sealing ring 240 and the semiconductor device 220 to reduce mechanical damage to the semiconductor device 220 caused by the cutting process and to prevent moisture from entering the semiconductor device 220. Figure 3b The diagram shows two semiconductor devices 220 for illustrative purposes. This disclosure does not limit the number of semiconductor devices 220; for example, it may include three, four, or more semiconductor devices 220. The semiconductor devices 220 may include memory arrays and / or CMOS control circuitry, etc.

[0033] It needs to be emphasized that, in combination Figure 3bAs shown, in this embodiment, the sealing ring 240 surrounds the semiconductor device 220, which means surrounding the side of the semiconductor device 220 and does not involve covering the top surface of the semiconductor device 220. The sealing ring 240 may not be in direct contact with the semiconductor device 220.

[0034] Reference Figure 3a As shown, in the z-direction perpendicular to the substrate 210, a sealing ring 240 is disposed above the substrate 210, and a first doped well 231 and a second doped well 232 are disposed in the substrate 210. The sealing ring 240 is coupled to the first doped well 231 and the second doped well 232. The first doped well 231 and the second doped well 232 have different doping types. For example, the first doped well 231 is a p-type doped well, and the second doped well 232 is an n-type doped well. Alternatively, the first doped well 231 is an n-type doped well, and the second doped well 232 is a p-type doped well. The holes in the p-type doped well and the free electrons in the n-type doped well attract each other to reach a state of equilibrium, reducing the influence of holes or free electrons on the pad 250 and reducing the probability of defects such as surface collapse or surface protrusion of the pad 250.

[0035] The semiconductor structure 200 also includes a first dielectric layer 234, which is located on the substrate 210 and covers the semiconductor device 220. A sealing ring 240 is disposed in the first dielectric layer 234. The first dielectric layer 234 protects the semiconductor device 220 and reduces damage to it. The first dielectric layer 234 electrically isolates the semiconductor device 220 and the sealing ring 240, reducing interference from the charge in the sealing ring 240 to the semiconductor device 220 and maintaining good performance of the semiconductor device 220.

[0036] The top surface of the pad 250 can be exposed from the first dielectric layer 234, which facilitates the coupling of the pad 250 with other semiconductor devices.

[0037] It is understood that the coupling in this embodiment may include direct contact between two components (the sealing ring 240 and the first doped well 231, and the sealing ring 240 and the second doped well 232) to form a coupling. Alternatively, the coupling method may also include providing a conductive structure (e.g., a conductive wire, a conductive layer, or a conductive plug), which directly contacts the two components to complete the coupling.

[0038] In some embodiments, refer to Figure 3aAs shown, in the z-direction, a first conductive plug 260a can be disposed between the sealing ring 240 and the first doped well 231, and a second conductive plug 260b can be disposed between the sealing ring 240 and the second doped well 232. The conductive plug 260a is in direct contact with the first doped well 231 and the sealing ring 240 to form a coupling, and the conductive plug 260b is in direct contact with the second doped well 232 and the sealing ring 240 to form a coupling.

[0039] In some embodiments, refer to Figure 3c As shown, the sealing ring 240 is in direct contact with the first doped well 231 and the second doped well 232.

[0040] In the z-direction, the sealing ring 240 is disposed on the first doped well 231 and the second doped well 232, and is in direct contact with the first doped well 231 and the second doped well 232 respectively to form a coupling.

[0041] In some other embodiments, in addition to Figure 3a As shown, the sealing ring 240 couples the first doped well 231 and the second doped well 232. The first doped well 231 and the second doped well 232 can also be coupled through direct contact or by providing a conductive structure. It is important to emphasize that when a conductive structure is provided between the first doped well 231 and the second doped well 232 for coupling, this conductive structure may not directly contact the sealing ring 240, but may directly contact either the first doped well 231 or the second doped well 232 to form a coupling.

[0042] In some embodiments, refer to Figure 3d As shown, the semiconductor structure 200 also includes: The conductive part 233 is located between the first doped well 231 and the second doped well 232, and is in direct contact with the first doped well 231 and the second doped well 232; the sealing ring 240 is in direct contact with the conductive part 233.

[0043] Specifically, refer to Figure 3d As shown, a conductive part 233 is provided between the first doped well 231 and the second doped well. The conductive part 233 is in direct contact with the first doped well 231 and the second doped well 232 respectively, realizing the coupling between the first doped well 231 and the second doped well 232. The sealing ring 240 is in direct contact with the conductive line 233, thereby realizing the coupling between the sealing ring 240 and the first doped well 231 and the second doped well 232 through the conductive part 233.

[0044] like Figure 3dAs shown, the conductive portion 233 can be disposed in the substrate 210 and directly contact the side surfaces of the first doped well 231 and the second doped well 232, respectively. In some other embodiments, the conductive portion 233 can also be disposed on the substrate 210 and directly contact the upper surfaces of the first doped well 231 and the second doped well 232, respectively.

[0045] For example, the conductive part 233 may include: a conductive wire or a conductive block. The constituent materials of the conductive part 233 include, but are not limited to: conductive materials such as copper, aluminum, nickel, tungsten, silver, gold or titanium.

[0046] In some embodiments, refer to Figure 3a and Figure 3e As shown, the semiconductor structure 200 also includes: The conductive plug 260 is located above the first doped well 231 and the second doped well 232 and below the sealing ring 240 in a direction perpendicular to the substrate 210; the conductive plug 260 is coupled to the first doped well 231, the second doped well 232 and the sealing ring 240.

[0047] For example, the conductive plug 260 is composed of conductive materials including but not limited to: copper, aluminum, nickel, tungsten, silver, gold, titanium and other conductive materials.

[0048] In the z-direction, a first conductive plug 260a may be disposed between the sealing ring 240 and the first doped well 231, and a second conductive plug 260b may be disposed between the sealing ring 240 and the second doped well 232. The conductive plug 260a is in direct contact with the first doped well 231 and the sealing ring 240 to form a coupling, and the conductive plug 260b is in direct contact with the second doped well 232 and the sealing ring 240 to form a coupling.

[0049] In some embodiments, the conductive plug 260 can be a conductive post, and multiple conductive posts can be arranged at intervals, similar to... Figure 3b The arrangement of the pads 250. In some other embodiments, the conductive plugs 260 may also be a continuous conductive layer, along a path perpendicular to... Figure 3e Extending in the direction of the xoz plane.

[0050] The sealing ring 240 can be a single, integrally formed structure or it can comprise multiple stacked substructures.

[0051] In some embodiments, refer to Figure 3a , Figure 3c and Figure 3d As shown, the sealing ring 240 may include at least two interconnecting layers that are stacked and in contact with each other, for example... Figure 3aAs an example, the sealing ring 240 may include interconnect layers 241, 242, and 243 stacked sequentially. In this embodiment, the sealing ring 240 can be formed simultaneously with the metal wiring layer, which is used for electrical signal transmission in the semiconductor device 220, while the sealing ring 240 does not participate in the electrical signal transmission of the semiconductor device 220. The sealing ring 240 and the metal wiring layer can share a single photomask, allowing for a single photolithography process to complete the photolithography and development of both the sealing ring 240 and the metal wiring layer, thus reducing manufacturing costs.

[0052] In other embodiments, a conductive structure perpendicular to the interconnect layer is provided between two adjacent, stacked interconnect layers for coupling the two adjacent interconnect layers. Exemplarily, the conductive structure may include a columnar or elongated contact plug.

[0053] Reference Figure 3a As shown, in the direction perpendicular to the substrate 210, the height of the sealing ring 240 is greater than or equal to the height of the semiconductor device 220, so as to provide sufficient protection for the semiconductor device 220, reduce mechanical damage to the semiconductor device 220 caused by the cutting process, and reduce the intrusion of moisture into the semiconductor device 220 after cutting. The heights of the sealing ring 240 and the semiconductor device 220 are relative to the upper surface of the substrate 210, and will not be elaborated further below.

[0054] When the height of the semiconductor device 220 is large, the height of the sealing ring 240 also increases. Compared to a sealing ring 240 with a smaller height, the process time required to continuously deposit to form a sealing ring 240 with a larger height is longer, which can easily lead to uneven deposition, increase the probability of void defects in the sealing ring 240, and reduce the protective performance of the sealing ring 240 for the semiconductor device 220. Therefore, in order to form a sealing ring 240 with a larger height, a step-by-step deposition method can be adopted, forming an interconnect layer with a smaller height in each step. This reduces the probability of void defects, improves the quality of the sealing ring 240, and thus improves the isolation and protection effect of the sealing ring 240 on the semiconductor device 220 during the dicing process, thereby improving the yield of the semiconductor device 220.

[0055] In some embodiments, refer to Figure 3e As shown, when the height of the semiconductor device 220 is small, the height of the sealing ring 240 can also be reduced accordingly. The integrally formed sealing ring 240 can reduce the number of process steps and reduce the manufacturing cost while ensuring the protection of the semiconductor device 220.

[0056] Reference Figure 3a , Figures 3c to 3eAs shown, in the z-direction, the pad 250 is located above the sealing ring 240 and coupled to the sealing ring 240 for bonding and / or coupling with other semiconductor structures or semiconductor devices. The pad 250 can directly contact the upper part of the sealing ring 240 to form coupling. Alternatively, a conductive structure can be provided between the pad 250 and the sealing ring 240, contacting both the pad 250 and the sealing ring 240 respectively, to achieve coupling between the pad 250 and the sealing ring 240.

[0057] Combination Figure 3b As shown, multiple pads 250 can be provided on the upper part of the sealing ring 240. This disclosure does not limit the number or arrangement of the pads 250.

[0058] For example, the materials used to make pad 250 include, but are not limited to, conductive materials such as copper, aluminum, nickel, tungsten, silver, gold, or titanium.

[0059] Compared to setting only one p-type doped well or one n-type doped well coupled to the sealing ring 240, in this embodiment, the holes and free electrons in the first doped well 231 and the second doped well 232 attract each other to achieve balance. This can reduce the promoting effect of holes in the first doped well 231 and the second doped well 232 on the oxidation process of the pad 250, or reduce the inhibiting effect of free electrons on the oxidation process of the pad 250. This reduces the probability of defects such as surface collapse or surface protrusion of the pad 250 during processes such as planarization and cleaning, thereby improving the yield of the semiconductor structure.

[0060] In some embodiments, the doping concentration of the first doped well 231 is substantially equal to the doping concentration of the second doped well 232.

[0061] The carrier concentration in the doped well can be determined by the doping concentration of the doped well. A higher doping concentration in the doped well results in a higher hole concentration or free electron concentration, and thus better conductivity. In this embodiment, essentially equal doping concentrations can include: two doping concentrations being completely equal; or, although the two doping concentrations differ, the difference is small or even negligible, and the difference in surface defects on the pads caused by this difference is also negligible, still achieving the effect of reducing the probability of defects such as collapse or protrusion on the pad surface. The difference in doping concentration between the first doped well 231 and the second doped well 232 can be a measurement error introduced by the concentration measurement process.

[0062] The doping type of the first doped well 231 is opposite to that of the second doped well 232. Taking the first doped well 231 as a p-type doped well and the second doped well 232 as an n-type doped well as an example, this embodiment will be explained.

[0063] The doping concentrations of the first doped well 231 (p-type doped well) and the second doped well 232 (n-type doped well) are basically equal, which makes the hole concentration in the first doped well 231 and the free electron concentration in the second doped well 232 basically equal, which is conducive to achieving a more stable equilibrium state between holes and electrons.

[0064] Specifically, refer to Figure 3a As shown, the first doped well 231 and the second doped well 232 are coupled by a sealing ring 240. Holes and free electrons with basically the same concentration attract each other and reach a more stable equilibrium state, reducing the probability of defects such as surface collapse or surface protrusion of the pad 250.

[0065] In some embodiments, the doping type of the first doped well 231 includes n-type doping, and the doping type of the second doped well 232 includes p-type doping. or, The first doped well 231 has p-type doping, and the second doped well 232 has n-type doping.

[0066] For example, the constituent materials of the first doped well 231 and the second doped well 232 include semiconductor materials, including but not limited to: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. Semiconductor materials, through doping with different elements, constitute different types of semiconductor materials, such as p-type semiconductor materials and n-type semiconductor materials.

[0067] In p-type semiconductor materials (hole-type semiconductor materials), the hole concentration is much greater than the free electron concentration. This can be achieved by doping a pure intrinsic semiconductor with a trivalent element (e.g., boron doping silicon). In p-type semiconductor materials, holes are the majority carriers, and free electrons are the minority carriers; conductivity is primarily achieved through holes acting as charge carriers.

[0068] In n-type semiconductor materials (electronic semiconductor materials), the concentration of free electrons is much greater than the concentration of holes. This can be achieved by doping a pure intrinsic semiconductor with pentavalent elements (e.g., phosphorus doping silicon). In n-type semiconductor materials, free electrons are the majority carriers, and holes are the minority carriers. Conductivity is primarily achieved by free electrons as the charge carriers.

[0069] The first doped well 231 and the second doped well 232 have different doping types. The holes and electrons in the first doped well 231 and the second doped well 232 attract each other to reach a balance, reducing the probability of defects such as surface collapse or surface protrusion of the pad 250.

[0070] In some embodiments, the first doped well 231 and / or the second doped well 232 are grounded.

[0071] The sealing ring 240 is grounded through the first doped well 231 and / or the second doped well 232 to release static charge and reduce damage to the semiconductor device 220 caused by static charge discharge. (Refer to...) Figure 3a As shown, since the sealing ring 240 is coupled to both the first doped well 231 and the second doped well 232, grounding at least one of the first doped well 231 and the second doped well 232 will ground the sealing ring 240. Specifically, one of the first doped well 231 and the second doped well 232 can be grounded, or both the first doped well 231 and the second doped well 232 can be grounded.

[0072] In some embodiments, the substrate 210 includes a doped substrate 210, wherein the doping type of the substrate 210 is the same as the doping type of the first doped well 231. or, The doping type of the substrate 210 is the same as that of the second doped well 232.

[0073] In some embodiments, the substrate 210 merely provides support for the semiconductor structure 200 and does not require doping. In this embodiment, in addition to providing support for the semiconductor structure 200, the substrate 210 can also serve as a grounding device, providing zero potential for the semiconductor device 220. By doping the substrate 210, the carrier concentration in the substrate 210 can be increased, thereby improving the conductivity of the substrate 210.

[0074] Reference Figure 3a As shown, the doping type of the substrate 210 is the same as that of the first doped well 231 or the second doped well 232, which allows the substrate 210 to be coupled to one of the first doped well 231 or the second doped well 232. This allows the sealing ring 240 to be directly grounded through the substrate 210 without the need for additional grounding wires to couple with the sealing ring 240, the first doped well 231 or the second doped well 232, thus reducing manufacturing costs.

[0075] In some embodiments, refer to Figure 4 As shown, semiconductor device 220 includes a CMOS control circuit.

[0076] CMOS control circuits can be used in memory to control the reading, writing, or erasing operations of the memory cells. Memory can include NAND flash memory (3D NAND flash memory), DRAM memory, or phase-change memory, etc.

[0077] In some embodiments, refer to Figure 4 As shown, the semiconductor structure 200 also includes: A memory array is bonded to a semiconductor device 220, wherein the semiconductor device 220 is located between the memory array and the substrate 210.

[0078] The semiconductor structure 200 may include: a three-dimensional memory or a portion thereof.

[0079] Specifically, refer to Figure 4 As shown, in the z-direction, the memory array is located on the semiconductor layer 310. The memory array includes a gate layer 312 and an insulating layer 311 stacked on top of each other. The gate layer 312 serves as the word line of the three-dimensional NAND memory.

[0080] For example, the gate layer 312 may be composed of conductive materials such as tungsten, gold, silver, copper, aluminum, or nickel. The insulating layer 311 may be composed of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0081] The memory array also includes a channel pillar 320 extending through the gate layer 312 and the insulating layer 311. The channel pillar 320 includes a channel layer and a functional layer surrounding the channel layer. Along the radial direction of the channel pillar 320, the functional layer includes a barrier sublayer, a storage sublayer, and a tunneling sublayer. The barrier sublayer may include silicon oxide, silicon oxynitride, a high-dielectric material, or any combination thereof. The storage sublayer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling sublayer may include silicon oxide, silicon oxynitride, or any combination thereof. In embodiments of this disclosure, the combination of functional layers may include a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0082] The semiconductor structure also includes a plurality of second conductive plugs 331 coupled to the gate layer 312. The second conductive plugs 331 are located at the ends of the gate layer 312 and can be bonded to a plurality of first conductive plugs 271 in a one-to-one correspondence. The plurality of first conductive plugs 271 are located above the second conductive plugs 331 and can be coupled to the semiconductor device 220 via a substrate 210 or other conductive structures (not shown). A plurality of third conductive plugs 332 are located between the semiconductor device and the channel pillar 320, coupling the channel layer of the channel pillar 320 and the semiconductor device. The semiconductor device 220 may include... Figure 4 The CMOS circuit shown in the dashed box.

[0083] In some embodiments, continue to refer to Figure 4 As shown, the semiconductor structure 200 also includes a sealing ring 330 located on the semiconductor layer 310 and a pad 340 coupled to the sealing ring 330. A first doped well 231 and a second doped well 232 are located in the substrate 210, a sealing ring 240 is coupled to the first doped well 231 and the second doped well 232, and a pad 250 is located at the end of the sealing ring 240 away from the substrate 210 and coupled to the sealing ring 240.

[0084] In some embodiments, refer to Figure 4 As shown, in the z-direction, pads 250 and 340 can be bonded to each other, achieving coupling between the two sealing rings. Static charge is released through the first doped well 231 and the second doped well 232, reducing damage to the semiconductor structure 200 caused by static charge accumulation. Sealing rings 240 and 340 can provide mutual support, enhancing the support for the semiconductor structure 200.

[0085] For example, the constituent materials of the semiconductor layer 310 include, but are not limited to: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

[0086] Continue to refer to Figure 4 As shown, the memory array and the semiconductor device can be bonded together via multiple third conductive plugs 332 to achieve electrical signal interconnection. The memory array can also be bonded together with multiple first conductive plugs 271 via multiple second conductive plugs 331. The multiple first conductive plugs 271 can be coupled to the semiconductor device via a substrate 210 or other conductive structures (not shown in the figure) to achieve electrical signal interconnection between the memory array and the semiconductor device 220.

[0087] Figure 5 This is a block diagram of a system 500 including a memory, according to an embodiment of the present disclosure.

[0088] Reference Figure 5 As shown, a storage system 502 includes: The memory 504 includes the semiconductor structure 200 in the above embodiments; Memory controller 506 is coupled to memory 504 and configured to control memory 504.

[0089] Specifically, system 500 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0090] like Figure 5As shown, system 500 may include host 508 and storage system 502, storage system 502 having one or more memories 504 and memory controller 506. Host 508 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 508 may be configured to send data to memory 504 or receive data from memory 504.

[0091] Memory 504 may include the semiconductor structure 200 of this disclosure, which may include a three-dimensional memory or a portion thereof, for example, Figure 4 The memory array and semiconductor device 220 (CMOS control circuitry) are shown. As detailed below, the memory 504 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0092] In some embodiments, memory controller 506 is coupled to memory 504 and host 508 and is configured to control memory 504. Memory controller 506 can manage data stored in memory 504 and communicate with host 508.

[0093] In some embodiments, the memory controller 506 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0094] In some embodiments, the memory controller 506 is designed to operate in a high duty cycle environment within an SSD or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise memory arrays. The memory controller 506 can be configured to control the operation of the memory 504, such as read, erase, and program operations. The memory controller 506 can also be configured to manage various functions relating to data stored or to be stored in the memory 504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0095] In some embodiments, memory controller 506 is also configured to process error correction codes (ECC) regarding data read from or written to memory 504. Memory controller 506 may also perform any other suitable functions, such as formatting memory 504. Memory controller 506 may communicate with external devices (e.g., host 508) according to specific communication protocols. For example, memory controller 506 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0096] The memory controller 506 and one or more memories 504 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 502 can be implemented and packaged into different types of end electronic products.

[0097] Reference Figure 6a As shown, in some embodiments, the memory controller 506 and a single memory 504 may be integrated into the memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 602 may also include a connection between the memory card 602 and a host computer (e.g., Figure 5 The memory card connector 604 is coupled to the host 508.

[0098] Reference Figure 6b As shown, in some embodiments, the memory controller 506 and multiple memories 504 may be integrated into the SSD 606. The SSD 606 may also include components for connecting the SSD 606 to a host computer (e.g., Figure 5 The host 508 in the SSD is coupled to the SSD connector 608.

[0099] In some embodiments, the storage capacity and / or operating speed of the SSD 606 may be greater than the storage capacity and / or operating speed of the memory card 602.

[0100] Figure 7This is a schematic circuit diagram of a memory 700 including peripheral circuitry according to an embodiment of the present disclosure. The memory 700 may be... Figure 5 Example of memory 504 in [the memory module]. See [reference]. Figure 7 As shown, the memory 700 may include a memory array 701 and peripheral circuitry 702 coupled to the memory array 701. The memory array 701 may be a NAND flash memory array, wherein memory cells 706 are provided in the form of an array of NAND memory strings 708, each NAND memory string 708 extending vertically above a substrate (not shown). Figure 7 The circuit diagram of the memory array 701 shown can be Figure 4 The circuit diagram of the memory array is shown in the figure.

[0101] In some embodiments, each NAND memory string 708 includes a plurality of memory cells 706 that are series-coupled and vertically stacked. Each memory cell 706 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 706. Each memory cell 706 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0102] Combination Figure 4 As shown, Figure 7 The storage string 708 in the memory may include Figure 4 Any channel post 320 that penetrates the gate layer 312 and the insulating layer 311.

[0103] A memory cell 706 may include, in the X direction, a portion of the channel layer and a portion of the functional layer of a channel pillar 320 corresponding to a gate layer 312. Gate layer 312 (i.e....) Figure 7 The number of layers (word lines 718) determines the number of storage units 706.

[0104] In some embodiments, each memory cell 706 is a single-level cell (SLC) having two possible memory states and thus being able to store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range.

[0105] In some embodiments, each memory cell 706 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to that cell. A fourth nominal storage value can be used for the erase state.

[0106] Reference Figure 7 As shown, each NAND memory string 708 may include a source select gate (SSG) 710 at its source end and a drain select gate (DSG) 712 at its drain end. The SSG 710 and DSG 712 may be configured to activate the selected NAND memory string 708 (column of the memory array) during read and program operations.

[0107] In some embodiments, the sources of NAND memory strings 708 in the same block 704 are coupled through the same source line (SL) 714 (e.g., common SL). All NAND memory strings 708 in the same block 704 may have an array common source (ACS).

[0108] In some embodiments, the DSG 712 of each NAND storage string 708 is coupled to a corresponding bit line 716, and data can be read from or written to the bit line 716 via an output bus (not shown).

[0109] In some embodiments, each NAND memory string 708 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 712) or a deselection voltage (e.g., 0V) to the corresponding DSG 712 via one or more DSG lines 713 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 710) or a deselection voltage (e.g., 0V) to the corresponding SSG 710 via one or more SSG lines 715.

[0110] Reference Figure 7 As shown, the NAND storage string 708 can be organized into multiple blocks 704, each of the multiple blocks 704 can have a common source line 714 (e.g., coupled to ground).

[0111] In some embodiments, each block 704 can be a basic data unit for an erase operation, that is, all memory cells 706 on the same block 704 can be erased simultaneously. To erase memory cells 706 in a selected block 704a, a source line 714 biased to the selected block 704a and an unselected block 704b on the same plane as the selected block 704a can be used.

[0112] Understandably, erase operations can be performed at the half-block level, the quarter-block level, or at any suitable fraction of a block with any suitable number of blocks. Memory cells 706 of adjacent NAND memory strings 708 can be coupled via word lines 718, which select which row of memory cells 706 is affected by read and program operations.

[0113] In some embodiments, each word line 718 is coupled to a page 720 of a memory cell 706, and the page 720 may be a basic data unit for programming operations. The size of a page 720, in bits, may be related to the number of NAND memory strings 708 coupled by word lines 718 in a block 704. Each word line 718 may include multiple control gates (gate electrodes) at each memory cell 706 in the corresponding page 720 and gate lines coupling the control gates.

[0114] Continue to refer to Figure 7 As shown, peripheral circuitry 702 can be coupled to memory array 701 via bit line 716, word line 718, source line 714, SSG line 715, and DSG line 713. Peripheral circuitry 702 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 701 by applying voltage and / or current signals to each target memory cell 706 via bit line 716, word line 718, source line 714, SSG line 715, and DSG line 713, and sensing voltage and / or current signals from each target memory cell 706. Peripheral circuitry 702 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, peripheral circuitry 702 may include… Figure 4 The CMOS control circuit (i.e., semiconductor device 220) shown is illustrated.

[0115] For example, Figure 8 Some exemplary peripheral circuitry is shown. Peripheral circuitry 702 may include a page buffer / sensor amplifier 804, a column decoder / bit line driver 806, a row decoder / word line driver 808, a voltage generator 810, a control logic unit 812, a register 814, an interface 816, and a data bus 818. It will be understood that in some embodiments, additional components may be included. Figure 8Additional peripheral circuitry not shown.

[0116] Combination Figure 7 and Figure 8 As shown, the page buffer / sensor amplifier 804 can be configured to read data from the memory array 701 and program (write) data to the memory array 701 according to control signals from the control logic unit 812.

[0117] In some embodiments, the page buffer / sensor amplifier 804 may store a page of programming data (write data) to be programmed into a page 720 of the memory array 701. In other embodiments, the page buffer / sensor amplifier 804 may perform a programming verification operation to ensure that data has been correctly programmed into the memory cell 706 coupled to the selected word line 718. In still other embodiments, the page buffer / sensor amplifier 804 may also sense a low-power signal from the bit line 716 representing a data bit stored in the memory cell 706 and amplify a small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 806 may be configured to be controlled by the control logic unit 812 and to select one or more NAND memory strings 708 by applying a bit line voltage generated from the voltage generator 810.

[0118] The line decoder / word line driver 808 can be configured to be controlled by the control logic unit 812 and to select / deselect block 704 of the memory array 701 and select / deselect word line 718 of block 704. The line decoder / word line driver 808 can also be configured to drive word line 718 using word line voltage generated from voltage generator 810.

[0119] In some embodiments, the row decoder / word line driver 808 may also select / deselect and drive SSG line 715 and DSG line 713. As described in detail below, the row decoder / word line driver 808 is configured to perform an erase operation on memory cell 706 coupled to one or more selected word lines 718. Voltage generator 810 may be configured to be controlled by control logic unit 812 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 701.

[0120] Control logic unit 812 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 814 can be coupled to control logic unit 812 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 816 can be coupled to control logic unit 812 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 812, as well as to buffer status information received from control logic unit 812 and relay it to the host. Interface 816 can also be coupled to column decoder / bit line driver 806 via data bus 818 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 701.

[0121] Figure 9 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Figures 10a to 10d This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. (In conjunction with...) Figure 9 , Figures 10a to 10d as well as Figure 3a As shown, the manufacturing method includes: Reference Figure 10a As shown, S100: provides substrate 210; Reference Figure 10b and Figure 10c As shown, S200: A first doped well 231 and a second doped well 232 are formed in the substrate 210; wherein the doping types of the first doped well 231 and the second doped well 232 are different; S300: A semiconductor device 220 is formed on the substrate 210; Reference Figure 10d As shown, S400: A sealing ring 240 is formed on the substrate 210; wherein the sealing ring 240 is coupled to the first doped well 231 and the second doped well 232, and surrounds the semiconductor device 220. Reference Figure 3a As shown, S500: A pad 250 is formed at the end of the sealing ring 240 that is relatively far from the substrate 210, and is coupled to the sealing ring 240.

[0122] The substrate 210 in S100 is a film structure with a certain thickness, which may include a bare wafer or an epitaxial layer. Therefore, the fabrication method may include providing a bare wafer that has not undergone deposition, photolithography, or etching processes. The fabrication method may further include providing the bare wafer, performing an epitaxial growth or deposition process on the surface of the bare wafer to form an epitaxial layer covering the surface of the bare wafer, and then removing the bare wafer, using the epitaxial layer as a substrate. Figure 10a The substrate 210 is shown. The bare wafer removal step can be performed after any of steps S100 to S500, and this disclosure does not limit the process sequence of bare wafer removal.

[0123] It should be emphasized that the order of S300 and S200 can be interchanged. Therefore, the fabrication method includes: providing a substrate 210, forming a semiconductor device 220 on the substrate 210, and then forming a first doped well 231 and a second doped well 232 in the substrate 210, wherein the first doped well 231 and the second doped well 232 have different doping types. The semiconductor device 220 may include a memory array and / or CMOS control circuitry, etc.

[0124] For example, the materials used to make the pads 250 and the sealing ring 240 include, but are not limited to, conductive materials such as copper, aluminum, nickel, tungsten, silver, gold, and titanium.

[0125] For example, the processes for forming the sealing ring 240 and the pad 250 include, but are not limited to, physical vapor deposition, chemical vapor deposition or electroplating processes.

[0126] For example, refer to Figure 10d As shown, a first dielectric layer 234 can be deposited on the substrate 210, an annular first trench surrounding the semiconductor device 220 can be etched, and the first trench can be filled with a conductive material to form a sealing ring 240. In the direction perpendicular to the substrate 210, the height of the sealing ring 240 is greater than or equal to the height of the semiconductor device 220. The first dielectric layer 234 can cover the semiconductor device 220 to provide protection for the semiconductor device 220.

[0127] In some embodiments, refer to Figure 10d and Figure 3aAs shown, the sealing ring 240 may include at least two interconnect layers stacked on top of each other, with the interconnect layers in contact and coupled to each other. Compared to a sealing ring 240 with a smaller height, the process time required to form a sealing ring 240 with a larger height through continuous deposition is longer, which can easily lead to uneven deposition, increasing the probability of voids and defects in the sealing ring 240 and reducing the protective performance of the sealing ring 240 for the semiconductor device 220. The sealing ring 240 can be formed simultaneously with the metal wiring layer, which is used for electrical signal transmission in the semiconductor device 220, while the sealing ring 240 does not participate in the electrical signal transmission of the semiconductor device 220. The sealing ring 240 and the metal wiring layer can share a single photomask, and the photolithography and development process of the sealing ring 240 and the metal wiring layer can be completed in a single photolithography step, reducing manufacturing costs.

[0128] Therefore, in order to form a sealing ring 240 with a larger height, a step-by-step etching and step-by-step deposition method can be adopted, forming an interconnect layer with a smaller height in each step, reducing the probability of void defects, improving the quality of the sealing ring 240, thereby improving the isolation and protection effect of the sealing ring 240 on the semiconductor device 220 in the cutting process, improving the static charge release performance of the sealing ring 240, and improving the yield of the semiconductor device 220.

[0129] In some embodiments, after forming the sealing ring 240, a heat treatment process is performed on the sealing ring 240, including annealing, to reduce stress concentration and internal structural defects. When the sealing ring 240 is made of a metallic material, annealing can also reduce the hardness of the metal, increase its plasticity, and reduce the risk of breakage. After forming the pad 250, a heat treatment process can also be performed on the pad 250, including annealing. The heat treatment process includes, but is not limited to, furnace tube annealing, laser annealing, or any combination thereof.

[0130] In some embodiments, a third dielectric layer is formed at the end of the sealing ring 240 away from the substrate 210, and the third dielectric layer is etched to form a third groove, exposing the sealing ring 240 at the bottom of the third groove. The third groove is then filled with conductive material to form a pad 250. During the deposition of the conductive material, the conductive material may partially cover the third dielectric layer. Therefore, the conductive material can be subsequently planarized to remove the conductive material from the surface of the third dielectric layer, ultimately forming the pad 250.

[0131] Planarization can make the surface of pad 250 flush with the surface of the third dielectric layer, improve the surface flatness of pad 250, increase the bonding strength of pad 250 with other semiconductor devices or other semiconductor structures, reduce the contact resistance of pad 250 with other semiconductor devices or other semiconductor structures, and improve the coupling performance of pad 250.

[0132] The materials comprising the first, second, and third dielectric layers may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The materials comprising the first, second, and third dielectric layers may be the same or different.

[0133] For example, planarization processes include, but are not limited to, chemical mechanical polishing, wet etching, or cleaning processes.

[0134] In this embodiment, the first doped well 231 and the second doped well 232 have different doping types. For example, the first doped well 231 is a p-type doped well and the second doped well 232 is an n-type doped well, or the first doped well 231 is an n-type doped well and the second doped well 232 is a p-type doped well. The pad 250 can be coupled to the first doped well 231 and the second doped well 232 of different types through the sealing ring 240. Holes in the p-type doped well and free electrons in the n-type doped well attract each other to achieve a balance state, reducing the probability of defects such as surface collapse or surface protrusion of the pad 250 in the semiconductor structure 200 during chemical mechanical polishing or cleaning processes.

[0135] In some embodiments, S400 includes: A sealing ring 240 is formed on the first doped well 231 and the second doped well 232; wherein the sealing ring 240 is in direct contact with the first doped well 231 and the second doped well 232.

[0136] Formation as Figure 10c Following the first doped well 231 and the second doped well 232 shown, in the z-direction, a structure is formed on the top surface of the first doped well 231 and the second doped well 232 as shown. Figure 3c The sealing ring 240 shown is in direct contact with both the first doped well 231 and the second doped well 232 to form a coupling.

[0137] In some embodiments, the manufacturing method further includes: A conductive portion 233 is formed between the first doped well 231 and the second doped well 232; wherein the conductive portion 233 is in direct contact with the first doped well 231 and the second doped well 232. A sealing ring 240 is formed on the substrate 210, including: A sealing ring 240 is formed on the conductive part 233, and the sealing ring 240 is in direct contact with the conductive part 233.

[0138] Specifically, in the formation of such Figure 10c After showing the first doped well 231 and the second doped well 232, the substrate 210 between the first doped well 231 and the second doped well 232 can be etched to form a groove, and the groove can be filled with a conductive material to form a conductive portion 233. Then, combined with... Figure 3d As shown, a sealing ring 240 is formed in the z-direction that is in direct contact with the top surface of the conductive part 233.

[0139] The conductive part 233 may include conductive wires or conductive blocks. The constituent materials of the conductive part 233 include, but are not limited to, conductive materials such as copper, aluminum, nickel, tungsten, silver, gold, or titanium.

[0140] In some embodiments, combined with Figure 10b and Figure 10c As shown, forming a first doped well 231 and a second doped well 232 in the substrate 210 includes: A first groove and a second groove are formed in the substrate 210; The first and second grooves are filled with semiconductor material; The semiconductor material in the first groove is doped to form a first doped well 231; The semiconductor material in the second groove is doped to form a second doped well 232; wherein the doping concentration of the second doped well 232 is substantially equal to the doping concentration of the first doped well 231.

[0141] For example, the semiconductor material includes, but is not limited to: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

[0142] For example, the process of forming the first groove and the second groove includes: dry etching process, wet etching process, or any combination thereof.

[0143] Reference Figure 10b As shown, the first groove and the second groove can be formed simultaneously to reduce process steps and manufacturing costs. The bottoms of both the first groove and the second groove are within the substrate 210, meaning that neither the first groove nor the second groove penetrates the substrate 210.

[0144] For example, doping processes include, but are not limited to, ion implantation processes, diffusion processes, or any combination thereof.

[0145] In some embodiments, after doping the semiconductor material in the first and second trenches to form a first doped well 231 and a second doped well 232, the first doped well 231 and the second doped well 232 are subjected to heat treatment. The heat treatment process can make the dopant element distribution in the first doped well 231 and the second doped well 232 more uniform, and can also repair the lattice damage caused by the doping process to the semiconductor material in the doped well.

[0146] The doping concentrations of the first doped well 231 and the second doped well 232 are essentially equal, meaning the two doping concentrations are completely equal, or the two concentrations have a small difference, which is negligible. The difference in surface defects on the pads caused by this difference is also negligible, yet the effect of reducing the probability of defects such as collapse or protrusion on the pad surface can still be achieved. The difference in doping concentration between the first doped well 231 and the second doped well 232 can be due to measurement errors introduced by the concentration measurement process.

[0147] The doping concentrations of the first doped well 231 and the second doped well 232 are basically equal, which makes the hole and free electron concentrations in the first doped well 231 and the second doped well 232 basically equal, so that a more stable equilibrium state is formed between the first doped well 231 and the second doped well 232, reducing the probability of defects such as surface collapse or surface protrusion of the pad 250.

[0148] In some embodiments, doping the semiconductor material in the first groove; doping the semiconductor material in the second groove includes: The semiconductor material in the first groove is n-type doped; The semiconductor material in the second groove is p-type doped; or, The semiconductor material in the first groove is p-type doped; The semiconductor material in the second groove is subjected to n-type doping.

[0149] p-type doping elements include trivalent elements such as boron, gallium, or indium. In p-type doped wells, holes are the majority carriers and free electrons are the minority carriers; conductivity is primarily achieved through holes as charge carriers.

[0150] n-type doping includes pentavalent elements, such as nitrogen, phosphorus, or arsenic. In an n-type doped well, free electrons are the majority carriers and holes are the minority carriers; conductivity is primarily achieved by free electrons as the charge carriers.

[0151] In some embodiments, refer to Figure 10e As shown, before forming the sealing ring 240, the manufacturing method further includes: Conductive plugs 260 are formed on the first doped well 231 and the second doped well 232; wherein, the conductive plugs 260 are coupled to the first doped well 231 and the second doped well 232; after the sealing ring 240 is formed, the conductive plugs 260 are coupled to the sealing ring 240.

[0152] For example, the conductive plug 260 is composed of conductive materials including but not limited to: copper, aluminum, nickel, tungsten, silver, gold, titanium and other conductive materials.

[0153] For example, the process for forming the conductive plug 260 includes, but is not limited to, physical vapor deposition, chemical vapor deposition, or electroplating processes.

[0154] In some embodiments, the conductive plug 260 may be a conductive post, with multiple conductive posts arranged at intervals, similar to... Figure 3b The arrangement of the pads 250. The fabrication method also includes forming a second dielectric layer covering the first doped well 231 and the second doped well 232, forming a via through the second dielectric layer, exposing the first doped well 231 and the second doped well 232 at the bottom of the via, filling the via with a conductive material to form a conductive pillar coupled to the first doped well 231 and the second doped well 232.

[0155] In other embodiments, the conductive plug 260 may also be a continuous conductive layer extending in a direction perpendicular to the xoz plane. The fabrication method further includes forming a second dielectric layer covering the first doped well 231 and the second doped well 232, forming a second trench penetrating the second dielectric layer, exposing the first doped well 231 and the second doped well 232 at the bottom of the second trench, and filling the second trench with a conductive material to form a conductive layer coupling the first doped well 231 and the second doped well 232.

[0156] In some embodiments, the semiconductor device 220 includes a CMOS control circuit.

[0157] CMOS control circuits can be used in memory to control the reading, writing, or erasing operations of the memory cells. The memory can include NAND flash memory (3D NAND flash memory), DRAM memory, or phase-change memory.

[0158] In some embodiments, the manufacturing method further includes: Form a storage array; A bonding memory array and a semiconductor device 220 are present; wherein the semiconductor device 220 is located between the memory array and the substrate 210.

[0159] Reference Figure 11a As shown, the memory array can be formed on the semiconductor layer 310. The memory array includes a gate layer 312 and an insulating layer 311 stacked on top of each other. The gate layer 312 serves as the word line of the three-dimensional NAND memory.

[0160] A channel post 320 is formed that penetrates the gate layer 312 and the insulating layer 311. The channel post 320 includes a channel layer and a functional layer surrounding the channel layer. Along the radial direction of the channel post 320, the functional layer includes a barrier sublayer, a storage sublayer, and a tunneling sublayer.

[0161] For example, the formation process of the gate layer 312, the insulating layer 311, the channel layer, and the functional layer may include any process known in the art, such as low-temperature chemical vapor deposition, low-pressure chemical vapor deposition, thermal chemical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, etc.

[0162] Continue to refer to Figure 11a As shown, in the z-direction, a plurality of second conductive plugs 331 coupled to the gate layer 312 are formed at the end of the gate layer 312. A third conductive plug 332 is formed at the top of the channel pillar 320, and the third conductive plug 332 is coupled to the channel layer of the channel pillar 320.

[0163] In some embodiments, refer to Figure 11a As shown, the fabrication method further includes forming a sealing ring 330 on the semiconductor layer 310 and forming a pad 340 coupled to the sealing ring 330 above the sealing ring 330.

[0164] In some embodiments, refer to Figure 11b As shown, a semiconductor device 220 is formed on a substrate 210, and the semiconductor device 220 may include... Figure 11b The CMOS circuit is shown in the dashed box. A first doped well 231 and a second doped well 232 are formed in the substrate 210. A sealing ring 240 coupled to the first doped well 231 and the second doped well 232 is formed on the substrate 210. A pad 250 is formed on the sealing ring 240 and coupled to the sealing ring 240.

[0165] In some embodiments, continue to refer to Figure 11b As shown, the fabrication method further includes forming a plurality of first conductive plugs 271 on the substrate 210, which can be coupled to the semiconductor device 220 through the substrate 210 or other conductive structures (not shown in the figure).

[0166] Combination Figure 11a , Figure 11b as well as Figure 4 As shown, the first conductive plug 271 and the second conductive plug 331 are bonded and coupled one-to-one, and the third conductive plug 332 is bonded and coupled to the semiconductor device 220, thereby realizing the bonding between the memory array and the semiconductor device 220.

[0167] In some embodiments, pads 250 and 340 can be bonded to achieve coupling between the two sealing rings and release static charge through the first doped well 231 and the second doped well 232, reducing the damage to the semiconductor structure 200 caused by static charge accumulation. Sealing rings 240 and 330 can provide mutual support, improving the support for the semiconductor structure 200.

[0168] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; Semiconductor devices are located on the substrate; A first sealing ring is located on the substrate and surrounds the semiconductor device; Multiple first pads are connected to a first sealing ring, the first sealing ring being located between the substrate and the first pads in a first direction; the first direction is perpendicular to the substrate. The plurality of first pads are spaced apart in a plane parallel to the first direction.

2. The semiconductor structure according to claim 1, characterized in that, The first sealing ring has a circumferentially continuous structure and extends into the substrate along the first direction.

3. The semiconductor structure according to claim 2, characterized in that, The plurality of first pads are arranged at circumferential intervals along the first sealing ring.

4. The semiconductor structure according to claim 1, characterized in that, The first sealing ring includes a plurality of interconnect layers and conductive structures that are alternately stacked along the first direction, the conductive structures being located between adjacent interconnect layers along the first direction.

5. The semiconductor structure according to claim 1, characterized in that, In the first direction, the height of the first sealing ring is greater than or equal to the height of the semiconductor device.

6. The semiconductor structure according to claim 1, characterized in that, Also includes: A conductive plug is located between the substrate and the first sealing ring in the first direction, and the conductive plug is connected to the substrate and the first sealing ring respectively.

7. The semiconductor structure according to claim 1, characterized in that, The substrate includes a doped well, and the first sealing ring is connected to the doped well.

8. The semiconductor structure according to claim 7, characterized in that, Also includes: A conductive plug is located in the first direction between the substrate and the first sealing ring, and the conductive plug is connected to the doped trap and the first sealing ring respectively.

9. The semiconductor structure according to claim 8, characterized in that, The doped well includes a first doped well and a second doped well, and the conductive plug includes a first conductive plug connected to the first doped well and a second conductive plug connected to the second doped well. Both the first conductive plug and the second conductive plug are connected to the interconnect layer in the first sealing ring.

10. The semiconductor structure according to claim 7, characterized in that, Also includes: Conductive parts; The doped well includes a first doped well and a second doped well, and the conductive portion is located between the first doped well and the second doped well; The first sealing ring is connected to the conductive part.

11. The semiconductor structure according to claim 6, characterized in that, The first pad is composed of at least one of the following materials: copper, aluminum, nickel, tungsten, silver, gold, or titanium; The conductive plug is composed of at least one of the following materials: copper, aluminum, nickel, tungsten, silver, gold, or titanium.

12. The semiconductor structure according to claim 1, characterized in that, The semiconductor device includes complementary metal-oxide-semiconductor (CMOS) circuitry.

13. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a memory array bonded to the first pad.

14. The semiconductor structure according to claim 13, characterized in that, The semiconductor structure further includes: a second sealing ring surrounding the memory array and a second pad connected to the second sealing ring; the second pad is bonded to the first pad.

15. A semiconductor structure, characterized in that, include: Base; Semiconductor devices and memory arrays are stacked on the substrate and arranged along a first direction; Doped wells are located in the substrate; A sealing ring, connected to the doped well, surrounds the semiconductor device and the memory array along a plane perpendicular to the first direction.

16. The semiconductor structure according to claim 15, characterized in that, The sealing ring includes: a first sealing ring and a second sealing ring connected along the first direction; the first sealing ring surrounds the semiconductor device along a plane perpendicular to the first direction and is connected to the well region, and the second sealing ring surrounds the memory array along a plane perpendicular to the first direction.

17. The semiconductor structure according to claim 16, characterized in that, Also includes: A plurality of first pads are connected to the first sealing ring; the first sealing ring is located between the doped well and the first pads in the first direction; Multiple second pads are connected to the second sealing ring; the second pads are bonded to the first pads.

18. The semiconductor structure according to claim 17, characterized in that, The plurality of first pads are arranged at intervals along a plane perpendicular to the first direction; The plurality of second pads are arranged at intervals along a plane perpendicular to the first direction.

19. The semiconductor structure according to claim 15, characterized in that, The sealing ring includes a circumferentially continuous structure, and the sealing ring extends to the doped trap along the first direction.

20. The semiconductor structure according to claim 16, characterized in that, The first sealing ring includes a plurality of interconnect layers and conductive structures that are alternately stacked along the first direction; The second sealing ring includes multiple interconnect layers and conductive structures that are alternately stacked along the first direction.

21. The semiconductor structure according to claim 16, characterized in that, In the first direction, the height of the first sealing ring is greater than or equal to the height of the semiconductor device; In the first direction, the height of the second sealing ring is greater than or equal to the height of the storage array.

22. The semiconductor structure according to claim 20, characterized in that, Also includes: A conductive plug is located in the first direction between the doped well and the first sealing ring, and the conductive plug is connected to the doped well and the first sealing ring respectively.

23. The semiconductor structure according to claim 22, characterized in that, The doped well includes a first doped well and a second doped well, and the conductive plug includes a first conductive plug connected to the first doped well and a second conductive plug connected to the second doped well. Both the first conductive plug and the second conductive plug are connected to the interconnect layer in the first sealing ring.

24. The semiconductor structure according to claim 16, characterized in that, Also includes: Conductive parts; The doped well includes a first doped well and a second doped well, and the conductive portion is located between the first doped well and the second doped well; The first sealing ring is connected to the conductive part.

25. The semiconductor structure according to claim 15, characterized in that, The semiconductor device includes complementary metal-oxide-semiconductor (CMOS) circuitry.

26. A semiconductor structure, characterized in that, include: Base; Semiconductor devices and memory arrays are stacked on the substrate and arranged along a first direction; The first doped well and the second doped well are located in the substrate; A sealing ring is connected to the first doped well and the second doped well, respectively, and surrounds the semiconductor device and the memory array.

27. The semiconductor structure according to claim 26, characterized in that, The sealing ring includes: a first sealing ring and a second sealing ring connected along the first direction; the first sealing ring surrounds the semiconductor device along a plane perpendicular to the first direction and is connected to the first doped well and the second doped well, and the second sealing ring surrounds the memory array along a plane perpendicular to the first direction.

28. The semiconductor structure according to claim 27, characterized in that, Also includes: A plurality of first pads are connected to the first sealing ring; the first sealing ring is located between the doped well and the first pads in the first direction; Multiple second pads are connected to the second sealing ring; the second pads are bonded to the first pads.

29. The semiconductor structure according to claim 28, characterized in that, The first pads are arranged at intervals along a plane perpendicular to the first direction; The second pads are arranged at intervals along a plane perpendicular to the first direction.

30. The semiconductor structure according to claim 26, characterized in that, The sealing ring has a circumferentially continuous structure and extends along the first direction to the first doped well and the second doped well.

31. The semiconductor structure according to claim 27, characterized in that, The first sealing ring includes a plurality of interconnect layers and conductive structures that are alternately stacked along the first direction; The second sealing ring includes multiple interconnect layers and conductive structures that are alternately stacked along the first direction.

32. The semiconductor structure according to claim 27, characterized in that, In the first direction, the height of the first sealing ring is greater than or equal to the height of the semiconductor device; In the first direction, the height of the second sealing ring is greater than or equal to the height of the storage array.

33. The semiconductor structure according to claim 31, characterized in that, Also includes: A first conductive plug located between the first doped well and the first sealing ring in the first direction, and a second conductive plug located between the second doped well and the first sealing ring in the first direction; Both the first conductive plug and the second conductive plug are connected to the interconnect layer in the first sealing ring.

34. The semiconductor structure according to claim 27, characterized in that, Also includes: A conductive portion located between the first doped well and the second doped well; The first sealing ring is connected to the conductive part.

35. The semiconductor structure according to claim 26, characterized in that, The semiconductor device includes complementary metal-oxide-semiconductor (CMOS) circuitry.

36. A storage system, characterized in that, include: A memory controller and a memory, the controller being coupled to the memory and used to control the memory, the memory comprising a semiconductor structure as described in any one of claims 1 to 35.

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