Metallized electrode structure, back contact solar cell and method of manufacturing thereof

Abstract

The application provides a kind of metallized electrode structure, back contact solar cell and preparation method thereof, and is particularly related to solar cell preparation technical field.The metallized electrode structure includes grid layer structure and copper layer embedded and coated on the grid layer structure;Wherein, the grid layer structure includes grid line layer and pad layer;Metal in the grid layer structure is arranged using dot matrix structure.The metallized electrode structure has the following advantages: dot matrix structure significantly reduces the coverage area of noble metal, significantly reduces silver consumption under the premise of ensuring ohmic contact between each unit and silicon doped region;Dot matrix fine grid and main grid are set in cross to consider current lateral collection and longitudinal confluence, discrete distribution releases metal / silicon thermal mismatch stress, and inhibits hidden crack;Copper layer three-dimensional bridging and filling dot matrix gap, realize metallurgical combination, maintain electrical continuity while giving mechanical redundancy, improve the ability of local damage resistance and long-term reliability.

Description

Technical Field

[0001] This invention relates to the field of solar cell fabrication technology, and in particular to a metallized electrode structure, a back-contact solar cell, and a method for fabricating the same. Background Technology

[0002] Back-contact solar cells, by moving all electrodes to the back of the silicon wafer and completely eliminating light loss due to front-side metal shading, have become the mainstream technology for improving the photoelectric conversion efficiency of crystalline silicon cells. In terms of metallization processes, the industry generally adopts a composite approach of printing a silver seed layer and electroplating copper for thickening, thereby reducing the amount of precious metals used while ensuring conductivity.

[0003] Despite the advantages of mature technology, the aforementioned continuous grid structure has inherent limitations in terms of materials, electrical and mechanical reliability. (1) There is a physical bottleneck in reducing silver loss: the continuous fine grid needs to cover the entire current collection path, and its minimum linewidth is constrained by printing accuracy and ohmic contact area. Further narrowing will lead to a sharp increase in contact resistance.

[0004] (2) Lack of current collection matching: The transverse transport resistance of charge carriers inside the battery is distributed in a gradient. The central region of the battery, far from the main grid, has high transverse impedance due to the silicon resistivity, while the impedance is significantly reduced due to the longitudinal current collection near the main grid. The uniform geometric parameters of the continuous fine grid cannot respond to this spatial non-uniformity, resulting in insufficient collection in the central region and excessive metallization in the edge region.

[0005] (3) Risk of thermomechanical stress concentration: The thermal expansion coefficients of silver and monocrystalline silicon differ by 7.6 times. Under the conditions of module lamination and outdoor hot and cold cycles, the interface between the continuous metal lines and the silicon substrate generates periodic shear stress, resulting in a high incidence of microcracks.

[0006] (4) Deterioration of uniformity in electroplating process: There are current density peaks at the edge of continuous fine grid, which leads to the electroplated copper being too thick at the edge of the grid line and too thin in the center. The uneven thickness not only increases the risk of subsequent poor soldering, but also exacerbates the tendency to bend and break due to the reduced ductility of the locally thick copper layer.

[0007] It is evident that existing back-contact solar cell metallization technologies suffer from several drawbacks, including high silver paste consumption, an inability to balance carrier collection capacity with silver consumption, cumbersome process steps, poor alignment accuracy leading to short circuits, poor uniformity of copper plating bridging, and insufficient electrode conductivity and welding reliability.

[0008] In view of this, the present invention is hereby proposed. Summary of the Invention

[0009] The purpose of this invention is to provide a metallized electrode structure, a back-contact solar cell, and a method for fabricating the same, in order to solve at least one of the aforementioned technical problems in the prior art.

[0010] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: A first aspect of the present invention provides a metallized electrode structure, including a gate layer structure and a copper layer embedded on the gate layer structure; wherein the gate layer structure includes a gate line layer and a pad layer; and the metal in the gate layer structure is arranged in a lattice structure.

[0011] Furthermore, the lattice structure is arranged in a gradient discontinuous manner.

[0012] Preferably, the gate structure includes intersecting fine gate layers and main gate layers, as well as pad layers.

[0013] Preferably, the lattice structure density of the fine gate layer is less than that of the main gate layer.

[0014] Preferably, the dot matrix density of the pad layer is the same as that of the main gate layer.

[0015] Preferably, the lattice structure of the fine grid layer includes a dotted structure or line segments.

[0016] Preferably, the dot-like structure includes a circle, an ellipse, a rectangle, or a hexagon.

[0017] Preferably, the length of the gap between adjacent line segments is greater than the length of the line segment itself.

[0018] Preferably, the lattice structure of the main gate layer includes strips.

[0019] Preferably, the crossing method includes perpendicularity.

[0020] Preferably, the size and / or spacing of the lattice structure of the fine gate layer are gradient-distributed along the direction perpendicular to the main gate layer.

[0021] Preferably, in regions far from the main gate layer, the lattice structure of the fine gate layer is enlarged and / or the spacing is reduced.

[0022] Preferably, in the region near the main gate layer, the lattice structure of the fine gate layer is reduced and / or the spacing is increased.

[0023] Preferably, the material of the fine gate layer and / or the main gate layer includes silver or a silver alloy.

[0024] Furthermore, the upper surface of the copper layer continuously wraps around and embeds the gate structure to form a continuous conductive network.

[0025] A second aspect of the present invention provides a back-contact solar cell, comprising a silicon substrate, wherein alternating P-type doped regions and N-type doped regions are provided on the back side of the silicon substrate, and metallized electrodes are independently disposed on the P-type doped regions and N-type doped regions respectively; wherein the metallized electrodes have the metallized electrode structure described in the first aspect.

[0026] The third aspect of the present invention provides a method for fabricating a back-contact solar cell, comprising the following steps: S1, forming contact windows for a P-type doped region and an N-type doped region on the back passivation film of the cell semi-finished product to expose the surface of the underlying silicon substrate; S2, forming a gate structure, wherein the metal in the gate structure is arranged in a lattice structure; and finally, electroplating a copper layer on the gate structure.

[0027] Furthermore, the methods for creating contact windows for P-type and N-type doped regions include laser ablation or photolithography.

[0028] Preferably, in the laser ablation, the wavelength of the laser is 266~1064nm, the pulse width is from nanosecond to femtosecond, the single pulse energy is 1~100μJ, the repetition frequency is 100~1000kHz, and the scanning speed is 100~2000mm / s.

[0029] Preferably, the specific process of photolithography etching is as follows: first, photoresist is spin-coated on the back passivation film, then ultraviolet exposure and development are performed through a mask with a contact window pattern, then reactive ion etching is used, and finally the photoresist in the unetched area is stripped off to obtain the contact window.

[0030] Preferably, in the reactive ion etching, the etching gas is CF4 and Ar.

[0031] Preferably, the flow rate of CF4 is 20~50 sccm, and the flow rate of Ar is 5~15 sccm.

[0032] Preferably, in the reactive ion etching, the etching is performed for 30 to 120 seconds under the conditions of a cavity pressure of 5 to 20 Pa and a radio frequency power of 50 to 150 W.

[0033] Preferably, the contact window is used to form a dot matrix structure.

[0034] Preferably, the accuracy error of the contact window is ±10μm.

[0035] The methods for forming the grid structure include screen printing, PVD deposition with a mask, or printing etching paste after PVD deposition.

[0036] Furthermore, the preparation method further includes chemical cleaning or passivation treatment of the exposed silicon substrate after step S1 and before step S2.

[0037] Preferably, the conductive paste used for screen printing includes conductive silver paste or conductive silver alloy paste.

[0038] Preferably, the conductive paste is heated at 25°C with a shear rate of 10 s. -1 The viscosity is 50~150 Pa·s, the thixotropic index is 4.0~6.0, and the solid content is 80~95%.

[0039] Preferably, the screen printing process further includes drying and sintering to form a grid structure.

[0040] Preferably, the drying is carried out under an inert atmosphere at a temperature of 100-200°C for 1-5 minutes.

[0041] Preferably, the peak temperature of the sintering is 300~500°C, and the residence time at the peak temperature is 30~120s.

[0042] Furthermore, the preparation method further includes activating the gate structure after it is formed and before it is electroplated.

[0043] Preferably, the activation treatment involves immersing the battery cells in a 1-5% sulfuric acid or hydrochloric acid solution for 15-60 seconds.

[0044] Furthermore, the copper electroplating solution used in the electroplating comprises: copper sulfate pentahydrate 40~100 g / L, sulfuric acid 50~100 g / L, chloride ions 30~100 mg / L, sodium polydisulfide dipropane sulfonate 1~20 mg / L, polyethylene glycol or polypropylene glycol 50~500 mg / L, tetrahydrozoline 5~50 mg / L, and the balance being pure water.

[0045] Furthermore, the electroplating employs a pulsed reverse electroplating process, the waveform cycle of which includes: a forward pulse stage for driving copper deposition and lateral growth, a reverse pulse stage for micro-refining the deposited layer, and a turn-off stage for ensuring that the entire growth process remains stable and uniform for tens of minutes.

[0046] Preferably, the current density during the positive pulse phase is 2~6 A / dm. 2 Pulse width 10~100ms; reverse current density -1.0~-0.2 A / dm 2 Pulse width 1~5ms; turn-off time 0~20ms.

[0047] Preferably, the electroplating time is 5 to 20 minutes.

[0048] Preferably, the thickness of the copper layer is 5~20μm.

[0049] In some embodiments of the present invention, the metallized electrode structure is a cross-arranged fine gate and main gate structure, and each main gate corresponds to at least one pad. The main gate and the pad are partially overlapped. The main gate is a continuous structure or a partially discontinuous structure.

[0050] In some embodiments of the present invention, the metallized electrode structure is a plurality of parallel fine gate structures, and each fine gate corresponds to a plurality of pads, wherein the fine gates and the pads are partially overlapped.

[0051] In some embodiments of the present invention, the metallized electrode structure comprises multiple parallel fine grid structures in the middle region of the battery cell, and each fine grid corresponds to multiple pads, wherein the fine grids and the pads are partially overlapped; the edge of the battery cell is configured as a local main grid structure, wherein the main grids and the pads are partially overlapped.

[0052] Compared with the prior art, the present invention has at least the following beneficial effects: The metallized electrode structure provided by this invention achieves a triple synergistic effect by constructing the gate structure as a lattice structure rather than continuous lines and embedding and covering the lattice gate layer with a copper layer: First, the lattice structure significantly reduces the physical coverage area of ​​precious metals, directly reducing the amount of precious metals used while ensuring effective ohmic contact between each discrete unit and the silicon doped region; Second, the cross arrangement of the lattice gate lines retains the topological connectivity of lateral current collection and vertical current convergence, while the discrete distribution characteristics release the thermal mismatch stress at the metal / silicon interface and suppress the initiation of microcracks; Third, the embedded covering of the lattice gate layer with a copper layer ensures that copper bridges adjacent lattice units in three-dimensional space, fills their gaps, and is metallurgically bonded to each unit, thereby maintaining electrical continuity while giving the electrode structure mechanical redundancy. The failure of a single lattice unit does not affect the overall conductive path, improving the electrode's resistance to local damage and long-term reliability.

[0053] The back-contact solar cell provided by this invention avoids the risk of short circuits caused by metal bridging between the front and back electrodes or between the P / N regions on the back side of a silicon substrate by setting alternating P-type and N-type doped regions on the back side, and independently setting metallized electrodes with lattice gate structures and embedded copper layers on them, thereby improving the intrinsic safety of the device structure. Each electrode adopts the lattice gate structure and embedded copper layer structure defined in the first aspect, so that the P-region electrode and the N-region electrode can simultaneously enjoy all the structural advantages such as reduced precious metal loss, thermal stress release, and mechanical redundancy brought by three-dimensional copper bridging, ensuring the consistency and synergy of bipolar electrodes in terms of material usage, electrical performance and reliability. The lattice structure forms a natural metal spacer band near the P / N region interface, which suppresses the local recombination enhancement induced by metal diffusion or tip discharge at the high doping concentration boundary, which is beneficial to maintaining the carrier selective collection capability of the P / N junction region.

[0054] The preparation method provided by this invention establishes P / N region contact windows to ensure that the subsequent metallization process strictly corresponds to their respective doping types in physical space, avoiding cross-region short circuits caused by photolithography or laser alignment deviations, and improving process robustness and batch yield. By forming a gate structure through mask printing, the patterns of the lattice fine gate and the main gate are synchronously defined on the same mask, eliminating the cumulative errors caused by multi-step registration, ensuring the precise overlap of the lattice unit and the contact window, thereby ensuring that each discrete seed unit is located above the effective doping region, achieving a high proportion of ohmic contacts. The post-thickening process of electroplating a copper layer on the gate structure allows the nucleation, vertical thickening, and lateral bridging of copper to be completely controlled by predefined lattice anchor points. It can self-assemble into a continuous conductive network without additional patterning steps, which simplifies the process chain and ensures that the copper layer and the lattice gate layer form a dense metallurgical bond at the interface through an electrochemically driven in-situ bridging mechanism, significantly improving the overall adhesion and peel strength of the electrode. Attached Figure Description

[0055] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of the first metallized electrode structure; Figure 2 This is a schematic diagram of the second type of metallized electrode structure; Figure 3 This is a schematic diagram of the first type of gate structure; Figure 4This is a schematic diagram of the second type of gate structure; Figure 5 This is a schematic diagram of the metal electrode structure of a back-contact solar cell.

[0057] Explanation of key component symbols: 100 - gate structure; 110 - fine gate layer; 130 - main gate layer; 200 - copper layer; 300 - silicon substrate; 400 - N-region electrode; 500 - P-region electrode. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0059] A first aspect of the present invention provides a metallized electrode structure, including a gate structure 100 and a copper layer 200 embedded on the gate structure 100; wherein the gate structure 100 includes a gate line layer and a pad layer; and the metal in the gate structure 100 is arranged in a lattice structure.

[0060] The metallized electrode structure provided by this invention achieves a triple synergistic effect by constructing the gate structure 100 as a lattice structure rather than continuous lines, and embedding and covering the copper layer 200 on the lattice gate layer: First, the lattice structure significantly reduces the physical coverage area of ​​precious metals, directly reducing the amount of precious metals used while ensuring effective ohmic contact between each discrete unit and the silicon doped region; Second, the discrete distribution characteristics of the lattice gate layer release the thermal mismatch stress at the metal / silicon interface and suppress the initiation of microcracks; Third, the embedded covering of the lattice gate layer by the copper layer 200 ensures that copper bridges adjacent lattice units in three-dimensional space, fills their gaps, and is metallurgically bonded to each unit, thereby maintaining electrical continuity while giving the electrode structure mechanical redundancy. The failure of a single lattice unit does not affect the overall conductive path, improving the electrode's resistance to local damage and long-term reliability.

[0061] A schematic diagram of the structure of the metallized electrode is shown below. Figure 1 As shown, the fine gate layer 110 has a lateral structure; in another embodiment of the present invention, the structural schematic diagram of the metallized electrode is as follows. Figure 2 As shown, the fine gate layer 110 has a vertical structure.

[0062] Furthermore, the lattice structure is arranged in a gradient discontinuous manner.

[0063] Preferably, the gate structure includes a fine gate layer 110 and a main gate layer 130 arranged in a cross configuration, as well as a pad layer.

[0064] Preferably, the lattice structure density of the fine gate layer 110 is less than the lattice structure density of the main gate layer 130.

[0065] Preferably, the dot matrix density of the pad layer is the same as that of the main gate layer.

[0066] Preferably, the lattice structure of the fine gate layer 110 includes a dotted structure or line segments.

[0067] Preferably, the dot-like structure includes a circle, an ellipse, a rectangle, or a hexagon.

[0068] Preferably, the length of the gap between adjacent line segments is greater than the length of the line segment itself.

[0069] Preferably, the lattice structure of the main gate layer 130 includes strips.

[0070] Preferably, the crossing method includes perpendicularity.

[0071] Preferably, the size and / or spacing of the lattice structure of the fine gate layer 110 are gradient-distributed along a direction perpendicular to the main gate layer 130.

[0072] Preferably, such as Figure 3 As shown, in the region away from the main gate layer 130, the lattice structure of the fine gate layer 110 increases and / or the spacing decreases, while in the region close to the main gate layer 130, the lattice structure of the fine gate layer 110 decreases and / or the spacing increases.

[0073] In another embodiment of the present invention, such as Figure 4 As shown, the fine gate layer 110 is a rectangular dot matrix structure with the same size dot matrix structure but different spacing, and the main gate layer 130 is in the middle.

[0074] Preferably, the fine gate layer 110 and / or the main gate layer 130 are made of silver or a silver alloy.

[0075] Furthermore, the upper surface of the copper layer 200 continuously wraps around and embeds the gate structure 100 to form a continuous conductive network.

[0076] A second aspect of the present invention provides a back-contact solar cell, including a silicon substrate 300, wherein alternating P-type doped regions and N-type doped regions are provided on the back side of the silicon substrate 300, and metallized electrodes are independently disposed on the P-type doped regions and N-type doped regions respectively; wherein the metallized electrodes have the metallized electrode structure described in the first aspect.

[0077] The back-contact solar cell provided by this invention avoids the risk of short circuits caused by metal bridging between the front and back electrodes or between the back P / N regions due to metal bridging by setting alternating P-type and N-type doped regions on the back side of a silicon substrate 300, and independently setting metallized electrodes with a lattice gate structure 100 and an embedded copper cladding layer 200 on each of them, thereby improving the intrinsic safety of the device structure. Each electrode adopts the lattice gate structure and the embedded copper cladding layer 200 structure defined in the first aspect, so that the P-region electrode 500 and the N-region electrode 400 simultaneously enjoy all the structural advantages such as reduced precious metal loss, thermal stress release, and mechanical redundancy brought by three-dimensional copper bridging, ensuring the consistency and synergy of bipolar electrodes in terms of material usage, electrical performance, and reliability. The lattice structure forms a natural metal spacer band near the P / N region interface, suppressing the local recombination enhancement induced by metal diffusion or tip discharge at the high doping concentration boundary, which is beneficial to maintaining the carrier selective collection capability of the P / N junction region.

[0078] The third aspect of the present invention provides a method for preparing a back-contact solar cell, comprising the following steps: S1, forming contact windows for a P-type doped region and an N-type doped region on the back passivation film of the cell semi-finished product to expose the surface of the underlying silicon substrate 300; S2, forming a gate structure 100, wherein the metal in the gate structure is arranged in a lattice structure; and finally, electroplating a copper layer 200 on the gate structure 100.

[0079] The preparation method provided by this invention establishes P / N region contact windows to ensure that the subsequent metallization process strictly corresponds to their respective doping types in physical space, avoiding cross-region short circuits caused by photolithography or laser alignment deviations, and improving process robustness and batch yield. By forming the gate layer structure 100 through mask printing, the patterns of the lattice fine gate and the main gate are synchronously defined on the same mask, eliminating the cumulative errors caused by multi-step registration, ensuring the precise overlap of the lattice unit and the contact window, thereby ensuring that each discrete seed unit is located above the effective doping region, achieving a high proportion of ohmic contacts. The post-thickening process of electroplating a copper layer 200 on the gate layer structure 100 allows the nucleation, vertical thickening, and lateral bridging of copper to be completely controlled by predefined lattice anchor points. It can self-assemble to generate a continuous conductive network without additional patterning steps, which simplifies the process chain and ensures that the copper layer 200 and the lattice gate layer form a dense metallurgical bond at the interface through an electrochemically driven in-situ bridging mechanism, significantly improving the overall adhesion and peel strength of the electrode.

[0080] Figure 5This is a schematic diagram of the overall structure of the metal electrode of a back-contact solar cell, used to illustrate the spatial relationship of the alternating arrangement of the P-region electrode 500 on the P-type doped region and the N-region electrode 400 on the N-type doped region on the back side of the silicon substrate 300. Both adopt the metallized electrode structure described in the first aspect of the present invention, that is, each includes a lattice gate layer structure 100 and a continuous copper layer 200 embedded thereon.

[0081] Furthermore, the methods for creating contact windows for P-type and N-type doped regions include laser ablation or photolithography.

[0082] Preferably, in the laser ablation, the wavelength of the laser is 266~1064nm, the pulse width is from nanosecond to femtosecond, the single pulse energy is 1~100μJ, the repetition frequency is 100~1000kHz, and the scanning speed is 100~2000mm / s.

[0083] In the laser ablation process, typically, but not limitingly, the laser wavelength can be 266 nm, 355 nm, 532 nm, 808 nm, or 1064 nm, or any value within the range of 266 to 1064 nm; the pulse width is from nanosecond to femtosecond, typically, but not limitingly, for example, 1 ns, 10 ns, 100 ns, 1 ps, 10 ps, ​​100 ps, ​​1 fs, 10 fs, or 100 fs, or any value within the range of nanosecond to femtosecond; the single pulse energy can be, for example, 1 μJ, 10 μJ, 20 μJ, or 40 μJ. The values ​​can be 60μJ, 80μJ, 100μJ, or any value within the range of 1 to 100μJ; the repetition frequency can be, for example, 100kHz, 200kHz, 400kHz, 600kHz, 800kHz, 1000kHz, or any value within the range of 100 to 1000kHz; the scanning speed can be, for example, 100mm / s, 300mm / s, 500mm / s, 1000mm / s, 1500mm / s, 2000mm / s, or any value within the range of 100 to 2000mm / s.

[0084] Preferably, the specific process of photolithography etching is as follows: first, photoresist is spin-coated on the back passivation film, then ultraviolet exposure and development are performed through a mask with a contact window pattern, then reactive ion etching is used, and finally the photoresist in the unetched area is stripped off to obtain the contact window.

[0085] Preferably, in the reactive ion etching, the etching gas is CF4 and Ar.

[0086] Preferably, the flow rate of CF4 is 20~50 sccm, and the flow rate of Ar is 5~15 sccm.

[0087] The flow rate of CF4 can be, for example, 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm, or 50 sccm, or any value within the range of 20 to 50 sccm; the flow rate of Ar can be, for example, 5 sccm, 7 sccm, 10 sccm, 12 sccm, or 15 sccm, or any value within the range of 5 to 15 sccm.

[0088] Preferably, in the reactive ion etching, the etching is performed for 30 to 120 seconds under the conditions of a cavity pressure of 5 to 20 Pa and a radio frequency power of 50 to 150 W.

[0089] In the reactive ion etching, typically but not limitingly, the chamber pressure can be, for example, 5 Pa, 8 Pa, 10 Pa, 12 Pa, 15 Pa, 18 Pa, 20 Pa, or any value within the range of 5 to 20 Pa; the radio frequency power can be, for example, 50 W, 70 W, 90 W, 110 W, 130 W, 150 W, or any value within the range of 50 to 150 W; the etching time can be, for example, 30 s, 50 s, 70 s, 90 s, 110 s, 120 s, or any value within the range of 30 to 120 s, and the etching process is carried out under the above-mentioned chamber pressure and radio frequency power conditions.

[0090] Preferably, the contact window is used to form a dot matrix structure.

[0091] Preferably, the accuracy error of the contact window is ±10μm.

[0092] Preferably, the method of forming the grid structure includes screen printing, or PVD deposition with a mask, or printing an etching paste after PVD deposition.

[0093] Furthermore, the preparation method further includes chemical cleaning or passivation treatment of the exposed silicon substrate 300 after step S1 and before step S2.

[0094] Preferably, the conductive paste used for screen printing includes conductive silver paste or conductive silver alloy paste.

[0095] Preferably, the conductive paste is heated at 25°C with a shear rate of 10 s. -1 The viscosity is 50~150 Pa·s, the thixotropic index is 4.0~6.0, and the solid content is 80~95%.

[0096] The conductive paste is subjected to a shear rate of 10s at 25°C. -1The viscosity can be, typically but not limitingly, 50 Pa·s, 70 Pa·s, 90 Pa·s, 110 Pa·s, 130 Pa·s, or 150 Pa·s, or any value in the range of 50 to 150 Pa·s; the thixotropic index can be, for example, 4.0, 4.5, 5.0, 5.5, or 6.0, or any value in the range of 4.0 to 6.0; the solid content can be, for example, 80%, 83%, 86%, 89%, 92%, or 95%, or any value in the range of 80 to 95%.

[0097] Preferably, the screen printing process further includes drying and sintering to form a grid structure.

[0098] Preferably, the drying is carried out under an inert atmosphere at a temperature of 100-200°C for 1-5 minutes.

[0099] The drying is carried out under an inert atmosphere. Typically, but not limitingly, the drying temperature can be, for example, 100°C, 120°C, 140°C, 160°C, 180°C, or 200°C, or any value within the range of 100°C to 200°C; the drying time can be, for example, 1 min, 2 min, 3 min, 4 min, or 5 min, or any value within the range of 1 to 5 min.

[0100] Preferably, the peak temperature of the sintering is 300~500°C, and the residence time at the peak temperature is 30~120s.

[0101] The peak temperature of the sintering is typically, but not limitingly, 300°C, 350°C, 400°C, 450°C, 500°C, or any value within the range of 300 to 500°C; the residence time at the peak temperature is, for example, 30s, 50s, 70s, 90s, 110s, 120s, or any value within the range of 30 to 120s.

[0102] Furthermore, the preparation method further includes activating the gate structure 100 after it is formed and before it is electroplated.

[0103] Preferably, the activation treatment involves immersing the battery cells in a 1-5% sulfuric acid or hydrochloric acid solution for 15-60 seconds.

[0104] The activation treatment involves immersing the battery cells in a sulfuric acid or hydrochloric acid solution with a concentration of 1-5%. Typically, but not limitingly, the solution concentration can be, for example, 1%, 2%, 3%, 4%, 5%, or any value within the range of 1-5%. The immersion time can be, for example, 15s, 25s, 35s, 45s, 55s, 60s, or any value within the range of 15-60s.

[0105] Furthermore, the copper electroplating solution used in the electroplating comprises: copper sulfate pentahydrate 40~100 g / L, sulfuric acid 50~100 g / L, chloride ions 30~100 mg / L, sodium polydisulfide dipropane sulfonate 1~20 mg / L, polyethylene glycol or polypropylene glycol 50~500 mg / L, tetrahydrozoline 5~50 mg / L, and the balance being pure water.

[0106] Sodium didithiopropane sulfonate, polyethylene glycol (or polypropylene glycol), and tetrahydrozoline constitute a functional additive system in copper electroplating solutions, playing accelerating, inhibiting, and leveling roles, respectively: Sodium didithiopropane sulfonate, as a copper deposition accelerator, can enhance the electrochemical activity of the silver seed unit surface, promoting selective nucleation and initial deposition of copper on the lattice gate structure; Polyethylene glycol or polypropylene glycol, as an inhibitor, forms an adsorption layer on the electrode surface, especially in non-seed areas and protrusions in the early stage of copper layer growth, inhibiting non-directional deposition of copper and helping to control deposition uniformity; Tetrahydrozoline, as a leveling agent, can adjust the double layer state at the cathode interface, inhibiting localized excessively rapid growth (such as microdendritic growth caused by the tip effect) during electroplating, improving the surface smoothness of the copper layer, and synergistically promoting the lateral extension and bridging of copper above the gap between adjacent seed units.

[0107] Under the synergistic effect of the three-component additives and the control of pulse reverse electroplating process parameters, the copper deposition process exhibits controllable staged characteristics: firstly, nucleation and vertical thickening are completed on the surface of discrete silver seed units; then, under the combined influence of electric field gradient and additives, copper grows epitaxially in the horizontal direction, realizing physical connection between adjacent units; finally, gap filling and overall coating are completed, forming an integrated copper electrode layer with a continuous upper surface, dense interior, and metallurgical bonding with the seed layer interface.

[0108] The copper electroplating solution used for electroplating includes, typically but not limitingly, copper sulfate pentahydrate content, for example, 40 g / L, 50 g / L, 60 g / L, 70 g / L, 80 g / L, 90 g / L, 100 g / L, or any value within the range of 40 to 100 g / L; sulfuric acid content, for example, 50 g / L, 60 g / L, 70 g / L, 80 g / L, 90 g / L, 100 g / L, or any value within the range of 50 to 100 g / L; chloride ion content, for example, 30 mg / L, 40 mg / L, 60 mg / L, 80 mg / L, 100 mg / L, or any value within the range of 30 to 100 mg / L. The sodium polydisulfide dipropane sulfonate content can be, for example, 1 mg / L, 5 mg / L, 10 mg / L, 15 mg / L, 20 mg / L, or any value within the range of 1 to 20 mg / L; the polyethylene glycol or polypropylene glycol content can be, for example, 50 mg / L, 100 mg / L, 200 mg / L, 300 mg / L, 400 mg / L, 500 mg / L, or any value within the range of 50 to 500 mg / L; the tetrahydrozoline content can be, for example, 5 mg / L, 15 mg / L, 25 mg / L, 35 mg / L, 45 mg / L, 50 mg / L, or any value within the range of 5 to 50 mg / L; the balance is pure water.

[0109] Furthermore, the electroplating employs a pulsed reverse electroplating process, the waveform cycle of which includes: a forward pulse stage for driving copper deposition and lateral growth, a reverse pulse stage for micro-refining the deposited layer, and a turn-off stage for ensuring that the entire growth process remains stable and uniform for tens of minutes.

[0110] Preferably, the current density during the positive pulse phase is 2~6 A / dm. 2 Pulse width 10~100ms; reverse current density -1.0~-0.2 A / dm 2 Pulse width 1~5ms; turn-off time 0~20ms.

[0111] Typical, but not limiting, forward current density can be, for example, 2 A / dm. 2 3A / dm 2 4A / dm 2 5A / dm 2 6A / dm 2 It can also be 2~6A / dm 2 Any value within the range; the forward pulse width can be, for example, 10ms, 30ms, 50ms, 70ms, 90ms, 100ms, or any value within the range of 10~100ms; the reverse current density can be, for example, -1.0A / dm³. 2 -0.8A / dm2 -0.6A / dm 2 -0.4A / dm 2 -0.2A / dm 2 It can also be -1.0 to -0.2 A / dm. 2 Any value within the range; the reverse pulse width can be, for example, 1ms, 2ms, 3ms, 4ms, 5ms, or any value within the range of 1~5ms; the turn-off time can be, for example, 0ms, 5ms, 10ms, 15ms, 20ms, or any value within the range of 0~20ms.

[0112] Preferably, the electroplating time is 5 to 20 minutes.

[0113] The electroplating time is typically, but not limitingly, for example, 5 min, 8 min, 10 min, 12 min, 15 min, 18 min, 20 min, or any value within the range of 5 to 20 min.

[0114] Preferably, the thickness of the copper layer 200 is 5~20μm.

[0115] The thickness of the copper layer 200 is typically, but not limitingly, for example, 5μm, 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, or any value in the range of 5 to 20μm.

[0116] The electroplated copper layer 200 is not a simple surface covering of the silver seed units, but rather achieves controllable nucleation and directional growth of copper on discrete silver seed units by precisely controlling electroplating process parameters (including pulse current density, pulse width, turn-off time, and electrolyte composition): copper first nucleates independently on the surface of each silver seed unit, and preferentially grows in the vertical direction under the electric field drive of the positive pulse phase to thicken the seed unit body; as deposition proceeds, the copper layers 200 on the top of adjacent seed units gradually approach their initial spacing. Under the synergistic effect of the electric field distribution gradient and additives, copper undergoes lateral epitaxial growth and meets and merges in the space above the gap, forming a continuous copper bridge spanning the gap; after bridging is completed, electroplating continues, and copper deposition extends downward from the bridge body, gradually filling the remaining gap below the bridge body, so that the copper layer 200 completely covers each silver seed unit, with a continuous upper surface, a dense interior without macroscopic pores, and a metallurgical bond at the interface with the silver seed units, forming an integrated copper electrode layer with a complete structure and continuous conductivity.

[0117] The present invention is further illustrated below with specific embodiments and comparative examples. However, it should be understood that these embodiments are merely for illustrative purposes and should not be construed as limiting the invention in any way. Unless otherwise specified, the raw materials used in the embodiments and comparative examples of the present invention were carried out under conventional conditions or conditions recommended by the manufacturer. Reagents or instruments used, unless otherwise specified, are all commercially available conventional products.

[0118] In the embodiments and comparative examples of this invention, the back contact battery semi-finished product used is an N-type TBC battery front-end sheet, which has completed texturing, boron diffusion, phosphorus diffusion, and back-side Al2O3 / SiN coating. X The stacked passivation film deposition process is used for silicon wafers with an M10 size, a thickness of 150μm, and a resistivity of 1-3Ω·cm.

[0119] Example 1 This embodiment provides a back-contact solar cell, and the specific steps of its fabrication method are as follows: 1. Take the N-type TBC cell silicon wafer that has completed the previous process, and use an ultraviolet picosecond laser to open contact windows on the back passivation film corresponding to the P-type doped region and the N-type doped region respectively. The window opening position accuracy error is less than ±5μm. The laser process parameters are: wavelength 355nm, pulse width 12ps, single pulse energy 20μJ, repetition frequency 500kHz, and scanning speed 1000mm / s.

[0120] 2. Before printing, the exposed silicon substrate 300 surface in the contact window is treated with HF acid cleaning to remove the surface oxide layer; using high-precision screen printing technology, conductive silver paste is simultaneously deposited onto the contact window of the P-type and N-type doped regions in one printing operation through a screen mask with a preset pattern. After printing, it is dried at 150°C for 3 minutes in a nitrogen atmosphere to simultaneously form the lattice fine gate layer 110 and the main gate layer 130.

[0121] Among them, the conductive silver paste is at 25℃ for 10 seconds. -1 The viscosity at the shear rate is 100 Pa·s, the thixotropic index is 5.0, and the solid content is 90%.

[0122] The fine gate layer 110 has a dot matrix structure consisting of discretely distributed circular dot units, each dot unit having a diameter of 80 μm and a center-to-center spacing of 120 μm between adjacent units. The dot matrix is ​​arranged in a linear gradient along a direction perpendicular to the main gate layer 130: in the cell center region furthest from the main gate layer 130, the diameter of the dot units increases to 100 μm and the center-to-center spacing decreases to 100 μm; in the region adjacent to the main gate layer 130, the diameter of the dot units decreases to 60 μm and the center-to-center spacing increases to 140 μm.

[0123] The lattice structure of the main gate layer 130 is composed of discretely distributed rectangular strip units. Each strip unit is 300 μm long and 150 μm wide, and the center-to-center distance between adjacent units is 100 μm. All strip units are equidistantly arranged along the extension direction of the main gate, with a density of 10 units / cm (i.e., 10 independent strip anchor points per unit length), which is significantly higher than the unit density of the fine gate layer 110 in the same length direction. The strip units intersect the fine gate layer 110 at strict perpendicular angles, and there is no physical connection in the intersection area, thus preserving complete discreteness.

[0124] 3. The dried silicon wafer is sintered in air at a low temperature of 400°C for 60 seconds to form an ohmic contact between the fine gate layer 110 and the silicon substrate 300.

[0125] 4. After sintering, the silicon wafer is immersed in a 2% sulfuric acid solution for 30 seconds to activate it and remove the oxide layer on the surface of the seed layer. Then, the composite seed layer is used as the cathode and the insoluble titanium mesh is used as the anode. The wafer is immersed in a copper electroplating solution and electroplated using a pulse reverse electroplating process for 10 minutes to form an integrated electroplated copper layer 200 with an average thickness of 10 μm.

[0126] The copper electroplating solution consists of: 80 g / L copper sulfate pentahydrate, 80 g / L sulfuric acid, 50 mg / L chloride ions, 10 mg / L sodium dithiopropane sulfonate, 200 mg / L polyethylene glycol, 20 mg / L tetrahydrozoline, and the remainder is pure water.

[0127] The parameters for pulse reverse electroplating are: forward current density 4A / dm³. 2 Pulse width 50ms; reverse current density -0.5A / dm 2 Pulse width 2ms; turn-off time 10ms.

[0128] Example 2 This embodiment provides a back-contact solar cell, which differs from Embodiment 1 only in that: the conductive units of the lattice fine grid layer 110 are short dashed lines with a length of 100 μm and a gap length of 200 μm between adjacent dashed lines; in the region far from the main grid, the linewidth of the short dashed lines is 60 μm, and in the region close to the main grid, the linewidth of the short dashed lines is 30 μm, with the linewidth changing linearly along the direction perpendicular to the main grid; the remaining structural and fabrication parameters are the same as in Embodiment 1.

[0129] Example 3 This embodiment provides a back-contact solar cell, which differs from Embodiment 1 in that: the main grid layer 130 is a high-density lattice structure, the lattice structure is circular with a diameter of 200 μm, the center-to-center spacing between adjacent units is 100 μm, and the arrangement density is higher than that of the fine grid layer 110; the remaining structure and fabrication parameters are the same as those in Embodiment 1.

[0130] Example 4 This embodiment provides a back-contact solar cell, which differs from Embodiment 1 only in that the contact window fabrication in step S1 uses a photolithography etching process, specifically: Photoresist was spin-coated onto the passivation film on the back side. The film was then exposed to ultraviolet light and developed using a mask with a contact window pattern. Subsequently, reactive ion etching was performed with CF4 / Ar as the etching gas, CF4 flow rate of 30 sccm, Ar flow rate of 10 sccm, chamber pressure of 10 Pa, RF power of 100 W, and etching time of 60 s to completely remove the passivation film not protected by the photoresist. Finally, the photoresist was stripped with acetone to complete the preparation of the contact window. The parameters for the remaining steps were the same as in Example 1.

[0131] Example 5 This embodiment provides a back-contact solar cell, which differs from Embodiment 1 only in the electroplating parameters of step S4, specifically: Forward current density 2A / dm 2 Pulse width 100ms; reverse current density -0.2A / dm 2 The pulse width was 5ms; the turn-off time was 20ms; the electroplating time was 20min, and the average thickness of the integrated electroplated copper layer was 20μm. The parameters of the remaining steps were the same as those in Example 1.

[0132] Comparative Example 1 This comparative example provides a back-contact solar cell, which differs from Example 1 only in that the lattice-shaped fine grid layer 110 and the main grid layer 130 are both continuous strip-shaped fine grid structures with a linewidth of 50 μm. The remaining structure and fabrication parameters are the same as in Example 1.

[0133] Comparative Example 2 This comparative example provides a back-contact solar cell, which differs from Example 1 only in that step 4 uses a conventional DC electroplating process with a current density of 4 A / dm². 2 The electroplating time was 10 minutes, and the parameters for the remaining steps were the same as in Example 1.

[0134] Test Example 1 The following performance tests were performed on the back-contact solar cells prepared in the above embodiments and comparative examples: 1. Contact resistivity test: Cut the battery into 1cm wide strips along the grid direction. Use the four-probe method to measure the sheet resistance of the metal electrodes in the P-type doped region and the N-type doped region respectively, and calculate the average contact resistivity in mΩ·cm. 2 .

[0135] 2. Photovoltaic performance test: Under AM1.5G standard spectrum, 1000W / m² light intensity, and 25℃ test temperature, the open circuit voltage Uoc (mV), series resistance Rs (mΩ), fill factor FF (%), and photoelectric conversion efficiency Eff (%) of the cell were tested using a solar cell IV tester.

[0136] 3. Welding tensile test: First, deposit a 1μm thick tin layer on the surface of the electroplated copper grid line, and then weld tin-plated solder strips on the PAD points of the main grid at a welding temperature of 320℃. Use a tensile testing machine to measure the force required to vertically peel the metal electrode from the silicon substrate 300. Take the average value of 10 PAD points, in N. The industry standard is ≥0.8N.

[0137] 4. Silver paste consumption test: The silver paste consumption per 10,000 batteries is calculated, in kg / 10,000 batteries.

[0138] The test results are shown in Table 1 below: Table 1

[0139] As can be seen from Table 1, in terms of silver paste consumption, the silver paste consumption of Examples 1-5 is 17-19 kg / 10,000 wafers, which is significantly lower than that of Comparative Example 1 (32 kg / 10,000 wafers), representing a reduction of 40.6%-46.9%, or an overall reduction of approximately 41%-47%. This data directly confirms that the gradient lattice gate structure effectively reduces the amount of precious metals used by significantly reducing the physical coverage area of ​​the precious metals, while ensuring effective ohmic contact between each discrete seed unit and the silicon doped region.

[0140] In terms of electrical performance, the contact resistivity and series resistance of Examples 1-5 are significantly better than those of Comparative Examples 1 and 2, indicating that the gradient discontinuous arrangement of the lattice structure can respond to the spatial gradient distribution of the transverse transport resistance of charge carriers inside the battery. The lattice density or size is increased in the high-resistivity region far from the main grid to improve the collection capability, and the lattice is moderately sparse in the low-resistivity region near the main grid to avoid redundant metal, thereby achieving spatial adaptive matching between the current collection capability and the silicon bulk resistance characteristics, effectively suppressing resistance loss.

[0141] In terms of photoelectric performance, the open-circuit voltage of Examples 1-5 all reached 730-734 mV, and the photoelectric conversion efficiency (Eff) was higher than 26.01%, reaching a maximum of 26.28%, which is 10-14 mV and 0.89-1.16 percentage points higher than that of Comparative Example 1, respectively. This improvement is due to the fact that the discrete contacts of the lattice significantly reduced the metal-silicon interface recombination area, while the three-dimensional coating of the copper layer on the lattice seeds and the metallurgical bonding optimized the interface charge transport characteristics, which jointly promoted the synergistic improvement of Uoc and Eff.

[0142] In terms of mechanical reliability, the welding pull force of Example 15 was 1.41-1.64 N, all of which far exceeded the industry standard of 0.8 N, while Comparative Example 2 was only 0.81 N. This comparison shows that the pulse reverse electroplating process used in this invention, combined with a specially formulated three-component additive system and gradient lattice anchoring structure, jointly promotes dense growth of copper layer, uniform thickness distribution and strong interfacial bonding, thereby giving the electrode excellent anti-peeling performance.

[0143] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A metallized electrode structure, characterized in that, Includes a gate structure and a copper layer embedded on the gate structure; The gate structure includes a gate line layer and a pad layer; The metal in the gate structure is arranged in a lattice structure.

2. The metallized electrode structure according to claim 1, characterized in that, The lattice structure is arranged in a gradient discontinuous manner; Preferably, the gate structure includes intersecting fine gate layers and main gate layers, as well as pad layers; Preferably, the lattice structure density of the fine gate layer is less than that of the main gate layer; Preferably, the dot matrix density of the pad layer is the same as that of the main gate layer; Preferably, the lattice structure of the fine gate layer includes a dotted structure or line segments; Preferably, the dot-like structure includes a circle, an ellipse, a rectangle, or a hexagon; Preferably, the length of the gap between adjacent line segments is greater than the length of the line segment itself; Preferably, the lattice structure of the main gate layer includes strips; Preferably, the crossing method includes perpendicular; Preferably, the size and / or spacing of the lattice structure of the fine gate layer are gradient-distributed along the direction perpendicular to the main gate layer; Preferably, in regions far from the main gate layer, the lattice structure of the fine gate layer is enlarged and / or the spacing is reduced; Preferably, in the region near the main gate layer, the lattice structure of the fine gate layer is reduced and / or the spacing is increased; Preferably, the material of the fine gate layer and / or the main gate layer includes silver or a silver alloy.

3. The metallized electrode structure according to claim 1, characterized in that, The upper surface of the copper layer continuously wraps around and embeds the gate structure, forming a continuous conductive network.

4. A back-contact solar cell, characterized in that, The device includes a silicon substrate, on the back side of which are provided alternating P-type doped regions and N-type doped regions, and metallized electrodes are independently disposed on the P-type doped regions and N-type doped regions respectively. The metallized electrode has the metallized electrode structure according to any one of claims 1 to 3.

5. A method for fabricating a back-contact solar cell, characterized in that, Includes the following steps: S1. Contact windows for P-type doped regions and N-type doped regions are opened on the passivation film on the back of the battery semi-finished product to expose the surface of the underlying silicon substrate. S2. A gate structure is formed, wherein the metal in the gate structure is arranged in a lattice structure; a copper layer is formed by electroplating on the gate structure.

6. The preparation method according to claim 5, characterized in that, The methods for creating contact windows for P-type and N-type doped regions include laser ablation or photolithography. Preferably, in the laser ablation, the wavelength of the laser is 266~1064nm, the pulse width is from nanosecond to femtosecond, the single pulse energy is 1~100μJ, the repetition frequency is 100~1000kHz, and the scanning speed is 100~2000mm / s; Preferably, the specific process of photolithography etching is as follows: first, photoresist is spin-coated on the back passivation film, then ultraviolet exposure and development are performed through a mask with a contact window pattern, then reactive ion etching is used, and finally the photoresist in the unetched area is stripped off to obtain the contact window; Preferably, in the reactive ion etching, the etching gas is CF4 and Ar; Preferably, the flow rate of CF4 is 20~50 sccm, and the flow rate of Ar is 5~15 sccm; Preferably, in the reactive ion etching, the etching is performed for 30-120 seconds under the conditions of a cavity pressure of 5-20 Pa and a radio frequency power of 50-150 W. Preferably, the contact window is used to form a dot matrix structure; Preferably, the accuracy error of the contact window is ±10μm.

7. The preparation method according to claim 5, characterized in that, The method of forming the grid structure includes screen printing, or PVD deposition with a mask, or printing etching paste after PVD deposition. Preferably, the preparation method further includes chemical cleaning or passivation treatment of the exposed silicon substrate after step S1 and before step S2.

8. The preparation method according to claim 5, characterized in that, The process includes activating the gate structure after it is formed and before electroplating. Preferably, the activation treatment involves immersing the battery cell in a 1-5% sulfuric acid or hydrochloric acid solution for 15-60 seconds. Preferably, the battery semi-finished product is a silicon wafer that has undergone texturing, diffusion, passivation and coating.

9. The preparation method according to any one of claims 5 to 8, characterized in that, The copper electroplating solution used in the electroplating process includes: copper sulfate pentahydrate 40~100 g / L, sulfuric acid 50~100 g / L, chloride ions 30~100 mg / L, sodium polydisulfide dipropane sulfonate 1~20 mg / L, polyethylene glycol or polypropylene glycol 50~500 mg / L, tetrahydrozoline 5~50 mg / L, and the balance being pure water.

10. The preparation method according to any one of claims 5 to 8, characterized in that, The electroplating process employs a pulsed reverse electroplating process, with the waveform cycle including: a forward pulse stage for driving copper deposition and lateral growth, a reverse pulse stage for micro-refining the deposited layer, and a turn-off stage for ensuring the entire growth process remains stable and uniform for tens of minutes. Preferably, the current density during the positive pulse phase is 2~6 A / dm. 2 Pulse width 10~100ms; reverse current density -1.0~-0.2 A / dm 2 Pulse width 1~5ms; turn-off time 0~20ms; Preferably, the electroplating time is 5 to 20 minutes; Preferably, the thickness of the copper layer is 5~20μm.

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