Light emitting chip substrate and preparation method thereof, display substrate and preparation method thereof

Abstract

The application discloses a light-emitting chip substrate and a preparation method thereof, a display substrate and a preparation method thereof, and relates to the technical field of display. The light-emitting chip substrate comprises a support substrate, a bonding support layer, a chip support layer and a plurality of light-emitting chips. The chip support layer comprises a plurality of chip support portions, a virtual connection portion and a connecting portion. The plurality of light-emitting chips in the light-emitting chip substrate are transferred to a driving backboard at one time, and the transfer efficiency is relatively high without multiple transfer.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a light-emitting chip substrate and its preparation method, and a display substrate and its preparation method. Background Technology

[0002] The display substrate includes a driving backplane and multiple light-emitting chips connected to the driving backplane. The driving backplane can provide driving signals to the light-emitting chips so that the light-emitting chips emit light, thereby realizing the display.

[0003] In related technologies, the display substrate includes multiple light-emitting chips that need to be transferred to the driving backplane in a mass transfer manner. Moreover, the number of chips transferred each time is small, so multiple transfers are required, resulting in low efficiency. Summary of the Invention

[0004] This application provides a light-emitting chip substrate and its fabrication method, as well as a display substrate and its fabrication method, which can solve the problem of low transfer efficiency. The technical solution is as follows:

[0005] On one hand, a light-emitting chip substrate is provided, the light-emitting chip substrate comprising:

[0006] Support substrate;

[0007] A bonding support layer located on one side of the supporting substrate, the bonding support layer being a first grid-like structure composed of multiple first grids;

[0008] A chip support layer located on the side of the bonding support layer away from the support substrate includes multiple chip support portions, dummy connections, and connecting portions. The multiple chip support portions and multiple first grids are correspondingly arranged. The orthographic projection of each chip support portion on the support substrate lies within the orthographic projection of the corresponding first grid on the support substrate. Each chip support portion corresponds to multiple dummy connections. One end of each dummy connection is connected to the corresponding chip support portion, and the other end is connected to the connecting portion. There is a gap between the chip support portions and the dummy connections and the support substrate. The connecting portion is a second grid-like structure composed of multiple second grids. The orthographic projection of the connecting portion on the support substrate overlaps with the orthographic projection of the bonding support layer on the support substrate, and the connecting portion is connected to the bonding support layer.

[0009] A plurality of light-emitting chips are located on the side of the chip support layer away from the support substrate and are disposed corresponding to the plurality of chip support portions. The orthographic projection of each light-emitting chip on the support substrate is located within the orthographic projection of the corresponding chip support portion on the support substrate. The area of ​​the orthographic projection of the chip support portion on the support substrate is larger than the area of ​​the orthographic projection of the light-emitting chip on the support substrate.

[0010] Optionally, the light-emitting chip is a vertically structured light-emitting chip; the chip support layer includes: a bonding metal layer and a reflective metal layer stacked along a direction away from the support substrate;

[0011] The portion of the bonding metal layer belonging to the connecting portion is used for bonding with the bonding support layer, and the portion of the reflective metal layer belonging to the chip support portion is used for reflecting the light emitted by the light-emitting chip.

[0012] Optionally, the light-emitting chip includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially stacked along a direction away from the supporting substrate;

[0013] The first semiconductor layer comprises P-type doped gallium nitride, the second semiconductor layer comprises N-type doped gallium nitride, and the light-emitting layer comprises a multi-quantum-well layer.

[0014] Optionally, the area of ​​the cross-section of the light-emitting chip on the surface parallel to the supporting substrate gradually decreases as the distance between the chip and the supporting substrate increases.

[0015] Optionally, the cross-sectional shape of the light-emitting chip is trapezoidal, and the cross-section is perpendicular to the surface of the supporting substrate;

[0016] The length of the trapezoid on the side furthest from the supporting substrate is less than the length of the trapezoid on the side closest to the supporting substrate.

[0017] Optionally, the light-emitting chip is a flip-chip light-emitting chip; the chip support layer includes a bonding metal layer;

[0018] The portion of the bonding metal layer belonging to the connecting portion is used for bonding connection with the bonding support layer.

[0019] Optionally, the light-emitting chip includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially stacked along a direction away from the supporting substrate; the first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum-well layer;

[0020] The light-emitting layer and the second semiconductor layer expose a portion of the first semiconductor layer. The light-emitting chip also includes a first electrode and a second electrode. The first electrode is electrically connected to the portion of the first semiconductor layer exposed by the light-emitting layer and the second semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer.

[0021] Optionally, the dummy connection portion is a strip-shaped structure, and the width of the dummy connection portion ranges from 3 micrometers to 10 micrometers.

[0022] Optionally, the shape of the second grid, the shape of the light-emitting chip, and the shape of the chip support are all square;

[0023] The side length of the second grid is 1.5 to 3 times the side length of the light-emitting chip;

[0024] The side length of the chip support is 1 to 2 times the side length of the light-emitting chip.

[0025] On the other hand, a display substrate is provided, the display substrate comprising:

[0026] A driving backplane includes a substrate, a driving unit layer, and a plurality of driving connection portions. The driving unit layer includes a plurality of driving units corresponding to the plurality of driving connection portions, and the driving connection portions are electrically connected to the driving units.

[0027] Multiple light-emitting chips are located on one side of the driving backplate, and the multiple light-emitting chips and the multiple driving connection portions are correspondingly arranged. Each light-emitting chip includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked sequentially in a direction away from the driving backplate. The first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum well layer.

[0028] And a chip support portion located between the light-emitting chip and the driving connection portion;

[0029] The display substrate includes a plurality of light-emitting chips that are bonded to a light-emitting chip substrate as described in any one of claims 1 to 9 and a driving backplane; the area of ​​the cross section of the light-emitting chip parallel to the reference plane gradually decreases as the distance between it and the driving backplane increases, and the reference plane is parallel to the surface of the driving unit layer near the driving connection portion.

[0030] The orthographic projection of the light-emitting chip on the reference plane is located within the orthographic projection of the chip support on the reference plane, and the area of ​​the orthographic projection of the chip support on the reference plane is larger than the area of ​​the orthographic projection of the light-emitting chip on the reference plane.

[0031] Optionally, the chip support includes a bonding metal layer and a reflective metal layer. The bonding metal layer is close to the driving connection relative to the reflective metal layer. The bonding metal layer in the chip support is connected to the driving connection. The reflective metal layer in the chip support is used to reflect the light emitted by the light-emitting chip.

[0032] In another aspect, a method for fabricating a light-emitting chip substrate is provided, the method comprising:

[0033] A plurality of light-emitting chip sub-substrates are obtained, wherein the light-emitting chip sub-substrates include a chip substrate, an epitaxial layer, and a chip support film;

[0034] A support substrate is obtained, the support substrate including a support substrate and a bonding support layer located on one side of the support substrate, the bonding support layer being a first grid structure composed of multiple first grids;

[0035] The chip support film in the plurality of light-emitting chip sub-substrates and the bonding support layer in the support substrate are bonded together;

[0036] Remove the chip substrate from the plurality of light-emitting chip sub-substrates;

[0037] The epitaxial layer in the plurality of light-emitting chip sub-substrates is patterned to obtain a plurality of light-emitting chips;

[0038] The chip support film is patterned to obtain a chip support layer, which includes multiple chip support portions, dummy connections, and connecting portions. The multiple chip support portions are correspondingly disposed with the multiple first grids and with the multiple light-emitting chips. The orthographic projection of each chip support portion on the support substrate lies within the orthographic projection of the corresponding first grid on the support substrate. The orthographic projection of each light-emitting chip on the support substrate lies within the orthographic projection of the corresponding chip support portion on the support substrate. The area of ​​the orthographic projection of each chip support portion on the support substrate is larger than the area of ​​the orthographic projection of the light-emitting chip on the support substrate. Each chip support portion corresponds to multiple dummy connections, one end of each dummy connection is connected to the corresponding chip support portion, and the other end is connected to the connecting portion. There is a gap between the chip support portions and the dummy connections and the support substrate. The connecting portion is a second grid structure composed of multiple second grids. The orthographic projection of the connecting portion on the support substrate overlaps with the orthographic projection of the bonding support layer on the support substrate, and the connecting portion is connected to the bonding support layer.

[0039] Optionally, the light-emitting chip is a vertically structured light-emitting chip; the chip support layer includes: a bonding metal layer and a reflective metal layer stacked along a direction away from the support substrate; the portion of the bonding metal layer belonging to the connection portion is used to bond with the bonding support layer, and the portion of the reflective metal layer belonging to the chip support portion is used to reflect the light emitted by the light-emitting chip;

[0040] The light-emitting chip includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in a direction away from the supporting substrate. The first semiconductor layer, the light-emitting layer, and the second semiconductor layer are stacked sequentially in a direction away from the supporting substrate. The first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum-well layer.

[0041] Optionally, the light-emitting chip is a flip-chip light-emitting chip; the chip support layer includes a bonding metal layer, which is used to bond to the bonding support layer.

[0042] The light-emitting chip includes a second semiconductor layer, a light-emitting layer, and a first semiconductor layer stacked sequentially along a direction away from the supporting substrate; the first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum-well layer;

[0043] The light-emitting layer and the second semiconductor layer expose a portion of the first semiconductor layer. The light-emitting chip also includes a first electrode and a second electrode. The first electrode is electrically connected to the portion of the first semiconductor layer exposed by the light-emitting layer and the second semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer.

[0044] In another aspect, a method for fabricating a display substrate is provided, the method comprising:

[0045] Obtain the light-emitting chip substrate as described above or obtain the light-emitting chip substrate prepared by the method described above, wherein the light-emitting chip substrate includes a plurality of light-emitting chips;

[0046] A driving backplane is obtained, the driving backplane including a substrate, a driving unit layer, and a plurality of driving connection portions, the driving unit layer including a plurality of driving units corresponding to the plurality of driving connection portions, and the driving connection portions and the driving units being electrically connected;

[0047] The light-emitting chip substrate is bonded to the driving backplate so that the driving connection portion is connected to the light-emitting chip.

[0048] Optionally, bonding the light-emitting chip substrate to the driving backplane includes:

[0049] A pickup chip substrate is obtained, the pickup chip substrate includes a pickup substrate and a plurality of pickup parts located on the pickup substrate, the number of pickup parts is less than or equal to the number of light-emitting chips in the light-emitting chip substrate, and the plurality of pickup parts correspond to at least a portion of the light-emitting chips in the light-emitting chip substrate;

[0050] The light-emitting chip substrate is bonded to the pickup chip substrate so as to pick up multiple light-emitting chips corresponding to the multiple pickup parts onto the pickup chip substrate;

[0051] The pickup chip substrate, which picks up multiple light-emitting chips, is bonded to the driving backplate.

[0052] The beneficial effects of the technical solution provided in this application include at least the following:

[0053] This application provides a light-emitting chip substrate and its fabrication method, as well as a display substrate and its fabrication method. The light-emitting chip substrate includes a support substrate, a bonding support layer, a chip support layer, and multiple light-emitting chips. The chip support layer includes multiple chip support portions, dummy connection portions, and connection portions. Multiple light-emitting chips in the light-emitting chip substrate are transferred to a driving backplane in a single operation, eliminating the need for multiple transfers and achieving high transfer efficiency. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a partial cross-sectional schematic diagram of a light-emitting chip substrate provided in an embodiment of this application;

[0056] Figure 2 This is a partial top view of a light-emitting chip substrate provided in an embodiment of this application;

[0057] Figure 3 This is a partial top view of a bonding support layer provided in an embodiment of this application;

[0058] Figure 4 This is a partial top view of a chip support layer provided in an embodiment of this application;

[0059] Figure 5 These are cross-sectional schematic diagrams and top views of a single light-emitting chip provided in the embodiments of this application;

[0060] Figure 6This is a partial cross-sectional schematic diagram of another light-emitting chip substrate provided in an embodiment of this application;

[0061] Figure 7 This is a partial cross-sectional schematic diagram of another light-emitting chip substrate provided in the embodiments of this application;

[0062] Figure 8 This is a partial cross-sectional schematic diagram of a display substrate provided in an embodiment of this application;

[0063] Figure 9 This is a flowchart illustrating a method for fabricating a light-emitting chip substrate according to an embodiment of this application;

[0064] Figure 10 This is a schematic diagram of a light-emitting chip sub-substrate provided in an embodiment of this application;

[0065] Figure 11 This is a schematic diagram of a support substrate provided in an embodiment of this application;

[0066] Figure 12 This is a schematic diagram of a support substrate and a light-emitting chip sub-substrate after bonding and connection according to an embodiment of this application;

[0067] Figure 13 This is a schematic diagram of a chip after the substrate has been removed, provided in an embodiment of this application;

[0068] Figure 14 This is a schematic diagram of an epitaxial layer after etching, provided in an embodiment of this application;

[0069] Figure 15 This is a schematic diagram of a current transport layer provided in an embodiment of this application;

[0070] Figure 16 This is a flowchart of another method for preparing a light-emitting chip substrate provided in an embodiment of this application;

[0071] Figure 17 This is a schematic diagram of another epitaxial layer after etching, provided in an embodiment of this application;

[0072] Figure 18 This is a schematic diagram of forming a first electrode and a second electrode according to an embodiment of this application;

[0073] Figure 19 This is a flowchart of a method for preparing a display substrate according to an embodiment of this application;

[0074] Figure 20 This is a schematic diagram of a drive backplane provided in an embodiment of this application;

[0075] Figure 21 This is a schematic diagram of a chip-picking substrate provided in an embodiment of this application;

[0076] Figure 22 This is a schematic diagram of a chip pickup substrate picking up a light-emitting chip according to an embodiment of this application;

[0077] Figure 23 This is a schematic diagram of forming a display substrate according to an embodiment of this application;

[0078] Figure 24 This is a schematic diagram of a bonding connection between a driving backplane and a light-emitting chip substrate provided in an embodiment of this application;

[0079] Figure 25 This is a partial cross-sectional schematic diagram of another display substrate provided in an embodiment of this application. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0081] The display market is currently booming, and with the continued increase in consumer demand for various display products such as laptops, smartphones, televisions, tablets, smartwatches, and fitness trackers, even more new display products will emerge in the future. Micro LED display technology has advantages such as low power consumption, high brightness, ultra-high resolution and color saturation, fast response speed, ultra-low power consumption, long lifespan, and high efficiency, and is considered to be the most competitive next-generation display technology.

[0082] Mass transfer technology for MicroLEDs is currently a hot topic of research and attention in the industry, typically achieved using methods such as stamping or fluid self-alignment. Due to the small size of epitaxial wafers, the number of light-emitting chips obtained from epitaxial wafers is also relatively small. When transferring the light-emitting chips to the driver backplane, the number of chips transferred in a single step is limited, requiring multiple transfers, resulting in low efficiency.

[0083] The small area of ​​a single transfer requires multiple transfers, making the efficient and low-cost transfer of LEDs onto the display substrate a current challenge in the MLED display field.

[0084] Figure 1 This is a partial cross-sectional schematic diagram of a light-emitting chip substrate provided in an embodiment of this application. Figure 2 This is a partial top view of a light-emitting chip substrate provided in an embodiment of this application. (Reference) Figure 1 and Figure 2As can be seen, the light-emitting chip substrate 100 includes: a supporting substrate 101, a bonding support layer 102, a chip support layer 103, and multiple light-emitting chips 104. Optionally, the supporting substrate 101 can be glass. The light-emitting chips 104 can be Micro LEDs.

[0085] Figure 3 This is a partial top view of a bonding support layer provided in an embodiment of this application. (Combined with...) Figure 1 and Figure 3 The bonding support layer 102 is located on one side of the support substrate 101, and the bonding support layer 102 can be a first grid-like structure composed of multiple first grids. Figure 3 The shape of the first grid can be a quadrilateral, such as a square.

[0086] refer to Figure 1 The chip support layer 103 is located on the side of the bonding support layer 102 away from the support substrate 101. Figure 4 This is a partial top view of a chip support layer provided in an embodiment of this application. (Reference) Figure 4 As can be seen, the chip support layer 103 includes multiple chip support portions 1031, dummy connection portions 1032, and connection portions 1033.

[0087] Multiple chip support portions 1031 and multiple first grids are correspondingly arranged, and the orthographic projection of the chip support portion 1031 on the support substrate 101 lies within the orthographic projection of the corresponding first grid on the support substrate 101. Each chip support portion 1031 has multiple dummy connections 1032, one end of each dummy connection 1032 is connected to the corresponding chip support portion 1031, and the other end is connected to the connecting portion 1033. There is a gap between the chip support portion 1031 and the dummy connection portion 1032 and the support substrate 101. For example... Figure 3 and Figure 4 In the middle, each chip support part 1031 has four virtual connection parts 1032.

[0088] The connecting portion 1033 is a second mesh structure composed of multiple second meshes, and the shape and size of the second mesh structure are matched with those of the first mesh structure. The orthographic projection of the connecting portion 1033 on the supporting substrate 101 overlaps with the orthographic projection of the bonding support layer 102 on the supporting substrate 101, and the connecting portion 1033 and the bonding support layer 102 are connected.

[0089] In this embodiment, since the bonding support layer 102 has a certain height and is connected to the connecting portion 1033, the chip support portion 1031 and the dummy connection portion 1032, which are not connected to the bonding support layer 102, are spaced apart from the supporting substrate 101 due to the presence of the bonding support layer 102. That is, the chip support portion 1031 and the dummy connection portion 1032 are suspended relative to the supporting substrate 101.

[0090] Combination Figure 1 and Figure 2 Multiple light-emitting chips 104 are located on the side of the chip support layer 103 away from the support substrate 101, and are correspondingly arranged with multiple chip support portions 1031. The orthographic projection of each light-emitting chip 104 on the support substrate 101 lies within the orthographic projection of the corresponding chip support portion 1031 on the support substrate 101, and the area of ​​the orthographic projection of the chip support portion 1031 on the support substrate 101 is larger than the area of ​​the orthographic projection of the light-emitting chip 104 on the support substrate 101.

[0091] In this embodiment, the chip support portion 1031 can serve as a bonding pad for subsequent bonding of the light-emitting chip 104 and the driving backplane 201. Since the chip support portion 1031 has a large area, the bonding difficulty during subsequent bonding of the light-emitting chip 104 and the driving backplane 201 can be reduced.

[0092] Furthermore, the support substrate 101 in the light-emitting chip substrate can correspond to the driving backplate 201. Therefore, when transferring the light-emitting chips 104 in the light-emitting chip substrate to the driving backplate 201, multiple light-emitting chips 104 can be transferred to the driving backplate 201 at once, eliminating the need for multiple transfers and resulting in high transfer efficiency. During the transfer of multiple light-emitting chips 104 to the driving backplate 201, the detached connection portion 1032 can break under the transfer pressure, thereby separating the chip support portion 1031 and the connecting portion 1033. After the light-emitting chips 104 are transferred to the driving backplate 201, the support substrate 101 and the bonding support layer 102 connected to the connecting portion 1033 are removed.

[0093] In summary, this application provides a light-emitting chip substrate, which includes a support substrate, a bonding support layer, a chip support layer, and multiple light-emitting chips. The chip support layer includes multiple chip support portions, dummy connection portions, and connection portions. Multiple light-emitting chips in the light-emitting chip substrate are transferred to the driving backplane in a single transfer, eliminating the need for multiple transfers and achieving high transfer efficiency.

[0094] In this embodiment, the dummy connection portion 1032 can be a strip-shaped structure, and the width of the dummy connection portion 1032 can range from 3μm to 10μm. This width range of the dummy connection portion 1032 can ensure that the dummy connection portion 1032 can break when the light-emitting chip 104 and the driving backplate 201 are bonded, so as to separate the chip support portion 1031 and the connecting portion 1033.

[0095] Optionally, the shapes of the second grid, the light-emitting chip 104, and the chip support 1031 can all be square. Furthermore, the centers of the orthographic projections of the second grid onto the support substrate 101, the centers of the orthographic projections of the light-emitting chip 104 onto the support substrate 101, and the centers of the orthographic projections of the chip support 1031 onto the support substrate 101 can overlap.

[0096] Optional, see reference Figure 5 The side length d3 of the second grid is 1.5 to 3 times the side length d1 of the light-emitting chip 104. For example, the side length d3 of the second grid can be 2 or 2.5 times the side length d1 of the light-emitting chip 104. The side length d2 of the chip support portion 1031 can be 1 to 2 times the side length d1 of the light-emitting chip 104. For example, the side length d2 of the chip support portion 1031 can be 1.5 times the side length d1 of the light-emitting chip 104.

[0097] In the embodiments of this application, the first grid and the second grid can be squares, rectangles, or other polygons. The embodiments of this application do not limit the shape of the first grid and the second grid.

[0098] refer to Figure 5 It can be seen that each chip support portion 1031 can correspond to four dummy connection portions 1032. The four dummy connection portions 1032 correspond to the four corners of the square respectively. One end of each dummy connection portion 1032 is connected to a corner of a second grid of the connecting portion 1033, and the other end is connected to a corner of the chip support portion 1031.

[0099] Of course, each chip support portion 1031 may correspond to other numbers of dummy connections 1032, and the connection positions of the dummy connections 1032 may also be adjusted appropriately. For example, one end of the dummy connection 1032 may be connected to the edge of a grid of the connecting portion 1033, and the other end may be connected to the edge of the chip support portion 1031. This application embodiment does not specifically limit the number of dummy connections 1032 corresponding to the chip support portion 1031, nor the connection positions of the dummy connections 1032.

[0100] As an optional implementation, refer to Figures 1 to 5The light-emitting chip 104 is a vertically structured light-emitting chip 104. The chip support layer 103 includes a bonding metal layer a1 and a reflective metal layer a2 stacked along a direction away from the support substrate 101. The portion of the bonding metal layer a1 belonging to the connection portion 1033 is used for bonding with the bonding support layer 102. For example, when the portion of the bonding metal layer a1 belonging to the connection portion 1033 is bonded with the bonding support layer 102, an intermetallic compound (IMC) can be formed. The portion of the reflective metal layer a2 belonging to the chip support portion 1031 is used to reflect the light emitted by the light-emitting chip 104, thereby improving the luminous efficiency of the light-emitting chip 104 and improving the light extraction utilization rate of the light-emitting chip.

[0101] Optionally, the bonding metal layer a1 and the reflective metal layer a2 can be prepared by sputtering, electroplating, or evaporation. The thickness of the bonding metal layer a1 can range from 1 μm to 3 μm, and the thickness of the reflective metal layer a2 can range from 100 nm to 500 nm.

[0102] Optionally, the material of the bonding metal layer a1 can be at least one of silver (Ag), copper (Cu), and gold (Au). The bonding support layer 102 and the bonding metal layer a1 are bonded together. The bonding support layer 102 may include two stacked bonding materials. The bonding material closer to the support substrate 101 can be at least one of silver (Ag), copper (Cu), and gold (Au), and the bonding material farther from the support substrate 101 can be at least one of indium (In) and tin (Sn).

[0103] Optionally, the bonding material near the support substrate 101 can be the same material as the bonding metal layer a1, or it can be a different material. Furthermore, the material of the bonding metal layer a1 (or the bonding material of the bonding support layer 102 near the support substrate 101) and the bonding material of the bonding support layer 102 near the support substrate 101 can be arbitrarily combined.

[0104] Optionally, the material of the reflective metal layer a2 can be a metal material with high reflectivity, such as aluminum (Al) and silver (Ag), and preferably silver.

[0105] Figure 6 This is a partial cross-sectional schematic diagram of another light-emitting substrate provided in an embodiment of this application. (Reference) Figure 6The light-emitting chip 104 includes a first semiconductor layer 1041, a light-emitting layer 1042, and a second semiconductor layer 1043 sequentially stacked along a direction away from the supporting substrate 101. The first semiconductor layer 1041 comprises P-type doped gallium nitride (GaN), and can be referred to as P-GaN. The second semiconductor layer 1043 comprises N-type doped gallium nitride, and can be referred to as N-GaN. The light-emitting layer 1042 comprises a multiple quantum well (MQW) layer.

[0106] That is, in the light-emitting chip substrate 100, the first semiconductor layer 1041 (P-GaN) is closer to the supporting substrate 101 than the second semiconductor layer 1043 (N-GaN). In this case, the first semiconductor layer 1041 can be connected to the driving unit in the driving backplane 201 via the chip support portion 1031 (bonding pad), thereby enabling the driving unit to provide a driving signal to the first semiconductor layer 1041. In addition, after the light-emitting chips 104 are bonded to the driving backplane 201 to obtain the display substrate, the second semiconductor layers 1043 of the multiple light-emitting chips 104 can be connected to the common electrode in the driving backplane 201, thereby enabling the driving backplane 201 to provide a common signal to the second semiconductor layers 1043 of the multiple light-emitting chips 104.

[0107] In this embodiment, the first semiconductor layer 1041, the light-emitting layer 1042, and the second semiconductor layer 1043 of the plurality of light-emitting chips 104 in the light-emitting chip substrate 100 are obtained by etching the first semiconductor thin film b21, the light-emitting thin film b22, and the second semiconductor thin film b23 on the side of the chip support layer 103 away from the support substrate 101 after the bonding support layer 102 and the chip support layer 103 are connected. Since the second semiconductor thin film b23 is further away from the support substrate 101, it is etched first during the etching process, followed by the sequential etching of the light-emitting thin film b22 and the first semiconductor thin film b21.

[0108] Due to the inherent limitations of the etching process, the first thin film etched will have a smaller size, while the last thin film etched will have a larger size. Therefore, the area of ​​the cross-section of the light-emitting chip 104 parallel to the surface of the support substrate 101 gradually decreases as the distance between the chip and the support substrate 101 increases.

[0109] Optionally, the orthographic projection of the second semiconductor layer 1043 onto the supporting substrate 101 lies within the orthographic projection of the light-emitting layer 1042 onto the supporting substrate 101, and the area of ​​the orthographic projection of the second semiconductor layer 1043 onto the supporting substrate 101 is smaller than the area of ​​the orthographic projection of the light-emitting layer 1042 onto the supporting substrate 101. The orthographic projection of the light-emitting layer 1042 onto the supporting substrate 101 lies within the orthographic projection of the first semiconductor layer 1041 onto the supporting substrate 101, and the area of ​​the orthographic projection of the light-emitting layer 1042 onto the supporting substrate 101 is smaller than the area of ​​the orthographic projection of the first semiconductor layer 1041 onto the supporting substrate 101.

[0110] refer to Figure 6 The light-emitting chip 104 has a trapezoidal cross-section, which is perpendicular to the surface of the supporting substrate 101. The length of the side of the trapezoid away from the supporting substrate 101 is less than the length of the side of the trapezoid closer to the supporting substrate 101. In this case, after the light-emitting chip 104 is bonded to the driving backplane 201 via the chip support portion 1031 (bonding pad), the shape of the light-emitting chip 104 relative to the driving backplane 201 is a positive trapezoid.

[0111] refer to Figure 1 and Figure 6 The light-emitting chip substrate 100 also includes a current transport layer 105 formed on the side of the second semiconductor layer 1043 located away from the supporting substrate 101. The material of the current transport layer 105 can be indium tin oxide (ITO). The current transport layer 105 can also be referred to as a transparent electrode.

[0112] As another alternative implementation, refer to Figure 7 The light-emitting chip 104 can be a flip-chip structure light-emitting chip 104. The chip support layer 103 may include a bonding metal layer a1, and the portion of the bonding metal layer a1 belonging to the connection portion 1033 is used for bonding with the bonding support layer 102. For example, when the portion of the bonding metal layer a1 belonging to the connection portion 1033 is bonded with the bonding support layer 102, an intermetallic compound (IMC) can be formed.

[0113] Optionally, the bonding metal layer a1 and the reflective metal layer a2 can be prepared by sputtering, electroplating, or evaporation. The thickness of the bonding metal layer a1 can range from 1 μm to 3 μm, and the thickness of the reflective metal layer a2 can range from 100 nm to 500 nm.

[0114] Optionally, the bonding metal layer a1 can be made of at least one of silver (Ag), copper (Cu), and gold (Au). The bonding support layer 102 and the bonding metal layer a1 are bonded together, and the bonding support layer 102 can be made of at least one of indium (In) and tin (Sn). Furthermore, the materials of the bonding metal layer a1 and the bonding support layer 102 can be arbitrarily combined.

[0115] refer to Figure 7 The light-emitting chip 104 includes a first semiconductor layer 1041, a light-emitting layer 1042, and a second semiconductor layer 1043, sequentially stacked along a direction away from the supporting substrate 101. The first semiconductor layer 1041 includes P-type doped gallium nitride (GaN), and can be referred to as P-GaN. The second semiconductor layer 1043 includes N-type doped gallium nitride, and can be referred to as N-GaN. The light-emitting layer 1042 includes a multiple quantum well (MQW) layer. That is, in the light-emitting chip substrate 100, the first semiconductor layer 1041 (P-GaN) is closer to the supporting substrate 101 than the second semiconductor layer 1043 (N-GaN).

[0116] refer to Figure 7 The light-emitting layer 1042 and the second semiconductor layer 1043 may expose a portion of the first semiconductor layer 1041. The light-emitting chip 104 may also include a first electrode 1044 and a second electrode 1045. The first electrode 1044 and the portion of the first semiconductor layer 1041 exposed by the light-emitting layer 1042 and the second semiconductor layer 1043 are electrically connected, and the second electrode 1045 and the second semiconductor layer 1043 are electrically connected.

[0117] In this configuration, the first semiconductor layer 1041 can be connected to the driving unit in the driving backplane 201 via the first electrode 1044, thereby enabling the driving unit to provide a driving signal to the first semiconductor layer 1041. The second semiconductor layer 1043 is connected to the common electrode in the driving backplane 201 via the second electrode 1045, thereby enabling the driving backplane 201 to provide a common signal to the second semiconductor layer 1043 of the plurality of light-emitting chips 104. Furthermore, after the light-emitting chips 104 are bonded to the driving backplane 201 to obtain the display substrate, the chip support portion 1031 on the side of the first semiconductor layer 1041 away from the light-emitting layer 1042 can be removed.

[0118] If the light-emitting chip is a flip-chip structure, the second semiconductor layer 1043, the light-emitting layer 1042, and the first semiconductor layer 1041 in the light-emitting chip 104 are stacked sequentially in a direction away from the supporting substrate 101. The first semiconductor layer 1041 includes P-type doped gallium nitride (GaN), and can be referred to as P-GaN. The second semiconductor layer 1043 includes N-type doped gallium nitride, and can be referred to as N-GaN. The light-emitting layer 1042 includes a multiple quantum well (MQW) layer. That is, in the light-emitting chip substrate 100, the first semiconductor layer 1041 (P-GaN) is further away from the supporting substrate 101 than the second semiconductor layer 1043 (N-GaN).

[0119] In summary, this application provides a light-emitting chip substrate, which includes a support substrate, a bonding support layer, a chip support layer, and multiple light-emitting chips. The chip support layer includes multiple chip support portions, dummy connection portions, and connection portions. Multiple light-emitting chips in the light-emitting chip substrate are transferred to the driving backplane in a single transfer, eliminating the need for multiple transfers and achieving high transfer efficiency.

[0120] Figure 8 This is a partial cross-sectional schematic diagram of a display substrate provided in an embodiment of this application. The display substrate can be obtained by transferring multiple light-emitting chips 104 from the light-emitting chip substrate provided in the above embodiment to the driving backplane 201. (Reference) Figure 8 The display substrate 200 includes a driving backplate 201 and a plurality of light-emitting chips 104 located on one side of the driving backplate 201. The plurality of light-emitting chips 104 included in the display substrate 200 can be obtained by bonding the light-emitting chip substrate and the driving backplate 201 based on the above embodiments.

[0121] The driving backplane 201 includes a substrate 2011, a driving unit layer 2012, and a plurality of driving connection portions 2013. The driving unit layer 2012 includes a plurality of driving units corresponding to the plurality of driving connection portions 2013, and the driving connection portions 2013 are electrically connected to the driving units. Optionally, the substrate 2011 may be glass.

[0122] Optionally, the drive connection portion 2013 includes two layers of bonding material stacked together. The bonding material closer to the substrate 2011 can be at least one of silver (Ag), copper (Cu), and gold (Au), and the bonding material farther away from the substrate 2011 can be at least one of indium (In) and tin (Sn).

[0123] Multiple light-emitting chips 104 are located on one side of the driving backplate 201, and the multiple light-emitting chips 104 and multiple driving connection portions 2013 are correspondingly arranged. Each light-emitting chip 104 includes a first semiconductor layer 1041, a light-emitting layer 1042, and a second semiconductor layer 1043, sequentially stacked along a direction away from the driving backplate 201. The first semiconductor layer 1041 includes P-type doped gallium nitride (GaN), and can be referred to as P-GaN. The second semiconductor layer 1043 includes N-type doped gallium nitride, and can be referred to as N-GaN. The light-emitting layer 1042 includes a multiple quantum well (MQW) layer. That is, in the display substrate 200, the first semiconductor layer 1041 (P-GaN) is closer to the driving backplate 201 than the second semiconductor layer 1043 (N-GaN).

[0124] In the case where the light-emitting chip 104 is a vertically structured light-emitting chip 104, refer to Figure 8 The display substrate also includes a chip support portion 1031 located between the light-emitting chip 104 and the driving connection portion 2013. The area of ​​the cross-section of the light-emitting chip 104 parallel to the reference plane gradually decreases as the distance between it and the driving backplate 201 increases. The reference plane is parallel to the surface of the driving unit layer 2012 near the driving connection portion 2013. The orthographic projection of the light-emitting chip 104 on the reference plane lies within the orthographic projection of the chip support portion 1031 on the reference plane, and the area of ​​the orthographic projection of the chip support portion 1031 on the reference plane is larger than the area of ​​the orthographic projection of the light-emitting chip 104 on the reference plane.

[0125] That is, the chip support portion 1031 can serve as a bonding pad when bonding the light-emitting chip 104 and the driving backplane 201. Since the chip support portion 1031 has a large area, the bonding difficulty of the subsequent bonding of the light-emitting chip 104 and the driving backplane 201 can be reduced.

[0126] Optionally, the chip support portion 1031 includes a bonding metal layer a1 and a reflective metal layer a2. The bonding metal layer a1 is closer to the driving connection portion 2013 than the reflective metal layer a2. The bonding metal layer a1 in the chip support portion 1031 is connected to the driving connection portion 2013, and the reflective metal layer a2 in the chip support portion 1031 is used to reflect the light emitted by the light-emitting chip 104.

[0127] In summary, the embodiments of this application provide a display substrate, which includes a driving backplane and multiple light-emitting chips. The multiple light-emitting chips can be transferred from the light-emitting chip substrate to the driving backplane in one step, eliminating the need for multiple transfers and achieving high transfer efficiency.

[0128] Figure 9This is a flowchart illustrating a method for fabricating a light-emitting chip substrate according to an embodiment of this application. Taking a vertically structured light-emitting chip 104 as an example. (See reference...) Figure 9 The method includes:

[0129] Step S101: Obtain multiple light-emitting chip sub-substrates.

[0130] In the embodiments of this application, reference is made to Figure 10 The light-emitting chip sub-substrate may include a chip substrate b1, an epitaxial layer b2, and a chip support film b3. The chip substrate b1 and epitaxial layer b2 in the light-emitting chip sub-substrate may be epitaxial wafers on a silicon-based (or sapphire) substrate. The light-emitting chip sub-substrate may be based on an epitaxial wafer on which a chip support film b3 is fabricated.

[0131] Optionally, the epitaxial layer b2 may include a second semiconductor thin film b23, a light-emitting thin film b22, and a first semiconductor thin film b21 sequentially stacked along a direction away from the chip substrate b1. The first semiconductor thin film b21 includes P-type doped gallium nitride, the second semiconductor thin film b23 includes N-type doped gallium nitride, and the light-emitting thin film b22 includes a multiple quantum well (MQW) thin film. Specifically, the first semiconductor thin film b21 forms the first semiconductor layer 1041 in the light-emitting chip 104, the second semiconductor thin film b23 forms the second semiconductor layer 1043 in the light-emitting chip 104, and the light-emitting thin film b22 forms the light-emitting layer 1042 in the light-emitting chip 104.

[0132] Optionally, the chip support film b3 may include a reflective metal film b32 and a bonding metal film b31 stacked along a direction away from the chip substrate b1. The bonding metal film b31 and the reflective metal film b32 may be prepared by sputtering, electroplating, or evaporation. The thickness of the bonding metal film b31 may range from 1 μm to 3 μm, and the thickness of the reflective metal film b32 may range from 100 nm to 500 nm.

[0133] The reflective metal film b32 can be made of a highly reflective metal material, such as at least one of aluminum (Al) and silver (Ag), with silver being the preferred material. The bonding metal film b31 can be made of at least one of silver (Ag), copper (Cu), and gold (Au).

[0134] Step S102: Obtain the support substrate.

[0135] refer to Figure 11The supporting substrate includes a supporting substrate 101 and a bonding supporting layer 102 located on one side of the supporting substrate 101. The bonding supporting layer 102 is a first grid-like structure composed of multiple first grids. The area of ​​the supporting substrate 101 can be larger than the area of ​​the light-emitting chip sub-substrate. Optionally, the supporting substrate 101 can be glass.

[0136] Optionally, the support substrate can be a mesh-like bonded support layer 102 prepared on glass by electroplating, sputtering, or lift-off.

[0137] Step S103: Bond the chip support film in the multiple light-emitting chip sub-substrates and the bonding support layer in the support substrate together.

[0138] In the embodiments of this application, reference is made to Figure 12 Multiple light-emitting chip sub-substrates can be hot-pressed to a support substrate using a bonding device. During the hot-pressing process, the bonding support layer 102 in the support substrate reacts with the bonding metal film b31 in the light-emitting chip sub-substrates to generate an IMC intermetallic compound.

[0139] Optionally, the support substrate 101 can be used to bond multiple light-emitting chip sub-substrates. The bonding metal film b31 and the bonding support layer 102 in the chip support film b3 are bonded together, and the material of the bonding support film can be at least one of indium (In) and tin (Sn). Furthermore, the materials of the bonding metal film b31 and the bonding support layer 102 can be arbitrarily combined.

[0140] The portion of the bonding metal thin film b31 that is directly bonded to the bonding support layer 102 can be the connection portion 1033 in the chip support layer 103 of the light-emitting chip substrate.

[0141] In this embodiment, a grid-like bonding support layer 102 is prepared on the support substrate 101. The bonding support layer 102 is regionally bonded to the entire surface of the epitaxial wafer, which solves the problem of wafer cracking caused by stress after the epitaxial layer is transferred to the glass substrate.

[0142] Step S104: Remove the chip substrate from the multiple light-emitting chip sub-substrates.

[0143] refer to Figure 13 The chip substrate b1 in the light-emitting chip sub-substrate was removed, exposing the epitaxial layer b2 in the light-emitting chip sub-substrate.

[0144] When the chip substrate b1 in the light-emitting chip sub-substrate is a silicon-based substrate, it can be removed by silicon etching. When the chip substrate b1 in the light-emitting chip sub-substrate is sapphire, it can be removed by laser lift-off (LLO).

[0145] Step S105: Pattern the epitaxial layer in the multiple light-emitting chip sub-substrates to obtain multiple light-emitting chips.

[0146] In this embodiment, an inductively coupled plasma (ICP) dry etching apparatus can be used to pattern the epitaxial layer b2 to obtain a first semiconductor layer 1041, a light-emitting layer 1042, and a second semiconductor layer 1043 of multiple light-emitting chips 104. (See reference...) Figure 14 The first semiconductor layer 1041, the light-emitting layer 1042, and the second semiconductor layer 1043 are sequentially stacked along a direction away from the supporting substrate 101. The first semiconductor layer 1041 includes P-type doped gallium nitride, the second semiconductor layer 1043 includes N-type doped gallium nitride, and the light-emitting thin film b22 includes a multiple quantum well (MQW) layer.

[0147] During the etching process, the second semiconductor thin film b23 is etched first, followed by the light-emitting thin film b22 and the first semiconductor thin film b21. Due to the inherent characteristics of the etching process, the first film etched will have a smaller size, while the last film etched will have a larger size. Therefore, the area of ​​the cross-section of the light-emitting chip 104 parallel to the surface of the supporting substrate 101 gradually decreases as the distance between the chip and the supporting substrate 101 increases.

[0148] Optionally, the orthographic projection of the second semiconductor layer 1043 onto the supporting substrate 101 lies within the orthographic projection of the light-emitting layer 1042 onto the supporting substrate 101, and the area of ​​the orthographic projection of the second semiconductor layer 1043 onto the supporting substrate 101 is smaller than the area of ​​the orthographic projection of the light-emitting layer 1042 onto the supporting substrate 101. The orthographic projection of the light-emitting layer 1042 onto the supporting substrate 101 lies within the orthographic projection of the first semiconductor layer 1041 onto the supporting substrate 101, and the area of ​​the orthographic projection of the light-emitting layer 1042 onto the supporting substrate 101 is smaller than the area of ​​the orthographic projection of the first semiconductor layer 1041 onto the supporting substrate 101.

[0149] In the embodiments of this application, reference is made to Figure 15 After etching the epitaxial layer b2, a current transport layer can be formed on the side of the second semiconductor layer 1043 of the light-emitting chip 104 away from the supporting substrate 101. The material of the current transport layer can be indium tin oxide (ITO). The current transport layer can also be called a transparent electrode.

[0150] Step S106: Pattern the chip support film to obtain the chip support layer.

[0151] In this embodiment, the chip support film b3 can be patterned using exposure, development, and etching methods. (See reference...) Figure 6 The patterned chip support layer 103 includes multiple chip support portions 1031, dummy connection portions 1032, and connecting portions 1033. The multiple chip support portions 1031 are correspondingly arranged with multiple first grids and with multiple light-emitting chips 104. The orthographic projection of the chip support portion 1031 onto the support substrate 101 lies within the orthographic projection of the corresponding first grid onto the support substrate 101. The orthographic projection of each light-emitting chip 104 onto the support substrate 101 lies within the orthographic projection of the corresponding chip support portion 1031 onto the support substrate 101. The area of ​​the orthographic projection of the chip support portion 1031 onto the support substrate 101 is larger than the area of ​​the orthographic projection of the light-emitting chip 104 onto the support substrate 101.

[0152] Each chip support portion 1031 has a plurality of dummy connections 1032. One end of each dummy connection 1032 is connected to the corresponding chip support portion 1031, and the other end is connected to the connecting portion 1033. There is a gap between the chip support portion 1031 and the dummy connections 1032 and the support substrate 101. The connecting portion 1033 is a second grid structure composed of a plurality of second grids. The orthographic projection of the connecting portion 1033 on the support substrate 101 overlaps with the orthographic projection of the bonding support layer 102 on the support substrate 101, and the connecting portion 1033 is connected to the bonding support layer 102.

[0153] Figure 16 This is a flowchart illustrating a method for fabricating a light-emitting chip substrate according to an embodiment of this application. Taking a flip-chip light-emitting chip 104 as an example. (See reference...) Figure 16 The method includes:

[0154] Step S201: Obtain multiple light-emitting chip sub-substrates.

[0155] In the embodiments of this application, reference is made to Figure 10 The light-emitting chip sub-substrate may include a chip substrate b1, an epitaxial layer b2, and a chip support film b3. The chip substrate b1 and epitaxial layer b2 in the light-emitting chip sub-substrate may be epitaxial wafers on a silicon-based (or sapphire) substrate. The light-emitting chip sub-substrate may be based on an epitaxial wafer on which a chip support film b3 is fabricated.

[0156] Optionally, the epitaxial layer b2 may include a second semiconductor thin film b23, a light-emitting thin film b22, and a first semiconductor thin film b21 sequentially stacked along a direction away from the chip substrate b1. The first semiconductor thin film b21 includes P-type doped gallium nitride, the second semiconductor thin film b23 includes N-type doped gallium nitride, and the light-emitting thin film b22 includes a multiple quantum well (MQW) thin film. Specifically, the first semiconductor thin film b21 forms the first semiconductor layer 1041 in the light-emitting chip 104, the second semiconductor thin film b23 forms the second semiconductor layer 1043 in the light-emitting chip 104, and the light-emitting thin film b22 forms the light-emitting layer 1042 in the light-emitting chip 104.

[0157] Optionally, the chip support film b3 may include a bonding metal film b31. The bonding metal film b31 and the reflective metal film b32 may be sputtered. Sputter It can be prepared by electroplating or vapor deposition. The thickness of the bonded metal thin film b31 can range from 1 μm to 3 μm.

[0158] Step S202: Obtain the support substrate.

[0159] refer to Figure 11 The supporting substrate includes a supporting substrate 101 and a bonding supporting layer 102 located on one side of the supporting substrate 101. The bonding supporting layer 102 is a first grid-like structure composed of multiple first grids. The area of ​​the supporting substrate 101 can be larger than the area of ​​the light-emitting chip sub-substrate. Optionally, the supporting substrate 101 can be glass.

[0160] Optionally, the support substrate can be a mesh-like bonded support layer 102 prepared on glass by electroplating, sputtering, or lift-off.

[0161] Optionally, the order of steps S202 and S201 can be interchanged.

[0162] Step S203: Bond the chip support film in the multiple light-emitting chip sub-substrates and the bonding support layer in the support substrate together.

[0163] In the embodiments of this application, reference is made to Figure 12 Multiple light-emitting chip sub-substrates can be hot-pressed to a support substrate using a bonding device. During the hot-pressing process, the bonding support layer 102 in the support substrate reacts with the bonding metal film b31 in the light-emitting chip sub-substrates to generate an IMC intermetallic compound.

[0164] Optionally, the support substrate 101 can be used to bond multiple light-emitting chip sub-substrates. The bonding metal film b31 and the bonding support layer 102 in the chip support film b3 are bonded together, and the material of the bonding support film can be at least one of indium (In) and tin (Sn). Furthermore, the materials of the bonding metal film b31 and the bonding support layer 102 can be arbitrarily combined.

[0165] The portion of the bonding metal thin film b31 directly bonded to the bonding support layer 102 can be the connection portion 1033 in the chip support layer 103 of the light-emitting chip substrate. In this embodiment, a grid-like bonding support layer 102 is prepared on the support substrate 101, and the bonding support layer 102 is regionally bonded to the entire surface of the epitaxial wafer, solving the problem of wafer cracking caused by stress after the epitaxial layer is transferred to the glass substrate.

[0166] Step S204: Remove the chip substrate from the multiple light-emitting chip sub-substrates.

[0167] refer to Figure 13 The chip substrate b1 in the light-emitting chip sub-substrate was removed, exposing the epitaxial layer b2 in the light-emitting chip sub-substrate.

[0168] When the chip substrate b1 in the light-emitting chip sub-substrate is a silicon-based substrate, it can be removed by silicon etching. When the chip substrate b1 in the light-emitting chip sub-substrate is sapphire, it can be removed by laser lift-off (LLO).

[0169] Step S205: Pattern the epitaxial layer in the multiple light-emitting chip sub-substrates to obtain multiple light-emitting chips.

[0170] In this embodiment, an inductively coupled plasma (ICP) dry etching apparatus can be used to pattern the epitaxial layer b2 to obtain a first semiconductor layer 1041, a light-emitting layer 1042, and a second semiconductor layer 1043 of multiple light-emitting chips 104. (Referring to...) Figure 17 A first semiconductor layer 1041, a light-emitting layer 1042, and a second semiconductor layer 1043 are sequentially stacked in a direction away from the supporting substrate 101. The first semiconductor layer 1041 comprises P-type doped gallium nitride, the second semiconductor layer 1043 comprises N-type doped gallium nitride, and the light-emitting thin film b22 comprises a multiple quantum well (MQW) layer. The light-emitting layer 1042 and the second semiconductor layer 1043 expose a portion of the first semiconductor layer 1041.

[0171] Afterwards, refer to Figure 18The first electrode 1044 and the second electrode 1045 of the light-emitting chip 104 can be formed using metal deposition (DEP) and patterning processes. The first electrode 1044 is electrically connected to the light-emitting layer 1042 and a portion of the exposed first semiconductor layer 1041 of the second semiconductor layer 1043, and the second electrode 1045 is electrically connected to the light-emitting layer 1042 and the second semiconductor layer 1043.

[0172] Step S206: Pattern the chip support film to obtain the chip support layer.

[0173] In this embodiment, the chip support film b3 can be patterned using exposure, development, and etching methods. (See reference...) Figure 7 The patterned chip support layer 103 includes multiple chip support portions 1031, dummy connection portions 1032, and connecting portions 1033. The multiple chip support portions 1031 are correspondingly arranged with multiple first grids and with multiple light-emitting chips 104. The orthographic projection of the chip support portion 1031 onto the support substrate 101 lies within the orthographic projection of the corresponding first grid onto the support substrate 101. The orthographic projection of each light-emitting chip 104 onto the support substrate 101 lies within the orthographic projection of the corresponding chip support portion 1031 onto the support substrate 101. The area of ​​the orthographic projection of the chip support portion 1031 onto the support substrate 101 is larger than the area of ​​the orthographic projection of the light-emitting chip 104 onto the support substrate 101.

[0174] Each chip support portion 1031 has a plurality of dummy connections 1032. One end of each dummy connection 1032 is connected to the corresponding chip support portion 1031, and the other end is connected to the connecting portion 1033. There is a gap between the chip support portion 1031 and the dummy connections 1032 and the support substrate 101. The connecting portion 1033 is a second grid structure composed of a plurality of second grids. The orthographic projection of the connecting portion 1033 on the support substrate 101 overlaps with the orthographic projection of the bonding support layer 102 on the support substrate 101, and the connecting portion 1033 is connected to the bonding support layer 102.

[0175] In summary, this application provides a method for fabricating a light-emitting chip substrate. The light-emitting chip substrate fabricated by this method includes a supporting substrate, a bonding support layer, a chip support layer, and multiple light-emitting chips. The chip support layer includes multiple chip support portions, dummy connection portions, and connection portions. Multiple light-emitting chips in the light-emitting chip substrate are transferred to the driving backplane in a single step, eliminating the need for multiple transfers and achieving high transfer efficiency.

[0176] Figure 19 This is a flowchart illustrating a method for fabricating a display substrate according to an embodiment of this application. Taking a light-emitting chip 104 with a vertical structure as an example. (See reference...) Figure 19 The method includes:

[0177] Step S301: Obtain the light-emitting chip substrate.

[0178] In this embodiment of the application, the obtained light-emitting chip substrate can be Figure 1 , Figure 6 and Figure 7 The light-emitting chip substrate shown. That is, the obtained light-emitting chip substrate includes multiple light-emitting chips 104.

[0179] Step S302: Obtain the driver backplane.

[0180] refer to Figure 20 The driving backplane 201 includes a substrate 2011, a driving unit layer 2012, and a plurality of driving connection portions 2013. The driving unit layer 2012 includes a plurality of driving units corresponding to the plurality of driving connection portions 2013, and the driving connection portions 2013 are electrically connected to the driving units. Optionally, the substrate 2011 can be glass.

[0181] Optionally, the order of steps S301 and S302 can be interchanged.

[0182] Step S303: Bond the light-emitting chip substrate to the driving backplate so that the driving connection part is connected to the light-emitting chip.

[0183] If the light-emitting chip 104 is a vertically structured light-emitting chip 104, when the arrangement density of the light-emitting chip 104 in the light-emitting chip substrate corresponds to the arrangement density of the driving unit in the driving back plate 201, the light-emitting chip substrate and the driving back plate 201 can be directly aligned and bonded, so that the light-emitting chip 104 in the light-emitting chip substrate and the driving connection portion 2013 in the driving back plate 201 are bonded and connected.

[0184] When the arrangement density of the light-emitting chips 104 in the light-emitting chip substrate corresponds to the arrangement density of the driving units in the driving backplane 201, the pickup chip substrate can also be acquired. Taking a light-emitting chip 104 with a vertical structure as an example, refer to... Figure 21 The pickup chip substrate includes a pickup substrate c1 and a plurality of pickup portions c2 located on the pickup substrate c1. Optionally, the pickup substrate c1 can be glass.

[0185] The number of pickup units c2 is less than or equal to the number of light-emitting chips 104 in the light-emitting chip substrate, and the arrangement density of the pickup units c2 corresponds to the arrangement density of the driving units in the driving backplane 201. Multiple pickup units c2 correspond to at least a portion of the light-emitting chips 104 in the light-emitting chip substrate. For example... Figure 21 The diagram illustrates two pickup units, c2, while... Figure 6The diagram shows three light-emitting chips 104, with two pickup units c2 corresponding to the first and third light-emitting chips, respectively.

[0186] After acquiring the pickup substrate c1, refer to Figure 22 The light-emitting chip substrate and the pickup chip substrate can be bonded together to pick up multiple light-emitting chips 104 corresponding to multiple pickup units c2 onto the pickup chip substrate. For example Figure 22 The first and third light-emitting chips 104 are picked up and placed onto the pick-up chip substrate.

[0187] Optionally, the pickup part c2 can be an adhesive bump, which can be a polydimethylsiloxan (PDMS) stamp structure, or it can be composed of non-adhesive bumps and an adhesive coating. When picking up the light-emitting chip 104, the pickup part c2 can contact the light-emitting chip 104 to be picked up. Under pressure, the dummy connection part 1032 around the light-emitting chip 104 to be picked up breaks, thereby realizing the separation of the light-emitting chip 104 from the supporting substrate 101, and completing the selective mass transfer of the light-emitting chip 104. The light-emitting chip substrate with the dummy connection part 1032 can contact the laser dissociation process during the normal transfer process, simplifying the transfer process and improving the transfer yield.

[0188] After picking up the light-emitting chip 104 from the chip substrate, refer to Figure 23 The pickup chip substrate with multiple light-emitting chips 104 can be hot-pressed and bonded to the driving backplate 201. During the bonding process, since the chip support part 1031 acts as a bonding pad, its size is relatively large, which can effectively reduce the alignment accuracy requirements and improve the bonding yield.

[0189] If the light-emitting chip 104 is a flip-chip light-emitting chip 104, refer to Figure 24 When the arrangement density of the light-emitting chip 104 in the light-emitting chip substrate corresponds to the arrangement density of the driving unit in the driving back plate 201, the light-emitting chip substrate and the driving back plate 201 can be directly aligned and bonded, so that the light-emitting chip 104 in the light-emitting chip substrate and the driving connection portion 2013 in the driving back plate 201 are bonded and connected, and finally the support substrate 101 is removed.

[0190] If the light-emitting chip 104 is a flip-chip structure, and the arrangement density of the light-emitting chips 104 in the light-emitting chip substrate does not correspond to the arrangement density of the driving units in the driving backplane 201, a chip-picking substrate can be designed to pick up a portion of the light-emitting chips 104 in the light-emitting chip substrate. After picking up, the first electrode 1044 and the second electrode 1045 are closer to the picking substrate c1 relative to the light-emitting chips 104, so another transfer is required. For example, the picked-up multiple light-emitting chips 104 can be transferred to a temporary substrate, after which the first electrode 1044 and the second electrode 1045 are farther away from the temporary substrate relative to the light-emitting chips 104. Finally, the multiple light-emitting chips 104 transferred to the temporary substrate are bonded to the driving backplane 201.

[0191] Optional, see reference Figure 25 When the light-emitting chip 104 is a flip-chip structure, after the light-emitting chip 104 and the driving backplate 201 are bonded together, the chip support portion 1031 on the side of the light-emitting chip 104 away from the driving backplate 201 can be removed by wet etching process.

[0192] Optionally, when the light-emitting chip 104 is a vertically structured light-emitting chip 104, the light-emitting chip 104 can be connected via a chip support portion 1031 and a driving connection portion 2013. For example, the bonding metal layer a1 in the chip support portion 1031 and the driving connection portion 2013 are bonded together by forming an intermetallic compound (IMC). When the light-emitting chip 104 is a flip-chip structure light-emitting chip 104, the light-emitting chip 104 can be connected to the driving connection portion 2013 via a first electrode 1044 and a second electrode 1045. For example, an IMC is formed between the first electrode 1044 and the driving connection portion 2013, and between the second electrode 1045 and the driving connection portion 2013, to achieve bonding.

[0193] In summary, this application provides a method for fabricating a display substrate. The display substrate fabricated by this method includes a driving backplane and multiple light-emitting chips. The multiple light-emitting chips can be transferred from the light-emitting chip substrate to the driving backplane in a single transfer, eliminating the need for multiple transfers and achieving high transfer efficiency.

[0194] The terminology used in the embodiments section of this application is for explaining the embodiments of this application only and is not intended to limit this application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0195] The terminology used in the embodiments section of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a" and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including" and similar words mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The terms "connected" or "linked" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0196] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A light-emitting chip substrate, characterized in that, The light-emitting chip substrate includes: Support substrate; A bonding support layer located on one side of the supporting substrate, the bonding support layer being a first grid-like structure composed of multiple first grids; A chip support layer located on the side of the bonding support layer away from the support substrate includes multiple chip support portions, dummy connections, and connecting portions. The multiple chip support portions and multiple first grids are correspondingly arranged. The orthographic projection of each chip support portion on the support substrate lies within the orthographic projection of the corresponding first grid on the support substrate. Each chip support portion corresponds to multiple dummy connections. One end of each dummy connection is connected to the corresponding chip support portion, and the other end is connected to the connecting portion. There is a gap between the chip support portions and the dummy connections and the support substrate. The connecting portion is a second grid-like structure composed of multiple second grids. The orthographic projection of the connecting portion on the support substrate overlaps with the orthographic projection of the bonding support layer on the support substrate, and the connecting portion is connected to the bonding support layer. A plurality of light-emitting chips are located on the side of the chip support layer away from the support substrate and are disposed corresponding to the plurality of chip support portions. The orthographic projection of each light-emitting chip on the support substrate is located within the orthographic projection of the corresponding chip support portion on the support substrate. The area of ​​the orthographic projection of the chip support portion on the support substrate is larger than the area of ​​the orthographic projection of the light-emitting chip on the support substrate.

2. The light-emitting chip substrate according to claim 1, characterized in that, The light-emitting chip is a vertically structured light-emitting chip; the chip support layer includes: a bonding metal layer and a reflective metal layer stacked along a direction away from the support substrate; The portion of the bonding metal layer belonging to the connecting portion is used for bonding with the bonding support layer, and the portion of the reflective metal layer belonging to the chip support portion is used for reflecting the light emitted by the light-emitting chip.

3. The light-emitting chip substrate according to claim 2, characterized in that, The light-emitting chip includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially stacked along a direction away from the supporting substrate; The first semiconductor layer comprises P-type doped gallium nitride, the second semiconductor layer comprises N-type doped gallium nitride, and the light-emitting layer comprises a multi-quantum-well layer.

4. The light-emitting chip substrate according to claim 3, characterized in that, The area of ​​the cross-section of the light-emitting chip on the surface parallel to the supporting substrate gradually decreases as the distance between the chip and the supporting substrate increases.

5. The light-emitting chip substrate according to claim 4, characterized in that, The cross-sectional shape of the light-emitting chip is trapezoidal, and the cross-section is perpendicular to the surface of the supporting substrate; The length of the trapezoid on the side furthest from the supporting substrate is less than the length of the trapezoid on the side closest to the supporting substrate.

6. The light-emitting chip substrate according to claim 1, characterized in that, The light-emitting chip is a flip-chip structured light-emitting chip; the chip support layer includes a bonding metal layer; The portion of the bonding metal layer belonging to the connecting portion is used for bonding connection with the bonding support layer.

7. The light-emitting chip substrate according to claim 6, characterized in that, The light-emitting chip includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially along a direction away from the supporting substrate; the first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum-well layer; The light-emitting layer and the second semiconductor layer expose a portion of the first semiconductor layer. The light-emitting chip also includes a first electrode and a second electrode. The first electrode is electrically connected to the portion of the first semiconductor layer exposed by the light-emitting layer and the second semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer.

8. The light-emitting chip substrate according to any one of claims 1 to 7, characterized in that, The dummy joint is a strip-shaped structure, and the width of the dummy joint ranges from 3 micrometers to 10 micrometers.

9. The light-emitting chip substrate according to any one of claims 1 to 7, characterized in that, The shapes of the second grid, the light-emitting chip, and the chip support are all square. The side length of the second grid is 1.5 to 3 times the side length of the light-emitting chip; The side length of the chip support is 1 to 2 times the side length of the light-emitting chip.

10. A display substrate, characterized in that, The display substrate includes: A driving backplane includes a substrate, a driving unit layer, and a plurality of driving connection portions. The driving unit layer includes a plurality of driving units corresponding to the plurality of driving connection portions, and the driving connection portions are electrically connected to the driving units. Multiple light-emitting chips are located on one side of the driving backplate, and the multiple light-emitting chips and the multiple driving connection portions are correspondingly arranged. Each light-emitting chip includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked sequentially in a direction away from the driving backplate. The first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum well layer. And a chip support portion located between the light-emitting chip and the driving connection portion; The display substrate includes a plurality of light-emitting chips that are bonded to a light-emitting chip substrate as described in any one of claims 1 to 9 and a driving backplane; the area of ​​the cross section of the light-emitting chip parallel to the reference plane gradually decreases as the distance between it and the driving backplane increases, and the reference plane is parallel to the surface of the driving unit layer near the driving connection portion. The orthographic projection of the light-emitting chip on the reference plane is located within the orthographic projection of the chip support on the reference plane, and the area of ​​the orthographic projection of the chip support on the reference plane is larger than the area of ​​the orthographic projection of the light-emitting chip on the reference plane.

11. The display substrate according to claim 10, characterized in that, The chip support includes a bonding metal layer and a reflective metal layer. The bonding metal layer is close to the driving connection relative to the reflective metal layer. The bonding metal layer in the chip support is connected to the driving connection. The reflective metal layer in the chip support is used to reflect the light emitted by the light-emitting chip.

12. A method for preparing a light-emitting chip substrate, characterized in that, The method includes: A plurality of light-emitting chip sub-substrates are obtained, wherein the light-emitting chip sub-substrates include a chip substrate, an epitaxial layer, and a chip support film; A support substrate is obtained, the support substrate including a support substrate and a bonding support layer located on one side of the support substrate, the bonding support layer being a first grid structure composed of multiple first grids; The chip support film in the plurality of light-emitting chip sub-substrates and the bonding support layer in the support substrate are bonded together; Remove the chip substrate from the plurality of light-emitting chip sub-substrates; The epitaxial layer in the plurality of light-emitting chip sub-substrates is patterned to obtain a plurality of light-emitting chips; The chip support film is patterned to obtain a chip support layer, which includes multiple chip support portions, dummy connections, and connecting portions. The multiple chip support portions are correspondingly disposed with the multiple first grids and with the multiple light-emitting chips. The orthographic projection of each chip support portion on the support substrate lies within the orthographic projection of the corresponding first grid on the support substrate. The orthographic projection of each light-emitting chip on the support substrate lies within the orthographic projection of the corresponding chip support portion on the support substrate. The area of ​​the orthographic projection of each chip support portion on the support substrate is larger than the area of ​​the orthographic projection of the light-emitting chip on the support substrate. Each chip support portion corresponds to multiple dummy connections, one end of each dummy connection is connected to the corresponding chip support portion, and the other end is connected to the connecting portion. There is a gap between the chip support portions and the dummy connections and the support substrate. The connecting portion is a second grid structure composed of multiple second grids. The orthographic projection of the connecting portion on the support substrate overlaps with the orthographic projection of the bonding support layer on the support substrate, and the connecting portion is connected to the bonding support layer.

13. The method according to claim 12, characterized in that, The light-emitting chip is a vertically structured light-emitting chip; the chip support layer includes: a bonding metal layer and a reflective metal layer stacked along a direction away from the support substrate; the portion of the bonding metal layer belonging to the connection portion is used to bond with the bonding support layer, and the portion of the reflective metal layer belonging to the chip support portion is used to reflect the light emitted by the light-emitting chip; The light-emitting chip includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked in a direction away from the supporting substrate. The first semiconductor layer, the light-emitting layer, and the second semiconductor layer are stacked sequentially in a direction away from the supporting substrate. The first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum-well layer.

14. The method according to claim 12, characterized in that, The light-emitting chip is a flip-chip structure light-emitting chip; the chip support layer includes a bonding metal layer, which is used to bond and connect with the bonding support layer; The light-emitting chip includes a second semiconductor layer, a light-emitting layer, and a first semiconductor layer stacked sequentially along a direction away from the supporting substrate; the first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum-well layer; The light-emitting layer and the second semiconductor layer expose a portion of the first semiconductor layer. The light-emitting chip also includes a first electrode and a second electrode. The first electrode is electrically connected to the portion of the first semiconductor layer exposed by the light-emitting layer and the second semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer.

15. A method for preparing a display substrate, characterized in that, The method includes: Obtain a light-emitting chip substrate according to any one of claims 1 to 9 or obtain a light-emitting chip substrate prepared by the method according to any one of claims 12 to 14, wherein the light-emitting chip substrate comprises a plurality of light-emitting chips; A driving backplane is obtained, the driving backplane including a substrate, a driving unit layer, and a plurality of driving connection portions, the driving unit layer including a plurality of driving units corresponding to the plurality of driving connection portions, and the driving connection portions and the driving units being electrically connected; The light-emitting chip substrate is bonded to the driving backplate so that the driving connection portion is connected to the light-emitting chip.

16. The method according to claim 15, characterized in that, Bonding the light-emitting chip substrate to the driving backplane includes: A pickup chip substrate is obtained, the pickup chip substrate includes a pickup substrate and a plurality of pickup parts located on the pickup substrate, the number of pickup parts is less than or equal to the number of light-emitting chips in the light-emitting chip substrate, and the plurality of pickup parts correspond to at least a portion of the light-emitting chips in the light-emitting chip substrate; The light-emitting chip substrate is bonded to the pickup chip substrate so as to pick up multiple light-emitting chips corresponding to the multiple pickup parts onto the pickup chip substrate; The pickup chip substrate, which picks up multiple light-emitting chips, is bonded to the driving backplate.

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