Display device and electronic device including the same

Abstract

Disclosed are a display device and an electronic device including the same. The display device includes a substrate, a first electrode disposed on the substrate, a second electrode disposed on the first electrode, and a first light emitting layer disposed between the first electrode and the second electrode, the first light emitting layer including a first sub light emitting layer, a charge generation layer, and a second sub light emitting layer, wherein an area of the first sub light emitting layer is greater than an area of the charge generation layer.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2025-0007752, filed on January 20, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device and an electronic device including the display device. Background Technology

[0003] Electroluminescent displays can be classified into inorganic and organic light-emitting displays (OLEDs) depending on the material of their light-emitting layer. Active-matrix OLEDs include organic light-emitting diodes ("OLEDs") that emit light themselves. Furthermore, OLEDs offer advantages such as fast response times, high luminous efficiency, high brightness, and wide viewing angles. In OLEDs, an OLED is formed in each pixel. Due to their ability to represent black grayscale levels as full black, along with their fast response times, excellent luminous efficiency, high brightness, and wide viewing angles, OLEDs exhibit superior contrast and color reproduction. Summary of the Invention

[0004] The features of this disclosure provide a display device with improved light efficiency.

[0005] However, the features of this disclosure are not limited to those set forth herein. The foregoing and other features of this disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0006] According to various embodiments of the present disclosure, a display device includes: a substrate; a first electrode disposed on the substrate; a second electrode disposed on the first electrode; and a first light-emitting layer disposed between the first electrode and the second electrode, the first light-emitting layer including a first sub-light-emitting layer, a charge-generating layer and a second sub-light-emitting layer, wherein the area of ​​the first sub-light-emitting layer is larger than the area of ​​the charge-generating layer.

[0007] According to various embodiments of this disclosure, the area of ​​the second sub-light-emitting layer can be larger than the area of ​​the charge-generating layer.

[0008] According to various embodiments of the present disclosure, the display device may further include: a first common layer disposed between the first electrode and the first light-emitting layer; and a second common layer disposed between the first light-emitting layer and the second electrode.

[0009] According to various embodiments of the present disclosure, the display device may include: a first emitting region, a second emitting region, and a third emitting region, spaced apart from each other; a second light-emitting layer disposed in the second emitting region; and a third light-emitting layer disposed in the third emitting region, wherein the first light-emitting layer may be disposed in the first emitting region.

[0010] According to various embodiments of this disclosure, the area of ​​the first launch region may be larger than the area of ​​the second launch region and the area of ​​the third launch region.

[0011] According to various embodiments of the present disclosure, each of the second light-emitting layer and the third light-emitting layer may be disposed between the first common layer and the second common layer. The second light-emitting layer may include a second intermediate layer and a third sub-light-emitting layer, and the third light-emitting layer may include a third intermediate layer and a fourth sub-light-emitting layer.

[0012] According to various embodiments of the present disclosure, the second intermediate layer may include a second sub-intermediate layer and a third sub-intermediate layer, and the third intermediate layer may include a fourth sub-intermediate layer and a fifth sub-intermediate layer.

[0013] According to various embodiments of the present disclosure, the first light-emitting layer may include a first intermediate layer, which includes a charge-generating layer and a first sub-intermediate layer.

[0014] According to various embodiments of this disclosure, the area of ​​the first sub-light-emitting layer and the area of ​​the second sub-light-emitting layer can be greater than the area of ​​the first sub-intermediate layer.

[0015] According to various embodiments of the present disclosure, the charge generation layer may include a first charge generation layer and a second charge generation layer disposed between the first charge generation layer and the second sub-light-emitting layer.

[0016] According to various embodiments of the present disclosure, the second sub-light-emitting layer includes a first region overlapping with the first sub-light-emitting layer, and the first region includes a first sub-region overlapping with the charge-generating layer.

[0017] According to various embodiments of the present disclosure, the first region further includes a second sub-region adjacent to the first sub-region, and the distance from the lower surface of the first sub-light-emitting layer to the upper surface of the second sub-light-emitting layer is greater in the first sub-region than in the second sub-region.

[0018] According to various embodiments of the present disclosure, an electronic device includes: a processor for providing image signals; a display module for receiving image signals from the processor and displaying images; and a power module for supplying power to the display module, wherein the display module includes: a substrate defining a first emitting region, a second emitting region, and a third emitting region spaced apart from each other; a plurality of first electrodes disposed on the substrate; a first light-emitting layer disposed on a first electrode of the plurality of first electrodes that overlaps with the first emitting region; a second light-emitting layer disposed on a first electrode of the plurality of first electrodes that overlaps with the second emitting region; a third light-emitting layer disposed on a first electrode of the plurality of first electrodes that overlaps with the third emitting region; and a second electrode disposed on the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer, wherein the first light-emitting layer includes a first sub-light-emitting layer, a charge-generating layer, and a second sub-light-emitting layer, and each of the second light-emitting layer and the third light-emitting layer includes a single light-emitting layer.

[0019] According to various embodiments of the present disclosure, the second sub-light-emitting layer includes a first region overlapping with the first sub-light-emitting layer, and the first region includes a first sub-region overlapping with the charge-generating layer.

[0020] According to various embodiments of the present disclosure, the first region further includes a second sub-region adjacent to the first sub-region, and the distance from the lower surface of the first sub-light-emitting layer to the upper surface of the second sub-light-emitting layer is greater in the first sub-region than in the second sub-region.

[0021] According to various embodiments of this disclosure, the area of ​​the first sub-light-emitting layer can be larger than the area of ​​the charge-generating layer.

[0022] According to various embodiments of this disclosure, the area of ​​the second sub-light-emitting layer can be larger than the area of ​​the charge-generating layer.

[0023] According to various embodiments of the present disclosure, the electronic device may further include: a first common layer disposed between a plurality of first electrodes and a first light-emitting layer to overlap with a first emitting region, a second emitting region and a third emitting region; and a second common layer disposed between the first light-emitting layer and a second electrode to overlap with the first emitting region, the second emitting region and the third emitting region.

[0024] According to various embodiments of the present disclosure, the second light-emitting layer and the third light-emitting layer are each disposed between the first common layer and the second common layer. The second light-emitting layer includes a second intermediate layer and a third sub-light-emitting layer, and the third light-emitting layer includes a third intermediate layer and a fourth sub-light-emitting layer.

[0025] According to various embodiments of this disclosure, the second intermediate layer includes a second sub-intermediate layer and a third sub-intermediate layer, and the third intermediate layer includes a fourth sub-intermediate layer and a fifth sub-intermediate layer.

[0026] According to this disclosure, by providing a second sub-light-emitting layer on the portion of the first charge-generating layer disposed on the embankment, the possibility of leakage current being generated via the second common layer can be reduced. Furthermore, the area of ​​direct contact between the first charge-generating layer and the second charge-generating layer and the first and second common layers can be reduced.

[0027] According to this disclosure, by providing a first sub-light-emitting layer below the portion of the second charge-generating layer disposed on the embankment, the possibility of leakage current being generated via the first common layer can be reduced. Furthermore, the area of ​​direct contact between the second charge-generating layer and the first charge-generating layer and the second common layer and the first common layer can be reduced.

[0028] According to this disclosure, the luminous efficiency of the display device in a series structure can be standardized. Furthermore, since the luminous efficiency of the display device is improved, the display device can be driven with lower power. Attached Figure Description

[0029] These and / or other features will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0030] Figure 1A This is a perspective view of an embodiment of the display device according to the present disclosure, and Figure 1B yes Figure 1A An enlarged view of part AA;

[0031] Figure 2 These are schematic block diagrams illustrating embodiments of the display device according to the present disclosure;

[0032] Figure 3 This is a plan view of an embodiment of the display area according to the present disclosure;

[0033] Figure 4 It is a detailed cross-sectional view of a display device including light-emitting elements;

[0034] Figure 5 A schematic diagram illustrates the light-emitting elements of a display device;

[0035] Figure 6 Detailed map shown Figure 5 ;

[0036] Figure 7 The schematic map illustrates the current leakage caused by the deviation in the deposition location of the first charge generation layer;

[0037] Figure 8A Detailed map shown Figure 7 ,and Figure 8B yes Figure 8A A magnified view of the BB section;

[0038] Figure 9 The schematic map illustrates the current leakage caused by the deviation in the deposition location of the second charge generation layer;

[0039] Figure 10A Detailed map shown Figure 9 ,and Figure 10B yes Figure 10A A magnified view of the CC portion;

[0040] Figure 11 The schematic diagram illustrates an embodiment of a light-emitting element of a display device according to the present disclosure;

[0041] Figure 12 Detailed map shown Figure 11 ;

[0042] Figure 13 The schematic diagram illustrates an embodiment of an error occurring in the deposition location of the first charge generation layer in a display device according to the present disclosure;

[0043] Figure 14 Detailed map shown Figure 13 ;

[0044] Figure 15 The schematic diagram illustrates an embodiment of an error occurring in the deposition position of the second charge generation layer in a display device according to the present disclosure;

[0045] Figure 16 Detailed map shown Figure 15 ;

[0046] Figure 17 This is a plan view illustrating an embodiment of deposition margin applied to a display device according to the present disclosure;

[0047] Figure 18 This is a plan view illustrating an embodiment in which no error occurs in the deposition position in the display device according to the present disclosure;

[0048] Figure 19 This is a plan view illustrating an embodiment of an error occurring in the deposition position of the charge generation layer in a display device according to the present disclosure;

[0049] Figure 20 This is a plan view illustrating an embodiment of the present disclosure where errors occur in the deposition position of the charge generation layer and the deposition position of the light-emitting layer in a display device;

[0050] Figure 21 These are block diagrams of embodiments of the electronic device according to the present disclosure; and

[0051] Figure 22 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure. Detailed Implementation

[0052] The advantages and features of the embodiments disclosed herein, as well as the methods of implementing them, will become apparent from reference to the detailed description of the embodiments and the accompanying drawings. However, the disclosure according to this disclosure is not limited to the embodiments disclosed herein, but will be embodied in many different forms, and these embodiments are provided only to complete the disclosure and to fully inform those skilled in the art to which the disclosure pertains, and the disclosure according to this disclosure is defined by the scope of the claims.

[0053] When referring to an element or layer "on" another element or layer, two situations are included: the element or layer is directly on top of the other element or layer, or another element is situated between them. Throughout this specification, the same reference numerals refer to the same parts. The shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings to illustrate embodiments are exemplary and are not intended to be limited to those shown herein.

[0054] Although various components are described using terms such as "first" or "second," these components are not limited by these terms. Therefore, within the scope of the technical concept of this disclosure, a "first component" mentioned herein can also be a "second component."

[0055] As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviations for a given quantity, as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of that quantity (i.e., limitations of the measurement system). For example, the term “about” may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0056] Each of the features of the various embodiments disclosed herein may be partially or wholly combined with each other or may be partially or wholly combinable, and may be technically interlocked and operated in a variety of ways, and each embodiment may be practiced independently of each other or in combination with each other.

[0057] Specific embodiments will now be described with reference to the accompanying drawings. Constructions that are substantially identical in function between embodiments are given the same reference numerals, and repeated descriptions are omitted.

[0058] Figure 1A This is a perspective view of an embodiment of the display device 1 according to the present disclosure, and Figure 1B yes Figure 1A An enlarged view of part AA.

[0059] exist Figure 1AThe diagram defines a first direction D1, a second direction D2, and a third direction D3. The first direction D1 and the second direction D2 can be perpendicular to each other, the first direction D1 and the third direction D3 can be perpendicular to each other, and the second direction D2 and the third direction D3 can be perpendicular to each other. It is understood that the first direction D1 refers to the horizontal direction in the diagram, the second direction D2 refers to the vertical direction in the diagram, and the third direction D3 refers to the up-down direction in the diagram, i.e., the thickness direction. In the following description, unless otherwise specified, "direction" can refer to two directions extending to both sides along that direction. Furthermore, when it is desirable to distinguish between two "directions" extending to both sides, one side is referred to as "one side in that direction," and the other side is referred to as "the other side in that direction." In the diagram, the direction pointed to by the arrow is referred to as one side, and the direction opposite to that direction is referred to as the other side. However, the directions mentioned in the embodiments should be understood as relative directions, and this disclosure is not limited to the mentioned directions.

[0060] For ease of description below, when referring to the display device 1 or the surface of each component constituting the display device 1, a surface facing the direction of the displayed image (i.e., in the third direction D3) is also referred to as the upper surface, and the remaining (other) surfaces opposite to that surface are also referred to as the lower surface. However, embodiments of this disclosure are not limited thereto, and one surface and the remaining (other) surfaces of each component may also be referred to as the front surface and the rear surface, or the first surface and the second surface, respectively. Furthermore, when describing the relative positions of the components of the display device 1, the side in the third direction D3 may also be referred to as the upper side, and the opposite side in the third direction D3 may also be referred to as the lower side.

[0061] Display device 1 can refer to any electronic device that provides a display screen. In embodiments, display device 1 may include mobile phones, smartphones, tablet PCs (“PCs”), electronic watches, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (“PMPs”), navigation devices, game consoles, digital cameras, televisions, laptops, netbooks, monitors, billboards, and Internet of Things (IoT) devices, all of which provide a display screen. The illustrated embodiments show examples in which display device 1 is applied to portable devices such as tablet PCs or mobile phones.

[0062] The planar shape of the display device 1 is not limited. In embodiments, for example, depending on the field in which the display device 1 is applied, the planar shape of the display device 1 can be changed to various shapes such as rectangle, square, rhombus, other polygons, circle, and ellipse. An exemplary planar shape of the display device 1 is a rectangle with rounded corners, and the long sides LS1 and LS2 are arranged parallel to the second direction D2. For ease of description, the long side of the rectangle that is located on one side (left side in the plan view in the figure) will also be referred to as the first long side LS1, and the long side that is located on the opposite side (right side in the plan view in the figure) will also be referred to as the second long side LS2. In addition, the short side that is located on one side (lower side in the plan view in the figure) will also be referred to as the first short side SS1, and the short side that is located on the opposite side (upper side in the plan view in the figure) will also be referred to as the second short side SS2. The terms “first long side LS1”, “second long side LS2”, “first short side SS1” and “second short side SS2” will be used not only to refer to the corresponding side of the display device 1, but also to refer to the corresponding side of the element when the element included in the display device 1 has a shape and positional relationship similar to that of the display device 1.

[0063] The display device 1 includes a display area DA and a non-display area NDA. The display area DA is the area where the image is displayed, and the non-display area NDA is the area where the image is not displayed. The terms "display area DA" and "non-display area NDA" can be used not only to refer to the corresponding areas of the display device 1, but also to refer to the corresponding areas of an element when the element included in the display device 1 has a shape and positional relationship similar to that of the display device 1.

[0064] Multiple pixels (PX) can be set in the display area (DA). The structure of a pixel (PX) will be described later.

[0065] A non-display area NDA can be disposed around a display area DA. When the display area DA has a quadrilateral shape (e.g., a rectangular shape), the non-display area NDA can surround the four sides of the display area DA. However, embodiments of this disclosure are not limited thereto. In embodiments, for example, the non-display area NDA can also be disposed only on the outer side of some sides of the display area DA. In some cases, the non-display area NDA can exist inside the display area DA and can be surrounded by the display area DA.

[0066] Figure 2 This is a schematic block diagram of an embodiment of the display device 1 according to the present disclosure.

[0067] refer to Figures 1A to 2The display device 1 includes a display panel PNL. The display device 1 may further include a driving unit connected to the display panel PNL.

[0068] In this disclosure, the term "connection" can mean that any component is connected to another component not only through physical contact but also through another component. Furthermore, it can be understood that any part is connected to another part as a single integral component. Additionally, the connection between any component and another component can be interpreted not only as a connection through direct contact but also as including an electrical connection through another component.

[0069] The display panel PNL provides a display image. In the exemplary display device 1, the direction in which the display panel PNL provides the display image is a third direction D3. The display panel PNL may have a planar shape substantially similar to the planar shape of the display device 1. As described above, the display area DA of the display device 1 may also be referred to as the display area DA of the display panel PNL. The display area DA of the display panel PNL includes a plurality of pixels PX arranged in a matrix.

[0070] In embodiments, the display panel PNL may include an organic light-emitting display panel, a micron-sized light-emitting diode (LED) display panel, a nano-LED display panel, a quantum dot light-emitting display panel, a liquid crystal display panel, a plasma display panel, a field emission display panel, an electrophoretic display panel, and an electrowetting display panel. The following describes the application of an organic light-emitting display panel in embodiments of the display panel PNL; however, the embodiments of this disclosure are not limited to this, and other display panels may be applied as long as the same technical spirit is applicable.

[0071] The driving unit drives the display panel PNL. At least some elements in the driving unit drive the pixels PX disposed in the display area DA of the display panel PNL. In some embodiments, the driving unit may be provided in the form of a chip, a film, and / or a circuit board.

[0072] The driving unit may include a display scan driver 250, a data driver 210, a timing controller 220, and a power supply unit 230. Although the driving unit is located in the non-display area NDA of the display panel PNL, some of the driving units may also be located in the display area DA.

[0073] The display area DA contains not only pixels PX, but also multiple lines connected to the driving unit. These lines may include multiple display write lines GWL, multiple display initialization lines GIL, multiple display control lines GCL, multiple emit lines EL, and multiple data lines DTL.

[0074] The data line DTL can extend in the second direction D2. The display write line GWL, display initialization line GIL, display control line GCL, and transmit line EL can extend in the first direction D1.

[0075] Each pixel PX can be connected to any one of the display write lines GWL, any one of the display initialization lines GIL, any one of the display control lines GCL, and any one of the emitter lines EL. Each pixel PX can receive the data voltage of the data line DTL according to the display write signal of the display write line GWL, the display initialization signal of the display initialization line GIL, the display control signal of the display control line GCL, and the emitter signal of the emitter line EL, and can emit light by supplying driving current to the light-emitting element according to the data voltage.

[0076] The display scan driver 250 can be connected to the display write line GWL, the display initialization line GIL, the display control line GCL, and the transmit line EL. The display scan driver 250 may include a display signal output unit that outputs display write signals transmitted to the display write line GWL, display initialization signals transmitted to the display initialization line GIL, and display control signals transmitted to the display control line GCL, and a transmit signal output unit that outputs transmit signals transmitted to the transmit line EL.

[0077] The display scan driver 250 can receive a write control signal WCS, an initialization control signal ICS, a scan control signal CCS, and a transmit control signal ECS from the timing controller 220. The display signal output unit of the display scan driver 250 can generate a display write signal based on the write control signal WCS and output this display write signal to the display write line GWL. Furthermore, the display signal output unit of the display scan driver 250 can generate a display initialization signal based on the initialization control signal ICS and output this display initialization signal to the display initialization line GIL. Additionally, the display signal output unit of the display scan driver 250 can generate a display control signal based on the scan control signal CCS and output this display control signal to the display control line GCL. Finally, the transmit signal output unit of the display scan driver 250 can generate a transmit signal based on the transmit control signal ECS and output this transmit signal to the transmit line EL.

[0078] Data driver 210 converts digital video data DATA into data voltage and outputs the data voltage to the data line DTL. Data driver 210 can output the data voltage synchronously with the display write signal. Pixel PX can be selected by the display write signal of display scan driver 250, and the data voltage can be supplied to the selected pixel PX individually.

[0079] The timing controller 220 receives digital video data DATA and timing signals from an external graphics device. In embodiments, the external graphics device may be, but is not limited to, a computer graphics card or a set-top box.

[0080] The timing controller 220 can generate a write control signal (WCS), an initialization control signal (ICS), a scan control signal (CCS), and a transmit control signal (ECS) based on the timing signals to control the operation timing of the display scan driver 250. Furthermore, the timing controller 220 can generate a data control signal (DCS) based on the timing signals to control the operation timing of the data driver 210.

[0081] The timing controller 220 can output the write control signal WCS, the initialization control signal ICS, the scan control signal CCS, and the transmit control signal ECS to the display scan driver 250. The timing controller 220 can output digital video data DATA and the data control signal DCS to the data driver 210.

[0082] The power supply unit 230 can generate multiple driving voltages and output these driving voltages to the display area DA. The power supply unit 230 can output a first driving voltage VDD, a second driving voltage VSS, and an initialization voltage VINT to the display panel PNL. The first driving voltage VDD can be a high-level driving voltage, the second driving voltage VSS can be a low-level driving voltage with a voltage level lower than that of the high-level driving voltage, and the initialization voltage VINT can be a voltage used to initialize the gate electrode of the driving transistor of each pixel PX.

[0083] Figure 3 This is a plan view of an embodiment of the display area DA according to the present disclosure.

[0084] refer to Figure 3 The display area DA may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a light-sensing pixel LSP. Sub-pixels SP can be divided into first sub-pixels SP1, second sub-pixels SP2, and third sub-pixels SP3. First sub-pixels SP1, second sub-pixels SP2, third sub-pixels SP3, and the light-sensing pixel LSP can be defined as a unit sub-pixel USP. A unit sub-pixel USP can be defined as the smallest unit of a sub-pixel that can sense light when displaying white.

[0085] In this embodiment, the second sub-pixel SP2 may be disposed at the location where the light-sensing pixel LSP is disposed. The display device 1 in this embodiment may include only the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. However, the following description assumes that the light-sensing pixel LSP is also disposed in the display device 1.

[0086] The first sub-pixel SP1 may include a second emitting region EA2 that emits first light and a first pixel driver for supplying driving current to the light-emitting element of the second emitting region EA2. The first light may be red-band light. In an embodiment, for example, the main peak wavelength of the first light may be set between about 600 nanometers (nm) and about 750 nm.

[0087] The second sub-pixel SP2 may include a third emitting region EA3 for emitting second light and a second pixel driver for supplying driving current to the light-emitting element of the third emitting region EA3. The second light may be light in the green band. In an embodiment, for example, the main peak wavelength of the second light may be set between about 480 nm and about 560 nm.

[0088] The third sub-pixel SP3 may include a first emitting region EA1 that emits a third light and a third pixel driver for supplying driving current to the light-emitting element of the first emitting region EA1. The third light may be light in the blue band. In an embodiment, for example, the main peak wavelength of the third light may be set between about 370 nm and about 460 nm.

[0089] The light-sensing pixel LSP includes a light-sensing unit (PDU).

[0090] The first emission region EA1, the second emission region EA2, the third emission region EA3, and the photosensitive unit PDU may have a planar shape of polygons, including quadrilaterals, octagons, or rhombuses, but the embodiments disclosed herein are not limited thereto. The first emission region EA1, the second emission region EA2, the third emission region EA3, and the photosensitive unit PDU may also have a planar shape of polygons other than quadrilaterals, octagons, and rhombuses.

[0091] The second emission region EA2 can be disposed on the first direction D1, starting from the first emission region EA1. The photosensitive unit PDU can be disposed on the second direction D2, starting from the third emission region EA3. The second emission region EA2 and the first emission region EA1 can be disposed on a diagonal direction (e.g., the direction between the first direction D1 and the second direction D2), starting from the third emission region EA3. Furthermore, the second emission region EA2 and the first emission region EA1 can be disposed on a diagonal direction (e.g., the direction between the first direction D1 and the second direction D2), starting from the photosensitive unit PDU. This diagonal direction can form the same angle with the first direction D1 and the second direction D2, but the embodiments disclosed herein are not limited thereto.

[0092] Due to the positions and planar shapes of the second emission region EA2, the third emission region EA3, the first emission region EA1, and the photosensitive unit PDU, the distances D12 between the center C1 of the second emission region EA2 and the center C2 of the third emission region EA3, D23 between the center C2 of the third emission region EA3 and the center C3 of the first emission region EA1, D14 between the center C1 of the second emission region EA2 and the center C4 of the photosensitive unit PDU, and D34 between the center C4 of the photosensitive unit PDU and the center C3 of the first emission region EA1 can be substantially the same.

[0093] Figure 4 This is a detailed cross-sectional view of the display device 1, including the light-emitting element.

[0094] refer to Figure 4 The display device 1 may include a substrate SUB, a transistor layer TRL, a light-emitting element layer EMTL, and a packaging layer ENC.

[0095] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate that can be bent, folded, rolled, etc. In embodiments, the substrate SUB may include, for example, a polymer resin such as polyimide (“PI”), but the embodiments of this disclosure are not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material. In alternative embodiments, the substrate SUB can be a silicon substrate on which semiconductor patterns are formed. In embodiments, for example, the substrate SUB can be a silicon semiconductor substrate formed by a complementary metal-oxide-semiconductor (CMOS) process. The substrate SUB can include any one of a single-crystal silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer. Furthermore, the substrate SUB can be a germanium substrate or a silicon-germanium substrate.

[0096] The transistor layer TRL may include a first buffer layer BF1, a bottom metal layer BML, a second buffer layer BF2, a transistor TR, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0097] A first buffer layer BF1 may be disposed on a substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing the penetration of air or moisture. In an embodiment, for example, the first buffer layer BF1 may include multiple inorganic layers stacked alternately.

[0098] The bottom metal layer BML can be disposed on the first buffer layer BF1. Each of the bottom metal layers BML can be a single layer or multiple layers of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0099] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing the penetration of air or moisture. In an embodiment, for example, the second buffer layer BF2 may include multiple inorganic layers stacked alternately.

[0100] Transistors TR can be disposed on the second buffer layer BF2 and can form corresponding pixel circuits for multiple pixels. In an embodiment, for example, each of the transistors TR can be a driving transistor for the pixel circuit. Each of the transistors TR may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0101] The semiconductor layer ACT can be disposed on the second buffer layer BF2. The semiconductor layer ACT can overlap with the bottom metal layer BML and the gate electrode GE in the thickness direction (i.e., the third direction D3), and can be insulated from the gate electrode GE by the gate insulating layer GI. In the portion of the semiconductor layer ACT, the material of the semiconductor layer ACT can be made conductive to form the source electrode SE and the drain electrode DE.

[0102] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap with the semiconductor layer ACT through the gate insulating layer GI. The gate insulating layer GI can be disposed between the gate electrode GE and the semiconductor layer ACT.

[0103] A gate insulating layer GI can be disposed on the semiconductor layer ACT. In an embodiment, for example, the gate insulating layer GI can cover the semiconductor layer ACT and the second buffer layer BF2, and can insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0104] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0105] Capacitor electrodes CPE can be disposed on the first interlayer insulating layer ILD1. The capacitor electrodes CPE can overlap with the gate electrode GE in the thickness direction (i.e., the third direction D3). The capacitor electrodes CPE and the gate electrode GE can form a capacitor. In an embodiment, for example, each of the gate electrodes GE can correspond to a first electrode of the capacitor, and each of the capacitor electrodes CPE can correspond to a second electrode of the capacitor.

[0106] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may connect to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0107] The first connection electrode CNE1 can be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 can electrically connect the drain electrode DE of the transistor TR to the second connection electrode CNE2. The first connection electrode CNE1 can be inserted into a contact hole defined in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the transistor TR.

[0108] The first passivation layer PAS1 can cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 can protect the transistor TR. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0109] The second connection electrode CNE2 can be disposed on the first passivation layer PAS1. The second connection electrode CNE2 can electrically connect the first connection electrode CNE1 to the corresponding pixel electrodes PE1 to PE3 (or the first electrode) of the light-emitting elements ED1 to ED3, respectively. The second connection electrode CNE2 can be inserted into the contact hole defined in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0110] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the corresponding pixel electrodes PE1 to PE3 of the light-emitting elements ED1 to ED3 pass.

[0111] The light-emitting element layer EMTL can be disposed on the transistor TR. The light-emitting element layer EMTL may include multiple light-emitting elements ED1 to ED3 and a pixel electrode PE1 to PE3, the light-emitting layer EML, and a common electrode CE.

[0112] The display device 1 may include a plurality of emitting regions EA1 to EA3 disposed in the display area DA. The emitting regions EA1 to EA3 may include a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3 that emit light of different colors respectively. Each of the emitting regions EA1 to EA3 may emit blue light, red light, or green light, and the color of the light emitted from each of the emitting regions EA1 to EA3 may vary depending on the type of light-emitting element disposed in the light-emitting element layer EMTL. In an embodiment, the first emitting region EA1 may emit blue light, the second emitting region EA2 may emit red light, and the third emitting region EA3 may emit green light. However, the embodiments disclosed herein are not limited thereto.

[0113] The emitting regions EA1 to EA3 can each be defined by a plurality of openings defined in the diaphragm PDL of the light-emitting element layer EMTL. In embodiments, the areas or dimensions of the emitting regions EA1 to EA3 can be the same. In embodiments, for example, the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 can have the same area. However, the embodiments disclosed herein are not limited thereto.

[0114] The areas or dimensions of the emission regions EA1 to EA3 can be different from each other. The intensity of the light emitted from each of the emission regions EA1 to EA3 can be varied according to the area of ​​the emission regions EA1, EA2, or EA3, and can be controlled in the display device 1 or electronic device 10 (e.g., as shown in the image) by adjusting the area of ​​the emission regions EA1 to EA3. Figure 21 The colors displayed on the screen (as shown). Figure 4 In the embodiments described, the first to third emission regions EA1 to EA3 have the same area. However, the embodiments disclosed herein are not limited thereto. It is possible to use the display device 1 and the electronic device 10 (e.g., such as...) Figure 21 The area of ​​the emission regions EA1 to EA3 can be freely adjusted to achieve the desired color of the image (as shown). Furthermore, the area of ​​the emission regions EA1 to EA3 can be related to luminous efficiency, the lifespan of the light-emitting element (ED), and can be balanced with the reflection of external light. These factors can be considered when adjusting the area of ​​the emission regions EA1 to EA3.

[0115] In display device 1, a first emission region EA1, a second emission region EA2, and a third emission region EA3 that are adjacent to each other can form a unit pixel. A unit pixel may include emission regions EA1 to EA3 that emit light of different colors to represent white grayscale levels. However, embodiments of this disclosure are not limited thereto, and the combination of emission regions EA1 to EA3 constituting a unit pixel can vary depending on the arrangement of emission regions EA1 to EA3 and the color of the light emitted from emission regions EA1 to EA3.

[0116] Display device 1 may include a plurality of light-emitting elements ED1 to ED3 disposed in first to third emission regions EA1 to EA3. In an embodiment, for example, the light-emitting element layer EMTL of display device 1 may include a first light-emitting element ED1 disposed in the first emission region EA1, a second light-emitting element ED2 disposed in the second emission region EA2, and a third light-emitting element ED3 disposed in the third emission region EA3. Each of the first to third light-emitting elements ED1 to ED3 may include a first pixel electrode PE1, a second pixel electrode PE2 or a third pixel electrode PE3, a light-emitting layer EML, and a common electrode CE (or a second electrode).

[0117] The emission regions EA1 to EA3 constituting a unit pixel can provide various colors of light by emitting light-emitting elements ED1 to ED3 that emit light of different colors. In an embodiment, for example, a unit pixel may include a first pixel, a second pixel, and a third pixel arranged adjacent to each other. The first pixel may include a first light-emitting element ED1 that emits red light, the second pixel may include a second light-emitting element ED2 that emits blue light, and the third pixel may include a third light-emitting element ED3 that emits green light.

[0118] A unit pixel can provide light of various colors by mixing red light from the first light-emitting element ED1 provided in the first pixel, blue light from the second light-emitting element ED2 provided in the second pixel, and green light from the third light-emitting element ED3 provided in the third pixel.

[0119] Pixel electrodes PE1 to PE3 can be disposed on the second passivation layer PAS2. In an embodiment, for example, the first pixel electrode PE1 can be configured to correspond to the first emission region EA1, the second pixel electrode PE2 can be configured to correspond to the second emission region EA2, and the third pixel electrode PE3 can be configured to correspond to the third emission region EA3.

[0120] Each of pixel electrodes PE1 to PE3 can be electrically connected to the drain electrode DE of the transistor TR of the corresponding pixel via a first connection electrode CNE1 and a second connection electrode CNE2. In an embodiment, for example, the first pixel electrode PE1 can be connected to the drain electrode DE (or source electrode SE) of the transistor TR provided in the first pixel via the first connection electrode CNE1 and the second connection electrode CNE2. Furthermore, the second pixel electrode PE2 can be connected to the drain electrode DE (or source electrode SE) of the transistor TR provided in the second pixel via other first connection electrodes CNE1 and second connection electrodes CNE2. Additionally, the third pixel electrode PE3 can be connected to the drain electrode DE (or source electrode SE) of the transistor TR provided in the third pixel via other first connection electrodes CNE1 and second connection electrodes CNE2.

[0121] In an embodiment, each of the pixel electrodes PE1 to PE3 may have a stacked structure in which a material layer with a relatively high work function (such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO) or indium oxide (In2O3)) is stacked with a reflective material layer (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or any combination thereof). The layer with the relatively high work function may be disposed on the reflective material layer such that it is positioned close to the light-emitting layer EML. In an embodiment, for example, each of the pixel electrodes PE1 to PE3 may have, but is not limited to, a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, or ITO / Ag / ITO.

[0122] The dam PDL (or pixel confinement layer) can be set on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3.

[0123] The dam PDL can define the emission region of each pixel (first emission region EA1, second emission region EA2, and third emission region EA3). For this purpose, for example, the dam PDL can be disposed on the second passivation layer PAS2 to expose a portion of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. In embodiments, for example, the dam PDL can cover each edge of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The dam PDL can comprise an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0124] The light-emitting layer EML can be disposed on each of the pixel electrodes PE1 to PE3. This will be described in detail with reference to the accompanying drawings described below.

[0125] A common electrode CE can be disposed on each emissive layer EML. In an embodiment, for example, the common electrode CE can be disposed on each emissive layer EML to overlap with the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the first emitting region EA1, the second emitting region EA2, the third emitting region EA3, and the embankment PDL. The common electrode CE can be a common layer shared by each of the emissive elements ED1 to ED3. In other words, the emissive elements ED1 to ED3 of the emissive element layer EML can share the common electrode CE. In a top-emitting structure, the common electrode CE can include a transparent conductive material (“TCO”) such as indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) capable of transmitting light, or it can include a semi-transparent conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium and silver. When the common electrode CE includes a semi-transparent conductive material, light output efficiency can be improved by using a microcavity.

[0126] The capping layer CPL can be disposed on the common electrode CE. The capping layer CPL may include an inorganic insulating material. In embodiments, the capping layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0127] An encapsulation layer ENC can be disposed on the capping layer CPL. The encapsulation layer ENC can cover the upper and side surfaces of the light-emitting element layer EMTL and protect the EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer to encapsulate the light-emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the light-emitting element layer EMTL. Furthermore, the encapsulation layer ENC may include at least one organic layer TFE2 to protect the light-emitting element layer EMTL from foreign matter such as dust. In an embodiment, for example, the encapsulation layer ENC may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0128] A first encapsulation inorganic layer TFE1 may be disposed on a capping layer CPL, an encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and a second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE2. Each of the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be a multilayer in which one or more inorganic layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The encapsulation organic layer TFE2 may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0129] Figure 5 The schematic diagram shows the light-emitting element of the display device 1. Figure 6 Detailed map shown Figure 5 .

[0130] Figure 6 Too Figure 4 An enlarged view of the "J" part.

[0131] refer to Figure 5 and Figure 6 The first common layer HIL can be disposed on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The first common layer HIL may include a hole transport layer disposed on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3, or may include a hole transport layer and a hole injection layer.

[0132] In the first light-emitting element ED1, the first light-emitting layer EML1 can be disposed on the first common layer HIL. In the second light-emitting element ED2, the second light-emitting layer EML2 can be disposed on the first common layer HIL. In the third light-emitting element ED3, the third light-emitting layer EML3 can be disposed on the first common layer HIL.

[0133] The second common layer ETL can be disposed on the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3. The second common layer ETL may include an electron transport layer and / or an electron injection layer.

[0134] In the display device 1 of the embodiments of this disclosure, the first light-emitting element ED1 may include a plurality of sub-light-emitting layers including a first sub-light-emitting layer SEML1 and a second sub-light-emitting layer SEML2, the second light-emitting element ED2 may include a single (or one) third sub-light-emitting layer SEML3, and the third light-emitting element ED3 may include a single (or one) fourth sub-light-emitting layer SEML4. The luminous efficiency of the first light emitted from the first light-emitting element ED1, the second light emitted from the second light-emitting element ED2, and the third light emitted from the third light-emitting element ED3 can be controlled by the number of light-emitting layers, etc.

[0135] In an embodiment, the first light-emitting layer EML1 may include a first sub-light-emitting layer SEML1, a second sub-light-emitting layer SEML2, and a first intermediate layer IL1. The first intermediate layer IL1 may be disposed between the first sub-light-emitting layer SEML1 and the second sub-light-emitting layer SEML2.

[0136] The first intermediate layer IL1 may include a first sub-intermediate layer SIL1, a first charge generation layer CGL1, and a second charge generation layer CGL2, which are stacked sequentially. In an embodiment, for example, the first sub-intermediate layer SIL1 may include an electron transport layer and / or an electron injection layer.

[0137] The first light-emitting element ED1, which includes a first charge-generating layer CGL1 and a second charge-generating layer CGL2, can be a series-connected light-emitting element. Since the first light-emitting element ED1 has a structure in which multiple sub-light-emitting layers are stacked, color purity and luminous efficiency can be improved.

[0138] The first charge-generating layer CGL1 can be a negative charge-generating layer (n-CGL). The second charge-generating layer CGL2 can be a positive charge-generating layer (p-CGL). Each of the first charge-generating layer CGL1 and the second charge-generating layer CGL2 can include a host material and a dopant. The host material can include an organic material.

[0139] Negative charges supplied from the first charge generation layer CGL1 can move toward the first sub-emitting layer SEML1 and recombine with positive charges supplied from the first pixel electrode PE1 to generate excitons. The negative charges can be electrons and the positive charges can be holes. In reality, only electrons move. However, for ease of description, it is assumed that holes also move.

[0140] In the first sub-light-emitting layer SEML1, electrons generated from the first charge-generating layer CGL1 and passing through the first sub-intermediate layer SIL1 can recombine with holes generated from the first pixel electrode PE1 and passing through the first common layer HIL. Therefore, excitons are generated due to this recombination, thereby enabling light emission in the first sub-light-emitting layer SEML1.

[0141] Positive charges supplied from the second charge generation layer CGL2 can move toward the second sub-emissive layer SEML2 and recombine with negative charges supplied from the common electrode CE to generate excitons.

[0142] In the second sub-emitting layer SEML2, holes generated from the second charge generation layer CGL2 can recombine with electrons generated from the common electrode CE and passing through the second common layer ETL. Therefore, excitons are generated due to this recombination, thereby enabling light emission in the second sub-emitting layer SEML2.

[0143] In an embodiment, the second light-emitting layer EML2 may include a second intermediate layer IL2 and a third sub-light-emitting layer SEML3. The second intermediate layer IL2 may include a second sub-intermediate layer SIL2 and a third sub-intermediate layer SIL3. The third sub-intermediate layer SIL3 may be disposed between the second sub-intermediate layer SIL2 and the third sub-light-emitting layer SEML3.

[0144] Light emission can occur in the third sub-emitting layer SEML3. Positive charges supplied from the second pixel electrode PE2 can pass through the first common layer HIL, the second sub-intermediate layer SIL2, and the third sub-intermediate layer SIL3, and can subsequently recombine with negative charges supplied from the common electrode CE. Accordingly, excitons can be generated, and light emission can occur in the third sub-emitting layer SEML3.

[0145] In an embodiment, the second sub-intermediate layer SIL2 may include a hole transport layer, or may include a hole transport layer and a hole injection layer.

[0146] The third sub-intermediate layer SIL3 can perform auxiliary functions. In one embodiment, for example, the third sub-intermediate layer SIL3 can serve as an electron blocking layer that blocks electrons moving from the common electrode CE to the third sub-emitting layer SEML3 and subsequently passing through it. In an alternative embodiment, the third sub-intermediate layer SIL3 can be a layer used to balance the thickness and / or height of the second light-emitting element ED2 with that of the first light-emitting element ED1. In an alternative embodiment, the third sub-intermediate layer SIL3 can perform the function of facilitating the injection of holes moving from the second pixel electrode PE2 toward the third sub-emitting layer SEML3.

[0147] In an embodiment, the third light-emitting layer EML3 may include a third intermediate layer IL3 and a fourth sub-light-emitting layer SEML4. The third intermediate layer IL3 may include a fourth sub-intermediate layer SIL4 and a fifth sub-intermediate layer SIL5. The fifth sub-intermediate layer SIL5 may be disposed between the fourth sub-intermediate layer SIL4 and the fourth sub-light-emitting layer SEML4.

[0148] Light emission can occur in the fourth sub-emitting layer SEML4. Positive charges supplied from the third pixel electrode PE3 can pass through the first common layer HIL, the fourth sub-intermediate layer SIL4, and the fifth sub-intermediate layer SIL5, and can subsequently recombine with negative charges supplied from the common electrode CE. Accordingly, excitons can be generated, and light emission can occur in the fourth sub-emitting layer SEML4.

[0149] In an embodiment, the fourth sub-intermediate layer SIL4 may include a hole transport layer, or may include a hole transport layer and a hole injection layer.

[0150] The fifth sub-intermediate layer SIL5 can perform auxiliary functions. In one embodiment, for example, the fifth sub-intermediate layer SIL5 can serve as an electron blocking layer that blocks electrons moving from the common electrode CE to the fourth sub-emitting layer SEML4 and subsequently through it. In an alternative embodiment, the fifth sub-intermediate layer SIL5 can be a layer used to balance the thickness and / or height of the third light-emitting element ED3 with that of the first light-emitting element ED1. In an alternative embodiment, the fifth sub-intermediate layer SIL5 can perform a function of facilitating the injection of holes moving from the third pixel electrode PE3 toward the fourth sub-emitting layer SEML4.

[0151] refer to Figure 6 The third sub-pixel SP3 may include a first light-emitting element ED1, the first sub-pixel SP1 may include a second light-emitting element ED2, and the second sub-pixel SP2 may include a third light-emitting element ED3. As described above, the first sub-pixel SP1 may emit red light, the second sub-pixel SP2 may emit green light, and the third sub-pixel SP3 may emit blue light, but the embodiments disclosed herein are not limited thereto. Considering the efficiency and / or lifetime of the light-emitting elements, the first emission region EA1 provided in the third sub-pixel SP3 emitting blue light (e.g., as shown in the image) is... Figure 4 The area of ​​the second emission region EA2 (as shown) can be larger than that of the second emission region EA2 (e.g., as shown). Figure 4 (as shown) and the third launch area EA3 (e.g., as shown) Figure 4 The area shown is the area of ​​(as shown).

[0152] The first common layer HIL can cover the embankment PDL, and each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 can be disposed in the space between the multiple embankment PDLs spaced apart from each other.

[0153] The first light-emitting layer EML1 may include a first sub-light-emitting layer SEML1, a second sub-light-emitting layer SEML2, and a first sub-intermediate layer SIL1, a first charge-generating layer CGL1, and a second charge-generating layer CGL2 sequentially disposed between the first sub-light-emitting layer SEML1 and the second sub-light-emitting layer SEML2.

[0154] The second luminescent layer EML2 may include a second sub-intermediate layer SIL2, a third sub-intermediate layer SIL3, and a third sub-luminescent layer SEML3 disposed between the first common layer HIL and the second common layer ETL.

[0155] The third luminescent layer EML3 may include a fourth sub-intermediate layer SIL4, a fifth sub-intermediate layer SIL5, and a fourth sub-luminescent layer SEML4 disposed between the first common layer HIL and the second common layer ETL.

[0156] As described above, color efficiency can be improved when each of the first luminescent layer EML1, the second luminescent layer EML2, and the third luminescent layer EML3 is perfectly positioned between the first common layer HIL and the second common layer ETL without any errors or deviations caused by the deposition process.

[0157] When there are no errors due to the deposition process, one end and the opposite end of each element included in the first light-emitting layer EML1 can be disposed between multiple dam PDLs. Similarly, one end and the opposite end of each element included in the second light-emitting layer EML2 can be disposed between multiple dam PDLs. Furthermore, one end and the opposite end of each element included in the third light-emitting layer EML3 can be disposed between multiple dam PDLs. This arrangement is ideal, and the display device 1 including the ideally arranged light-emitting elements can provide the luminous efficiency in the desired wavelength band.

[0158] Figure 7 The schematic map illustrates the current leakage caused by the deposition location deviation of the first charge generation layer CGL1. Figure 8A Detailed map shown Figure 7 ,and Figure 8B yes Figure 8A A magnified view of the BB section. Figure 9 The schematic map illustrates the current leakage caused by the deposition location deviation of the second charge generation layer CGL2. Figure 10A Detailed map shown Figure 9 ,and Figure 10B yes Figure 10A A magnified view of the CC portion.

[0159] refer to Figures 7 to 8B When performing the process of depositing the first charge generation layer CGL1, errors and / or deviations may occur due to the deposition process. This may be due to errors in the fine cell aspects of the mask process.

[0160] In an embodiment, for example, one end of the first charge generation layer CGL1 may be disposed on a dam PDL, and the opposite end may be disposed between multiple dam PDLs. Assuming that there are no errors due to the deposition process when the components in the first light-emitting layer EML1 other than the first charge generation layer CGL1 are deposited, the third sub-pixel SP3 may include both the area in the planar view where the first charge generation layer CGL1 is disposed between multiple dam PDLs and the area in the planar view where the first charge generation layer CGL1 is not disposed.

[0161] As described above, when there is no deviation due to deposition location, the first charge generation layer CGL1 supplies electrons in the direction in which the first sub-light-emitting layer SEML1 is positioned. However, when a deviation exists as described above, electrons may move in the direction in which the second common layer ETL, including the electron transport layer, is positioned. Since the second common layer ETL performs the function of supplying electrons from the common electrode CE to the light-emitting layer, when an error occurs in the deposition location of the first charge generation layer CGL1, the second common layer ETL may supply negative charges generated from the first charge generation layer CGL1.

[0162] Referring to the arrow, the negative charge generated from the first charge generation layer CGL1 may not move towards the first sub-emitting layer SEML1, which is its original destination, but may instead move towards the third sub-emitting layer SEML3 and / or the fourth sub-emitting layer SEML4. Negative charge leakage may occur compared to a scenario without errors and / or deviations due to the deposition process. In this case, the luminous efficiency of the first light-emitting element ED1 may decrease.

[0163] refer to Figures 9 to 10B When performing the process of depositing the second charge generation layer CGL2, errors and / or deviations may occur due to the deposition process. This may be due to errors in the fine unit aspects of the mask process.

[0164] In an embodiment, for example, one end of the second charge generation layer CGL2 can be disposed on the embankment PDL, and the opposite end can be disposed between multiple embankment PDLs. Assuming that there are no errors due to the deposition process when the components in the first light-emitting layer EML1 other than the second charge generation layer CGL2 are deposited, the third sub-pixel SP3 can include both the area in the planar view where the second charge generation layer CGL2 is disposed between multiple embankment PDLs and the area in the planar view where the second charge generation layer CGL2 is not disposed.

[0165] As described above, when there is no deviation due to deposition location, the second charge generation layer CGL2 supplies holes in the direction in which the second sub-light-emitting layer SEML2 is positioned. However, when a deviation exists as described above, the holes may move in the direction in which the first common layer HIL, including the hole transport layer, is positioned. Since the first common layer HIL performs the function of supplying holes from the pixel electrode to the light-emitting layer, when an error occurs in the deposition location of the second charge generation layer CGL2, the first common layer HIL may supply positive charges generated from the second charge generation layer CGL2.

[0166] Referring to the arrow, the positive charges generated from the second charge generation layer CGL2 may not move towards the second sub-emitting layer SEML2, which is its original destination, but may instead move towards the third sub-emitting layer SEML3 and / or the fourth sub-emitting layer SEML4. This could result in positive charge leakage compared to a scenario without errors and / or deviations due to the deposition process. In this case, the luminous efficiency of the first light-emitting element ED1 may be reduced.

[0167] refer to Figures 7 to 10B When errors occur in the process of depositing the first charge generation layer CGL1 and / or the second charge generation layer CGL2 as described above, the current that should flow to the first light-emitting element ED1 may flow to the second light-emitting element ED2 and the third light-emitting element ED3. This is called lateral leakage.

[0168] When light-emitting elements, including those in a series configuration, are placed, the charge-generating layer may contribute to the emission of light in bands other than those intended by the implementer. This may reduce the efficiency of the display device in terms of light efficiency and / or color purity, as well as power consumption.

[0169] Figure 11 The schematic diagram illustrates an embodiment of the light-emitting element of the display device 1 according to the present disclosure. Figure 12 Detailed map shown Figure 11 .

[0170] refer to Figure 11 and Figure 12 The display device 1 in the embodiments of this disclosure provides a technical solution to the problems described above. In the embodiments, for example, the first sub-light-emitting layer SEML1 and the second sub-light-emitting layer SEML2 in the display device 1 can be formed to have an area larger than that of the first intermediate layer IL1.

[0171] In this embodiment, the first sub-emitting layer SEML1 and the second sub-emitting layer SEML2 may have an area larger than that of the first charge-generating layer CGL1. The first sub-emitting layer SEML1 and the second sub-emitting layer SEML2 may have an area larger than that of the second charge-generating layer CGL2. The first sub-emitting layer SEML1 and the second sub-emitting layer SEML2 may have an area larger than that of the first sub-intermediate layer SIL1.

[0172] The entire first charge generation layer CGL1 can overlap with the first sub-emitting layer SEML1 and the second sub-emitting layer SEML2. The entire second charge generation layer CGL2 can overlap with the first sub-emitting layer SEML1 and the second sub-emitting layer SEML2. The entire first sub-intermediate layer SIL1 can overlap with the first sub-emitting layer SEML1 and the second sub-emitting layer SEML2.

[0173] In an embodiment, the second sub-light-emitting layer SEML2 may include a first region EMA1 that overlaps with the first sub-light-emitting layer SEML1. Furthermore, a charge-generating region CMA may be defined within the first light-emitting element ED1. The charge-generating region CMA is the region that overlaps with the charge-generating layer. In the display device of this embodiment, the area of ​​the first region EMA1 may be larger than the area of ​​the charge-generating region CMA. In an embodiment, for example, the entire charge-generating region CMA may overlap with the first region EMA1. At least a portion of the first region EMA1 may overlap with the charge-generating region CMA.

[0174] Figure 13 The schematic diagram illustrates an embodiment of an error occurring in the deposition position of the first charge generation layer CGL1 in the display device 1 according to the present disclosure. Figure 14 Detailed map shown Figure 13 .

[0175] Figure 14 Too Figure 12 An enlarged view of the "K" part.

[0176] refer to Figure 13 and Figure 14 When an error occurs in the process of depositing the first charge generation layer CGL1, one end of the first charge generation layer CGL1 can be disposed on the dike PDL, and the opposite end can be disposed between multiple dike PDLs. The end of the first charge generation layer CGL1 disposed on the dike PDL can overlap with the portion of the first common layer HIL disposed on the dike PDL.

[0177] The second sub-emitting layer SEML2 may include a first region EMA1 that overlaps with the first sub-emitting layer SEML1. In an embodiment, the first region EMA1 may include a first sub-region SEMA1 that overlaps with the charge generation layer. Furthermore, the first region EMA1 may include a second sub-region SEMA2 that is adjacent to the first sub-region SEMA1.

[0178] When an error occurs in the process of depositing the first charge generation layer CGL1, the second charge generation layer CGL2 and the second sub-light-emitting layer SEML2 can be disposed on the first charge generation layer CGL1.

[0179] The second sub-emitting layer SEML2 has a larger area than the first charge-generating layer CGL1. Therefore, even if the deposition position of the first charge-generating layer CGL1 changes due to process errors, there is a relatively high probability that the second sub-emitting layer SEML2, rather than the second common layer ETL, will be disposed on the portion of the first charge-generating layer CGL1 that is disposed on the embankment PDL.

[0180] Referring to the process of lateral leakage of current described above, the possibility of leakage current generated via the second common layer ETL can be reduced by providing a second sub-light-emitting layer SEML2 on the portion of the first charge-generating layer CGL1 on the embankment PDL.

[0181] In the display device 1 of the embodiments of this disclosure, the areas of the first sub-light-emitting layer SEML1 and the second sub-light-emitting layer SEML2 can be larger than the areas of the first charge-generating layer CGL1 and the second charge-generating layer CGL2. Correspondingly, the areas of the first charge-generating layer CGL1 and the second charge-generating layer CGL2 that are in direct contact with the first common layer HIL and the second common layer ETL can be reduced. Here, "direct contact" refers to a state where no other element is disposed between a predetermined element and another predetermined element. By having this structure, the display device 1 can standardize the luminous efficiency in a series structure. Furthermore, since the luminous efficiency of the display device 1 is improved, the display device 1 can be driven with relatively low power.

[0182] In the second sub-region SEMA2, the first sub-emitting layer SEML1 and the second sub-emitting layer SEML2 can be formed in direct contact with each other. In the first sub-region SEMA1, the first sub-emitting layer SEML1 and the first charge-generating layer CGL1 can be formed in direct contact with each other on the embankment PDL. Furthermore, the second sub-emitting layer SEML2 and the second charge-generating layer CGL2 can be formed in direct contact with each other. In the first sub-region SEMA1, the second sub-emitting layer SEML2 can be in contact with the second charge-generating layer CGL2 among multiple embankment PDLs.

[0183] Regarding thickness, referring to the region above the embankment PDL, the distance H1 from the lower surface of the first sub-emissive layer SEML1 to the upper surface of the second sub-emissive layer SEML2 in the first sub-region SEMA1 can be defined. Furthermore, referring to the region above the embankment PDL, the distance H2 from the lower surface of the first sub-emissive layer SEML1 to the upper surface of the second sub-emissive layer SEML2 in the second sub-region SEMA2 can be defined. In the event of an error, distance H1 may be greater than distance H2 due to the first charge-generating layer CGL1.

[0184] Figure 15 The schematic diagram illustrates an embodiment of an error occurring in the deposition position of the second charge generation layer CGL2 in the display device 1 according to the present disclosure. Figure 16 Detailed map shown Figure 15 .

[0185] Figure 16 Too Figure 12 An enlarged view of the "K" part.

[0186] refer to Figure 15 and Figure 16 When errors occur in the process of depositing the second charge generation layer CGL2, one end of the second charge generation layer CGL2 can be disposed on the dike PDL, and the opposite end can be disposed between multiple dike PDLs. The end of the second charge generation layer CGL2 disposed on the dike PDL can overlap with the portion of the first common layer HIL disposed on the dike PDL.

[0187] The second sub-emitting layer SEML2 may include a first region EMA1 that overlaps with the first sub-emitting layer SEML1. In an embodiment, the first region EMA1 may include a first sub-region SEMA1 that overlaps with the charge generation layer. Furthermore, the first region EMA1 may include a second sub-region SEMA2 that is adjacent to the first sub-region SEMA1.

[0188] When errors occur in the process of depositing the second charge generation layer CGL2, the first charge generation layer CGL1 and the first sub-light-emitting layer SEML1 can be disposed below the second charge generation layer CGL2.

[0189] The first sub-emitting layer SEML1 has a larger area than the second charge-generating layer CGL2. Therefore, even if the deposition position of the second charge-generating layer CGL2 changes due to process errors, there is a relatively high probability that the first sub-emitting layer SEML1, rather than the first common layer HIL, will be disposed below the portion of the second charge-generating layer CGL2 that is disposed on the embankment PDL.

[0190] Referring to the process of lateral leakage of current described above, the possibility of leakage current generated via the first common layer HIL can be reduced by providing a first sub-light-emitting layer SEML1 below the portion of the second charge-generating layer CGL2 on the embankment PDL.

[0191] In the display device 1 of the embodiments of this disclosure, the areas of the first sub-light-emitting layer SEML1 and the second sub-light-emitting layer SEML2 can be larger than the areas of the second charge-generating layer CGL2 and the first charge-generating layer CGL1. Correspondingly, the areas of the second charge-generating layer CGL2 and the first charge-generating layer CGL1 that are in direct contact with the second common layer ETL and the first common layer HIL can be reduced. Here, "direct contact" refers to a state where no other element is disposed between a predetermined element and another predetermined element. By having this structure, the display device 1 can standardize the luminous efficiency in a series structure. Furthermore, since the luminous efficiency of the display device 1 is improved, the display device 1 can be driven with relatively low power.

[0192] In the second sub-region SEMA2, the first sub-emitting layer SEML1 and the second sub-emitting layer SEML2 can be formed in direct contact with each other. In the first sub-region SEMA1, the first sub-emitting layer SEML1 and the second charge-generating layer CGL2 can be formed in direct contact with each other on the embankment PDL. Furthermore, the second sub-emitting layer SEML2 and the first charge-generating layer CGL1 can be formed in direct contact with each other. In the first sub-region SEMA1, the second sub-emitting layer SEML2 can contact the first charge-generating layer CGL1 among multiple embankment PDLs.

[0193] Regarding thickness, referring to the region above the embankment PDL, the distance H1 from the lower surface of the first sub-emissive layer SEML1 to the upper surface of the second sub-emissive layer SEML2 in the first sub-region SEMA1 can be defined. Furthermore, referring to the region above the embankment PDL, the distance H2 from the lower surface of the first sub-emissive layer SEML1 to the upper surface of the second sub-emissive layer SEML2 in the second sub-region SEMA2 can be defined. In the event of errors, distance H1 may be greater than distance H2 due to the second charge-generating layer CGL2.

[0194] Figure 17 This is a plan view illustrating an embodiment of the deposition margin applied to the display device 1 according to the present disclosure. Figure 18 This is a plan view illustrating an embodiment in which no error occurs in the deposition position in the display device 1 according to the present disclosure. Figure 19 This is a plan view illustrating an embodiment of an error occurring in the deposition position of the charge generation layer in the display device 1 according to the present disclosure. Figure 20 This is a plan view illustrating an embodiment of an error occurring in the deposition position of the charge generation layer and the deposition position of the light-emitting layer in the display device 1 according to the present disclosure.

[0195] refer to Figure 17 The first sub-pixel SP1 may include a second emission region EA2, the second sub-pixel SP2 may include a third emission region EA3, and the third sub-pixel SP3 may include a first emission region EA1. The area of ​​the first emission region EA1 may be larger than the areas of the second emission region EA2 and the third emission region EA3. In an embodiment, an edge line defined by the edges of each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be provided.

[0196] In this embodiment, the distance D23E between the edge of the third emitting region EA3 and the edge of the first emitting region EA1 can be smaller than the distance D13E between the edge of the first emitting region EA1 and the edge of the second emitting region EA2. Therefore, when the maximum value of the deposition margin is preset considering the distance D23E between the edge of the third emitting region EA3 and the edge of the first emitting region EA1, even if deposition errors occur in the charge generation layer CGL1 or CGL2 and / or the sub-emitting layer SEML1 or SEML2, the distance D13E between the edge of the first emitting region EA1 and the edge of the second emitting region EA2 will not be substantially affected by errors caused by the deposition process. In the display device 1 of this embodiment, since the first light-emitting element ED1 includes charge generation layers CGL1 and CGL2, it is only necessary to compare the distance D13E between the edge of the first emitting region EA1 and the edge of the second emitting region EA2 and the distance D23E between the edge of the third emitting region EA3 and the edge of the first emitting region EA1.

[0197] The charge generation layers CGL1 and CGL2 can be deposited with the second margin line DML2, and the sub-emissive layers SEML1 and SEML2 can be deposited with the first margin line DML1.

[0198] refer to Figure 18 The dimensions of the first sub-emissive layer SEML1 and the second sub-emissive layer SEML2 can be larger than the dimensions of both the first charge generation layer CGL1 and the second charge generation layer CGL2. Therefore, the likelihood of reduced light efficiency due to current leakage when errors occur during the deposition process is relatively low.

[0199] In an embodiment, the second margin line DML2 may be closer to the center C3 of the first emission region EA1 than the line defined by the edges of the first sub-emitting layer SEML1 and the second sub-emitting layer SEML2.

[0200] refer to Figure 19 Even if the maximum error occurs in the deposition process of the first charge generation layer CGL1 and / or the second charge generation layer CGL2, since the area of ​​the first sub-emitting layer SEML1 and the second sub-emitting layer SEML2 is already larger than the area of ​​the first charge generation layer CGL1 and the second charge generation layer CGL2, and since the second margin line DML2 is closer to the center C3 of the first emission region EA1 than the edge line of the sub-emitting layers SEML1 and SEML2, the entire charge generation layer CGL1 and CGL2 can overlap with the sub-emitting layers SEML1 and SEML2.

[0201] Even if the sub-emitting layers SEML1 and SEML2 are deposited normally, the second margin line DML2 can be closer to the center C3 of the first emission region EA1 than the line defined by the edges of the sub-emitting layers SEML1 and SEML2. Therefore, the probability that the charge generating layers CGL1 or CGL2 will directly contact the common layer is low, and the light efficiency of the display device 1 can be improved.

[0202] refer to Figure 20 When maximum errors occur in the deposition processes of both charge generation layers CGL1 and CGL2, and sub-emissive layers SEML1 and SEML2, the probability that charge generation layer CGL1 or CGL2 will directly contact the common layer is relatively low, since the areas of the first sub-emissive layer SEML1 and the second sub-emissive layer SEML2 are already larger than the areas of the first charge generation layer CGL1 and the second charge generation layer CGL2. This is essentially similar to the case where no errors occur in the deposition process.

[0203] The display device in the embodiments of this disclosure can be applied to various electronic devices. The electronic device in the embodiments includes the display device described above, and may further include modules or devices with other additional functions in addition to the display device.

[0204] Figure 21 This is a block diagram of an embodiment of the electronic device 10 according to the present disclosure. Figure 22 This is a schematic diagram of an electronic device 10 according to various embodiments of the present disclosure.

[0205] refer to Figure 21 The electronic device 10 in the embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0206] The processor 12 may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and a controller.

[0207] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals (also known as image signals) and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0208] The power module 14 may include a power supply module such as a power adapter or a battery device. The power module 14 may also include a power conversion module. This power conversion module can convert the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0209] At least one of the components in the electronic device 10 described above may be included in the display device according to the embodiments described above. Furthermore, some of the modules described above may be included in the display device, and other modules may be provided separately from the display device. In embodiments, for example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may not be provided in the display device, but rather as other devices within the electronic device.

[0210] refer to Figure 22 Various electronic devices that apply the display devices in the embodiments of this disclosure may include image display electronic devices (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions 10_1d, and desktop monitors 10_1e). Furthermore, various electronic devices that apply the display devices in the embodiments of this disclosure may include wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) that include display modules, and vehicle electronic devices 10_3 that include display modules (such as rearview mirror displays and central information displays (CIDs) placed on the vehicle's dashboard, center console, and instrument panel).

[0211] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art to which this disclosure pertains will understand that the present disclosure can be practiced in other predetermined forms without altering the technical concept or essential features of the present disclosure. Therefore, it should be understood that the embodiments described above are exemplary in all respects and are not intended to be limiting.

Claims

1. A display device, comprising: substrate; A first electrode is disposed on the substrate; The second electrode is disposed on the first electrode; as well as A first light-emitting layer is disposed between the first electrode and the second electrode. The first light-emitting layer includes a first sub-light-emitting layer, a charge-generating layer, and a second sub-light-emitting layer. The area of ​​the first sub-light-emitting layer is larger than the area of ​​the charge-generating layer.

2. The display device according to claim 1, wherein, The area of ​​the second sub-light-emitting layer is larger than the area of ​​the charge-generating layer.

3. The display device according to claim 1, further comprising: A first common layer is disposed between the first electrode and the first light-emitting layer; as well as The second common layer is disposed between the first light-emitting layer and the second electrode.

4. The display device according to claim 3, comprising: The first launch area, the second launch area, and the third launch area are separated from each other; A second light-emitting layer is disposed in the second emitting region; as well as A third light-emitting layer is disposed in the third emission region. The first light-emitting layer is disposed in the first emitting region.

5. The display device according to claim 4, wherein, The area of ​​the first launch region is greater than the area of ​​the second launch region and the area of ​​the third launch region.

6. The display device according to claim 4, wherein, Each of the second light-emitting layer and the third light-emitting layer is disposed between the first common layer and the second common layer. The second light-emitting layer includes a second intermediate layer and a third sub-light-emitting layer, and the third light-emitting layer includes a third intermediate layer and a fourth sub-light-emitting layer.

7. The display device according to claim 6, wherein, The second intermediate layer includes a second sub-intermediate layer and a third sub-intermediate layer, and the third intermediate layer includes a fourth sub-intermediate layer and a fifth sub-intermediate layer.

8. The display device according to claim 4, wherein, The first light-emitting layer includes a first intermediate layer, which includes the charge-generating layer and a first sub-intermediate layer.

9. The display device according to claim 8, wherein, The area of ​​the first sub-light-emitting layer and the area of ​​the second sub-light-emitting layer are greater than the area of ​​the first sub-intermediate layer.

10. The display device according to any one of claims 1 to 9, wherein, The charge generation layer includes a first charge generation layer and a second charge generation layer disposed between the first charge generation layer and the second sub-light-emitting layer.

11. The display device according to claim 4, wherein, The second sub-light-emitting layer includes a first region that overlaps with the first sub-light-emitting layer, and the first region includes a first sub-region that overlaps with the charge-generating layer.

12. The display device according to claim 11, wherein, The first region further includes a second sub-region adjacent to the first sub-region, and the distance from the lower surface of the first sub-light-emitting layer to the upper surface of the second sub-light-emitting layer in the first sub-region is greater than the distance from the lower surface of the first sub-light-emitting layer to the upper surface of the second sub-light-emitting layer in the second sub-region.

13. An electronic device comprising: The processor provides the image signal; A display module receives the image signal from the processor and displays the image; the display module includes: A substrate, wherein a first emission region, a second emission region and a third emission region are defined spaced apart from each other; Multiple first electrodes are disposed on the substrate; A first light-emitting layer is disposed on a first electrode that overlaps with the first emission region among the plurality of first electrodes. The first light-emitting layer includes a first sub-light-emitting layer, a charge generation layer, and a second sub-light-emitting layer. The second light-emitting layer is disposed on the first electrode among the plurality of first electrodes that overlaps with the second emission region, and the second light-emitting layer includes a single light-emitting layer; A third light-emitting layer is disposed on one of the plurality of first electrodes, overlapping the third emitting region, the third light-emitting layer comprising a single light-emitting layer; and A second electrode is disposed on the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer; and The power supply module supplies power to the display module.

14. The electronic device according to claim 13, wherein, The second sub-light-emitting layer includes a first region that overlaps with the first sub-light-emitting layer, and the first region includes a first sub-region that overlaps with the charge-generating layer.

15. The electronic device according to claim 14, wherein, The first region further includes a second sub-region adjacent to the first sub-region, and the distance from the lower surface of the first sub-light-emitting layer to the upper surface of the second sub-light-emitting layer in the first sub-region is greater than the distance from the lower surface of the first sub-light-emitting layer to the upper surface of the second sub-light-emitting layer in the second sub-region.

16. The electronic device according to claim 13, wherein, The area of ​​the first sub-light-emitting layer is larger than the area of ​​the charge-generating layer.

17. The electronic device according to claim 16, wherein, The area of ​​the second sub-light-emitting layer is larger than the area of ​​the charge-generating layer.

18. The electronic device of claim 13, further comprising: A first common layer is disposed between the plurality of first electrodes and the first light-emitting layer, and overlaps with the first emitting region, the second emitting region and the third emitting region; as well as The second common layer is disposed between the first light-emitting layer and the second electrode, and overlaps with the first emission region, the second emission region and the third emission region.

19. The electronic device according to claim 18, wherein, Each of the second light-emitting layer and the third light-emitting layer is disposed between the first common layer and the second common layer. The second light-emitting layer includes a second intermediate layer and a third sub-light-emitting layer, and the third light-emitting layer includes a third intermediate layer and a fourth sub-light-emitting layer.

20. The electronic device according to claim 19, wherein, The second intermediate layer includes a second sub-intermediate layer and a third sub-intermediate layer, and the third intermediate layer includes a fourth sub-intermediate layer and a fifth sub-intermediate layer.

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