Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device. The array substrate is characterized in that a first light shielding part is arranged between a substrate and an active layer, a second light shielding part is arranged on a side of the active layer away from the substrate, a normal projection of a channel region on the substrate at least partially overlaps a normal projection of the first light shielding part on the substrate, and a normal projection of the channel region on the substrate at least partially overlaps a normal projection of the second light shielding part on the substrate. The first light shielding part and the second light shielding part shield light from below and above the channel region respectively, thereby improving the stability of the oxide transistor, improving the uniformity of display, and improving the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is considered the most promising next-generation display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] Based on this, this application provides an array substrate, a display panel, and a display device, which can effectively improve the performance of display products.

[0005] In a first aspect, this application provides an array substrate, comprising: Substrate; An active layer and multiple conductor layers are stacked on one side of the substrate. The active layer and the multiple conductor layers form at least one pixel circuit. The pixel circuit includes multiple transistors, and each transistor includes a channel region located in the active layer. A first light-shielding portion is disposed between the substrate and the active layer; The second light-shielding portion is disposed on the side of the active layer away from the substrate; Wherein, the orthographic projection of the channel region on the substrate at least partially overlaps with the orthographic projection of the first light-shielding portion on the substrate, and the orthographic projection of the channel region on the substrate at least partially overlaps with the orthographic projection of the second light-shielding portion on the substrate.

[0006] In one embodiment, the orthographic projection of the plurality of channel regions on the substrate is located within the orthographic projection of the first light-shielding portion on the substrate, and the orthographic projection of the plurality of channel regions on the substrate is located within the orthographic projection of the second light-shielding portion on the substrate.

[0007] In one embodiment, the plurality of transistors include a driving transistor, a data writing transistor, a reference voltage writing transistor, a reset transistor, and a light-emitting control transistor, and the pixel circuit further includes a storage capacitor and a compensation capacitor; Preferably, the orthogonal projections of the driving transistor, the data writing transistor, the reference voltage writing transistor, the reset transistor, the light-emitting control transistor, the storage capacitor, and at least a portion of the compensation capacitor onto the substrate are all located within the orthogonal projection of the second light-shielding portion onto the substrate.

[0008] In one embodiment, the first light-shielding portion is distributed over one or more of the conductor layers; And / or, the second light-shielding portion is distributed on one or more of the conductor layers.

[0009] In one embodiment, the multilayer conductor layer includes a first conductor layer, a second conductor layer, a third conductor layer, a fourth conductor layer, and a fifth conductor layer. The first conductor layer is located between the substrate and the active layer, the second conductor layer is located between the first conductor layer and the second conductor layer, the third conductor layer is located on the side of the active layer away from the substrate, and the fourth conductor layer is located on the side of the third conductor layer away from the substrate. The first light-shielding part is located in the first conductor layer, and the second light-shielding part is located in the fifth conductor layer.

[0010] In one embodiment, the plurality of transistors include light-emitting control transistors, the array substrate further includes light-emitting control signal lines, the light-emitting control transistors are connected to the light-emitting control signal lines, the light-emitting control signal lines are located within multiple conductor layers, and the light-emitting control signal lines in the multiple conductor layers are connected in parallel.

[0011] In one embodiment, the light-emitting control signal lines in the plurality of conductor layers extend in the same direction and their orthogonal projections on the substrate overlap each other.

[0012] In one embodiment, the light emission control signal line is located in at least three of the conductor layers; Preferably, the multilayer conductor layer includes a first conductor layer, a second conductor layer, a third conductor layer, a fourth conductor layer, and a fifth conductor layer. The first conductor layer is located between the substrate and the active layer, the second conductor layer is located between the first conductor layer and the second conductor layer, the third conductor layer is located on the side of the active layer away from the substrate, and the fourth conductor layer is located on the side of the third conductor layer away from the substrate. The light-emitting control signal line is partially located in the first conductor layer, partially in the third conductor layer, and partially in the fourth conductor layer.

[0013] On the other hand, this application also discloses a display panel comprising the array substrate described in any of the above claims.

[0014] Furthermore, this application also discloses a display device that includes the aforementioned display panel.

[0015] The array substrate provided in this application provides a first light-shielding portion between the substrate and the active layer, and a second light-shielding portion on the side of the active layer away from the substrate. The orthographic projection of the channel region on the substrate at least partially overlaps with the orthographic projection of the first light-shielding portion on the substrate, and the orthographic projection of the channel region on the substrate at least partially overlaps with the orthographic projection of the second light-shielding portion on the substrate. By using the first light-shielding portion and the second light-shielding portion to shield light from below and above the channel region, respectively, the stability of the oxide transistor is improved, which is beneficial to improving the uniformity of the display and thus improving the display effect. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a portion of the film layer structure of the array substrate in one embodiment of this application; Figure 2 This is a schematic diagram of the pixel circuit in the array substrate in another embodiment of this application; Figure 3 This is a timing diagram of the pixel circuit in the array substrate in another embodiment of this application; Figure 4 This is a layout of the first conductor layer in the array substrate in another embodiment of this application; Figure 5 This is a layout of the first conductor layer and the second conductor layer in the array substrate in another embodiment of this application; Figure 6 This is a layout of the first conductor layer, the second conductor layer, and the active layer in an array substrate according to another embodiment of this application; Figure 7 This is a layout of the first conductor layer, the second conductor layer, the active layer, and the third conductor layer in an array substrate according to another embodiment of this application; Figure 8 This is a layout of the first conductor layer, the second conductor layer, the active layer, the third conductor layer and the first interlayer dielectric layer in an array substrate according to another embodiment of this application; Figure 9 This is a layout of the first conductor layer, second conductor layer, active layer, third conductor layer, first interlayer dielectric layer and second interlayer dielectric layer in the array substrate in another embodiment of this application; Figure 10This is a layout of the first conductor layer, second conductor layer, active layer, third conductor layer, first interlayer dielectric layer, second interlayer dielectric layer and fourth conductor layer in an array substrate according to another embodiment of this application; Figure 11 This is a layout of the first conductor layer, second conductor layer, active layer, third conductor layer, first interlayer dielectric layer, second interlayer dielectric layer, fourth conductor layer and planarization layer in an array substrate according to another embodiment of this application; Figure 12 This is a layout of the first conductor layer, second conductor layer, active layer, third conductor layer, first interlayer dielectric layer, second interlayer dielectric layer, fourth conductor layer, planarization layer and fifth conductor layer in an array substrate in another embodiment of this application.

[0018] Marker explanation: 100. Array substrate; 1. Gate; 2. Source; 3. Drain; 10. Substrate; 20. Active layer; 21. Channel region; 30. Conductor layer; 31. First conductor layer; 32. Second conductor layer; 321. First upper electrode; 322. Lower electrode; 33. Third conductor layer; 331. Second upper electrode; 34. Fourth conductor layer; 35. Fifth conductor layer; 40. First light-shielding portion; 401. First sub-part; 402. Second sub-part; 50. Second light-shielding portion; 61. First interlayer dielectric layer; 62. Second interlayer dielectric layer; 71. Planarization layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0020] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0021] In related technologies, OLED display products generally employ pixel compensation circuits that compensate for the threshold voltage (Vth) of the driving transistor to drive OLED light emission. By compensating for the threshold voltage, the display unevenness caused by the drift of the threshold voltage of the driving transistor can be effectively improved. However, P-type transistors made of low-temperature polycrystalline silicon have poor characteristic uniformity. Under illumination, photogenerated carriers fill grain boundaries and interface traps, causing non-uniform drift in the threshold voltage and off-state current, further degrading the device uniformity and thus affecting the display effect of the display product.

[0022] Based on this, this application provides an array substrate solution to solve the above-mentioned technical problems.

[0023] Reference Figure 1 As shown, an array substrate 100 is disclosed in one embodiment of this application, which includes: a substrate 10; an active layer 20 and a multilayer conductor layer 30 stacked on one side of the substrate 10, wherein the active layer 20 and the multilayer conductor layer 30 form at least one pixel circuit, the pixel circuit including a plurality of transistors M, the transistors M including a channel region 21, the channel region 21 being located in the active layer 20.

[0024] The array substrate 100 also includes a first light-shielding portion 40 and a second light-shielding portion 50. The first light-shielding portion 40 is disposed between the substrate 10 and the active layer 20, and the second light-shielding portion 50 is disposed on the side of the active layer 20 away from the substrate 10.

[0025] The orthographic projection of the channel region 21 on the substrate 10 at least partially overlaps with the orthographic projection of the first light-shielding portion 40 on the substrate 10, and the orthographic projection of the channel region 21 on the substrate 10 at least partially overlaps with the orthographic projection of the second light-shielding portion 50 on the substrate 10.

[0026] The array substrate 100 provided in this embodiment provides a first light-shielding portion 40 between the substrate 10 and the active layer 20, and a second light-shielding portion 50 on the side of the active layer 20 away from the substrate 10. The orthographic projection of the channel region 21 on the substrate 10 at least partially overlaps with the orthographic projection of the first light-shielding portion 40 on the substrate 10, and the orthographic projection of the channel region 21 on the substrate 10 at least partially overlaps with the orthographic projection of the second light-shielding portion 50 on the substrate 10. By using the first light-shielding portion 40 and the second light-shielding portion 50 to shield light from below and above the channel region 21, respectively, the stability of the oxide transistor is improved, which is beneficial to improving the uniformity of the display and thus improving the display effect.

[0027] The substrate 10 has the functions of support, protection and buffer. The substrate 10 can be a flexible substrate, such as a polyimide (PI) substrate, or a rigid substrate, such as a glass substrate. No limitation is made here.

[0028] Optionally, the active layer 20 can be made of metal oxides such as IGZO, IGTO, ITZO, and other high-mobility materials.

[0029] Optionally, the first light-shielding part 40 and the second light-shielding part 50 are metal layers.

[0030] Optionally, the transistor M formed in this embodiment is a P-type metal-oxide thin-film transistor or an N-type oxide thin-film transistor.

[0031] In one embodiment, the orthographic projections of the plurality of channel regions 21 on the substrate 10 lie within the orthographic projections of the first light-shielding portion 40 on the substrate 10, and the orthographic projections of the plurality of channel regions 21 on the substrate 10 lie within the orthographic projections of the second light-shielding portion 50 on the substrate 10. By using the first light-shielding portion 40 to completely block the plurality of channel regions 21 from above, and by using the second light-shielding portion 50 to completely block the plurality of channel regions 21 from below, the stability of the oxide transistor is further improved, and the uniformity of the display is enhanced.

[0032] Optionally, the pixel circuit includes multiple transistors M, with the channel region 21 of each transistor M located in the active layer 20. The orthographic projection of the channel region 21 of each transistor onto the substrate 10 at least partially overlaps with the orthographic projection of the first light-shielding portion 40 onto the substrate 10, and the orthographic projection of the channel region 21 of each transistor onto the substrate 10 at least partially overlaps with the orthographic projection of the second light-shielding portion 50 onto the substrate 10. This achieves light shielding of the channel regions 21 of all transistors M in the display circuit, ensuring the stability of the oxide transistors in all transistors and the consistency of the performance of different transistors.

[0033] Optionally, the orthographic projection of the channel region 21 of each transistor onto the substrate 10 lies within the orthographic projection of the first light-shielding portion 40 onto the substrate 10, and the orthographic projection of the channel region 21 of each transistor onto the substrate 10 lies within the orthographic projection of the second light-shielding portion 50 onto the substrate 10. This achieves complete shielding of the channel regions 21 of all transistors M in the pixel circuit, ensuring the stability and performance consistency of the oxide transistors in all transistors, thereby improving the uniformity of the display.

[0034] In one embodiment, the plurality of transistors includes a driving transistor, a data writing transistor, a reference voltage writing transistor, a reset transistor, and a light-emitting control transistor. The pixel circuit also includes a storage capacitor and a compensation capacitor. The driving transistor, data writing transistor, reference voltage writing transistor, reset transistor, light-emitting control transistor, storage capacitor, and compensation capacitor constitute a 5T2C pixel circuit.

[0035] Among them, the 5T2C pixel circuit can fully adapt to the characteristics of oxide transistors, which have relatively low carrier mobility and threshold voltage that is easily affected by light and bias voltage. Through the collaborative compensation mechanism of dual capacitors and multiple transistors, it effectively offsets the threshold voltage drift of the driving transistor, mobility fluctuations and brightness deviation caused by OLED device aging. It significantly suppresses the impact of uneven electrical characteristics caused by light on the display effect, improves current stability and pixel brightness uniformity, and reduces the stringent requirements for device characteristic consistency. It achieves low image retention, low flicker and high reliability display in high resolution and high refresh rate AMOLED panels, giving full play to the process advantages of oxide transistors, such as low leakage current and suitability for large size and high PPI backplanes.

[0036] Combining the simultaneous top and bottom light-blocking design in this application with the 5T2C pixel circuit can further improve the uniformity of the display panel.

[0037] Reference Figure 2 The diagram shows a 5T2C pixel circuit provided in an embodiment of this application, which includes a driving transistor M1, a data writing transistor M2, a reset transistor M3, a light-emitting control transistor M4, a reference voltage writing transistor M5, a storage capacitor Cst1, and a compensation capacitor Cst2.

[0038] The gate of driving transistor M1 is connected to node G, its drain is connected to the drain of light-emitting control transistor M4, and its source is connected to node S; the gate of data writing transistor M2 is connected to the write scan signal SnW, its source is connected to the data voltage signal Data, and its drain is connected to node G; the gate of reset transistor M3 is connected to the reset signal Reset, its source is connected to the initialization voltage signal Vini, and its drain is connected to node G; the gate of light-emitting control transistor M4 is connected to the light-emitting control signal EM, its source is connected to the high-level power supply signal VDD, and its drain is connected to the drain of driving transistor M1; the gate of reference voltage writing transistor M5 is connected to the reference scan signal SnR, its source is connected to the reference voltage signal Vref, and its drain is connected to node S; one end of storage capacitor Cst1 is connected to the high-level power supply signal VDD, and the other end is connected to node S; one end of compensation capacitor Cst2 is connected to node G, and the other end is connected to node S; the anode of light-emitting device D1 is connected to node S, and the cathode is connected to the low-level power supply signal VSS.

[0039] Reference Figure 3 The diagram shown is the timing diagram of the 5T2C pixel circuit described above. t0 represents the initial state, and t1, t2, t3, and t4 represent stage one, stage two, stage three, and stage four, respectively.

[0040] In the initial stage: the driving transistor M1 and the light-emitting control transistor M4 are turned on, the light-emitting device D1 (OLED) is lit, and the data writing transistor M2, the reset transistor M3 and the reference voltage writing transistor M5 are all turned off; the storage capacitor Cst1 and the compensation capacitor Cst2 maintain the voltage state of the previous frame, maintain the light-emitting current of the OLED, and achieve stable display of the current grayscale.

[0041] In Phase 1: The reference scan signal SnR and the reset signal Reset are set high, which turns on the reset transistor M3 and the reference voltage write transistor M5, and turns off the drive transistor M1, the data write transistor M2, and the light emission control transistor M4, thus completing the global reset of the pixel node and the capacitor.

[0042] Specifically, the gate node G is pulled to the initialization voltage signal Vini through the turned-on reset transistor M3, and the source / anode node S (Anode) is pulled to the reference voltage signal Vref through the turned-on reference voltage write transistor M5, completely clearing the residual charge of the previous frame and establishing a unified initial potential for subsequent threshold compensation and data writing.

[0043] The voltage difference across the storage capacitor Cst1 is VDD-Vref, and the voltage difference across the compensation capacitor Cst2 is Vini-Vref, thus completing the initial charging of the capacitors and eliminating the interference of historical voltage on the current frame.

[0044] In stage two: the reference scan signal SnR is set low, the reference voltage writing transistor M5 is turned off, the driving transistor M1 is turned on, the reset transistor M3 remains on (the potential at point G is clamped to Vini by the reset transistor M3), the light-emitting control transistor M4 and the data writing transistor M2 remain off, and the sampling and storage of the threshold voltage of the driving transistor M1 is completed.

[0045] Specifically, the source node S potential starts from the initial reference voltage signal Vref and is continuously charged by the conduction current of the driving transistor M1, gradually increasing to VG-Vth=Vini-Vth (the driving transistor M1 is operating in the source follower state, and when the gate-source voltage Vgs is equal to the threshold voltage Vth, the driving current is 0, and the charging at point S stops). The voltage difference across the compensation capacitor Cst2 is updated to Vini-(Vini-Vth)=Vth, and the voltage across the capacitor remains unchanged, thus completing the accurate sampling and storage of the threshold voltage Vth of the driving transistor M1. The voltage difference across the storage capacitor Cst1 is synchronously updated to VDD-(Vini-Vth), providing a stable foundation for capacitive coupling during the subsequent data writing phase.

[0046] In stage three: the light emission control signal EM and the reset signal Reset are set low in sequence, turning off the light emission control transistor M4 and the reset transistor M3. Then, the scan signal SnW is set high, and only the data writing transistor M2 is turned on, completing the writing and coupling of the data voltage.

[0047] Specifically, the gate node G is written with data voltage Vdata through the turned-on data writing transistor M2, and the potential change is ΔVG=Vdata-Vini; Based on the principle of charge conservation in capacitors, the potential of the source node S jumps synchronously with the potential of point G, satisfying the coupling relationship: ΔVS*(Cst1+Cst2)=ΔVG*Cst2. The final potential of point S is derived as: Vs=(Vdata-Vini)*Cst2 / (Cst1+Cst2)+Vini-Vth; the voltage across the compensation capacitor Cst2 (i.e., the gate-source voltage Vgs of the driving transistor M1) is updated to: Vgs=(Vdata-Vini)*Cst1 / (Cst1+Cst2)+Vth; this process couples the data voltage Vdata with the sampled threshold voltage Vth, preparing for the cancellation of Vth drift during the light emission stage.

[0048] In stage four: the scanning signal SnW is set low, the light emission control signal EM is set high, the driving transistor M1 and the light emission control transistor M4 are turned on, and the light emission device D1 is lit. The lighting current is controlled by Vgs-Vth of the driving transistor M1, which is a function of (Vdata-Vini)*Cst1 / (Cst1+Cst2). This function does not include VDD, VSS, or Vth. Therefore, this pixel circuit has a good compensation effect for VDD, VSS, IR drop, and Vth.

[0049] Preferably, the orthogonal projections of the driving transistor, data writing transistor, reference voltage writing transistor, reset transistor, light-emitting control transistor, storage capacitor, and at least part of the compensation capacitor onto the substrate 10 are all located within the orthogonal projection of the second light-shielding portion 50 onto the substrate 10. Specifically, the second light-shielding portion 50 simultaneously shields the driving transistor, data writing transistor, reference voltage writing transistor, reset transistor, light-emitting control transistor, storage capacitor, and compensation capacitor.

[0050] In other embodiments, the pixel circuit is not limited to a 5T2C pixel circuit, but can also be a 6T2C pixel circuit, a 7T2C pixel circuit, etc.

[0051] In one embodiment, the first light-shielding portion 40 is distributed on one or more conductor layers 30. The first light-shielding portion 40 can be formed simultaneously with the semiconductor layer 30, eliminating the need for additional film layers and avoiding additional fabrication steps, thus reducing fabrication difficulty. In other embodiments, the first light-shielding portion 40 can also be implemented independently of the semiconductor layer 30 by adding a new metal layer.

[0052] In one embodiment, the second light-shielding portion 50 is distributed on one or more conductor layers 30. The second light-shielding portion 50 can be formed simultaneously with the semiconductor layer 30, eliminating the need for additional film layers and avoiding additional fabrication steps, thus reducing fabrication difficulty. In other embodiments, the second light-shielding portion 50 can also be implemented independently of the semiconductor layer 30 by adding a new metal layer.

[0053] Reference Figure 1 As shown, in one embodiment, the multilayer conductor layer 30 includes a first conductor layer 31, a second conductor layer 32, a third conductor layer 33, a fourth conductor layer 34, and a fifth conductor layer 35. The first conductor layer 31 is located between the substrate 10 and the active layer 20, the second conductor layer 32 is located between the first conductor layer 31 and the second conductor layer 32, the third conductor layer 33 is located on the side of the active layer 20 away from the substrate 10, and the fourth conductor layer 34 is located on the side of the third conductor layer 33 away from the substrate 10.

[0054] Optionally, the lower plate of one of the storage capacitor Cst1 and the compensation capacitor Cst2 is located in the first conductor layer 31, and the upper plate is located in the second conductor layer 32; the lower plate of the other of the storage capacitor Cst1 and the compensation capacitor Cst2 is located in the second conductor layer 32, and the upper plate is located in the third conductor layer 33; the gate 1 of the transistor (driving transistor M1, data writing transistor M2, reset transistor M3, light-emitting control transistor M4, reference voltage writing transistor M5) is located in the third conductor layer 33, and the source 2 and drain 3 of the transistor (driving transistor M1, data writing transistor M2, reset transistor M3, light-emitting control transistor M4, reference voltage writing transistor M5) are located in the fourth conductor layer 34.

[0055] Optionally, the first light-shielding portion 40 is located on the first conductor layer 31, and the second light-shielding portion 50 is located on the fifth conductor layer 35. By using the first conductor layer 31 and the fifth conductor layer 35 to shield the channel region 21 from the bottom and top of the array substrate 100, respectively, the stability of the oxide transistor is improved, which is beneficial to improving the uniformity of the display and thus improving the display effect.

[0056] Specifically, a first light-shielding portion 40 is formed simultaneously with the formation of the first conductor layer 31, and a second light-shielding portion 50 is formed simultaneously with the formation of the fifth conductor layer 35.

[0057] Reference Figure 2 As shown, in one embodiment, the plurality of transistors include a light-emitting control transistor M4, and the array substrate 100 also includes a light-emitting control signal line EM. The light-emitting control transistor M4 is connected to the light-emitting control signal line EM, which is located in a multilayer conductor layer 30. The light-emitting control signal lines EM in the multilayer conductor layer 30 are connected in parallel. In this way, the load on the light-emitting control signal line EM can be reduced, thereby improving the uniformity of the display panel.

[0058] In one embodiment, the light-emitting control signal lines EM in the plurality of conductor layers 30 extend in the same direction, and their orthogonal projections on the substrate 10 overlap. This ensures consistency among the different light-emitting control signal lines EM, which helps to further improve the uniformity of the display panel.

[0059] In one embodiment, the light emission control signal line EM is located at least in three conductor layers 30 to minimize the load on the light emission control signal line EM and improve the uniformity of the display panel display.

[0060] Optionally, the multilayer conductor layer 30 includes a first conductor layer 31, a second conductor layer 32, a third conductor layer 33, a fourth conductor layer 34, and a fifth conductor layer 35. The first conductor layer 31 is located between the substrate 10 and the active layer 20, the second conductor layer 32 is located between the first conductor layer 31 and the second conductor layer 32, the third conductor layer 33 is located on the side of the active layer 20 away from the substrate 10, and the fourth conductor layer 34 is located on the side of the third conductor layer 33 away from the substrate 10. The light-emitting control signal line EM is partially located in the first conductor layer 31, partially in the third conductor layer 33, and partially in the fourth conductor layer 34. In other embodiments, the light-emitting control signal line EM may also be distributed in other multilayer conductor layers 30, and there is no specific limitation.

[0061] Optionally, the scan signal line SnW, the reference scan signal line SnR, and the reference voltage line Vref are located on the fourth conductor layer 34, and the high-level power supply signal line VDD, the data voltage signal line Data, and the initialization voltage signal line Vini are located on the fifth conductor layer 35.

[0062] Optionally, an insulating layer is also provided between adjacent conductor layers 30.

[0063] Reference Figure 4-12 The diagram shown is a layout of the array substrate 100, combined with... Figure 1 In one specific embodiment, the fabrication process of the array substrate 100 is as follows: (1) First, a first conductor layer 31 is formed on the substrate, referring to... Figure 4 As shown. The first conductor layer 31 partially serves as the first light-shielding part 40 and partially serves as part of the light-emitting control signal line EM.

[0064] Optionally, the first light-shielding part 40 includes a first sub-part 401 and a second sub-part 402. The first sub-part 401 is connected to the light-emitting control signal line EM, and the second sub-part 402 is connected to the high-level power supply signal line VDD. Therefore, in order to avoid mutual interference between different signals, the first sub-part 401 and the second sub-part 402 are arranged alternately.

[0065] Optionally, the first sub-part 401 extends along the row direction, and the second sub-part 402 extends along the column direction. The first sub-parts 401 located in the same row are connected to each other, and the second sub-parts 402 located in the same column are connected to each other.

[0066] Optionally, the orthographic projection of the channel region 21 of the light-emitting control transistor M4 onto the substrate 10 is located within the orthographic projection of the first sub-section 401 onto the substrate 10, and the orthographic projections of the channel regions 21 of the driving transistor M1, the data writing transistor M2, the reset transistor M3, and the reference voltage writing transistor M5 onto the substrate 10 are located within the orthographic projection of the second sub-section 402 onto the substrate 10. Therefore, the area of ​​the orthographic projection of the second sub-section 402 onto the substrate 10 is larger than the area of ​​the orthographic projection of the first sub-section 401 onto the substrate 10.

[0067] Optionally, the second sub-part 402 serves as the lower electrode of the storage capacitor Cst1. Therefore, the area of ​​the second sub-part 402 is relatively large to meet the requirement of forming a larger storage capacitor Cst1.

[0068] (2) A second conductor layer 32 is formed on the side of the first conductor layer 31 away from the substrate, as shown in the figure. Figure 5 As shown. The second conductor layer 32 comprises two parts: one part serves as the first upper plate 321 of the storage capacitor Cst1, and the other part serves as the lower plate 322 of the compensation capacitor Cst2.

[0069] (3) An active layer 20 is formed on the side of the second conductor layer 32 away from the substrate, as shown in the figure. Figure 6 As shown. The active layer 20 includes five spaced-apart sections, which are used to form the channel region 21 of the driving transistor M1, the data writing transistor M2, the reset transistor M3, the light-emitting control transistor M4, and the reference voltage writing transistor M5, respectively.

[0070] (4) A third conductor layer 33 is formed on the side of the active layer 20 away from the substrate, as shown in the figure. Figure 7 As shown. The third conductor layer 33 serves as the second upper plate 331 of the compensation capacitor Cst2. The third conductor layer 33 also serves as the gate 1 of the transistors (driving transistor M1, data writing transistor M2, reset transistor M3, light-emitting control transistor M4, and reference voltage writing transistor M5).

[0071] The third conductor layer 33 serves as the light emission control signal line EM and the third conductor layer 33 serves as the reset signal line Reset. The light emission control signal line EM extends along the row direction, and the reset signal line Reset extends along the row direction. The reset signal line Reset is connected to the reset transistor M3. The orthographic projection of the reset signal line Reset on the substrate overlaps with the orthographic projection of the reset transistor M3 on the substrate.

[0072] (5) A first interlayer dielectric layer 61 is formed on the side of the third conductor layer 33 away from the substrate, as shown in the figure. Figure 8 As shown. The first interlayer dielectric layer 61 conducts through a via to the second conductor layer 32 and the fourth conductor layer 34.

[0073] (6) A second interlayer dielectric layer 62 is formed on the side of the first interlayer dielectric layer 61 away from the substrate, as shown in the figure. Figure 9 As shown. The second interlayer dielectric layer 62 connects the active layer 20 and the fourth conductor layer 34, as well as the third conductor layer 33 and the fourth conductor layer 34, through vias.

[0074] (7) A fourth conductor layer 34 is formed on the side of the second interlayer dielectric layer 62 away from the substrate, as shown in the figure. Figure 10 As shown. The fourth conductor layer 34 serves as the source 2 and drain 3 of the transistors (driving transistor M1, data writing transistor M2, reset transistor M3, light-emitting control transistor M4, and reference voltage writing transistor M5). The fourth conductor layer 34 also serves as the scan signal line SnW, the reference scan signal line SnR, the reference voltage line Vref, and the light-emitting control signal line EM.

[0075] Among them, the scan signal line SnW, the reference scan signal line SnR, the reference voltage line Vref, and the light emission control signal line EM all extend along the row direction.

[0076] Specifically, the scan signal line SnW is connected to the data writing transistor M2, and the orthographic projection of the scan signal line SnW on the substrate overlaps with the orthographic projection of the data writing transistor M2 on the substrate; the reference scan signal line SnR is connected to the reference voltage writing transistor M5, and the orthographic projection of the reference scan signal line SnR on the substrate overlaps with the orthographic projection of the reference voltage writing transistor M5 on the substrate; the light emission control signal line EM is connected to the light emission control transistor M4, and the orthographic projection of the light emission control signal line EM on the substrate overlaps with the orthographic projection of the light emission control transistor M4 on the substrate.

[0077] (8) A planarization layer 71 is formed on the side of the fourth conductor layer 34 away from the substrate; refer to Figure 11 As shown.

[0078] (9) A fifth conductor layer 35 is formed on the side of the planarization layer 71 away from the substrate; refer to Figure 12As shown. The fifth conductor layer 35 serves as the second light-shielding part 50, the high-level power signal line VDD, the data voltage signal line Data, and the initialization voltage signal line Vini.

[0079] Optionally, the high-level power supply signal line VDD, the data voltage signal line Data, and the initialization voltage signal line Vini extend along the column direction; the high-level power supply signal line VDD is connected to the light-emitting control transistor M4, the initialization voltage signal line Vini is connected to the reset transistor M3, and the data voltage signal line Data is connected to the data writing transistor M2.

[0080] Optionally, the high-level power signal line VDD is multiplexed as the second light-shielding part 50.

[0081] Based on the same inventive concept, another embodiment of this application discloses a display panel, which includes the array substrate 100 of any of the above-mentioned embodiments. The display panel may further include a light-emitting device (OLED), and the pixel circuit in the array substrate 100 is connected to the light-emitting device OLED to drive the light-emitting device OLED to emit light. The display panel includes the array substrate 100 provided in any embodiment of the present invention, and therefore has the same beneficial effects as the array substrate provided in any embodiment of the present application, which will not be described again here. The display panel can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, etc.

[0082] Based on the same inventive concept, another embodiment of this application discloses a display device that includes the aforementioned display panel. This display device may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, in-vehicle displays, wearable devices, etc. Because this display device includes the display panel described in this application, the reliability of this electronic device is higher.

[0083] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the technical concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; An active layer and multiple conductor layers are stacked on one side of the substrate. The active layer and the multiple conductor layers form at least one pixel circuit. The pixel circuit includes multiple transistors, and each transistor includes a channel region located in the active layer. A first light-shielding portion is disposed between the substrate and the active layer; The second light-shielding portion is disposed on the side of the active layer away from the substrate; Wherein, the orthographic projection of the channel region on the substrate at least partially overlaps with the orthographic projection of the first light-shielding portion on the substrate, and the orthographic projection of the channel region on the substrate at least partially overlaps with the orthographic projection of the second light-shielding portion on the substrate.

2. The array substrate according to claim 1, characterized in that, The orthographic projections of the plurality of channel regions on the substrate are located within the orthographic projections of the first light-shielding portion on the substrate, and the orthographic projections of the plurality of channel regions on the substrate are located within the orthographic projections of the second light-shielding portion on the substrate.

3. The array substrate according to claim 1, characterized in that, The plurality of transistors include a driving transistor, a data writing transistor, a reference voltage writing transistor, a reset transistor, and a light-emitting control transistor; the pixel circuit also includes a storage capacitor and a compensation capacitor. Preferably, the orthogonal projections of the driving transistor, the data writing transistor, the reference voltage writing transistor, the reset transistor, the light-emitting control transistor, the storage capacitor, and at least a portion of the compensation capacitor onto the substrate are all located within the orthogonal projection of the second light-shielding portion onto the substrate.

4. The array substrate according to claim 1, characterized in that, The first light-shielding portion is distributed in one or more of the conductor layers; And / or, the second light-shielding portion is distributed on one or more of the conductor layers.

5. The array substrate according to claim 1, characterized in that, The multilayer conductor layer includes a first conductor layer, a second conductor layer, a third conductor layer, a fourth conductor layer, and a fifth conductor layer. The first conductor layer is located between the substrate and the active layer. The second conductor layer is located between the first conductor layer and the second conductor layer. The third conductor layer is located on the side of the active layer away from the substrate. The fourth conductor layer is located on the side of the third conductor layer away from the substrate. The first light-shielding part is located in the first conductor layer, and the second light-shielding part is located in the fifth conductor layer.

6. The array substrate according to claim 1, characterized in that, The plurality of transistors include light-emitting control transistors, and the array substrate further includes light-emitting control signal lines. The light-emitting control transistors are connected to the light-emitting control signal lines, which are located within multiple conductor layers. The light-emitting control signal lines in the multiple conductor layers are connected in parallel.

7. The array substrate according to claim 6, characterized in that, The light-emitting control signal lines in the plurality of conductor layers extend in the same direction and their orthogonal projections on the substrate overlap each other.

8. The array substrate according to claim 6, characterized in that, The light emission control signal line is located in at least three of the conductor layers; Preferably, the multilayer conductor layer includes a first conductor layer, a second conductor layer, a third conductor layer, a fourth conductor layer, and a fifth conductor layer. The first conductor layer is located between the substrate and the active layer, the second conductor layer is located between the first conductor layer and the second conductor layer, the third conductor layer is located on the side of the active layer away from the substrate, and the fourth conductor layer is located on the side of the third conductor layer away from the substrate. The light-emitting control signal line is partially located in the first conductor layer, partially in the third conductor layer, and partially in the fourth conductor layer.

9. A display panel, characterized in that, include: The array substrate as described in any one of claims 1-8.

10. A display device, characterized in that, include: The display panel as described in claim 9.

Images