Display panel and electronic device

Abstract

The application discloses a display panel and an electronic device. The display panel comprises an array substrate, a display array arranged on the array substrate, and a pixel circuit. The pixel circuit comprises a driving transistor, a gate of which is connected with a first node, a first electrode of which is connected with a second node, and a second electrode of which is connected with a third node; a threshold compensation transistor, a gate of which is connected with a first signal line for inputting a first scanning signal, a first electrode of which is connected with the first node, and a second electrode of which is connected with the third node; and a data writing transistor, a gate of which is connected with a second signal line for inputting a second scanning signal, a first electrode of which is used for inputting a data signal, and a second electrode of which is connected with the first node. One of the threshold compensation transistor and the data writing transistor is an NMOS, and the other is a PMOS. A photosensitive device arrangement area is arranged in a first sub-display area. In the first sub-display area, a plurality of rows of light emitting elements are arranged in a path passing through the photosensitive device arrangement area, and the first scanning signal input by the first signal line has a delay period for closing the threshold compensation transistor.

Description

Technical Field

[0001] This application relates to the field of display device technology, and more particularly to a display panel and electronic device. Background Technology

[0002] The main device for enabling display functions in electronic devices is the display panel. Compared to liquid crystal displays (LCDs) that require backlighting, OLED (Organic Light Emitting Diode) display panels utilize self-emissive OLEDs. OLED display panels offer numerous advantages, including thinness, high brightness, low power consumption, fast response time, high resolution, and suitability for flexible display devices, making them one of the mainstream display technologies today.

[0003] In existing OLED display panels, a photosensitive area needs to be set within the display area to accommodate under-display photosensitive devices (such as under-display front cameras). This photosensitive area can cause uneven display in OLED panels. Summary of the Invention

[0004] In view of the above problems, this application provides a display panel and electronic device to solve the problem of uneven display on the display panel. The specific solution is as follows:

[0005] The first aspect of this application provides a display panel, wherein the display area of ​​the display panel has a photosensitive device setting area, and the display panel includes:

[0006] An array substrate, which includes pixel circuitry;

[0007] A display array disposed on an array substrate, the display array comprising multiple light-emitting elements arranged in an array, the light-emitting elements being connected to pixel circuits;

[0008] The pixel circuit includes:

[0009] A driving transistor, the gate of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the second node, and the second terminal of the driving transistor is connected to the third node;

[0010] A threshold compensation transistor, the gate of which is connected to a first signal line for receiving a first scan signal, the first terminal of which is connected to a first node, and the second terminal of which is connected to a third node;

[0011] A data writing transistor has its gate connected to a second signal line for receiving a second scan signal, its first terminal for receiving a data signal, and its second terminal connected to a first node; both the first and second signal lines extend along the row direction of the light-emitting element.

[0012] Among them, one of the threshold compensation transistor and the data write transistor is an NMOS, and the other is a PMOS;

[0013] The display area includes a first sub-display area and a second sub-display area arranged along the column direction. The first sub-display area is provided with a photosensitive device setting area. In the first sub-display area, there are multiple rows of light-emitting elements arranged with a path passing through the photosensitive device setting area. In the first sub-display area, the first scan signal input by the first signal line has a delay period of the delay-off threshold compensation transistor.

[0014] As described above, in the display panel provided by this application, one of the threshold compensation transistor and the data writing transistor is an NMOS transistor that is turned on at a high level, and the other is a PMOS transistor that is turned on at a low level. Therefore, the turn-on voltages of the first scan signal and the second scan signal are out of phase, and the first signal line and the second signal line can form anti-coupling to the first node. Based on this, in the first sub-display area, the first signal line inputs a first scan signal with a delay period, which increases the delay time of the first scan signal and increases the coupling between the first signal line and the first node. This can significantly lower the potential of the first node. Through the aforementioned anti-coupling relationship, the coupling of the second signal line to the first node can be better counteracted, thereby solving the problem of increased pixel circuit coupling caused by the photosensitive device setting area, and thus solving the problem of uneven display caused by this.

[0015] A second aspect of this application provides an electronic device including the aforementioned display panel.

[0016] As can be seen from the above description, the electronic device provided by this application adopts the above-mentioned display panel that can reduce the pixel circuit coupling problem, solves the problem of uneven display caused by increased coupling, and improves the display quality. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

[0019] Figure 1 A top view of a display panel;

[0020] Figure 2 for Figure 1 A schematic diagram of the pixel circuit in the display panel shown;

[0021] Figure 3 for Figure 1 The diagram shows the layout of the scan lines in the display panel.

[0022] Figure 4 for Figure 1 The control timing diagram of the pixel circuit in the display panel is shown.

[0023] Figure 5 for Figure 1 The image shown is an actual waveform diagram of the second scan signal in the pixel circuit of the display panel.

[0024] Figure 6 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0025] Figure 7 This application provides a schematic diagram of the structure of a pixel circuit in a display panel.

[0026] Figure 8 for Figure 7 The circuit layout of the pixel circuit shown;

[0027] Figure 9 A control timing diagram of a pixel circuit located in a first sub-display area is provided for an embodiment of this application;

[0028] Figure 10 A control timing diagram of a pixel circuit located in a second sub-display area is provided for an embodiment of this application;

[0029] Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0030] Figure 12 for Figure 11 The control timing diagram of the first sub-display area in the display panel is shown below;

[0031] Figure 13 for Figure 12 The control timing diagram of the second sub-display area in the display panel is shown below;

[0032] Figure 14 A circuit diagram of a shift register in a first driving circuit provided in an embodiment of this application;

[0033] Figure 15This is a schematic diagram of the structure of another display panel provided in an embodiment of this application;

[0034] Figure 16 This is a schematic diagram of a layout of the first signal line and the first node in the pixel circuit located in the first sub-display area;

[0035] Figure 17 This is a schematic diagram of a layout of the first signal line and the first node in the pixel circuit located in the second sub-display area;

[0036] Figure 18 This is a schematic diagram of another layout of the first signal line and the first node in the pixel circuit located in the first sub-display area;

[0037] Figure 19 This is a schematic diagram of another layout of the first signal line and the first node in the pixel circuit located in the second sub-display area;

[0038] Figure 20 This is a schematic diagram of a layout of the second signal line and the first node in the pixel circuit located in the first sub-display area;

[0039] Figure 21 This is a schematic diagram of a layout of the second signal line and the first node in the pixel circuit located in the second sub-display area;

[0040] Figure 22 This is a schematic diagram of another layout of the second signal line and the first node in the pixel circuit located in the first sub-display area;

[0041] Figure 23 This is a schematic diagram of another layout of the second signal line and the first node in the pixel circuit located in the second sub-display area;

[0042] Figure 24 This is a schematic diagram of a layout of the first signal line, the second signal line, and the first node in the first sub-display area.

[0043] Figure 25 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0044] The annotations in the attached figures are explained as follows:

[0045] Display panel 100, light-emitting element 101, photosensitive device setting area 102, pixel circuit 103, array substrate 104, display array 105, first driving circuit 106, driving chip 107, data line 108, substrate 109, pixel structure 110, anode 111, light-emitting layer 112, cathode 113, pixel definition layer 114, polysilicon layer 115, conductive connection part 116, non-display area BB, display area AA, first sub-display area AA1, second sub-display area AA2, row direction X, column direction Y, thickness direction Z, setting direction F, storage capacitor Cst, first light-emitting control Transistor Q1, data writing transistor Q2, drive transistor Q3, threshold compensation transistor Q4, first reset transistor Q5, second light-emitting control transistor Q6, second reset transistor Q7, bias adjustment transistor Q8, light-emitting control signal EM, first signal line L1, second signal line L2, drive signal line SL, first node N1, second node N2, third node N3, fourth node N4, first coupling capacitor C1, second coupling capacitor C2, first metal layer M1, capacitor metal layer MC, second metal layer M2, third metal layer M3, first power supply voltage VDD, second power supply voltage VDD. Voltage VSS, Data signal Data, Bias adjustment signal DVH, First scan signal S2N, Second scan signal SP, Third scan signal S1N, Fourth scan signal SPX, First reset voltage VREF1, Second reset voltage VREF2, Delay period T0, Shift register VSR, Start signal STV, First transistor T1, Second transistor T2, Third transistor T3, Fourth transistor T4, Fifth transistor T5, Sixth transistor T6, Seventh transistor T7, Eighth transistor T8, Ninth transistor T9, Tenth transistor T10, Eleventh transistor T11, ... Twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, sixteenth transistor T16, first capacitor C01, second capacitor C02, third capacitor C03, first terminal D1, second terminal D2, third terminal D3, fourth terminal D4, fifth terminal D5, sixth terminal D6, seventh terminal D7, eighth terminal D8, ninth terminal D9, first clock signal XCK, second clock signal CK, first set voltage V1, second set voltage V2, third set voltage RST, high level VGH, low level VGL, input signal IN. Detailed Implementation

[0046] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0047] refer to Figures 1-5 , Figure 1 This is a top view of a display panel. Figure 2 for Figure 1 The diagram shows a schematic of the pixel circuitry in the display panel. Figure 3 for Figure 1 The diagram shows the layout of the scan lines in the display panel. Figure 4 for Figure 1 The diagram shows the control timing of the pixel circuit in the display panel. Figure 5 for Figure 1 The diagram shows the actual waveform of the second scan signal in the pixel circuit of the display panel. The display panel 100 includes a display area AA, which includes multiple pixel structures 110. Figure 2 As shown, the pixel structure includes a light-emitting element 101 and a pixel circuit 103 connected to the light-emitting element.

[0048] The display area AA includes multiple arrayed light-emitting elements 101, which can be OLEDs. Each light-emitting element 101 includes an anode, a light-emitting layer, and a cathode stacked sequentially. The specific film structure of the light-emitting element 101 can be found in subsequent sections. Figure 6 The relevant descriptions in the illustrated embodiments.

[0049] The display area AA includes a first sub-display area AA1 and a second sub-display area AA2 arranged along the column direction Y. The first sub-display area AA1 contains a photosensitive device setting area 102.

[0050] like Figure 1 As shown, a through hole or blind hole needs to be provided in the first sub-display area AA1 (such as the top area of ​​display area AA) to form a photosensitive device setting area 102 for light collection by the photosensitive device. The drive signal line SL needs to be as follows: Figure 3 As shown, an arc is formed to bypass the photosensitive device setting area 102, which causes the resistance / capacitance load (RC_Loading) of the drive signal line SL in the first sub-display area AA1 to be greater than the resistance / capacitance load of the drive signal line SL in the second sub-display area AA2.

[0051] like Figure 2As shown, the display panel 100 includes a pixel circuit connected to the light-emitting element 101. The pixel circuit includes a data writing transistor Q2, a driving transistor Q3, and a threshold compensation transistor Q4. The gate, first electrode, and second electrode of the driving transistor Q3 are sequentially connected to a first node N1, a second node N2, and a third node N3. A storage capacitor Cst is connected between the first node N1 and the second node N2. The first node N1 is used to input a first power supply voltage VDD. The third node N3 is used to connect to the anode of the light-emitting element 101, and the cathode of the light-emitting element 101 is connected to a second power supply voltage VSS. The first electrode of the threshold compensation transistor Q4 is connected to the first node N1, the second electrode of the threshold compensation transistor Q4 is connected to the third node N3, and the gate of the threshold compensation transistor Q4 is connected to a first signal line for transmitting a first scan signal S2N. The first electrode of the data writing transistor Q2 is connected to a data line for transmitting a data signal Data, the second electrode of the data writing transistor Q2 is connected to the second node N2, and the gate of the data writing transistor Q2 is connected to a second signal line for transmitting a second scan signal SP.

[0052] In this embodiment, the data writing transistor Q2 is a PMOS and the threshold compensation transistor Q4 is an NMOS as an example. The PMOS is turned on when the gate input signal is low and turned off when the gate input signal is high. The NMOS is turned on when the gate input signal is high and turned off when the gate input signal is low. Therefore, the turn-on voltages of the gate input signals of the PMOS and NMOS are out of phase.

[0053] exist Figure 2 In the pixel circuit shown, by setting the second scan signal SP to a low level and setting the first scan signal S2N to a high level, the data writing transistor Q2 and the threshold compensation transistor Q4 are turned on, and the data signal Data is written to the first node N1 to control the light-emitting element 101 to emit light for display.

[0054] One light emission control cycle of pixel circuit 103 includes an initialization phase, a data writing phase, and a light emission phase.

[0055] During the initialization phase, the lines controlling the first power supply voltage VDD and the second node N2, as well as the lines controlling the third node N3 and the anode of the light-emitting element 101, are all turned off, and the voltage of the first node N1 is reset. Optionally, as described below... Figure 7 The method can be described as follows: the first light-emitting control transistor Q1 and the second light-emitting control transistor Q6 can be turned off by controlling the light-emitting control signal EM to achieve the turn-off of the above-mentioned circuit; by controlling the first reset transistor Q5 to turn on, the first reset voltage VREF1 input to the first reset transistor Q5 is transmitted to the first node N1 to reset the voltage of the first node N1.

[0056] In the data writing phase following the initialization phase, the lines between the first power supply voltage VDD and the second node N2, and between the third node N3 and the anode of the light-emitting element 101, are kept off. The data writing transistor Q2 and the threshold compensation transistor Q4 are both turned on. The storage capacitor Cst maintains the voltage at the first node N1 at the initial reset voltage VREF1 input, thereby controlling the driving transistor Q3 to turn on. The gate voltage of the driving transistor Q3 is pulled high until it turns off. When the driving transistor Q3 turns off, the gate voltage is Data + Vth, allowing the data signal Data to be written to the first node N1. Here, Vth is the threshold voltage of the driving transistor Q3.

[0057] During the light-emitting stage, the control data writing transistor Q2 and the threshold compensation transistor Q4 are both turned off, and the lines between the first power supply voltage VDD and the second node N2, as well as between the third node N3 and the anode of the light-emitting element 101, are both turned on. The voltage of the second node N2 is a constant first power supply voltage VDD, which is greater than the voltage of the first node N1. This causes the driving transistor Q3 to turn on, allowing the driving current to be transmitted to the light-emitting element 101, causing it to emit light. The greater the driving current transmitted to the light-emitting element 101, the greater its brightness.

[0058] The driving current through the driving transistor Q3 can be expressed as: I = K(VDD - Vdata). Based on this calculation, it can be seen that the larger the data signal Data, the smaller the driving current I, and the dimmer the brightness of the light-emitting element 101; conversely, the smaller the data signal Data, the larger the driving current I, and the brighter the light-emitting element 101. Different brightness levels of the light-emitting element 101 require different data signals Data.

[0059] like Figure 3 As shown, the display panel requires a driving circuit to provide scanning signals to the pixel circuit. The driving circuit provides scanning signals to the pixel circuit through a driving signal line SL. The driving signal line SL extends along the row direction X. The driving signal line SL includes a first signal line and a second signal line.

[0060] Ideally, such as Figure 4 As shown, when the pixel circuit is driven based on the first scan signal S2N, the second scan signal SP, and the data signal Data, the first scan signal S2N and the second scan signal SP are square wave signals.

[0061] In reality, such as Figure 2As shown, there is a coupling capacitor (defined as the second coupling capacitor C2) between the second signal line and the first node N1. When the second scan signal SP is off, during the switching process of the potential of the second scan signal SP from low level to high level, the potential of the first node N1 will be coupled high through the second coupling capacitor C2, as shown. Figure 1 As shown, in the first sub-display area AA1, because the second signal line has an arc that bypasses the photosensitive device setting area 102, the second signal line in the first sub-display area AA1 has a larger resistance / capacitance load than the second signal line in the second sub-display area AA2.

[0062] like Figure 5 As shown, the second scan signal SP located in the first sub-display area AA1 is designated as SP1, and the second scan signal SP located in the second sub-display area AA2 is designated as SP2. In the first sub-display area AA1, due to its larger resistive / capacitive load, SP1 has a longer delay time than SP2 at the rising edge of the second scan signal SP. Let the delay time of SP1 be t1 and the delay time of SP2 be t2, then t1 > t2. The coupling time of the first node N1 in the first sub-display area AA1 is longer than that of the first node N1 in the second sub-display area AA2. This longer coupling time leads to a larger coupling amount. Therefore, for a pixel circuit using PMOS as the driving transistor Q3, the potential of the first node N1 in the first sub-display area AA1 will be greater than that of the first node N1 in the second sub-display area AA2, resulting in a dimmer brightness in the first sub-display area AA1 compared to the second sub-display area AA2, causing uneven display.

[0063] Based on the above description, it can be seen that in the first sub-display area AA1, the potential of the first node N1 is pulled up to a greater extent by the coupling of the second signal line, which will cause the brightness of the first sub-display area AA1 to be darker, thus causing uneven display on the display panel.

[0064] like Figure 2 As shown, the inventors discovered that a coupling capacitance (defined as the first coupling capacitance C1) also exists between the first signal line and the first node N1. Furthermore, since the first signal line and the second signal line are connected to the gates of the PMOS and NMOS respectively, the turn-on voltages of the scan signals transmitted in the first and second signal lines are in opposite phase. Therefore, the first and second signal lines can form an anti-coupling to the first node N1, and the coupling of the first signal line to the first node N1 can counteract the coupling of the second signal line to the first node N1. However, in the current pixel circuit layout, the coupling amount of the first signal line to the first node N1 is much smaller than the coupling amount of the second signal line to the first node N1.

[0065] The inventors discovered that within the first sub-display area AA1, by increasing the delay time of the falling edge of the first scan signal S2N, the threshold compensation transistor can be turned off in a delayed manner. This increases the coupling of the first signal line to the first node N1, allowing the first coupling capacitor C1 to pull the potential of the first node N1 down to a greater extent. This better compensates for the coupling of the second signal line to the first node N1, thereby improving the uniformity of display brightness in different sub-display areas and solving the problem of uneven display on the display panel.

[0066] In view of this, embodiments of this application provide a display panel, wherein the display area of ​​the display panel has a photosensitive device setting area, and the display panel includes:

[0067] An array substrate, which includes pixel circuitry;

[0068] A display array disposed on an array substrate, the display array comprising multiple light-emitting elements arranged in an array, the light-emitting elements being connected to pixel circuits;

[0069] The pixel circuit includes:

[0070] A driving transistor, the gate of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the second node, and the second terminal of the driving transistor is connected to the third node;

[0071] A threshold compensation transistor, the gate of which is connected to a first signal line for receiving a first scan signal, the first terminal of which is connected to a first node, and the second terminal of which is connected to a third node;

[0072] A data writing transistor has its gate connected to a second signal line for receiving a second scan signal, its first terminal for receiving a data signal, and its second terminal connected to a first node; both the first and second signal lines extend along the row direction of the light-emitting element.

[0073] Among them, one of the threshold compensation transistor and the data write transistor is an NMOS, and the other is a PMOS;

[0074] The display area includes a first sub-display area and a second sub-display area arranged along the column direction. The first sub-display area is provided with a photosensitive device setting area. In the first sub-display area, there are multiple rows of light-emitting elements arranged with a path passing through the photosensitive device setting area. In the first sub-display area, the first scan signal input by the first signal line has a delay period of the delay-off threshold compensation transistor.

[0075] In the display panel provided in this application embodiment, within the first sub-display area, a first scan signal with a delay period is input to the first signal line. This increases the delay time of the first scan signal and the coupling between the first signal line and the first node, which can significantly lower the potential of the first node and reduce the difference in coupling between the first signal line and the second signal line to the first node. Furthermore, based on the reverse coupling relationship between the first signal line and the second signal line to the first node, the coupling between the first signal line and the first node can better counteract the coupling between the second signal line and the first node. This solves the problem of increased pixel circuit coupling caused by the photosensitive device setting area, and thus solves the problem of uneven display caused by this.

[0076] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0077] This application embodiment provides a display panel, and the top view of the display panel 100 can be as follows: Figure 1 As shown, the display area AA has a photosensitive device setting area 102. The display panel 100 is used in electronic devices, and the photosensitive device setting area 102 is used for under-display photosensitive devices in the electronic devices. The photosensitive device can be a camera module or other light sensors. One or more photosensitive device setting areas 102 can be provided according to the layout requirements of the photosensitive devices. The plane where the row direction X and column direction Y of the array containing the light-emitting elements 101 intersect is parallel to the plane of the display panel 100.

[0078] refer to Figure 6 , Figure 6 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application, combined with... Figure 1 and Figure 6 As shown, the display panel 100 includes: an array substrate 104, which includes pixel circuits 103; and a display array 105 disposed on the array substrate 104, which includes a plurality of light-emitting elements 101 arranged in an array, the light-emitting elements 101 being connected to the pixel circuits 103. The thickness direction Z of the display panel is perpendicular to the row direction X and the column direction Y. The plane containing the set direction F and the thickness direction Z is defined as... Figure 6 The cross-section shown can be configured such that direction F is parallel to the row direction X, parallel to the column direction Y, or parallel to the plane of the display panel and not perpendicular to either the row direction X or the column direction Y. The structure of pixel circuit 103 can be as follows: Figure 7 As shown.

[0079] In some embodiments, the light-emitting element 101 can be an OLED, including an anode 111, a light-emitting layer 112, and a cathode 113 sequentially disposed along the thickness direction Z. An anode metal layer is disposed on the surface of the array substrate 104, the anode metal layer including a plurality of anodes 111. A pixel definition layer 114 is covered on one side of the surface of the array substrate 104 where the anode metal layer is disposed. The pixel definition layer 114 has pixel openings corresponding one-to-one with the anodes 111, the pixel openings being used to expose the corresponding anodes 111. The light-emitting layer 112 of the light-emitting element 101 is located within the corresponding pixel opening. Each light-emitting element 101 has a common cathode 113.

[0080] like Figure 6 As shown, the array substrate 104 includes a substrate 109 and multiple metal layers located on the substrate 109, with an insulating layer between adjacent metal layers. The multiple metal layers include a first metal layer M1, a capacitor metal layer MC, a second metal layer M2, and a third metal layer M3 sequentially stacked on the substrate 109. The first metal layer M1 is used at least to fabricate the gate of a transistor; the capacitor metal layer MC is used at least to fabricate a substrate for storing a capacitor or a substrate for a capacitor in a driving circuit; the second metal layer M2 is used at least to fabricate the source and drain electrodes of the transistor; and the third metal layer M3 is used at least to fabricate the connection line between the light-emitting element 101 and the transistor in the pixel circuit 103. A polysilicon layer 115 is located between the substrate 109 and the first metal layer M1, and the polysilicon layer 115 is used at least to fabricate the channel layer in the transistor.

[0081] refer to Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of the pixel circuit in a display panel provided in an embodiment of this application. Figure 8 for Figure 7 The diagram shows the circuit layout of the pixel circuit. The pixel circuit 103 includes: a driving transistor Q3, the gate of which is connected to a first node N1, the first terminal of which is connected to a second node N2, and the second terminal of which is connected to a third node N3; a threshold compensation transistor Q4, the gate of which is connected to a first signal line L1 for receiving a first scan signal S2N, the first terminal of which is connected to the first node N1, and the second terminal of which is connected to the third node N3; and a data writing transistor Q2, the gate of which is connected to a second signal line L2 for receiving a second scan signal SP, the first terminal of which is used to receive a data signal Data, and the second terminal of which is connected to the first node N1; both the first signal line L1 and the second signal line L2 extend along the row direction X of the light-emitting element 101.

[0082] In this embodiment, one of the threshold compensation transistor Q4 and the data writing transistor Q2 is an NMOS and the other is a PMOS. In this embodiment, the threshold compensation transistor Q4 is an NMOS and the driving transistor Q3 is a PMOS as an example for illustration.

[0083] like Figure 7 As shown, the pixel circuit 103 further includes: a first light-emitting control transistor Q1, a second light-emitting control transistor Q6, a first reset transistor Q5, and a second reset transistor Q7. The first terminal of the first light-emitting control transistor Q1 is connected to a first power supply voltage VDD, and the second terminal of the first light-emitting control transistor Q1 is connected to a second node N2. The first terminal of the second light-emitting control transistor Q6 is connected to a third node N3, and the second terminal of the second light-emitting control transistor Q6 is connected to a fourth node N4. The gates of both the first light-emitting control transistor Q1 and the second light-emitting control transistor Q6 are connected to a light-emitting control signal EM. The first terminal of the first reset transistor Q5 is connected to a first reset voltage VREF1, the second terminal of the first reset transistor Q5 is connected to the first node N1, and the gate of the first reset transistor Q5 is connected to a third scan signal S1N. The first reset transistor Q5 is used to reset the voltage of the first node N1. The first terminal of the second reset transistor Q7 is connected to a second reset voltage VREF2, the second terminal of the second reset transistor Q7 is connected to the fourth node N4, and the gate of the second reset transistor Q7 is connected to a fourth scan signal SPX. The second reset transistor Q7 is used to reset the voltage of the fourth node N4.

[0084] In this configuration, the fourth node N4 is used to connect the anode of the light-emitting element 101, and the cathode of the light-emitting element 101 is connected to the second power supply voltage VSS. The first power supply voltage VDD is greater than the second power supply voltage VSS.

[0085] Optionally, such as Figure 7 As shown, the pixel circuit 103 also includes a bias adjustment transistor Q8. The first terminal of the bias adjustment transistor Q8 is connected to the second node N2, the second terminal of the bias adjustment transistor Q8 is connected to the bias adjustment signal DVH, and the gate of the bias adjustment transistor Q8 is connected to the fourth scan signal SPX.

[0086] like Figure 8 As shown, the first scan signal S2N, the second scan signal SP, the third scan signal S1N, the fourth scan signal SPX, the light emission control signal EM, and the bias adjustment signal DVH correspond to different signal lines, and these signal lines can all extend along the row direction X.

[0087] It should be noted that the pixel circuit 103 is not limited to the following: Figure 7 and Figure 8The 8T1C (8 transistors and 1 storage capacitor) circuit structure shown can also be a 7T1C circuit structure with no bias adjustment transistor or other pixel circuits. This application does not limit the specific structure of the pixel circuit in its embodiments.

[0088] In the display panel 100, such as Figure 8 As shown, the driving transistor Q3, the first signal line L1 (for transmitting the first scan signal S2N), and the second signal line L2 (for transmitting the second scan signal SP) are arranged sequentially in the column direction Y. The gate of the driving transistor Q3 is connected to the conductive hole corresponding to the first node N1.

[0089] like Figure 7 As shown, the first node N1 needs to be connected to the threshold compensation transistor Q4 and the first reset transistor Q5 respectively. In order to realize the connection between the first node N1 and the threshold compensation transistor Q4 and the first reset transistor Q5, the first node is connected with a conductive connection part, so as to connect to the threshold compensation transistor Q4 and the first reset transistor Q5 respectively based on the highly conductive connection part.

[0090] Optionally, the conductive connection can be fabricated from a polysilicon layer 115 in the array substrate. To meet the requirements of circuit interconnection, the conductive connection can also be fabricated from a metal layer in the array substrate. This embodiment does not limit the location of the conductive connection within the conductive layer. In this embodiment, the conductive connection is located in the polysilicon layer 115 as an example. Figure 8 The conductive connection is not shown.

[0091] like Figure 8 As shown, the first reset transistor Q5, the threshold compensation transistor Q4, and the drive transistor Q3 are arranged sequentially along the column direction. Based on this arrangement, the conductive connection portion connected to the first node N1 needs to pass through the first signal line L1 and the second signal line L2 sequentially. Therefore, the conductive connection portion has insulating cross-regions with the first signal line L1 and the second signal line L2, respectively. A first coupling capacitor C1 is formed between the conductive connection portion and the first signal line L1 in the corresponding insulating cross-region. A second coupling capacitor C2 is formed between the conductive connection portion and the second signal line L2 in the corresponding insulating cross-region.

[0092] As described above, the coupling of the first signal line L1 to the first node N1 in the current display panel is much smaller than that of the second signal line L2 to the first node N1, resulting in a stronger coupling effect of the second coupling capacitor C2 to the first node N1. During the transition of the second scan signal SP from the on period to the off period, there is a delay period caused by the second coupling capacitor C2, which leads to a decrease in the display brightness of the first sub-display area AA1. The first coupling capacitor C1 and the second coupling capacitor C2 form reverse coupling to the first node N1 during the delay period T0 of the first scan signal S2N and the delay period of the second scan signal SP, respectively. In this embodiment, by introducing an additional delay period T0 at the falling edge of the first scan signal S2N, the first coupling capacitor C1 can be increased to enhance the coupling effect of the first signal line L1 to the first node N1, thereby better counteracting the coupling effect of the second signal line L2 to the first node N1.

[0093] As described above, the main factor causing the reduced brightness of the first sub-display area AA1 is that the second signal line L2 within the first sub-display area AA1 has an arc section that bypasses the photosensitive device setting area 102, resulting in a greater resistive / capacitive load of the second signal line L2 in the first sub-display area AA1 than in the second sub-display area AA2. For a given display panel, the design parameters of the photosensitive device setting area 102 and the signal lines are fixed, and the delay time t1 of the second scan signal SP transmitted by the second signal line L2 in the first sub-display area AA1 at the rising edge is also fixed. Related to the aforementioned design parameters, the delay time t1 of the second scan signal SP in the second signal line of the display panel can be confirmed through simulation testing or by testing the actual display panel. Based on the confirmed delay time t1 of the second scan signal SP, a matching delay period T0 is provided for the first scan signal S2N, such that the duration of the delay period T0 of the first scan signal S2N is greater than the duration of the delay period of the second scan signal SP, i.e., T0 is greater than t1. This utilizes the reverse coupling relationship between the first signal line L1 and the second signal line L2 to the first node N1, and the coupling effect of the first signal line L1 to the first node N1 is better reversely canceled by the coupling effect of the second signal line L2 to the first node N1.

[0094] In this embodiment, the display area AA includes a first sub-display area AA1 and a second sub-display area AA2 arranged along the column direction Y. The first sub-display area AA1 is provided with a photosensitive device setting area 102. Both the first sub-display area AA1 and the second sub-display area AA2 include multiple rows of light-emitting elements 101. Each light-emitting element 101 is connected to a corresponding pixel circuit 103. For light-emitting elements 101 within the same sub-display area, the pixel circuit 103 connected to the light-emitting element 101 and the first signal line L1 and the second signal line L2 connected to the pixel circuit 103 can be located within that sub-display area.

[0095] Within the first sub-display area AA1, there are multiple rows of light-emitting elements 101 arranged with paths passing through the photosensitive device setting area 102. Pixel circuits 103 connected to the same row of light-emitting elements 101 are located in the same row, and the same row of pixel circuits 103 are connected to the same first signal line L1 and second signal line L2. For example... Figure 3 As shown, the first signal line L1 and the second signal line L2 serve as driving signal lines SL. Within the first sub-display area AA1, the first signal line L1 and the second signal line L2 need to be provided with an arc that bypasses the photosensitive device setting area 102.

[0096] refer to Figure 9 , Figure 9 This application provides a control timing diagram for a pixel circuit located in a first sub-display area. Within the first sub-display area AA1, the first scan signal S2N input to the first signal line L1 has a delay period T0 for the delay-off threshold compensation transistor Q4. As described above, within the first sub-display area AA1, the increased length of the second signal line L2 results in a larger shutdown delay time t1 for SP1 during the switching process from low to high level, increasing the coupling of the second signal line L2 to the first node N1. In this approach, based on the reverse coupling relationship between the first signal line L1 and the second signal line L2 to the first node N1, by adding an additional delay period T0 to the first scan signal S2N within the first sub-display area AA1, the coupling of the first signal line L1 to the first node N1 can cancel the coupling of the second signal line L2 to the first node N1, thereby improving the uniformity of display brightness in different sub-display areas of the display panel.

[0097] Taking threshold compensation transistor Q4 as an example, if it is an NMOS transistor, then... Figure 9 As shown, the NMOS switches from the on state to the off state after the first scan signal S2N switches from high to low. Because the first scan signal S2N has a delay period T0 of the delay-off threshold compensation transistor Q4, the process of the first scan signal S2N switching from high to low is not a direct vertical jump from high to low.

[0098] In this embodiment, one of the threshold compensation transistor Q4 and the data writing transistor Q2 is a high-level NMOS and the other is a low-level PMOS. Therefore, the turn-on voltages of the first scan signal S2N and the second scan signal SP are out of phase, and the first signal line L1 and the second signal line L2 can form anti-coupling with the first node N1. Based on this, in the first sub-display area AA1, the first signal line L1 inputs the first scan signal S2N with a delay period T0, which increases the delay time of the first scan signal S2N and increases the coupling between the first signal line L1 and the first node N1. This can significantly lower the potential of the first node N1. Through the above-mentioned anti-coupling relationship, the coupling of the second signal line L2 to the first node N1 can be better counteracted, thereby solving the problem of increased coupling in the pixel circuit 103 caused by the photosensitive device setting area 102, and thus solving the problem of uneven display caused by this.

[0099] It should be noted that for PMOS, the gate voltage is low and the gate voltage is high. For NMOS, the gate voltage is high and the gate voltage is low. A delayed-turn-off transistor refers to a transistor that experiences a delay during the transition from an on to an off state. For NMOS, delayed turn-off means that there is a transition voltage between high and low levels during the gate signal's transition from high to low. For PMOS, delayed turn-off means that there is a transition voltage between high and low levels during the gate signal's transition from low to high.

[0100] refer to Figure 10 , Figure 10 This application provides a control timing diagram for a pixel circuit located in a second sub-display area. In this method, within the second sub-display area AA2, since SP2, to which the second signal line L2 is connected, has a small shutdown delay time t1, the coupling to the first node N1 is small, resulting in a small impact on display brightness. Therefore, the first scan signal S2N does not require an additional delay period T0.

[0101] In other ways, with Figure 10 The difference lies in that, in the second sub-display area, the first scan signal S2N input by the first signal line L1 has a delay period of the delay-off threshold compensation transistor Q4; in the first sub-display area AA1, the duration of the delay period T0 of the first scan signal S2N input by the first signal line L1 is Te1; ​​in the second sub-display area AA2, the duration of the delay period of the first scan signal S2N input by the first signal line L1 is Te2; wherein, Te1 > Te2.

[0102] Within the second sub-display area AA2, although there is no problem of increased resistance / capacitance load caused by the arc bypassing the photosensitive device setting area 102, a relatively large second coupling capacitance C2 can be formed due to the overlap between the second signal line L2 and the first node N1 in the thickness direction Z. Figure 5 As shown, there will still be a small delay time t2 at the rising edge of SP2. By setting Te1 > Te2, the coupling effect of the second signal line to the first node N1 can be reversed in the first sub-display area AA1 through Te1, and the coupling effect of the second signal line to the first node N1 can be reversed in the second sub-display area AA2 through Te2. This not only improves the uniformity of display brightness in the first sub-display area AA1 and the second sub-display area AA2, but also provides the two sub-display areas with first scan signals with appropriate delay times, thereby improving display accuracy and reducing the color shift problem caused by the delay of the rising edge of the second scan signal SP.

[0103] refer to Figure 11 and Figure 12 , Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 12 for Figure 11 The diagram shows the control timing of the first sub-display area in the display panel. Based on other embodiments, in this method, the display panel 100 further includes a first driving circuit 106, which is connected to a first signal line L1 to provide a first scan signal S2N to the pixel circuit 103. The first driving circuit 106 is used to output the first scan signal S2N based on a first clock signal XCK. The falling edge of the first clock signal XCK has a delay period T0, thereby ensuring that the output first scan signal S2N has the required delay period T0.

[0104] Optionally, such as Figure 11 As shown, the display panel 100 includes a non-display area BB surrounding the display area AA, and the first driving circuit 106 is located within the non-display area BB on one side of the display area AA. For borderless or narrow-bezel display panels, the first driving circuit 106 can also be placed within the display area AA. The first driving circuit 106 includes multiple cascaded shift registers VSRs, and each first signal line L1 is connected to the corresponding first-level shift register VSR. The first scan signal S2N output by the previous-level shift register serves as the input signal for the next-level shift register VSR. The first-level shift register VSR receives the start signal STV.

[0105] exist Figure 11 and Figure 12 As shown, based on the timing control of the first clock signal XCK input to the first driving circuit 106, a first scan signal S2N with the required delay period T0 can be obtained, and the control timing is simple.

[0106] like Figure 12 As shown, the high level of the first clock signal XCK is a first voltage, and the low level of the first clock signal XCK is a second voltage. The delay period T0 of the first clock signal XCK includes at least one stepped band, and the voltage of the stepped band is between the first voltage and the second voltage. In this method, by adding one or more stepped bands at the falling edge of the first clock signal XCK, the required delay period T0 can be set at its falling edge, thereby forming the required delay period T0 in the first scan signal S2N.

[0107] The required delay period T0 can be formed by controlling the step duration, number of steps, and step voltage magnitude of the step band through the driver chip. In this embodiment, the step potential and step length can be adjusted to suit the brightness non-uniformity in the two sub-display areas.

[0108] refer to Figure 13 , Figure 13 for Figure 12 The diagram shows the control timing of the second sub-display area in the display panel. In this method, within the second sub-display area AA2, since SP2, to which the second signal line L2 is connected, has a small shutdown delay time t1, the coupling to the first node N1 is small, resulting in a small impact on display brightness. Therefore, the first scan signal S2N does not require an additional delay period T0, and the corresponding first clock signal XCK does not require an additional delay period T0.

[0109] refer to Figure 14 , Figure 14 The circuit diagram of a shift register in a first driving circuit provided in this application embodiment includes 16 transistors and 3 capacitors. The 16 transistors are sequentially designated as transistor T1 to transistor T16, wherein transistor T2 is a dual-gate transistor comprising a first sub-transistor T2_1 and a second sub-transistor T2_2. The three capacitors are sequentially designated as capacitor C01 to capacitor C03.

[0110] The first transistor T1 has its first terminal connected to terminal D1, its second terminal connected to terminal D2, and its gate connected to a low level VGL. The second transistor T2 has its first terminal connected to terminal D1, its second terminal connected to a second clock signal CK, and its gate connected to terminal D3. The third transistor T3 has its gate connected to terminal D2, its first terminal connected to terminal D4, and its second terminal connected to a first clock signal XCK. The fourth transistor T4 has its first terminal connected to the input signal IN, its second terminal connected to the second clock signal CK, and its second terminal connected to terminal D3. The fifth transistor T5 has its first terminal connected to a low level VGL, its second terminal connected to terminal D1, and its gate connected to the second clock signal CK. The sixth transistor T6 has its first terminal connected to terminal D5, its second terminal connected to a high level VGH, and its gate connected to terminal D3. The seventh transistor T7 has its first terminal connected to terminal D4, its second terminal connected to terminal D5, and its gate connected to the first clock signal XCK. The eighth transistor T8 has its first terminal connected to terminal D3, its second terminal connected to a first set voltage V1, and its gate connected to a low level VGL. The ninth transistor T9 has its first terminal connected to a high level VGH, its second terminal connected to the output terminal, and its gate connected to the fifth terminal D5. A first capacitor C01 is connected between the first terminal and the gate. The tenth transistor T10 has its first terminal connected to the output terminal, its second terminal connected to a low level VGL, and its gate connected to the second terminal of the sixteenth transistor T16. The eleventh transistor T11 has its first terminal connected to the first clock signal XCK, its second terminal connected to the sixth terminal D6, and its gate connected to the seventh terminal D7. The twelfth transistor T12 has its first terminal connected to a high level VGH, its second terminal connected to the sixth terminal D6, and its gate connected to the second set voltage V2. The thirteenth transistor T13 has its first terminal connected to a high level VGH, its second terminal connected to the third terminal D3, and its gate connected to the third set voltage RST. The fourteenth transistor T14 has its first terminal connected to the input signal IN, its second terminal connected to the eighth terminal D8, and its gate connected to the second clock signal CK. The fifteenth transistor T15 has its first terminal connected to the eighth terminal D8, its second terminal connected to the ninth terminal D9, and its gate connected to a low level VGL. The sixteenth transistor T16 has its first terminal connected to the ninth terminal D9, and its gate connected to the seventh terminal D7.

[0111] The second clock signal CK is out of phase with the first clock signal XCK; that is, when one is high, the other is low. A second capacitor C02 is connected between the second terminal D2 and the fourth terminal D4. The first scan signal S2N is output. A third capacitor C03 is connected between the sixth terminal D6 and the seventh terminal D7.

[0112] refer to Figure 15 , Figure 15 This is a schematic diagram of another display panel structure provided in an embodiment of this application. Based on other embodiments, Figure 15In the display panel 100 shown, a driver chip 107 connected to the first driving circuit 106 is also provided in the non-display area BB. The driver chip 107 is used to output a first clock signal XCK. The driver chip 107 can provide the first clock signal XCK and the second clock signal CK required to the first driving circuit 106. Based on the clock circuit built into the driver chip 107, the driver chip 107 can provide a clock signal to the first signal line L1 in the first sub-display area AA1 with the required delay period T0 through a pre-stored calculation program, without the need to add an additional clock module.

[0113] Optionally, the driver chip 107 is further configured to provide a first clock signal XCK with a delay period to the first driving circuit 106 connected to the first signal line L1 when it is determined that the first signal line L1 is within the first sub-display area AA1. In this mode, the driver chip 107 has a position recognition function, which can identify whether the currently driven first signal line L1 is within the first sub-display area AA1, and when it is confirmed that the first signal line L1 is within the first sub-display area AA1, it provides a first clock signal XCK with a delay period T0 to the first driving circuit 106 to provide a first scan signal S2N with a set delay period T0 to the currently scanned first signal line L1.

[0114] In some embodiments of this application, the driver chip 107 is further configured to provide a first clock signal XCK with no delay period to the first driving circuit 106 connected to the first signal line L1 when it is determined that the first signal line L1 is located within the second sub-display area AA2. In this method, the driver chip 107 can provide different first clock signals XCK to the first driving circuit 106 based on whether the currently driven first signal line L1 is located within the first sub-display area AA1. If the first signal line L1 is located within the first sub-display area AA1, such as... Figure 12 As shown, a first clock signal XCK with a delay period T0 is provided to the shift register VSR to which it is connected, in order to provide a first scan signal with a delay period T0 to the first signal line L1, thereby improving the coupling between the first signal line L1 and the first node N1, and better counteracting the coupling of the second signal line L2 to the first node N1. If the first signal line L1 is located in the second sub-display area AA2, as... Figure 13 The diagram shows the first clock signal XCK that provides a delay-free period T0 to the shift register VSR to which it is connected, which can simplify the driving timing of the clock signal required for the first signal line L1 in the second sub-display area AA2.

[0115] like Figure 15As shown, in some embodiments, the driver chip 107 is also used to provide a data signal Data to the pixel circuit 103. The driver chip 107 can be connected to a data line 108 to provide the data signal Data to the pixel circuit 103. The data signal Data corresponds to the row number of the pixel circuit 103, and the driver chip is used to determine whether the first signal line L1 is within the first sub-display area AA1 based on this correspondence. For a given set of data to be displayed, the data signal Data required by each row of pixel circuits 103 corresponds to the row number of the pixel circuit 103. The driver chip 107 can determine whether the first signal line L1 connected to it is within the first sub-display area AA1 based on this correspondence, so as to provide an adapted first clock signal XCK to the shift register VSR connected to the first signal line L1 based on the determination result.

[0116] In some embodiments of this application, the first signal line L1 located in the first sub-display area AA1 and the first signal line L1 located in the second sub-display area AA2 can have the same first coupling capacitance C1. In this method, the first signal line L1 in different sub-display areas has the same first coupling capacitance C1, and the problem of uneven display brightness caused by the coupling of the second signal line L2 to the first node N1 in the first sub-display area AA1 is solved only by delaying the first scan signal S2N during the falling edge delay period T0. There is no need to change the circuit layout of the pixel circuit in the display panel. The pixel circuits in the first sub-display area AA1 and the second sub-display area AA2 can have the same circuit layout, without the need to differentiate the circuit layout of the pixel circuits in the two sub-display areas, which facilitates the manufacturing process of the display panel.

[0117] In some embodiments of this application, the first signal line L1 located in the first sub-display area AA1 and the first signal line L1 located in the second sub-display area AA2 may have different first coupling capacitances C1. The first coupling capacitance C1 of the first signal line L1 located in the first sub-display area AA1 relative to the first node N1 is greater than the first coupling capacitance C1 of the first signal line L1 located in the second sub-display area AA2 relative to the first node N1. Specifically, in the first sub-display area AA1, the capacitance value of the first coupling capacitance C1 is CV1; in the second sub-display area AA2, the capacitance value of the first coupling capacitance C1 is CV2; wherein, CV1 > CV2. In this method, not only can the coupling effect of the first coupling capacitor C in the first sub-display area AA1 on the first node N1 be increased by increasing the delay period T0 of the first scanning signal S2N during the falling edge, as described in the previous embodiment, thus solving the problem of uneven display brightness caused by the coupling of the second signal line L2 to the first node N1 in the first sub-display area AA1, the capacitance value of the first coupling capacitor C1 in the two sub-display areas can be differentiated. By increasing the first coupling capacitor C1 in the first sub-display area AA1, the coupling effect of the first signal line L1 on the first node N1 in the first sub-display area AA1 can be improved, so as to better counteract the coupling effect of the second signal line L2 on the first node N1 in the first sub-display area AA1.

[0118] When CV1 > CV2, for the second sub-display area AA2, due to the requirement of the arc winding of the drive signal line, the second coupling capacitor C2 has a small impact on the coupling of the first node N1. Therefore, it is not necessary to perform reverse cancellation coupling through the first coupling capacitor C1. Thus, the first coupling capacitor C1 in the second sub-display area AA2 can be set to have a small capacitance value CV2. There is no need to improve the layout design in the second sub-display AA2 to increase the first coupling capacitor C1, thereby reducing the manufacturing process difficulty of the display panel.

[0119] As can be seen from the capacitance calculation formula, the capacitance between two plates is directly proportional to the area of ​​their opposing surfaces and inversely proportional to the relative distance between them. Based on this principle, in the embodiments of this application, the capacitance value of the coupling capacitor can be adjusted by adjusting the distance and / or area between the two plates of the coupling capacitor.

[0120] refer to Figure 16 and Figure 17 , Figure 16 This is a schematic diagram of a layout of the first signal line and the first node in the pixel circuit located in the first sub-display area. Figure 17 This is a schematic diagram of a layout of the first signal line and the first node in the pixel circuit located in the second sub-display area. In this method, the capacitance value of the first coupling capacitor C1 in the first sub-display area AA1 and the second sub-display area AA2 is designed differently by adjusting the distance between the two plates of the first coupling capacitor C1.

[0121] like Figure 16 As shown, within the first sub-display area AA1, the distance d1 in the thickness direction Z between the conductive connection portion 116 connecting the first signal line L1 and the first node N1 is d1; Figure 17 As shown, within the second sub-display area AA2, the distance in the thickness direction Z between the conductive connection portion 116 connecting the first signal line L1 and the first node N1 is d2; where d1 < d2. In this method, when the distance d2 is constant, reducing the distance d1 allows the first signal line L1 in the first sub-display area AA1 to form a larger first coupling capacitance C1, making CV1 > CV2. This can improve the coupling effect of the first signal line L1 to the first node N1 within the first sub-display area AA1, and better counteract the coupling effect of the second signal line L2 to the first node N1 within the first sub-display area AA1.

[0122] In the first sub-display area AA1 and the second sub-display area AA2, the conductive layer where the conductive connection portion 116 and / or the first signal line L1 are located can be adjusted to make d1 < d2, thereby making CV1 > CV2. This embodiment of the application does not limit the conductive layer where the conductive connection portion 116 and the first signal line L1 are located. The conductive layer includes a metal layer and a polysilicon layer in the display panel.

[0123] Optionally, the signal line for transmitting the reference voltage, the first signal line L1, and the signal line for transmitting the third scan signal S1N can be located in the capacitor metal layer MC.

[0124] refer to Figure 18 and Figure 19 , Figure 18 This is a schematic diagram of another layout of the first signal line and the first node in the pixel circuit located in the first sub-display area. Figure 19 This is a schematic diagram of another layout of the first signal line and the first node in the pixel circuit located in the second sub-display area. In this method, the capacitance value of the first coupling capacitor C1 in the first sub-display area AA1 and the second sub-display area AA2 is differentiated by adjusting the area of ​​the two plates facing each other.

[0125] like Figure 18 As shown, within the first sub-display area AA1, the area directly opposite the first signal line L1 and the conductive connection portion 116 in the thickness direction Z is S1; as Figure 19As shown, within the second sub-display area AA2, the area of ​​the first signal line L1 and the conductive connection portion 116 facing each other in the thickness direction Z is S2; where S1 > S2. In this method, when the area S2 of the first signal line L1 and the conductive connection portion 116 in the second sub-display area AA2 is constant, by increasing the area S1 of the first signal line L1 and the conductive connection portion 116 in the first sub-display area AA1, a larger first coupling capacitance C1 can be formed by the first signal line L1 in the first sub-display area AA1, making CV1 > CV2. This can improve the coupling effect of the first signal line L1 in the first sub-display area AA1 on the first node N1, and can better counteract the coupling effect of the second signal line L2 in the first sub-display area AA1 on the first node N1.

[0126] like Figure 18 As shown, within the first sub-display area AA1, at the intersection of the conductive connection portion 116 and the first signal line L1 ( Figure 18 (The area shown in the dashed box) has a line width of W21 for the conductive connection portion 116 and a line width of W11 for the first signal line L1. For example... Figure 19 As shown, within the second sub-display area AA2, at the intersection of the conductive connection portion 116 and the first signal line L1 ( Figure 19 (The area shown in the dashed box) has a line width of W22 for the conductive connection portion 116 and a line width of W12 for the first signal line L1. W21 > W22 and W11 > W12 can be set such that S1 > S2. Alternatively, W21 > W22 and W11 = W12, or W21 = W22 and W11 > W12 can be set.

[0127] When S1 > S2, d1 < d2 can be set to increase the first coupling capacitor C1 formed by the first signal line L1 in the first sub-display area AA1 to a greater extent. In other ways, in the display panel, S1 > S2 and / or d1 < d2 can be set. When S1 > S2, d1 < d2 or d1 = d2; when d1 < d2, S1 > S2 or S1 = S2.

[0128] In some embodiments of this application, the second signal line L2 located in the first sub-display area AA1 and the second signal line L2 located in the second sub-display area AA2 can have the same second coupling capacitor C2. In this method, the second signal line L2 in different sub-display areas has the same second coupling capacitor C2, and the problem of uneven display brightness caused by the coupling of the second signal line L2 to the first node N1 in the first sub-display area AA1 is solved only by delaying the first scan signal S2N during the falling edge delay period T0. There is no need to change the circuit layout of the pixel circuit in the display panel. The pixel circuits in the first sub-display area AA1 and the second sub-display area AA2 can have the same circuit layout, without the need to differentiate the circuit layout of the pixel circuits in the two sub-display areas, which facilitates the manufacturing process of the display panel.

[0129] In other embodiments of this application, the second signal line L2 located in the first sub-display area AA1 and the second signal line L2 located in the second sub-display area AA2 may have different second coupling capacitances C2. The second coupling capacitance C2 formed by the second signal line L2 located in the first sub-display area AA1 is smaller than the second coupling capacitance C2 formed by the second signal line L2 located in the second sub-display area AA2. The first node N1 is connected to a conductive connection portion, and the conductive connection portion is insulated from and crosses the second signal line L2 to form the second coupling capacitance C2.

[0130] In the first sub-display area AA1, the capacitance value of the second coupling capacitor C2 is CV3; in the second sub-display area AA2, the capacitance value of the second coupling capacitor C2 is CV4; where CV3 < CV4. This method not only solves the problem of uneven display brightness in the first sub-display area AA1 caused by the coupling of the second signal line L2 to the first node N1 by delaying the first scan signal S2N during the falling edge T0, but also reduces the coupling effect of the second signal line L2 to the first node N1 by differentially designing the capacitance values ​​of the second coupling capacitor C2 in the two sub-display areas. This reduces the degree of reverse coupling required by the first signal line L1, thus reducing the difficulty of counteracting the coupling effect of the second signal line L2 through the first signal line L1.

[0131] refer to Figure 20 and Figure 21 , Figure 20 This is a schematic diagram of a layout of the second signal line and the first node in the pixel circuit located in the first sub-display area. Figure 21 This is a schematic diagram of a layout of the second signal line and the first node in the pixel circuit located in the second sub-display area. In this method, the capacitance value of the second coupling capacitor C2 in the first sub-display area AA1 and the second sub-display area AA2 is differentiated by adjusting the distance between the two plates of the second coupling capacitor C2.

[0132] like Figure 20 As shown, in the first sub-display area AA1, the distance between the second signal line L2 and the conductive connection portion 116 in the thickness direction Z is d3; Figure 21 As shown, in the second sub-display area AA2, the distance between the second signal line L2 and the conductive connection portion 116 in the thickness direction Z is d4; where d3 > d4. In this method, when the distance d4 is constant, by increasing the distance d3, the second coupling capacitance C2 formed by the second signal line L2 in the first sub-display area AA1 can be reduced, making CV3 < CV4. This reduces the degree of reverse coupling required by the first signal line L1, thereby reducing the difficulty of counteracting the coupling effect of the second signal line L2 through the first signal line L1.

[0133] In the first sub-display area AA1 and the second sub-display area AA2, the conductive layer where the conductive connection portion 116 and / or the second signal line L2 are located can be adjusted to make d3 > d4, thereby making CV3 < CV42. This embodiment of the application does not limit the conductive layer where the conductive connection portion 116 and the second signal line L2 are located. The conductive layer includes a metal layer and a polysilicon layer in the display panel.

[0134] Optionally, the second signal line L2, the signal line for transmitting the light emission control signal EM, and the signal line for transmitting the fourth scan signal SPX can be located in the first metal layer M1.

[0135] refer to Figure 22 and Figure 23 , Figure 22 This is a schematic diagram of another layout of the second signal line and the first node in the pixel circuit located in the first sub-display area. Figure 23 This diagram illustrates an alternative layout of the second signal line and the first node in the pixel circuit located within the second sub-display area. In this approach, the capacitance values ​​of the second coupling capacitor C2 in the first sub-display area AA1 and the second sub-display area AA2 are differentiated by adjusting the area of ​​the opposing plates between the two plates of the second coupling capacitor C2.

[0136] like Figure 22 As shown, within the first sub-display area AA1, the area directly opposite the second signal line L2 and the conductive connection portion 116 in the thickness direction Z is S3; Figure 23As shown, within the second sub-display area AA2, the area directly opposite the second signal line L2 and the conductive connection portion 116 in the thickness direction Z is S4; where S3 < S4. In this method, when the area S4 directly opposite the second signal line L2 and the conductive connection portion 116 in the second sub-display area AA2 is constant, by reducing the area S3 directly opposite the second signal line L2 and the conductive connection portion 116 in the first sub-display area AA1, the second coupling capacitance C2 formed by the second signal line L2 in the first sub-display area AA1 can be reduced, thereby reducing the coupling effect of the second signal line L2 on the first node N1. In this method, in the first sub-display area AA1, based on setting a delay period to cancel the direction of the second coupling capacitance C2, the coupling effect of the second coupling capacitance C2 is further reduced by directly reducing the capacitance value of the second coupling capacitance C2, thereby greatly reducing the impact of the second coupling capacitance C2 on the display effect.

[0137] like Figure 22 As shown, within the first sub-display area AA1, at the intersection of the conductive connection portion 116 and the second signal line L2 ( Figure 22 (The area shown in the dashed box) has a line width of W23 for the conductive connection portion 116 and a line width of W13 for the second signal line L2. For example... Figure 23 As shown, within the second sub-display area AA2, at the intersection of the conductive connection portion 116 and the second signal line L2 ( Figure 23 (The area shown in the dashed box) has a line width of W24 for the conductive connection portion 116 and a line width of W14 for the second signal line L2. W24 > W23 and W14 > W13 can be set so that S4 > S3. Alternatively, W24 > W23 and W14 = W13, or W14 > W13 and W24 = W23 can also be set.

[0138] In other embodiments, the relative position between the second signal line L2 and the first node N1 can be adjusted to increase the current path between the second coupling capacitor C2 and the first node N1, thereby reducing the influence of the second coupling capacitor C2 on the first node N1. In this case, the layout of the signal line and the first node can be as follows: Figure 24 As shown.

[0139] refer to Figure 24 , Figure 24This diagram illustrates a layout of a first signal line, a second signal line, and a first node within a first sub-display area AA1. For the first signal line L1 and the second signal line L2 connected by the same pixel circuit 103, the first signal line L1 is located between the second signal line L2 and the first node N1. In this layout, by optimizing the relative positions of the signal lines and the first node N1, the distance between the second signal line L2 and the first node N1 in the column direction Y is increased. This reduces the influence of the second coupling capacitor C2 formed by the second signal line L2 on the first node N1, thereby reducing the required degree of reverse coupling by the first signal line L1 and simplifying the process of counteracting the coupling effect of the second signal line L2 through the first signal line L1.

[0140] Optionally, such as Figure 24 As shown, within the first sub-display area AA1, the distance d5 between the first signal line L1 and the first node N1 is greater than the distance d6 between the first signal line L1 and the second signal line L2, so as to increase the distance between the first node N1 and the first signal line L1 and the second signal line L2 to a greater extent, thereby reducing the influence of the second coupling capacitor C2 on the first node N1.

[0141] refer to Figure 25 , Figure 25 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device includes a display panel provided in any of the above embodiments. The electronic device can be an electronic device with display function, such as a mobile phone, tablet computer, or wearable device. This application does not limit the specific type of electronic device.

[0142] The electronic devices and display panel embodiments disclosed in the above embodiments have the same or corresponding beneficial effects, and will not be repeated here to avoid repetition.

[0143] The various embodiments in this application are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. The embodiments provided in this application can be combined with each other without contradiction.

[0144] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0145] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0146] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0147] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, wherein the display area of ​​the display panel has a photosensitive device setting area, characterized in that, The display panel includes: An array substrate, the array substrate including pixel circuitry; A display array disposed on the array substrate includes a plurality of light-emitting elements arranged in an array, and the light-emitting elements are connected to the pixel circuit. The pixel circuit includes: A driving transistor, wherein the gate of the driving transistor is connected to a first node, the first terminal of the driving transistor is connected to a second node, and the second terminal of the driving transistor is connected to a third node; A threshold compensation transistor, wherein the gate of the threshold compensation transistor is connected to a first signal line for receiving a first scan signal, the first terminal of the threshold compensation transistor is connected to the first node, and the second terminal of the threshold compensation transistor is connected to the third node; A data writing transistor, wherein the gate of the data writing transistor is connected to a second signal line for receiving a second scan signal, the first terminal of the data writing transistor is used to receive a data signal, and the second terminal of the data writing transistor is connected to the first node; Among them, one of the threshold compensation transistor and the data writing transistor is an NMOS and the other is a PMOS; The display area includes a first sub-display area and a second sub-display area arranged along the column direction. The first sub-display area is provided with the photosensitive device setting area. In the first sub-display area, there are multiple rows of light-emitting elements arranged with a path passing through the photosensitive device setting area. In the first sub-display area, the first scan signal input by the first signal line has a delay period for delaying the shutdown of the threshold compensation transistor.

2. The display panel according to claim 1, characterized in that, Also includes: A first driving circuit is connected to the first signal line; the first driving circuit is used to output the first scan signal based on a first clock signal. The falling edge of the first clock signal has a delay period.

3. The display panel according to claim 2, characterized in that, The high level of the first clock signal is the first voltage, and the low level of the first clock signal is the second voltage; The delay period of the first clock signal includes at least one stepped band, the voltage of which is between the first voltage and the second voltage.

4. The display panel according to claim 2, characterized in that, It also includes a driver chip connected to the first driver circuit, the driver chip being used to output the first clock signal.

5. The display panel according to claim 4, characterized in that, The driver chip is also used to provide a first clock signal with a delay period to the first driver circuit connected to the first signal line when it is determined that the first signal line is within the first sub-display area.

6. The display panel according to claim 5, characterized in that, The driver chip is also used to provide a first clock signal with no delay period to the first driver circuit connected to the first signal line when it is determined that the first signal line is located in the second sub-display area.

7. The display panel according to claim 4, characterized in that, The driving chip is also used to provide the data signal to the pixel circuit. The data signal has a corresponding relationship with the row number of the pixel circuit. The driving chip is used to determine whether the first signal line is within the first sub-display area based on the corresponding relationship.

8. The display panel according to claim 1, characterized in that, The first signal line and the first node have a first coupling capacitor; The second signal line has a second coupling capacitor with the first node, and the second scan signal has a delay period due to the second coupling capacitor during the process of switching from the on period to the off period. Wherein, the first coupling capacitor forms a reverse coupling with the second coupling capacitor during the delay period of the second scanning signal and the first node during the delay period of the first scanning signal.

9. The display panel according to claim 1, characterized in that, The duration of the delay period of the first scan signal is longer than the duration of the delay period of the second scan signal.

10. The display panel according to claim 1, characterized in that, Within the second sub-display area, the first scan signal input to the first signal line has a delay period for turning off the threshold compensation transistor; In the first sub-display area, the duration of the delay period of the first scan signal input by the first signal line is Te1; In the second sub-display area, the duration of the delay period of the first scan signal input by the first signal line is Te2; Among them, Te1 > Te2.

11. The display panel according to claim 1, characterized in that, The first signal line and the first node have a first coupling capacitor; In the first sub-display area, the capacitance value of the first coupling capacitor is CV1; In the second sub-display area, the capacitance value of the first coupling capacitor is CV2; Among them, CV1 > CV2.

12. The display panel according to claim 11, characterized in that, The first node is connected to a conductive connection part; the conductive connection part is insulated from and intersects with the first signal line to form the first coupling capacitor; Within the first sub-display area, the distance between the first signal line and the conductive connection portion in the thickness direction of the display panel is d1; Within the second sub-display area, the distance between the first signal line and the conductive connection portion in the thickness direction of the display panel is d2; Where d1 < d2.

13. The display panel according to claim 11, characterized in that, The first node is connected to a conductive connection part; the conductive connection part is insulated from and intersects with the first signal line to form the first coupling capacitor; Within the first sub-display area, the area directly opposite the first signal line and the conductive connection portion is S1; Within the second sub-display area, the area directly opposite the first signal line and the conductive connection portion is S2; Where S1 > S2.

14. The display panel according to claim 1, characterized in that, The first node is connected to a conductive connection part; the conductive connection part is insulated from and intersects with the second signal line to form the second coupling capacitor; In the first sub-display area, the capacitance value of the second coupling capacitor is CV3; In the second sub-display area, the capacitance value of the second coupling capacitor is CV4; Where CV3 < CV4.

15. The display panel according to claim 14, characterized in that, In the first sub-display area, the distance between the second signal line and the conductive connection portion in the thickness direction of the display panel is d3; In the second sub-display area, the distance between the second signal line and the conductive connection portion in the thickness direction of the display panel is d4; Among them, d3 > d4.

16. The display panel according to claim 14, characterized in that, Within the first sub-display area, the area directly opposite the second signal line and the conductive connection portion is S3; Within the second sub-display area, the area directly opposite the second signal line and the conductive connection portion is S4; Where S3 < S4.

17. The display panel according to claim 1, characterized in that, Within the first sub-display area, for the first signal line and the second signal line connected to the same pixel circuit, the first signal line is located between the second signal line and the first node.

18. The display panel according to claim 17, characterized in that, Within the first sub-display area, the distance between the first signal line and the first node is greater than the distance between the first signal line and the second signal line.

19. An electronic device, characterized in that, Includes the display panel as described in any one of claims 1-18.

Images