Display device

Abstract

A display device is provided. In general, according to embodiments, the display device includes: a substrate; a first lower electrode and a second lower electrode disposed above the substrate and separated from each other; a rib layer disposed above the first lower electrode and the second lower electrode, having a first pixel opening overlapping the first lower electrode and a second pixel opening overlapping the second lower electrode; a partition wall including a lower portion disposed above the rib layer and having conductivity, and an upper portion disposed above the lower portion and protruding from a side surface of the lower portion; an encapsulation layer having a recess disposed directly above the partition wall; and a lens formed in a convex shape, covering a portion of a bottom surface of the recess in a direction in which the first lower electrode and the second lower electrode are arranged.

Description

Cross-reference of related applications

[0001] This application claims priority based on Japanese Patent Application No. 2025-007818, filed on January 20, 2025, and incorporates all the contents of that Japanese Patent Application. Technical Field

[0002] Embodiments of the present invention relate to display devices. Background Technology

[0003] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. In such display devices, technologies that can improve display quality are needed. Summary of the Invention

[0004] Generally speaking, according to the embodiments, the display device includes: a substrate; a first lower electrode and a second lower electrode disposed above the substrate and separated from each other; a rib layer disposed above the first lower electrode and the second lower electrode, having a first pixel opening overlapping the first lower electrode and a second pixel opening overlapping the second lower electrode; a partition wall comprising a lower portion disposed above the rib layer and having conductivity, and an upper portion disposed above the lower portion and protruding from the side of the lower portion; a first organic layer that is in contact with the first lower electrode through the first pixel opening; and a second organic layer that is... The second lower electrode is connected to the second lower electrode through the second pixel opening; the first upper electrode is disposed above the first organic layer and connected to the lower part; the second upper electrode is disposed above the second organic layer and connected to the lower part; the sealing layer has a recess located between the first lower electrode and the second lower electrode and disposed directly above the partition wall, the sealing layer covering the first upper electrode and the second upper electrode; and a convex lens is disposed above the sealing layer and covers a portion of the bottom surface of the recess in the direction in which the first lower electrode and the second lower electrode are arranged.

[0005] According to other embodiments, the display device includes: a substrate; a first lower electrode and a second lower electrode disposed above the substrate and separated from each other; a rib layer disposed above the first lower electrode and the second lower electrode, having a first pixel opening overlapping the first lower electrode and a second pixel opening overlapping the second lower electrode; a partition wall comprising a lower portion disposed above the rib layer and having conductivity, and an upper portion disposed above the lower portion and protruding from the side of the lower portion; a first organic layer connected to the first lower electrode through the first pixel opening; and a second organic layer, which... The second pixel opening is connected to the second lower electrode; a first upper electrode is disposed above the first organic layer and connected to the lower part; a second upper electrode is disposed above the second organic layer and connected to the lower part; a sealing layer has a recess located between the first lower electrode and the second lower electrode and disposed directly above the partition wall, the sealing layer covering the first upper electrode and the second upper electrode; and a convex lens disposed above the sealing layer, completely covering the bottom surface of the recess in the direction in which the first lower electrode and the second lower electrode are arranged.

[0006] According to the embodiments, a display device capable of improving display quality can be provided. Attached Figure Description

[0007] Figure 1 This is a diagram showing an example of the configuration of the display device according to the first embodiment.

[0008] Figure 2 This is a schematic top view showing an example of the layout of subpixels.

[0009] Figure 3 It is a schematic top view showing the constituent elements that overlap with the sub-pixels.

[0010] Figure 4 It is a schematic top view showing other constituent elements that overlap with the sub-pixels.

[0011] Figure 5 It shows along Figure 3 A schematic cross-sectional view of the VV line display device.

[0012] Figure 6 This is a diagram illustrating an example of a layer structure that can be applied to a display element.

[0013] Figure 7 It is a cross-sectional view showing the lens magnified.

[0014] Figure 8 This is a cross-sectional view used to illustrate the effects of the display device according to the first embodiment.

[0015] Figure 9AThis is a schematic cross-sectional view showing the manufacturing process of the display device according to the first embodiment.

[0016] Figure 9B It shows the next step. Figure 9A A rough cross-sectional view of the process.

[0017] Figure 9C It shows the next step. Figure 9B A rough cross-sectional view of the process.

[0018] Figure 10 This is a schematic top view showing the sub-pixels of the display device according to the second embodiment.

[0019] Figure 11 This is a schematic cross-sectional view of the display device according to the third embodiment.

[0020] Figure 12 This is a schematic top view showing the sub-pixels of the display device according to the fourth embodiment.

[0021] Figure 13 It is along Figure 12 A schematic cross-sectional view of the display device for the XIII-XIII line.

[0022] Figure 14 This is a diagram illustrating an example of the layer structure of a display element that can be applied to the display device of the fourth embodiment.

[0023] Figure 15 It is a cross-sectional view showing the lens magnified.

[0024] Figure 16A This is a schematic cross-sectional view showing the manufacturing process of the display device according to the fourth embodiment.

[0025] Figure 16B It shows the next step. Figure 16A A rough cross-sectional view of the process.

[0026] Figure 16C It shows the next step. Figure 16B A rough cross-sectional view of the process.

[0027] Figure 16D It shows the next step. Figure 16C A rough cross-sectional view of the process.

[0028] Figure 17 This is a schematic cross-sectional view of the display device according to the fifth embodiment. Detailed Implementation

[0029] Several implementation methods are described with reference to the accompanying drawings.

[0030] The disclosure is merely one example, and appropriate modifications that can be readily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of this invention. Furthermore, to make the description clearer, the width, thickness, shape, etc., of various parts of the drawings are sometimes shown schematically compared to the actual form, but this is only an example and not a limitation on the interpretation of the invention. Additionally, in this specification and the figures, the same reference numerals are used for constituent elements that perform the same or similar functions as those described above with respect to the existing figures, and sometimes repeated detailed descriptions are appropriately omitted.

[0031] It should be noted that, for ease of understanding and as needed, the accompanying drawings show mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. Furthermore, observing various elements parallel to the Z-direction is called a top-down view.

[0032] The display device in each embodiment is an organic electroluminescent display device that uses organic light-emitting diodes (OLEDs) as display elements, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet computers, smartphones, mobile phone terminals, and wearable terminals.

[0033] [First Embodiment]

[0034] Figure 1 This diagram illustrates a configuration example of the display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying images and a peripheral area SA located outside the display area DA. The substrate 10 may be glass or a flexible resin film.

[0035] In this embodiment, the shape of the substrate 10 when viewed from above is a rectangle with a long side in the Y direction. However, the shape of the substrate 10 when viewed from above is not limited to this example, and may also be other shapes such as square, circle or ellipse.

[0036] The display area DA has a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX contains a plurality of sub-pixels SP that display different colors. In this embodiment, it is envisioned that pixel PX contains a green sub-pixel SP1, a red sub-pixel SP2, and a blue sub-pixel SP3. However, pixel PX may also contain sub-pixels SP of other colors such as white, either together with or replacing any of the sub-pixels SP1, SP2, and SP3.

[0037] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements, for example, made of thin-film transistors.

[0038] The display area DA is configured with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply image signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. Figure 1 In the example, the scan line GL and the power line PL extend along the X direction, and the signal line SL extends along the Y direction.

[0039] The gate electrode of pixel switch 2 is connected to scan line GL. The source electrode of pixel switch 2 is connected to signal line SL. The drain electrode of pixel switch 2 is connected to the gate electrode of driving transistor 3 and capacitor 4. The source electrode of driving transistor 3 is connected to power line PL and capacitor 4. The drain electrode of driving transistor 3 is connected to display element DE.

[0040] It should be noted that the configuration of pixel circuit 1 is not limited to the example shown in the figure. For example, pixel circuit 1 may also have more thin-film transistors and capacitors.

[0041] Although not detailed, the surrounding area SA is equipped with terminals for connecting IC chips and flexible printed circuit boards.

[0042] Figure 2 This is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. Figure 2 In the example, subpixels SP1 and SP2 are arranged with subpixel SP3 in the X direction. Furthermore, subpixels SP1 and SP2 are arranged in the Y direction.

[0043] With this layout of sub-pixels SP1, SP2, and SP3, the display area DA contains columns of sub-pixels SP1 and SP2 arranged alternately in the Y direction, and multiple columns of sub-pixels SP3 arranged repeatedly in the Y direction. These columns are arranged alternately in the X direction. It should be noted that the layout of sub-pixels SP1, SP2, and SP3 is not limited to this. Figure 2 Examples.

[0044] A rib layer 5 is configured in the display area DA. Rib layer 5 has pixel openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. Figure 2In the example shown, pixel aperture AP2 is larger than pixel aperture AP1, and pixel aperture AP3 is larger than pixel aperture AP2. That is, among subpixels SP1, SP2, and SP3, subpixel SP3 has the largest aperture ratio, and subpixel SP1 has the smallest aperture ratio. It should be noted that the size and shape of pixel apertures AP1, AP2, and AP3 are not limited to the example shown.

[0045] Sub-pixel SP1 has a lower electrode LE1 (first lower electrode), an upper electrode UE1 (first upper electrode), and an organic layer OR1 (first organic layer) that overlap with pixel opening AP1 (first pixel opening). Sub-pixel SP2 has a lower electrode LE2 (second lower electrode), an upper electrode UE2 (second upper electrode), and an organic layer OR2 (second organic layer) that overlap with pixel opening AP2 (second pixel opening). Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0046] In the lower electrode LE1, upper electrode UE1, and organic layer OR1, the portion overlapping with pixel opening AP1 constitutes display element DE1 of sub-pixel SP1. In the lower electrode LE2, upper electrode UE2, and organic layer OR2, the portion overlapping with pixel opening AP2 constitutes display element DE2 of sub-pixel SP2. In the lower electrode LE3, upper electrode UE3, and organic layer OR3, the portion overlapping with pixel opening AP3 constitutes display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may also include a capping layer described later. Rib layer 5 surrounds each of these display elements DE1, DE2, and DE3. In the example of this embodiment, display elements DE1, DE2, and DE3 are configured to emit white light.

[0047] A conductive partition 6 is disposed in the display area DA. The partition 6 is located above the rib layer 5 and overlaps with the rib layer 5 entirely. Figure 2 In this example, partition 6 has the same planar shape as rib 5. That is, partition 6 has openings in sub-pixels SP1, SP2, and SP3 respectively. From another perspective, when viewed from above, rib 5 and partition 6 form a grid pattern, surrounding each of display elements DE1, DE2, and DE3. Furthermore, partition 6 surrounds pixel openings AP1, AP2, and AP3. Partition 6 serves as wiring to supply a common voltage to the upward electrodes UE1, UE2, and UE3.

[0048] Figure 3 This is a schematic top view showing the constituent elements overlapping with sub-pixels SP1, SP2, and SP3. Figure 3 The diagrams of the lower electrode, organic layer, upper electrode, etc., that make up the display elements of each sub-pixel are omitted.

[0049] Multiple lenses ML1 are arranged in the display area DA. When viewed from above, each lens ML1 appears circular. In the illustrated example, all lenses ML1 have the same diameter. It should be noted that lenses ML1 with diameters different from the other lenses ML1 can also be arranged. In one example, the diameter of the lens ML1 is the same as the length of the interval between the pixel openings AP1, AP2, and AP3.

[0050] Multiple lenses ML1 surround pixel openings AP1, AP2, and AP3, respectively. The multiple lenses ML1 are positioned directly above pixel openings AP1, AP2, and AP3. Figure 3 In the example shown, four lenses ML1 are positioned directly above pixel aperture AP1. Four lenses ML1 are positioned directly above pixel aperture AP2. Eight lenses ML1 are positioned above pixel aperture AP3. The lenses ML1 are arranged in a non-overlapping manner.

[0051] Figure 4 This is a schematic top view showing other constituent elements overlapping with sub-pixels SP1, SP2, and SP3. A color filter layer CF is disposed above display elements DE1, DE2, and DE3.

[0052] The color filter layer CF has a green-colored color filter CF1 (first color filter), a red-colored color filter CF2 (second color filter), and a blue-colored color filter CF3. Color filter CF1 covers pixel opening AP1. When viewed from above, the periphery of color filter CF1 overlaps with rib layer 5 and partition wall 6. Color filter CF2 covers pixel opening AP2. When viewed from above, the periphery of color filter CF2 overlaps with rib layer 5 and partition wall 6. Color filter CF3 covers pixel opening AP3. When viewed from above, the periphery of color filter CF3 overlaps with rib layer 5 and partition wall 6.

[0053] Color filter CF1 is configured to block light of wavelengths other than green from passing through. Color filter CF2 is configured to block light of wavelengths other than red from passing through. Color filter CF3 is configured to block light of wavelengths other than blue from passing through.

[0054] By passing white light emitted from display element DE1 through color filter CF1, sub-pixel SP1 is displayed as green. Similarly, by passing white light emitted from display element DE2 through color filter CF2, sub-pixel SP2 is displayed as red. Additionally, by passing white light emitted from display element DE3 through color filter CF3, sub-pixel SP3 is displayed as blue.

[0055] Figure 5 It is along Figure 3A schematic cross-sectional view of the VV-line display device DSP. A circuit layer 11 is disposed on the aforementioned substrate 10. The circuit layer 11 includes... Figure 1 The diagram shows various circuits and wiring, including pixel circuit 1, scan line GL, signal line SL, and power line PL. Circuit layer 11 is covered by organic insulating layer 12. Organic insulating layer 12 functions as a planarization film to flatten the unevenness generated by circuit layer 11.

[0056] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12 and are separated from each other. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Figure 5 The cross-section is not shown, but the lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12. Figure 1 The drain electrode of the driving transistor 3 shown is connected.

[0057] The partition 6 includes a lower portion 61 that is conductive and disposed above the rib layer 5, and an upper portion 62 disposed above the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the sides of the lower portion 61. Such a shape of the partition 6 is called a cantilever.

[0058] exist Figure 5 In this example, the lower portion 61 has a bottom layer 63 disposed above the rib layer 5 and a shaft layer 64 disposed above the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the shaft layer 64. Figure 5 In this example, the two ends of the bottom layer 63 protrude from the sides of the shaft layer 64. Furthermore, when viewed from above, the ends of the bottom layer 63 are located between the ends of the upper part 62 and the sides of the shaft layer 64. The upper part 62 is positioned above the shaft layer 64.

[0059] Organic layer OR1 covers the lower electrode LE1 through pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and is opposite to the lower electrode LE1. Organic layer OR2 covers the lower electrode LE2 through pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and is opposite to the lower electrode LE2. Organic layer OR3 covers the lower electrode LE3 through pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and is opposite to the lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the side of the lower portion 61 of partition 6.

[0060] Display element DE1 includes a capping layer CP1 covering the upper electrode UE1. Display element DE2 includes a capping layer CP2 covering the upper electrode UE2. Display element DE3 includes a capping layer CP3 covering the upper electrode UE3. Capping layers CP1, CP2, and CP3 respectively serve as optical adjustment layers to improve the light extraction efficiency emitted by organic layers OR1, OR2, and OR3.

[0061] In the following description, the multilayer containing organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as laminated film FL1, the multilayer containing organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as laminated film FL2, and the multilayer containing organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as laminated film FL3.

[0062] In this embodiment, the upper surface of the upper portion 62 is covered by laminated films FL1, FL2, and FL3. The laminated films FL1, FL2, and FL3, and the partition 6 are covered by a sealing layer SE1 (first sealing layer). The sealing layer SE1 has a first portion SE11, a second portion SE12, and a third portion SE13.

[0063] A first portion SE11 of a cover layer FL1 is disposed in sub-pixel SP1. A second portion SE12 of a cover layer FL2 is disposed in sub-pixel SP2. A third portion SE13 of a cover layer FL3 is disposed in sub-pixel SP3. In this embodiment, the first portion SE11, the second portion SE12, and the third portion SE13 are formed as a single unit.

[0064] Sealing layer SE1 is covered by sealing layer SE2 (second sealing layer). Sealing layer SE2 has a recess R located directly above partition 6. Figure 5 In the example, the recess R is located between the lower electrodes LE1 and LE2 and between the lower electrodes LE1 and LE3. When viewed from above, the recess R is formed along the partition 6. That is, when viewed from above, the recess R surrounds the pixel openings AP1, AP2, and AP3, respectively.

[0065] It should be noted that, in Figure 5 In the example, sealing layers SE1 and SE2 are stacked on top of each other, or sealing layers SE1 and SE2 can be formed as one unit.

[0066] Multiple lenses ML1 are disposed on the sealing layer SE2. The lenses ML1 are formed in a convex shape that protrudes towards the opposite side of the substrate 10. The lenses ML1 cover a portion of the recess R.

[0067] Multiple lenses ML1 are covered by a resin layer RS1. The resin layer RS1 is covered by a sealing layer SE3 (third sealing layer). A color filter layer CF is disposed on top of the sealing layer SE3. Lens ML1 is located between the sealing layer SE2 and the color filter layer CF. The color filter layer CF is covered by a resin layer RS2.

[0068] Color filter CF1 is positioned above display element DE1. Color filter CF2 is positioned above display element DE2. Color filter CF3 is positioned above display element DE3.

[0069] A cover component, such as a polarizer, protective film, or cover glass, can also be further disposed above the resin layer RS2. Such a cover component can also be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0070] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE1, SE2, and SE3 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE1, SE2, and SE3 are formed of silicon nitride. The resin layers RS1 and RS2 are formed, for example, of resin materials (organic insulating materials) such as epoxy resin or acrylic resin.

[0071] The lower electrodes LE1, LE2, and LE3 have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, from a metallic material with excellent light reflectivity, such as silver. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0072] The upper electrodes UE1, UE2, and UE3 are formed, for example, of a metallic material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0073] The capping layers CP1, CP2, and CP3, for example, have a stacked structure composed of multiple overlapping transparent layers. These transparent layers can include layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive index of the sealing layer SE1. It should be noted that at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0074] The bottom layer 63 and the axial layer 64 of the partition 6 are formed of, for example, metallic materials. For example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the axial layer 64. It should be noted that at least one of the bottom layer 63 and the axial layer 64 may also have a multi-layered structure. Additionally, the axial layer 64 may also include a layer formed of an insulating material.

[0075] For example, the upper portion 62 of partition 6 has a laminated structure consisting of a lower layer made of a metallic material and an upper layer made of a conductive oxide. Examples of metallic materials forming the lower layer include titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloys, or molybdenum-niobium alloys. Examples of conductive oxides forming the upper layer include ITO or IZO. It should be noted that the upper portion 62 may also have a single-layer structure of metallic material. Furthermore, the upper portion 62 may also include a layer formed of an insulating material.

[0076] The partition 6 is supplied with a common voltage. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the image signals of the signal line SL through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0077] Figure 6 This diagram illustrates an example of a layer structure that can be applied to display elements DE1, DE2, and DE3. The organic layers OR1, OR2, and OR3 are composed of multiple thin films containing light-emitting layers.

[0078] The organic layer OR1 comprises a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EM1, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. The hole injection layer HIL is located above the lower electrode LE1. The hole transport layer HTL is located above the hole injection layer HIL. The electron blocking layer EBL is located above the hole transport layer HTL. The light-emitting layer EM1 is located above the electron blocking layer EBL. The hole blocking layer HBL is located above the light-emitting layer EM1. The electron transport layer ETL is located above the hole blocking layer HBL. The electron injection layer EIL is located above the electron transport layer ETL. The upper electrode UE1 is located above the electron injection layer EIL.

[0079] The emitting layer EM1 comprises an emitting layer EM11 emitting red light, an emitting layer EM12 emitting green light, and an emitting layer EM13 emitting blue light. Emitting layer EM12 is located above emitting layer EM11, and emitting layer EM13 is located above emitting layer EM12. It should be noted that the stacking order of emitting layers EM11, EM12, and EM13 is not limited to this example. Additionally, the organic layer OR1 may also include emitting layers emitting light of colors other than those mentioned above.

[0080] Organic layer OR2 comprises a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EM2, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. The hole injection layer HIL is located above the lower electrode LE2. The hole transport layer HTL is located above the hole injection layer HIL. The electron blocking layer EBL is located above the hole transport layer HTL. The light-emitting layer EM2 is located above the electron blocking layer EBL. The hole blocking layer HBL is located above the light-emitting layer EM2. The electron transport layer ETL is located above the hole blocking layer HBL. The electron injection layer EIL is located above the electron transport layer ETL. The upper electrode UE2 is located above the electron injection layer EIL.

[0081] The emitting layer EM2 comprises an emitting layer EM21 that emits red light, an emitting layer EM22 that emits green light, and an emitting layer EM23 that emits blue light. Emitting layer EM22 is located above emitting layer EM21, and emitting layer EM23 is located above emitting layer EM22. It should be noted that the stacking order of emitting layers EM21, EM22, and EM23 is not limited to this example. Additionally, the organic layer OR2 may also contain emitting layers that emit light of colors other than those mentioned above.

[0082] The organic layer OR3 comprises a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EM3, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. The hole injection layer HIL is located above the lower electrode LE3. The hole transport layer HTL is located above the hole injection layer HIL. The electron blocking layer EBL is located above the hole transport layer HTL. The light-emitting layer EM3 is located above the electron blocking layer EBL. The hole blocking layer HBL is located above the light-emitting layer EM3. The electron transport layer ETL is located above the hole blocking layer HBL. The electron injection layer EIL is located above the electron transport layer ETL. The upper electrode UE3 is located above the electron injection layer EIL.

[0083] The emitting layer EM3 comprises an emitting layer EM31 that emits red light, an emitting layer EM32 that emits green light, and an emitting layer EM33 that emits blue light. Emitting layer EM32 is located above emitting layer EM31, and emitting layer EM33 is located above emitting layer EM32. It should be noted that the stacking order of emitting layers EM31, EM32, and EM33 is not limited to this example. Additionally, the organic layer OR3 may also include emitting layers that emit light of colors other than those mentioned above.

[0084] It should be noted that, in addition to the functional layers mentioned above, the organic layers OR1, OR2, and OR3 may include other functional layers such as a carrier generation layer as needed, or at least one of the aforementioned functional layers may be omitted.

[0085] Organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layers EM11, EM12, and EM13 emit light. By mixing the red light emitted from the light-emitting layer EM11, the green light emitted from the light-emitting layer EM12, and the blue light emitted from the light-emitting layer EM13, the display element DE1 displays white. Organic layers OR2 and OR3 also emit light in the same way as organic layer OR1, and the display elements DE2 and DE3 display white.

[0086] Figure 7 This is a magnified cross-sectional view showing lens ML1. Figure 7 In the image, the area between sub-pixels SP1 and SP2 is shown magnified. Figure 7 In the text, elements below the organic insulating layer 12 are omitted.

[0087] Sealing layer SE2 has a lower surface S1 and an upper surface S2. The lower surface S1 is opposite to sealing layer SE1. Figure 7 In this example, the lower surface S1 is in contact with the sealing layer SE1. The upper surface S2 is located on the opposite side of the lower surface S1. The upper surface S2 is in contact with the resin layer RS1 and the lens ML1.

[0088] A recess R is formed on the upper surface S2. The recess R has a bottom surface S3. Lens ML1 covers a portion of the bottom surface S3 in the Y direction (the direction in which the lower electrodes LE1 and LE2 are arranged). Figure 7 In the example, two lenses ML1 cover a portion of the bottom surface S3.

[0089] The two lenses ML1 are separated in the Y direction. Therefore, in the Y direction, there is a region in the bottom surface S3 that is not covered by the two lenses ML1. This region is covered by the resin layer RS1. That is, in this region, the sealing layer SE2 is in contact with the resin layer RS1.

[0090] Here, the thickness of the sealing layer SE1 is defined as thickness T1, the thickness of the sealing layer SE2 is defined as thickness T2, the thickness of the resin layer RS1 is defined as thickness T3, and the thickness of the sealing layer SE3 is defined as thickness T4. Thicknesses T1, T2, T3, and T4 correspond to the thickness of the portion of each layer that overlaps with the display elements DE1, DE2, and DE3.

[0091] exist Figure 7 In the example, thicknesses T2, T3, and T4 are less than thickness T1 (T1 > T2, T3, and T4). Furthermore, thicknesses T2, T3, and T4 are equal to each other (T2 = T3 = T4). It should be noted that the relationship between thicknesses T1, T2, T3, and T4 is not limited to this example.

[0092] Furthermore, the depth of the recess R is defined as depth D1. Depth D1 is approximately the distance in the Z direction between the upper surface S2 and the bottom surface S3. In one example, depth D1 is about half the thickness T2.

[0093] The refractive indices of the sealing layers SE1 and SE2 are equal. The refractive index of the lens ML1 is less than that of the sealing layer SE2. The refractive index of the resin layer RS1 is less than that of the lens ML1. In one example, the refractive indices of the sealing layers SE1 and SE2 are both 2.0, the refractive index of the lens ML1 is 1.6, and the refractive index of the resin layer RS1 is 1.4.

[0094] Next, the effects of the display device DSP in this embodiment will be explained. Figure 8 This is a cross-sectional view used to illustrate the effect of the display device DSP in this embodiment.

[0095] The light rays emitted obliquely from the display element DE2 are designated as rays L1 and L2. Ray L2 is more obliquely positioned relative to the axis parallel to the Z direction compared to ray L1. Rays L1 and L2 contain red wavelength light emitted from the light-emitting layer EM21, green wavelength light emitted from the light-emitting layer EM22, and blue wavelength light emitted from the light-emitting layer EM23.

[0096] Light beam L1 is directed toward lens ML1, which overlaps with display element DE2. Figure 8 The light ray L1 travels along the right-hand lens ML1. The light ray L1 reaching lens ML1 is refracted at the interface between lens ML1 and resin layer RS1. As mentioned above, the refractive index of resin layer RS1 is less than the refractive index of lens ML1. Therefore, light ray L1 is refracted towards the Z-direction (the front side of the display device DSP).

[0097] The refracted light ray L1 passes through the color filter CF2 located above the display element DE2. As described above, the color filter CF2 is configured to prevent light of wavelengths other than red from passing through. Therefore, the green and blue wavelengths contained in the light ray L1 are absorbed by the color filter CF2. That is, the light ray L1 passing through the color filter CF2 contains a large amount of red wavelength light. As a result, the sub-pixel SP2 displays red.

[0098] On the other hand, light L2 is directed toward lens ML1, which overlaps with display element DE1, which is adjacent to display element DE2. Figure 8 The light ray L2 travels along the left-hand lens ML1. As described above, the refractive index of lens ML1 is less than that of the sealing layer SE2. Therefore, light ray L2 undergoes total internal reflection at the interface between lens ML1 and the sealing layer SE2. This prevents light ray L2 from interfering with lens ML1, which overlaps with display element DE1. As a result, color mixing can be suppressed, and the degradation of display quality of the display device DSP can be prevented.

[0099] Furthermore, in the absence of lens ML1 in the display device DSP, a portion of the light emitted obliquely from near the periphery of display element DE2 does not pass through color filter CF2. Therefore, the brightness of the periphery of display element DE2 decreases, and seams between subpixels may sometimes be visible.

[0100] As a countermeasure, one could consider placing lenses above the color filter layer CF that cover the pixel openings AP1, AP2, and AP3 respectively. However, in this case, the lens size becomes larger relative to the distance between sub-pixels. Therefore, the effect of the lens at the connection point may not be possible when adjacent lenses are connected.

[0101] In this embodiment, lens ML1 is located below the color filter layer CF. Furthermore, lens ML1 is positioned to overlap with the periphery of pixel openings AP1, AP2, and AP3, but does not cover them. Therefore, the size of lens ML1 in this embodiment is smaller than the lens in the example described above. In one example, the diameter of lens ML1 is equal to the spacing between each of the pixel openings AP1, AP2, and AP3.

[0102] Therefore, the light rays emitted obliquely from near the periphery of each display element DE1, DE2, and DE3, as described above, are refracted by lens ML1 and travel along the Z direction. Thus, the reduction in brightness at the periphery of each display element DE1, DE2, and DE3 can be suppressed.

[0103] Furthermore, since adjacent lenses ML1 are not easily connected, the effect of lens ML1 can be improved. As a result, the brightness reduction at the periphery of each display element DE1, DE2, and DE3 can be further suppressed.

[0104] Furthermore, in this embodiment, the sealing layer SE2 has a recess R disposed directly above the partition wall 6. Additionally, the lens ML1 covers a portion of the bottom surface S3 of the recess R. Therefore, compared to the case where the sealing layer SE2 does not have the recess R, the amount of light L1 refracted at the interface between the lens ML1 and the resin layer RS1 increases. Thus, the brightness reduction at the periphery of each display element DE1, DE2, and DE3 can be suppressed. Furthermore, color mixing can be suppressed, and the display quality degradation of the display device DSP can be prevented.

[0105] Furthermore, in this embodiment, by providing the recess R, the distance in the Z direction between the top of lens ML1 and the upper surface S2 can be increased without increasing the amount of light L1 refracted by lens ML1. Therefore, the thickness T3 of resin layer RS1 can be reduced. This reduces the amount of light L1 refracted by lens ML1 that enters the color filter CF1 adjacent to color filter CF2. As a result, color mixing can be further suppressed. Additionally, it is unnecessary to place a light-shielding layer between color filters CF1, CF2, and CF3 to suppress color mixing. Therefore, the brightness of each sub-pixel SP1, SP2, and SP3 can be improved.

[0106] Furthermore, in this embodiment, the sealing layer SE2 is in contact with the sealing layer SE1. That is, no other layers, such as an organic insulating layer, are sandwiched between the sealing layers SE1 and SE2. Therefore, the distance in the Z direction between the lens ML1 and the display elements DE1, DE2, and DE3 can be reduced. As a result, the amount of light L1 illuminating the lens ML1 can be increased. Consequently, the brightness of the peripheral areas of the display elements DE1, DE2, and DE3 can be further improved. In addition, the amount of light L2 can be reduced simultaneously. Furthermore, the amount of light L2 traveling at an angle smaller than the critical angle can be reduced. This suppresses color mixing.

[0107] Next, an example of a method for forming the recess R will be explained. Figures 9A to 9C This is a schematic cross-sectional view showing the manufacturing process of the display device DSP according to the first embodiment. Figures 9A to 9C In the text, elements below the organic insulating layer 12 are omitted.

[0108] First, such as Figure 9A As shown, lower electrodes LE1 and LE2, rib layer 5, and spacer 6 are formed on the organic insulating layer 12. Rib layer 5 can be formed by CVD (Chemical Vapor Deposition). After forming layers corresponding to the bottom layer 63, axial layer 64, and upper layer 62 in the display area DA, the spacer 6 is formed by etching each layer using a patterned resist as a mask. After forming the spacer 6, pixel openings AP1 and AP2 are formed by etching the rib layer 5 using a patterned resist as a mask. It should be noted that the process of forming pixel openings AP1 and AP2 can be performed after or before the process of forming the spacer 6.

[0109] Next, the process for forming display elements DE1 and DE2 is performed. Display elements DE1 and DE2 are formed in the same process. Specifically, organic layers OR1 and OR2 are formed throughout the entire surface of the display area DA. The formed layers are divided into multiple parts by partition 6, forming organic layer OR1 covering pixel opening AP1 and organic layer OR2 covering pixel opening AP2. Upper electrodes UE1 and UE2 and capping layers CP1 and CP2 are also formed through the same process. The sealing layer SE1 is not separated by partition 6 and continuously covers the laminated films FL1 and FL2 and partition 6. Thus, display elements DE1 and DE2 are formed. It should be noted that, although the illustration is omitted, display element DE3 is also formed through the same process as display elements DE1 and DE2.

[0110] Organic layers OR1 and OR2, upper electrodes UE1 and UE2, and capping layers CP1 and CP2 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE1 can be formed, for example, by CVD.

[0111] Then, as Figure 9B As shown, an adhesive layer SE2 is formed to cover the adhesive layer SE1. The adhesive layer SE2 is formed to cover the entire surface of the display area DA.

[0112] Then, resist R1 is applied over the sealing layer SE2. Resist R1 covers pixel openings AP1 and AP2. Resist R1 is not applied directly above the adjacent layer 6.

[0113] Then, dry etching is performed using resist R1 as a mask. Thus, as... Figure 9C As shown, the portion of the sealing layer SE2 exposed from the resist R1 is removed, forming a recess R on the upper surface S2. After this etching, the resist R1 is removed (stripped off).

[0114] After the recess R is formed, lens ML1, resin layer RS1, sealing layer SE3, color filter layer CF and resin layer RS2 are formed, and the display device DSP is completed.

[0115] It should be noted that the method for forming the recess R is not limited to the examples described above. In other examples, after forming the sealing layer SE1, a photoresist disposed on the sealing layer SE1 is used as a mask to perform dry etching, thereby forming a groove in the sealing layer SE1 corresponding to the recess R. Then, when the material of the sealing layer SE2 is applied, the material of the sealing layer SE2 flows into the groove. As a result, a recess R with a shape corresponding to the groove is formed on the upper surface S2.

[0116] [Second Embodiment]

[0117] Figure 10 This is a schematic top view showing the sub-pixels SP1, SP2, and SP3 of the display device DSP according to the second embodiment. Elements that are the same or similar to those in the first embodiment are labeled with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0118] In the second embodiment, the shape of lens ML1 differs from that in the first embodiment. Figure 10 In the example, lens ML1 surrounds pixel openings AP1, AP2, and AP3 respectively. That is, pixel opening AP1 is surrounded by a single lens ML1, pixel opening AP2 is surrounded by a single lens ML2, and pixel opening AP3 is surrounded by a single lens ML1. Lens ML1 is arranged along the periphery of each pixel opening AP1, AP2, and AP3. With this configuration, the same effect as described above can be achieved.

[0119] [Third Implementation]

[0120] Figure 11 This is a schematic cross-sectional view of the display device DSP according to the third embodiment. Figure 11 In the example, the bottom surface S3 of the recess R is not covered by the lens ML1. The lens ML1 is only in contact with the upper surface S2 in the sealing layer SE2. Therefore, the recess R is covered by the resin layer RS1.

[0121] The refractive index of resin layer RS1 is lower than that of sealing layer SE2. Therefore, light emitted obliquely from display elements DE1, DE2, and DE3 is totally internally reflected by the recess R. Thus, it is possible to suppress light intrusion into adjacent sub-pixels SP1, SP2, and SP3.

[0122] [Fourth Embodiment]

[0123] Figure 12 This is a schematic top view showing the sub-pixels SP1, SP2, and SP3 of the display device DSP according to the fourth embodiment.

[0124] The display device DSP of the fourth embodiment includes a lens ML1 that overlaps with any one of the pixel openings AP1, AP2, and AP3, and a lens ML2 that overlaps with a plurality of pixel openings among the pixel openings AP1, AP2, and AP3. Figure 12 In the example, a lens ML1 overlapping pixel aperture AP3, a lens ML2 overlapping pixel apertures AP1 and AP2, a lens ML2 overlapping pixel apertures AP2 and AP3, and a lens ML2 overlapping pixel apertures AP1 and AP3 are arranged in the display area DA. The diameter of lens ML2 is larger than the diameter of lens ML1. In one example, the diameter of lens ML2 is more than twice the diameter of lens ML1.

[0125] exist Figure 12 In the example, lens ML1 is positioned between adjacent pixel openings AP3 in the Y direction. However, lens ML1 can also be positioned between pixel openings AP1 and AP2, between pixel openings AP2 and AP3, or between pixel openings AP1 and AP3. Additionally, lens ML2 can also be positioned between adjacent pixel openings AP3 along the Y direction.

[0126] It should be noted that the number and arrangement of lenses ML1 and ML2 are not limited to... Figure 12 For example, lens ML2 can be configured in the display area DA without lens ML1. Conversely, lens ML1 can be configured in the display area DA without lens ML2.

[0127] Figure 13 It is along Figure 12 A schematic cross-sectional view of the DSP display device for lines XIII-XIII. Figure 13 In the example, the first part SE11, the second part SE12, and the third part SE13 are separated from each other. Specifically, the first part SE11 on the partition 6 between sub-pixels SP1 and SP2 is separated from the second part SE12 on the same partition 6. In addition, the first part SE11 on the partition 6 between sub-pixels SP1 and SP3 is separated from the third part SE13 on the same partition 6.

[0128] For example, gaps are formed between the first part SE11, the second part SE12, and the third part SE13 and the upper part 62 of the partition wall 6. Laminated membranes FL1, FL2, and FL3 may also be disposed in at least a portion of these gaps.

[0129] The sealing layer SE2 continuously covers the first part SE11, the second part SE12, and the third part SE13. The sealing layer SE2 is in contact with the upper surface of the upper part 62 between the first part SE11 and the second part SE12. In addition, the sealing layer SE2 is in contact with the upper surface of the upper part 62 between the first part SE11 and the third part SE13.

[0130] Lens ML2 is disposed between display elements DE1 and DE2, and between display elements DE1 and DE3. Lens ML2 disposed between display elements DE1 and DE2 completely covers the recess R in the direction in which display elements DE1 and DE2 are arranged. Lens ML2 disposed between display elements DE1 and DE3 completely covers the recess R in the direction in which display elements DE1 and DE3 are arranged.

[0131] Organic layers OR1, OR2, and OR3 are configured to emit light of different colors. Organic layer OR1 emits green light. Organic layer OR2 emits red light. Organic layer OR3 emits blue light.

[0132] Color filter CF1 is positioned above organic layer OR1 and is colored the same as the green emitted by organic layer OR1. Color filter CF2 is positioned above organic layer OR2 and is colored the same as the red emitted by organic layer OR2. Color filter CF3 is positioned above organic layer OR3 and is colored the same as the blue emitted by organic layer OR3.

[0133] Figure 14 The diagram shows an example of the layer structure of the display elements DE1, DE2, and DE3 that can be applied to the display device DSP of the fourth embodiment.

[0134] The emitting layer EM1 is formed of a material that emits light in the green wavelength range. The emitting layer EM2 is formed of a material that emits light in the red wavelength range. The emitting layer EM3 is formed of a material that emits light in the blue wavelength range. It should be noted that the organic layers OR1, OR2, and OR3 may also have other structures, such as a so-called tandem structure containing multiple emitting layers.

[0135] Figure 15 This is a magnified cross-sectional view of lens ML2. Lens ML2 completely covers the bottom surface S3 in the Y direction (the direction in which the lower electrodes LE1 and LE2 are arranged). The refractive index of lens ML2 is the same as that of lens ML1.

[0136] The sealing layer SE2 has a protrusion P formed on the upper surface S2. The protrusion P is located above the partition wall 6 and is formed along the partition wall 6. The protrusion P is adjacent to both sides of the recess R. Figure 15In the example, the cross-sectional shape of the convex part P is semi-circular, but it is not limited to this example. The convex part P is covered by lens ML2.

[0137] Here, the effects of the display device DSP in the fourth embodiment will be explained. For example... Figure 15 As shown, the light rays emitted obliquely from the display element DE2 are designated as rays L3 and L4. Ray L4 is more oblique relative to the axis parallel to the Z direction compared to ray L3. Rays L3 and L4 contain a large amount of red wavelength light emitted from the light-emitting layer EM2.

[0138] Light L3 and Figure 8 Similarly, the light ray L1 shown is refracted in the Z direction (the front side of the display device DSP) at the interface between the lens ML1 and the resin layer RS1. The refracted light ray L3 passes through the color filter CF2 located above the display element DE2. As described above, the color filter CF2 is configured to prevent light of wavelengths other than red from passing through. Therefore, the light ray L3, which contains a large amount of red wavelength, passes through the color filter CF2 with almost no absorption.

[0139] On the other hand, ray L4 travels towards sub-pixel SP1. A portion of ray L4 is... Figure 8 Similarly, ray L2 is totally internally reflected at the interface between lens ML2 and sealing layer SE2. However, depending on the exit angle of ray L4, sometimes ray L4 travels straight at the interface between lens ML2 and sealing layer SE2, and is refracted laterally in the Z direction at the interface between lens ML2 and resin layer RS1.

[0140] In this configuration, light L4 travels towards the color filter CF1 located above the display element DE1. As described above, the color filter CF1 is configured to prevent light of wavelengths other than green from passing through. Therefore, most of the light L4, which contains a large amount of red wavelength, is absorbed by the color filter CF1. This suppresses color mixing and prevents degradation of the display quality of the display device DSP. Furthermore, this configuration can achieve the same effect as described above.

[0141] Next, an example of the method for forming the recess R in this embodiment will be described. Figures 16A to 16D This is a schematic cross-sectional view illustrating the manufacturing process of the display device DSP according to the fourth embodiment. Figures 16A to 16D In the text, elements below the organic insulating layer 12 are omitted.

[0142] The method for forming the organic insulating layer 12, lower electrodes LE1 and LE2, rib layer 5, partition 6, and pixel openings AP1 and AP2 is the same as in the first embodiment. After forming the pixel openings AP1 and AP2, as follows: Figure 16AAs shown, a laminated film FL1 and a first portion SE11 are formed to cover the entire surface of the display area DA. The laminated film FL1 is divided into multiple portions by partitions 6. The first portion SE11 continuously covers each of the partitioned portions of the laminated film FL1 and partitions 6.

[0143] Next, the laminated film FL1 and the first part SE11 are patterned. In this patterning, as... Figure 16A As shown, resist R2 is disposed above part SE11. Resist R2 covers a portion of the pixel opening AP1 and the surrounding partition 6.

[0144] Then, etching is performed using resist R2 as a mask. Thus, as... Figure 16B As shown, the portions of the laminated film FL1 and the first portion SE11 exposed from the resist R2 are removed. In other words, the portions of the laminated film FL1 and the first portion SE11 that overlap with the lower electrode LE1 are retained, while the remaining portions are removed. Thus, the display element DE1 is formed in the sub-pixel SP1. This etching process can include wet etching and dry etching performed sequentially on the first portion SE11, the capping layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R2 is removed (stripped off).

[0145] It should be noted that during the wet etching of the laminated film FL1, the laminated film FL1 located above the partition wall 6 and below the first portion SE11 is also removed. This creates a gap between the first portion SE11 above the partition wall 6 and the partition wall 6. The laminated film FL1 constituting the display element DE1 is completely surrounded by the first portion SE11 and the partition wall 6, and therefore is not eroded by the aforementioned wet etching.

[0146] Then, as Figure 16C As shown, the process for forming display element DE2 is performed. Display element DE2 can be formed using the same steps as display element DE1. Next, the process for forming display element DE3 is performed. Display element DE3 can be formed using the same steps as display elements DE1 and DE2.

[0147] It should be noted that this is an assumption that display elements DE1, DE2, and DE3 are formed in this order, but display elements DE1, DE2, and DE3 can also be formed in other orders.

[0148] After forming display elements DE1, DE2, and DE3, as follows Figure 16DThe sealing layer SE2 is formed as shown. Unlike the first embodiment, in the fourth embodiment, the recess R is not formed by etching. Specifically, the recess R is formed by the material of the sealing layer SE2 flowing into the gap between the first portion SE11 and the second portion SE12 located above the partition wall 6. In addition, the portion of the first portion SE11 and the second portion SE12 located above the partition wall 6 is raised compared to the portion covering the pixel openings AP1 and AP2. Therefore, the shape of this raised portion is reflected in the sealing layer SE2, forming a protrusion P.

[0149] After forming the sealing layer SE2, lenses ML1 and ML2, resin layer RS1, sealing layer SE3, color filter layer CF, and resin layer RS2 are formed, completing the display device DSP. It should be noted that the method for forming the recess R is not limited to the examples described above.

[0150] [Fifth Embodiment]

[0151] Figure 17 This is a schematic cross-sectional view of the display device DSP according to the fifth embodiment. The display device DSP of the fifth embodiment does not include the lens ML2. Therefore, the arrangement of the lens ML1 is different from... Figure 3 The example shown is the same. Furthermore, the configuration of display elements DE1, DE2, and DE3 is the same as... Figure 14 The structures shown are the same.

[0152] Lens ML1 covers a portion of the bottom surface S3. The convex portion P adjacent to the concave portion R is also covered by lens ML1. This configuration achieves the same effect as described above.

[0153] Based on the display device described above as an embodiment of the present invention, all display devices that can be appropriately designed, modified, and implemented by those skilled in the art as long as they contain the essence of the present invention also fall within the scope of the present invention.

[0154] Within the scope of this invention, various modifications will be conceived by those skilled in the art, and these modifications should also be considered within the scope of this invention. For example, any addition, deletion, or design change of constituent elements, or the addition, omission, or alteration of processes or conditions, made by those skilled in the art in relation to the above-described embodiments, as long as the essence of this invention is present, is also included within the scope of this invention.

[0155] Furthermore, any other effects resulting from the methods described in the above embodiments, as known from the description in this specification or that can be reasonably conceived by those skilled in the art, should naturally be considered as effects brought about by the present invention.

Claims

1. A display device, characterized in that, include: substrate; A first lower electrode and a second lower electrode are disposed above the substrate and are separated from each other; A rib layer, disposed above the first lower electrode and the second lower electrode, has a first pixel opening overlapping the first lower electrode and a second pixel opening overlapping the second lower electrode; The partition includes a lower portion disposed on the rib layer and having electrical conductivity, and an upper portion disposed on the lower portion and projecting from the side of the lower portion; The first organic layer is connected to the first lower electrode through the first pixel opening; The second organic layer is connected to the second lower electrode through the second pixel opening; The first upper electrode is disposed on the first organic layer and is in contact with the lower part; The second upper electrode is disposed on the second organic layer and is in contact with the lower part; A sealing layer having a recess located between the first lower electrode and the second lower electrode and disposed directly above the partition wall, the sealing layer covering the first upper electrode and the second upper electrode; as well as A convex lens is disposed above the sealing layer and covers a portion of the bottom surface of the recess in the direction in which the first lower electrode and the second lower electrode are arranged.

2. The display device according to claim 1, characterized in that, It also features a color filter layer disposed above the sealing layer. The lens is located between the sealing layer and the color filter layer.

3. The display device according to claim 2, characterized in that, The first organic layer and the second organic layer are configured to emit light of the same color as each other. The color filter layer has a first color filter disposed above the first organic layer and a second color filter disposed above the second organic layer and having a different color from the first color filter.

4. The display device according to claim 3, characterized in that, The sealing layer has the following characteristics: A first sealing layer, which covers the first upper electrode, the second upper electrode, and the partition wall; and The second sealing layer covers the first sealing layer.

5. The display device according to claim 4, characterized in that, The thickness of the second sealing layer is less than the thickness of the first sealing layer.

6. A display device, characterized in that, include: substrate; A first lower electrode and a second lower electrode are disposed above the substrate and are separated from each other; A rib layer, disposed above the first lower electrode and the second lower electrode, has a first pixel opening overlapping the first lower electrode and a second pixel opening overlapping the second lower electrode; The partition includes a lower portion disposed on the rib layer and having electrical conductivity, and an upper portion disposed on the lower portion and projecting from the side of the lower portion; The first organic layer is connected to the first lower electrode through the first pixel opening; The second organic layer is connected to the second lower electrode through the second pixel opening; The first upper electrode is disposed on the first organic layer and is in contact with the lower part; The second upper electrode is disposed on the second organic layer and is in contact with the lower part; A sealing layer having a recess located between the first lower electrode and the second lower electrode and disposed directly above the partition wall, the sealing layer covering the first upper electrode and the second upper electrode; as well as A convex lens is disposed above the sealing layer and completely covers the bottom surface of the recess in the direction in which the first lower electrode and the second lower electrode are arranged.

7. The display device according to claim 1 or 6, characterized in that, The first organic layer and the second organic layer are configured to emit light of different colors.

8. The display device according to claim 7, characterized in that, It also includes a color filter layer disposed above the sealing layer, the color filter layer having a first color filter disposed above the first organic layer and having the same color as the color emitted by the first organic layer, and a second color filter disposed above the second organic layer and having the same color as the color emitted by the second organic layer. The lens is located between the sealing layer and the color filter layer.

9. The display device according to claim 7, characterized in that, The sealing layer has the following characteristics: A first sealing layer comprising a first portion covering the first upper electrode and a second portion covering the second upper electrode, the second portion being separated from the first portion directly above the partition wall; and The second sealing layer covers the first sealing layer.

10. The display device according to claim 9, characterized in that, The thickness of the second sealing layer is less than the thickness of the first sealing layer.

11. The display device according to claim 7, characterized in that, The sealing layer has a protrusion adjacent to the recess.

12. The display device according to claim 11, characterized in that, The lens covers the convex portion.

13. The display device according to claim 1 or 6, characterized in that, The first pixel opening is surrounded by multiple lenses when viewed from above.

14. The display device according to claim 1 or 6, characterized in that, The first pixel opening is surrounded by a single lens when viewed from above.

15. The display device according to claim 1 or 6, characterized in that, The refractive index of the lens is less than that of the sealing layer.

16. The display device according to claim 1 or 6, characterized in that, The sealing layer is formed of inorganic material.

17. The display device according to claim 1 or 6, characterized in that, It also includes a resin layer covering the lens and having a refractive index less than that of the lens.

18. The display device according to claim 17, characterized in that, The thickness of the resin layer is less than the thickness of the sealing layer.

19. The display device according to claim 17, characterized in that, Also includes: A third sealing layer covering the resin layer; as well as A color filter layer disposed on the third sealing layer.

20. The display device according to claim 19, characterized in that, The thickness of the third sealing layer is less than the thickness of the sealing layer.

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