A method, apparatus, device, and medium for wafer drift monitoring

Abstract

The application provides a wafer drift monitoring method, device, equipment and medium, which divides an existing pad set of a wafer into a force end pad subset and a sensing pad subset, configures two force end pads and two sensing pads for a to-be-monitored object, applies an electric excitation through the force end pads, collects an electric response through the sensing pads, simultaneously performs a contact influence suppression operation, generates equivalent resistance indexes and / or equivalent pressure drop indexes, and generates quality marking information during a wafer probe test stage, stores the equivalent indexes, the quality marking information, a chip unique identification, a condition identification and a rewiring layer version identification as interconnection characteristic records, aligns the interconnection characteristic records of the same chip based on the chip unique identification, calculates a drift amount according to the quality marking information after screening, and generates alarm information or evidence chain based on the drift amount. The application realizes small resistance extraction and drift monitoring of a rewiring layer interconnection without adding an on-chip module and increasing packaging pin constraints.

Description

Technical Field

[0001] This application relates to the field of wafer monitoring technology, and more specifically, to a method, apparatus, equipment, and medium for wafer drift monitoring. Background Technology

[0002] Fan-In redistribution layer (FDL) technology is a crucial step in chip manufacturing. By redistributing pad positions on the wafer surface, it optimizes chip package size and adjusts pin layout. As chip integration density continues to increase and feature size continues to shrink, the size of redistribution layer interconnect structures is also decreasing, with interconnect resistance reduced to the milliohm level or even lower.

[0003] Currently, the wafer probe testing stage after redistribution layers typically employs the two-end method to evaluate interconnect electrical performance. This method applies excitation and acquires the response simultaneously using the same pair of probes. The measurement results include not only the resistance of the interconnect network under test but also the probe contact resistance, test path resistance, and their fluctuations. Because the interconnect resistance itself is extremely small, contact resistance fluctuations are often on the same order of magnitude or even larger than the measured resistance, resulting in measurement results that fail to accurately reflect changes in the interconnect itself and making it difficult to generate repeatable and verifiable quantitative data.

[0004] In mass production environments, these problems are even more pronounced. When yield fluctuations occur after the introduction of redistribution layer processes, engineers struggle to distinguish whether the root cause stems from changes in the interconnect structure or fluctuations in test contact states due to the lack of direct, observable measurements of the interconnect itself. Furthermore, because package pins are fully occupied by customers, preventing the addition of on-chip modules and discrete devices, traditional four-terminal measurement methods relying on on-chip test structures or package pins cannot be directly applied. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a method, apparatus, device and medium for wafer drift monitoring to overcome the problems in the prior art.

[0006] In a first aspect, embodiments of this application provide a method for wafer drift monitoring, wherein the wafer has undergone fan-in redistribution layer processing, the method comprising: The existing pad set of the wafer is divided into a force-end pad set and a sensing pad set. Two force-end pads are configured for the object to be monitored from the force-end pad set, and two sensing pads are configured for the object to be monitored from the sensing pad set. During the wafer probe testing phase, an electrical excitation is applied to the object to be monitored through the force-end pad, and the electrical response is collected through the sensing pad. During the collection process, a contact influence suppression operation is performed. Based on the correspondence between the electrical excitation and the electrical response, an equivalent resistance index and / or an equivalent voltage drop index are generated, and quality mark information is generated based on the execution status of the contact influence suppression operation. The equivalent resistance index and / or equivalent voltage drop index, the quality mark information, the chip unique identifier, the condition identifier, and the redistribution layer version identifier are associated and stored as an interconnect feature record; Based on the chip's unique identifier, the interconnect feature records of the same chip in at least two testing phases and / or before and after reliability retesting phases are aligned, and the drift amount is calculated after filtering or downweighting the interconnect feature records involved in the calculation based on the quality tag information. The drift amount is compared with a preset drift criterion, and alarm information and / or evidence chain information are generated when the conditions are met.

[0007] In some technical solutions of this application, the aforementioned object to be monitored is determined in the following ways: A candidate interconnection object library is established, and interconnection networks and / or interconnection segments are selected from the candidate interconnection object library as the objects to be monitored based on a preset selection and sorting mechanism; The selection and ranking mechanism includes the priority ranking of one or more of the following indicators: the magnitude of expected resistance / voltage drop; the degree of impact on yield and testability; root cause distinguishability; historical anomaly distribution; and pad reuse gain.

[0008] In some technical solutions of this application, the above-mentioned contact influence suppression operation includes one or more combinations of the following operations: High-impedance sampling at the sensing end; excitation polarity reversal; repetitive measurement and statistical aggregation; open / short circuit calibration; force end compliance monitoring.

[0009] In some technical solutions of this application, the aforementioned quality marking information includes at least: The compliance status marker characterizes the output state of the force end; the dispersion marker characterizes the consistency of repeatable measurements; and the calibration status marker characterizes whether calibration has been applied and the version of the calibration parameters.

[0010] In some technical solutions of this application, the above method also includes: When the resources of the sensing pad set are insufficient to support configuring an independent sensing pad for each of the objects to be monitored, a segmented sampling configuration is adopted; The segmented sampling configuration is as follows: a current path is formed on an interconnect network containing multiple sampling nodes through a fixed one-force end pad, and the potential difference between different combinations of sampling nodes is collected in a time-division manner using a limited number of sensing pads to extract segmented equivalent indices.

[0011] In some technical solutions of this application, the above-mentioned filtering or weighting of the interconnect feature records participating in the calculation based on the quality tag information specifically includes: Interconnect feature records with abnormal compliance status markings or dispersion markings exceeding preset thresholds are excluded from drift calculation. Alternatively, the weight of interconnect feature records whose compliance status is marked as abnormal or whose dispersion exceeds a preset threshold can be reduced, so that their contribution to the drift calculation is less than that of interconnect feature records that have not triggered anomalies.

[0012] In some technical solutions of this application, the aforementioned alarm information and / or evidence chain information includes at least: The identifier of the object to be monitored; the drift amount; the condition identifier; the redistribution layer version identifier; and the quality mark information.

[0013] Secondly, embodiments of this application provide a wafer drift monitoring device, the device comprising: The pad configuration module divides the existing pad set of the wafer into a force-end pad set and a sensing pad set, and configures two force-end pads for the object to be monitored from the force-end pad set, and configures two sensing pads for the object to be monitored from the sensing pad set. The measurement execution module is used to apply electrical excitation to the object to be monitored through the force end pad during the wafer probe testing stage, collect electrical response through the sensing pad, perform contact influence suppression operation during the acquisition process, generate equivalent resistance index and / or equivalent voltage drop index according to the correspondence between the electrical excitation and the electrical response, and generate quality mark information based on the execution status of the contact influence suppression operation. The storage module is used to associate and store the equivalent resistance index and / or equivalent voltage drop index, the quality mark information, the chip unique identifier, the condition identifier, and the redistribution layer version identifier as an interconnect feature record; The alignment and calculation module is used to align the interconnect feature records of the same chip in at least two test phases and / or before and after reliability retesting phases based on the chip's unique identifier, and to calculate the drift amount after filtering or downweighting the interconnect feature records involved in the calculation based on the quality tag information. The determination and output module is used to compare the drift amount with a preset drift criterion and generate alarm information and / or evidence chain information when the conditions are met.

[0014] Thirdly, embodiments of this application provide an electronic device, a processor, a memory, and a bus. The memory stores machine instructions executed by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine instructions are executed by the processor, the steps of the above-described wafer drift monitoring method are performed.

[0015] Fourthly, embodiments of this application provide a computer storage medium storing a computer program, which, when run by a processor, executes the steps of the above-described wafer drift monitoring method.

[0016] The technical solutions provided by the embodiments of this application may include the following beneficial effects: This application provides a wafer drift monitoring method. On a wafer that has undergone fan-in redistribution layer processing, the existing pad set is divided into a force-end pad set and a sensing pad set. Independent force-end and sensing pads are configured for each monitored object. During the wafer probe testing stage, a four-terminal measurement method is used to apply electrical excitation and acquire electrical responses. Simultaneously, contact influence suppression is performed to significantly suppress the interference of probe contact resistance and test path resistance on the measurement results, achieving true and repeatable extraction of milliohm-level micro-resistance or voltage drop. Based on this, quality marker information is generated according to the execution status of the contact influence suppression operation and associated with equivalent indicators, chip unique identifiers, condition identifiers, and redistribution layer version identifiers, forming a structured interconnect feature record. This record is then used to... The chip's unique identifier aligns data from different testing phases or reliability retesting phases for the same chip. Based on quality tag information, the records involved in the calculation are filtered or downweighted before the drift amount is calculated. This effectively eliminates interference data introduced by abnormal operating conditions such as poor probe contact, avoiding misjudgment as interconnect drift. Finally, the drift amount is compared with preset criteria. When the conditions are met, alarm information or evidence chain containing the identifier of the monitored object, drift amount, condition identifier, version identifier, and quality tag is output. Thus, without adding on-chip modules, package pins, or introducing mass production constraints of discrete devices, it achieves accurate quantitative extraction of redistribution layer interconnect performance and full life cycle drift monitoring, providing highly reliable traceable evidence for process improvement, version acceptance, and failure analysis.

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This diagram shows an overall block diagram of a wafer drift monitoring method provided in an embodiment of this application; Figure 2 This illustration shows a schematic diagram of the connection relationship of a four-terminal measurement port provided in an embodiment of this application; Figure 3 This illustration shows a schematic diagram of a four-terminal measurement sequence and quality marker generation process provided in an embodiment of this application; Figure 4 A schematic diagram of a wafer drift monitoring device provided in an embodiment of this application is shown; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0021] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0023] In the measurement of minute interconnect resistance (mΩ to hundreds of mΩ), the traditional two-terminal method superimposes the measured interconnect resistance with the test path resistance and probe contact resistance. This makes the measurement results highly sensitive to probe pressure, oxidation, wear, and fixture condition, making it difficult to form a repeatable and verifiable quantitative evidence chain. When yield or electrical parameter fluctuations occur after the introduction of RDL (Redistribution Layer), relying solely on single thresholds or functional phenomena of FT (Final Test) is insufficient to distinguish between interconnect body / interface problems and test contact / fixture problems, and it is also difficult to support RDL version acceptance and process early warning.

[0024] The purpose of this application is to establish a four-terminal (Kelvin) measurement and data closed-loop scheme that can be implemented in the wafer CP (ChipProbing / WaferSort) stage after the introduction of fan-inRDL (fan-in redistribution scheme, where RDL traces and pad redistribution are within the chip outline projection range) process, and under the constraints of not adding new on-chip modules / functions, not adding discrete devices in the RDL stage, and having no extra pins in the package for mass production. This scheme is used to repeatedly and quantifiably extract the minute resistance / voltage drop of key interconnect networks / interconnect segments, and further realize drift monitoring and alarm output across testing stages and across reliability retesting. Specifically, this application aims to solve the following technical problems: Firstly, considering that the RDL interconnect resistance is in the milliohm range and is easily masked by probe contact resistance and fixture path fluctuations, a four-terminal measurement sequence with force (force end, the pad / channel for applying constant current or constant voltage electrical excitation) / sense (sensing end, the pad / channel for sampling voltage / current response with high input impedance) separation is provided. Contact influence suppression and quality marking methods such as polarity reversal, repeatability statistics, open-short calibration, and force end compliance monitoring are introduced to obtain an equivalent index that is sensitive to small changes in interconnection and robust to contact fluctuations.

[0025] Secondly, to address the problem of data dispersion and difficulty in forming a verifiable data chain in the existing mass production chain, the interconnection equivalent index is associated with the chip's unique identifier (batch number / wafer number / XY), condition identifier, and RDL version identifier for storage. This achieves alignment with the FT and HTOL retest data before and after, and calculates the drift amount to support version acceptance and process early warning.

[0026] Third, given the limited pad resources and the inability to reserve Sense terminals for each path, this application provides a path selection and segmented sampling (tap point) mechanism with a reserved pad set P (number ≥ N) as the parameterized entry point. This enables a limited number of pads to form interconnect feature vectors with high information density, thereby improving the statistical confidence and interpretability of drift determination.

[0027] By achieving the above objectives, we can provide forward-looking, mass-producible measurement data and evidence chains for RDL version iteration, process window management, and design optimization.

[0028] The following describes some embodiments of this application in detail. Unless otherwise specified, the following embodiments and features can be combined with each other. Figure 1 This diagram illustrates an overall block diagram of a wafer drift monitoring method provided in an embodiment of this application. The diagram shows the physical process of establishing a baseline through four-terminal measurement in the wafer CP stage after RDL, acquiring full test logs in the FT stage, and conducting comparative testing in the HTOL retesting stage. It also shows the data closed-loop processing flow that achieves cross-stage data alignment, drift calculation, and alarm output based on the chip unique identifier ID, condition identifier CID, and redistribution layer version identifier VID (representing the chip unique identifier (batch number + wafer number + X / Y, etc.), measurement condition identifier, and RDL version / process version identifier, respectively).

[0029] Specifically, the wafer drift monitoring method provided in this application targets wafers that have completed a fan-in redistribution layer process. On this wafer, the redistribution layer has formed the required interconnect network and pad redistribution structure, but the chip is still in wafer form, and electrical tests can be performed by directly contacting the pads with probes. Since the package pins are already occupied, it is impossible to bring out additional test points through the package, and mass production constraints require that no new on-chip test modules be added before the redistribution layer and no discrete test devices be added during the redistribution layer process. Therefore, accurate evaluation of the interconnect performance of this type of wafer can only be carried out during the wafer probe testing stage, utilizing the existing pad resources on the wafer. This application is specifically for wafers under the above-mentioned mass production constraints.

[0030] A wafer contains several physical pads that can be used for electrical testing; these pads constitute the existing pad set. The number of pads in this set is typically limited and must meet mass production constraints of not adding new on-chip modules or package pins. To perform accurate four-terminal measurements on the object under test, this pad set first needs to be functionally partitioned. Specifically, the existing pad set is divided into a force-end pad set and a sensing pad set. The pads in the force-end pad set are used to apply electrical excitation to the object under test, while the pads in the sensing pad set are used to acquire the electrical response from the object under test. The force-end pads and sensing pads can be physically different to ensure that the current path for applying excitation at the force end is separated from the sampling path for acquiring voltage at the sensing end, thereby suppressing the influence of probe contact resistance on the measurement results. Based on this, two pads are selected from the force-end pad set for each monitored object, serving as the positive force-end pad and the negative force-end pad respectively, to form a complete excitation application loop. Simultaneously, two pads are selected from the sensing pad set for each monitored object, serving as the positive sensing pad and the negative sensing pad respectively, to acquire the voltage response across the monitored object. With this configuration, each monitored object has an independent pair of force-end pads and a pair of sensing pads, laying the foundation for the subsequent execution of the four-terminal measurement sequence.

[0031] In one specific implementation, the existing pad set comprises several aluminum or copper pads uniformly distributed on the wafer surface. The division between the force-end pad set and the sensing pad set is determined based on the pad layout and test resource allocation. For example, when the number of pads is sufficient, each object to be monitored can be configured with completely independent force-end pad pairs and sensing pad pairs. That is, the two pads of the force-end pad pair are dedicated to applying excitation to a specific object to be monitored and are not shared with other objects; the two pads of the sensing pad pair are also dedicated to voltage sampling of the object to be monitored and are similarly not shared with other objects. In this case, there is no overlap between the force-end pad set and the sensing pad set, and the number of pads contained in each set is more than twice the number of objects to be monitored.

[0032] In another specific implementation, when the number of pads in the sensing pad set is insufficient to support configuring independent sensing pad pairs for each monitored object, a pad reuse method is adopted. Specifically, a pair of pads in the force-end pad set is fixed as a common excitation application terminal to provide a stable current path for multiple monitored objects; the pads in the sensing pad set are connected to voltage sampling nodes of different monitored objects in a time-division manner through switching switches. For example, for an interconnection network containing multiple branches, several voltage sampling nodes are set on the network. The sensing pad pairs are connected to different sampling nodes at different times through probe cards or switch matrices to collect the potential difference between the corresponding nodes. At this time, although the number of sensing pad pairs is limited, voltage sampling of multiple monitored objects or different segments of the same object can still be achieved through time-division multiplexing. After the above configuration is completed, a pad mapping table is formed. This table records the specific pad number or location information of the force-end pad pair and sensing pad pair corresponding to each monitored object, and when the pad reuse method is adopted, it also records the correspondence and switching sequence between sampling nodes and sensing pads. This pad mapping table serves as the direct basis for subsequent test procedures, ensuring that the probes can accurately contact the designated pads and complete the four-terminal measurements.

[0033] In an alternative implementation, such as Figure 2 The diagram shown illustrates the connection relationship of the four-terminal measurement ports provided in this embodiment, demonstrating a Kelvin connection method that separates the force end and the sensing end. For each object to be monitored, four independent connection ports are configured: a positive force end, a negative force end, a positive sensing end, and a negative sensing end. Through this connection method that separates the force end and the sensing end, the current path for applying the excitation and the sampling path for acquiring the voltage are independent of each other. This ensures that the final measured voltage value only reflects the true voltage across the two ends of the object to be monitored, while the probe contact resistance, test lead resistance, and their fluctuations are effectively excluded from the measurement circuit.

[0034] Specifically, the force-end pads are connected to both ends of the object under monitoring, forming a complete current loop; the sensing-end pads are also connected to both ends of the object under monitoring, but are independent of the force-end pads, directly acquiring voltage signals. Based on Ohm's law, the equivalent small resistance of the object under monitoring can be calculated using the known excitation current value and the voltage value acquired by the sensing end. If a constant voltage excitation is used, the equivalent voltage drop index can be obtained directly. Figure 2In the diagram, solid arrows represent current paths, and dashed arrows represent voltage sampling paths. The Force terminal carries the current path and applies excitation (e.g., constant current), and its contact resistance / jig path resistance is superimposed on the Force terminal potential. The Sense terminal samples the potential difference AV between two points with a high input impedance, and almost no current flows through it, thus significantly suppressing the influence of contact resistance. Under constant current excitation, the interconnect equivalent index can be obtained: Rk≈AV / 1 (used for mQ-level interconnects / voltage drop extraction and drift monitoring).

[0035] In one alternative implementation, it is necessary to select worthy interconnects from the numerous interconnects on the wafer, as comprehensive measurement of all interconnects is not possible due to limitations in pad resources and test cycles. To address this, a candidate interconnect object library is first established, encompassing all interconnects and / or interconnect segments on the wafer that may require monitoring. This library records the endpoint locations, topology, and correlation information with mass production testing phenomena for each object.

[0036] Subsequently, a pre-defined optimization and ranking mechanism is used to select the final monitoring targets from the candidate library. This optimization and ranking mechanism comprehensively considers the priority of multiple indicators, including: the magnitude of expected resistance or voltage drop, prioritizing targets with extremely low resistance values ​​that are easily masked by contact resistance in two-terminal measurements; the impact on yield and testability, prioritizing critical paths that would lead to numerous failures or prevent normal chip testing if an anomaly occurs; root cause distinguishability, prioritizing targets where interconnect body issues or test contact issues can be clearly distinguished through four-terminal measurements; historical anomaly distribution, prioritizing local networks that have been proven to be high-frequency failure points in past mass production data; and pad reuse gain, prioritizing configurations that support segmented sampling through fixed force terminals and switching sensing terminals. Through the above optimization and ranking mechanism, the final set of monitoring targets is selected from the candidate interconnect object library, ensuring that limited test resources can cover the most critical and valuable interconnect networks and / or interconnect segments.

[0037] After screening the objects to be monitored, the selection results need to be transformed into structured information that can be directly used for subsequent mass production testing. This process generates three core tables: a vector definition table, a pad mapping table, and a condition table. The vector definition table records the final set of objects to be monitored. Each object is assigned a unique interconnect object identifier (e.g., L_k) and its measurement target is clearly defined, i.e., whether the equivalent resistance index (R_k) or the equivalent voltage drop index (ΔV_k) needs to be extracted. For objects using a segmented sampling configuration, this table further defines the combination method of sampling nodes, thus providing a clear logical framework for subsequent index calculations. The pad mapping table establishes the correspondence between the objects to be monitored and the physical pads, listing in detail the force-end pad pairs (F_k+, F_k+, F_k+) corresponding to each object to be monitored. ) and sensing pad pairs (S_k+, S_k The table records the specific pad numbers or location coordinates of the sensor. When a pad reuse mechanism is used, the table also records the switching relationship between multiple objects of the shared force end pad pair, as well as the connection timing between the sensing pads and each sampling node, ensuring that the probe card design, test equipment channel allocation, and field execution can be carried out accurately according to the predetermined plan. The condition table (CID set) summarizes all measurement conditions, assigns a unique condition identifier to each set of conditions, and clearly records the corresponding electrical excitation type and level, excitation polarity setting, number of repeated measurements, and the condition points that need to be switched when the same insertion supports multiple condition tests. These condition identifiers are bound to the actual measurement data, so that subsequent data comparisons can be strictly limited to the same conditions. The above three tables together constitute the key bridge from theoretical planning to mass production execution. They are not only the unified input basis for probe card manufacturing, test program development, and data management system, but also provide a standardized data dictionary for subsequent cross-stage data alignment and drift calculation.

[0038] like Figure 3 As shown (Note: The loop boundary is "single network Lk". Each loop: A4 selects Lk and configures four terminals → B executes forward / reverse + repeat statistics + extract indicators → B10 summarizes the output. The Q sub-tag comes from compliance monitoring / direction consistency / repeat statistics; Contact_OK and Calibration_OK come from column A), after completing the pad configuration and generating the vector definition table, pad mapping table and condition table, the actual measurement stage of the wafer probe testing phase begins. For each object to be monitored, the probe is precisely contacted to the corresponding force end pad pair and sensing pad pair according to the pad mapping table, and the four-terminal measurement sequence is executed according to the parameters set in the condition table. Specifically, a preset electrical excitation is applied to the object to be monitored through the force end pad pair, such as a constant current provided by a constant current source or a constant voltage provided by a constant voltage source; at the same time, the electrical response at both ends of the object to be monitored is collected through the sensing pad pair, which is usually a voltage signal. Since the sensing end adopts a high input impedance sampling method, the current flowing through the sensing probe is extremely weak, so the influence of the probe contact resistance on the voltage measurement result is effectively suppressed.

[0039] During the acquisition of the electrical response, a contact influence suppression operation is performed simultaneously to further improve the accuracy and reliability of the measurement data. This contact influence suppression operation includes, but is not limited to, the following methods: excitation polarity reversal, i.e., applying positive and reverse electrical excitations sequentially, using the difference or mean of the two measurement results to offset the effects of thermoelectric potential and system zero bias; repeated measurement and statistical aggregation, i.e., performing multiple measurements on the same monitored object under the same conditions, calculating the mean and evaluating the dispersion between the multiple results; open-circuit or short-circuit calibration, i.e., obtaining the system's own error baseline through a measurement reference path to correct the measured results; force-end compliance monitoring, i.e., real-time monitoring of whether the force-end output triggers a preset voltage or current compliance threshold, indicating a possible abnormality in the force-end contact if compliance is triggered. The above contact influence suppression operations can be automatically completed in a preset sequence during a single insertion test without manual intervention.

[0040] Based on the correspondence between the applied electrical excitation and the acquired electrical response, equivalent resistance and / or equivalent voltage drop indices are calculated. For example, in constant current excitation mode, the equivalent minute resistance of the monitored object can be obtained by dividing the voltage value acquired at the sensing end by the known current value; in constant voltage excitation mode, the equivalent voltage drop across the monitored object can be directly obtained. These indices reflect the electrical performance status of the interconnect network or interconnect segment itself.

[0041] Simultaneously, quality marker information is generated based on the execution status of the contact impact suppression operation. This quality marker information includes at least: a compliance status marker, used to record whether the force end triggers or approaches the compliance threshold during excitation application, thus characterizing the health status of the force end contact; a dispersion marker, used to record the degree of fluctuation in repeated measurement results; if the dispersion is too high, it indicates that the probe contact may be unstable in this measurement; and a calibration status marker, used to record whether open-circuit or short-circuit calibration was applied and the version of calibration parameters used. These quality marker information correspond one-to-one with equivalent indicators, together constituting the output result of a complete measurement, providing an objective basis for subsequent data reliability assessment and outlier sample removal.

[0042] The generation of quality marker information based on the execution status of contact impact suppression operations specifically refers to: during the execution of the four-terminal measurement sequence, recording the execution results or status parameters of each contact impact suppression operation in real time, and converting these status parameters into structured quality markers to characterize the reliability and contact health status of this measurement. This includes the following scenarios: For force-end compliance monitoring, the output voltage or current of the force-end pads during the application of electrical excitation is monitored in real time to see if it reaches a preset compliance threshold. If the force-end output reaches or exceeds the compliance threshold, it is determined to be a compliance anomaly, and a corresponding compliance status flag is generated, such as "Compliance Triggered" or "Compliance Warning". If the force-end output remains stable within the normal range, it is marked as "Compliance Normal". This flag reflects the contact quality between the force-end probe and the tested pad. If compliance is triggered, it usually indicates poor probe contact, pad oxidation, or an open circuit in the test path.

[0043] For reverse excitation polarity operation, after performing two measurements (one with forward excitation and one with reverse excitation), the degree of difference between the two measurement results is calculated. If the difference between the forward and reverse measurement results significantly exceeds the expected range, it may indicate the presence of thermoelectric potential interference or a change in the contact state between the two measurements. In this case, a corresponding polarity consistency marker is generated, such as marked as "abnormal polarity deviation" or "normal polarity consistency." This marker can be used to evaluate the thermoelectric potential elimination effect and the stability of the contact state during the measurement process.

[0044] For repeated measurements and statistical aggregation operations, after performing multiple measurements on the same monitored object under the same conditions, the dispersion of the multiple measurement results is calculated, such as standard deviation, range, or coefficient of variation. The calculated dispersion is compared with a preset dispersion threshold. If the dispersion is lower than the threshold, the measurement is considered stable, and a dispersion label of "low dispersion" or "stable" is generated; if the dispersion is higher than the threshold, the measurement is considered to have large fluctuations, and a dispersion label of "high dispersion" or "unstable" is generated. This label directly reflects the stability of probe contact during the measurement process. High dispersion usually indicates that there is micro-jumping of the probe, fluctuation of contact pressure, or contamination of the pad surface.

[0045] Subsequently, the equivalent resistance and / or equivalent voltage drop metrics obtained from each measurement, along with the accompanying quality marker information, are associated with the chip's unique identifier, the condition identifier used in this measurement, and the current redistribution layer version identifier, and stored together as a structured interconnect feature record. This interconnect feature record is a structured encapsulation of a complete four-terminal measurement. The chip's unique identifier uniquely identifies the chip under test, and can be composed of, for example, a combination of wafer batch number, wafer serial number, and the chip's coordinate position on the wafer. The condition identifier points to the specific condition table entry used in this measurement, recording parameters such as electrical excitation type, range, and polarity settings. The redistribution layer version identifier distinguishes different batches of process versions or design versions, facilitating subsequent tracking of performance changes during version evolution. The quality marker information, as a crucial component of this record, provides a quantitative basis for evaluating the reliability of the measurement data. Through this associative storage method, the measurement data generated by each chip in different testing stages, under different testing conditions, and in different process versions are organized in an orderly manner, forming a data chain that runs through the entire life cycle of the chip, laying the data structure foundation for subsequent data alignment and drift calculation based on the chip's unique identifier.

[0046] Subsequently, based on the chip's unique identifier, interconnect feature records generated by the same chip at different testing stages or before and after reliability retesting are aligned across stages. Specifically, all interconnect feature records with the same chip's unique identifier are extracted from massive amounts of test data and sorted according to the testing stage or retesting sequence, thereby establishing a complete data view of the same chip at various time points, from wafer probe testing and post-packaging testing to before and after high-temperature operational life stress testing. During the alignment process, it is necessary to ensure that the monitoring object identifier and condition identifier corresponding to the interconnect feature records participating in the comparison are consistent, so as to ensure that the drift calculation is performed on the same object and under the same test conditions. On this basis, the interconnect feature records participating in the calculation are filtered or downweighted based on quality tag information.

[0047] Specifically, records marked as abnormal in compliance status, exceeding a preset threshold in dispersion, or marked as uncalibrated in calibration status are considered unreliable data. These records can be directly removed from subsequent calculations, or their weight in the calculation can be reduced so that their contribution to the final drift is less than that of records marked as normal. After screening or weight reduction, reliable records marked as normal or with higher weights are retained for drift calculation. For two different stages of records of the same monitored object under the same condition, the difference or rate of change of their equivalent resistance or equivalent voltage drop indices is calculated to obtain the drift.

[0048] For example, subtracting the resistance value from the wafer probe testing stage from the resistance value during the post-packaging testing stage yields the resistance drift of the interconnect object after the packaging process is introduced; or subtracting the resistance value before testing from the resistance value after high-temperature operating life testing yields the resistance drift under stress. Through the above processing, highly reliable drift data that accurately reflects changes in the interconnect's performance is finally obtained.

[0049] Next, the calculated drift amount is compared with a preset drift criterion. This drift criterion can be a threshold band constructed based on the golden baseline sample distribution. For example, it can be determined by adding or subtracting a certain number of standard deviations from the mean to determine the normal fluctuation range, or by using quantile thresholds to set upper and lower limits. Alternatively, different threshold sets can be set for different types of interconnect networks or different test conditions. If the drift amount does not exceed the threshold band, the interconnect performance of the monitored object is determined to be in a stable state, and this monitoring ends or the next cycle of regular monitoring begins. If the drift amount exceeds the threshold band or meets the preset abnormal mode criterion, it is determined to be a drift anomaly, and an alarm mechanism is triggered. At this time, the system automatically generates alarm information and / or evidence chain information.

[0050] Alarm information includes at least the identifier of the monitored object experiencing drift, the specific drift amount, the condition identifier used in the drift calculation, the current redistribution layer version identifier, and relevant quality marker information involved in the calculation. The evidence chain information further enriches this, and may include timestamps of interconnect feature records at each stage of alignment, original measurements, details of filtered or downweighted records, and optional test program execution status fields, such as the executability marker in the post-packaging testing phase, to provide a complete traceable path from raw data to the final judgment result. The generated alarm information and evidence chain information are output to a designated storage location or monitoring platform to support subsequent engineering decisions. Specific uses include, but are not limited to: serving as acceptance criteria for redistribution layer version iterations to determine whether the new version resolves the drift issues present in the old version; serving as a process warning signal to indicate potential process window offsets on the production line; or serving as input data for design iterations to guide the design team in optimizing the interconnect network topology or adding redundant design. Through the above mechanism, this application realizes a complete closed loop from data acquisition and drift calculation to anomaly warning and evidence consolidation, providing quantitative and traceable technical support for quality monitoring and continuous improvement of fan-in redistribution layer technology.

[0051] Example 1, Kelvin's minimum verifiable measurement in the post-RDL wafer CP stage: (1) Obtain the set of reserved pads P (number ≥ N) that the wafer can access after RDL, and divide them into P_F (number ≥ N_f) and P_S (number ≥ N_s).

[0052] (2) Establish a candidate interconnect object library and determine the mapping relationship between {L_k} and pads according to the preferred principle / sorting mechanism to form a vector definition table and a pad mapping table.

[0053] (3) Configure (F_k+, F_k) for each L_k. ) and (S_k+, S_k) Set force end compliance restrictions; perform CID within the same insertion: contact pre-inspection → +stimulus sampling → -stimulus sampling → repeat r times.

[0054] (4) Extract R_k and / or ΔV_k and generate quality flags Q_flags (including at least compliance status and dispersion flags).

[0055] (5) Store {ID, Stage=RDL_CP, VID, CID, L_k, R_k / ΔV_k, Q_flags} together as the baseline for subsequent cross-stage alignment and drift monitoring.

[0056] Example 2, Segmented sampling and pad reuse of tap points (voltage sampling nodes and Sense candidate points arranged on the same network, used for segmented extraction of voltage drop / resistance features) under Sense resource constraints: When the P_S budget is insufficient to configure independent (S_k+, S_k) for multiple L_k nodes respectively. When reusing networks / paths that have a high impact on yield and can distinguish root causes, select those networks / paths as reuse targets.

[0057] (1) Fixed force end pad pair (F+, F To form a stable current path; (2) Select at least one sampling node T_i (tap point) on the same network / path, and use a limited number of sensing pads to collect the potential difference between different combinations of T_i; (3) Extract the segmented equivalent index (e.g., inter-segment voltage drop or equivalent resistance) from the end-to-end and segmented ΔV combination, and generate L_k sub-objects or feature dimensions corresponding to the segmented combination; (4) Repeat the measurement under the same CID and output the dispersion mark. If necessary, reduce the weight of specific segment combinations or transfer them to the verification set.

[0058] This embodiment improves the information content and positioning resolution per pad without increasing package pins or introducing discrete components.

[0059] Example 3: Using multiple conditions for the same insertion to form a P2 feature vector to improve the confidence of drift determination: When the test platform allows the same insertion switching condition, four-terminal measurement sequences are executed on the same L_k at multiple condition points to form a feature vector P2 with higher information density.

[0060] (1) Define a set of CIDs, including at least one set of power supply discrete points and / or a set of excitation positions, and record the condition parameters corresponding to each CID; (2) For each CID, perform the minimum verifiable sequence of Example 1 to obtain {R_k / ΔV_k, Q_flags}; (3) The indices of the same L_k under multiple CIDs are combined into a vector feature, which can be used to distinguish voltage-sensitive / nonlinear paths or abnormal interface behavior; (4) Multi-condition vectors can be used to construct more robust threshold bands or improve the statistical confidence of drift determination (e.g., thresholds grouped by network type / condition).

[0061] Example 4: Drift determination and evidence chain output for cross-FT / HTOL pre- and post-test alignment: (1) Form interconnect baseline records in the RDL_CP stage; obtain full FT log in the FT and HTOL retest stages, and align records of different stages based on the chip's unique ID.

[0062] (2) After alignment, calculate the drift amount ΔR_k and / or Δ(ΔV_k) of each L_k, and apply a quality label-driven screening / reduction strategy: remove / reduction samples with compliance anomalies or dispersion exceeding the threshold, and transfer them to the review set if necessary.

[0063] (3) Construct a threshold band (mean ± kσ or quantile threshold, etc.) based on the golden baseline sample distribution, and compare the drift amount with the threshold band to obtain the drift determination.

[0064] (4) Output alarm and evidence chain information, including at least: L_k, drift amount, CID, VID, quality flag Q_flags, and (optional) FT_Executable and other executable fields, for version acceptance, process warning and design iteration input.

[0065] Figure 4 This illustration shows a schematic diagram of a wafer drift monitoring device provided in an embodiment of this application. The device includes: The pad configuration module divides the existing pad set of the wafer into a force-end pad set and a sensing pad set, and configures two force-end pads for the object to be monitored from the force-end pad set, and configures two sensing pads for the object to be monitored from the sensing pad set. The measurement execution module is used to apply electrical excitation to the object to be monitored through the force end pad during the wafer probe testing stage, collect electrical response through the sensing pad, perform contact influence suppression operation during the acquisition process, generate equivalent resistance index and / or equivalent voltage drop index according to the correspondence between the electrical excitation and the electrical response, and generate quality mark information based on the execution status of the contact influence suppression operation. The storage module is used to associate and store the equivalent resistance index and / or equivalent voltage drop index, the quality mark information, the chip unique identifier, the condition identifier, and the redistribution layer version identifier as an interconnect feature record; The alignment and calculation module is used to align the interconnect feature records of the same chip in at least two test phases and / or before and after reliability retesting phases based on the chip's unique identifier, and to calculate the drift amount after filtering or downweighting the interconnect feature records involved in the calculation based on the quality tag information. The determination and output module is used to compare the drift amount with a preset drift criterion and generate alarm information and / or evidence chain information when the conditions are met.

[0066] The object to be monitored is determined in the following way: A candidate interconnection object library is established, and interconnection networks and / or interconnection segments are selected from the candidate interconnection object library as the objects to be monitored based on a preset selection and sorting mechanism; The selection and ranking mechanism includes the priority ranking of one or more of the following indicators: the magnitude of expected resistance / voltage drop; the degree of impact on yield and testability; root cause distinguishability; historical anomaly distribution; and pad reuse gain.

[0067] The contact effect suppression operation includes one or more combinations of the following operations: High-impedance sampling at the sensing end; excitation polarity reversal; repetitive measurement and statistical aggregation; open / short circuit calibration; force end compliance monitoring.

[0068] The quality marking information includes at least: The compliance status marker characterizes the output state of the force end; the dispersion marker characterizes the consistency of repeatable measurements; and the calibration status marker characterizes whether calibration has been applied and the version of the calibration parameters.

[0069] When the resources of the sensing pad set are insufficient to support configuring an independent sensing pad for each of the objects to be monitored, a segmented sampling configuration is adopted; The segmented sampling configuration is as follows: a current path is formed on an interconnect network containing multiple sampling nodes through a fixed one-force end pad, and the potential difference between different combinations of sampling nodes is collected in a time-division manner using a limited number of sensing pads to extract segmented equivalent indices.

[0070] The filtering or weighting of the interconnect feature records participating in the calculation based on the quality tag information specifically includes: Interconnect feature records with abnormal compliance status markings or dispersion markings exceeding preset thresholds are excluded from drift calculation. Alternatively, the weight of interconnect feature records whose compliance status is marked as abnormal or whose dispersion exceeds a preset threshold can be reduced, so that their contribution to the drift calculation is less than that of interconnect feature records that have not triggered anomalies.

[0071] The alarm information and / or evidence chain information shall include at least: The identifier of the object to be monitored; the drift amount; the condition identifier; the redistribution layer version identifier; and the quality mark information.

[0072] like Figure 5 As shown, this application provides an electronic device for executing the wafer drift monitoring method of this application. The device includes a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the wafer drift monitoring method described above.

[0073] Specifically, the aforementioned memory and processor can be general-purpose memory and processor, without any specific limitations. When the processor runs the computer program stored in the memory, it can execute the aforementioned wafer drift monitoring method.

[0074] Corresponding to the wafer drift monitoring method in this application, this application embodiment also provides a computer storage medium storing a computer program, which is executed by a processor to perform the steps of the wafer drift monitoring method described above.

[0075] Specifically, the storage medium can be a general-purpose storage medium, such as a removable disk or hard disk. When the computer program on the storage medium is run, it can execute the aforementioned wafer drift monitoring method.

[0076] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interface; the indirect coupling or communication connection between systems or units may be electrical, mechanical, or other forms.

[0077] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0078] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0079] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0080] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0081] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A method for monitoring wafer drift, characterized in that, The wafer has completed the fan-in redistribution layer process, and the method includes: The existing pad set of the wafer is divided into a force-end pad set and a sensing pad set. Two force-end pads are configured for the object to be monitored from the force-end pad set, and two sensing pads are configured for the object to be monitored from the sensing pad set. During the wafer probe testing phase, an electrical excitation is applied to the object to be monitored through the force-end pad, and the electrical response is collected through the sensing pad. During the collection process, a contact influence suppression operation is performed. Based on the correspondence between the electrical excitation and the electrical response, an equivalent resistance index and / or an equivalent voltage drop index are generated, and quality mark information is generated based on the execution status of the contact influence suppression operation. The equivalent resistance index and / or equivalent voltage drop index, the quality mark information, the chip unique identifier, the condition identifier, and the redistribution layer version identifier are associated and stored as an interconnect feature record; Based on the chip's unique identifier, the interconnect feature records of the same chip in at least two testing phases and / or before and after reliability retesting phases are aligned, and the drift amount is calculated after filtering or downweighting the interconnect feature records involved in the calculation based on the quality tag information. The drift amount is compared with a preset drift criterion, and alarm information and / or evidence chain information are generated when the conditions are met.

2. The method according to claim 1, characterized in that, The object to be monitored is determined in the following way: A candidate interconnection object library is established, and interconnection networks and / or interconnection segments are selected from the candidate interconnection object library as the objects to be monitored based on a preset selection and sorting mechanism; The selection and ranking mechanism includes the priority ranking of one or more of the following indicators: the magnitude of expected resistance / voltage drop; the degree of impact on yield and testability; root cause distinguishability; historical anomaly distribution; and pad reuse gain.

3. The method according to claim 1, characterized in that, The contact effect suppression operation includes one or more combinations of the following operations: High-impedance sampling at the sensing end; excitation polarity reversal; repetitive measurement and statistical aggregation; open / short circuit calibration; force end compliance monitoring.

4. The method according to claim 3, characterized in that, The quality marking information includes at least: The compliance status marker characterizes the output state of the force end; the dispersion marker characterizes the consistency of repeatable measurements; and the calibration status marker characterizes whether calibration has been applied and the version of the calibration parameters.

5. The method according to claim 1, characterized in that, The method further includes: When the resources of the sensing pad set are insufficient to support configuring an independent sensing pad for each of the objects to be monitored, a segmented sampling configuration is adopted; The segmented sampling configuration is as follows: a current path is formed on an interconnect network containing multiple sampling nodes through a fixed one-force end pad, and the potential difference between different combinations of sampling nodes is collected in a time-division manner using a limited number of sensing pads to extract segmented equivalent indices.

6. The method according to claim 1, characterized in that, The filtering or weighting of the interconnect feature records participating in the calculation based on the quality tag information specifically includes: Interconnect feature records with abnormal compliance status markings or dispersion markings exceeding preset thresholds are excluded from drift calculation. Alternatively, the weight of interconnect feature records whose compliance status is marked as abnormal or whose dispersion exceeds a preset threshold can be reduced, so that their contribution to the drift calculation is less than that of interconnect feature records that have not triggered anomalies.

7. The method according to claim 1, characterized in that, The alarm information and / or evidence chain information shall include at least: The identifier of the object to be monitored; the drift amount; the condition identifier; the redistribution layer version identifier; and the quality mark information.

8. A device for monitoring wafer drift, characterized in that, The device includes: The pad configuration module divides the existing pad set of the wafer into a force-end pad set and a sensing pad set, and configures two force-end pads for the object to be monitored from the force-end pad set, and configures two sensing pads for the object to be monitored from the sensing pad set. The measurement execution module is used to apply electrical excitation to the object to be monitored through the force end pad during the wafer probe testing stage, collect electrical response through the sensing pad, perform contact influence suppression operation during the acquisition process, generate equivalent resistance index and / or equivalent voltage drop index according to the correspondence between the electrical excitation and the electrical response, and generate quality mark information based on the execution status of the contact influence suppression operation. The storage module is used to associate and store the equivalent resistance index and / or equivalent voltage drop index, the quality mark information, the chip unique identifier, the condition identifier, and the redistribution layer version identifier as an interconnect feature record; The alignment and calculation module is used to align the interconnect feature records of the same chip in at least two test phases and / or before and after reliability retesting phases based on the chip's unique identifier, and to calculate the drift amount after filtering or downweighting the interconnect feature records involved in the calculation based on the quality tag information. The determination and output module is used to compare the drift amount with a preset drift criterion and generate alarm information and / or evidence chain information when the conditions are met.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine instructions that the processor executes. When the electronic device is running, the processor communicates with the memory via the bus. When the machine instructions are executed by the processor, they perform the steps of the wafer drift monitoring method as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that, The computer storage medium stores a computer program that, when executed by a processor, performs the steps of the wafer drift monitoring method as described in any one of claims 1 to 7.

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